#ifndef _PCI_H
#define _PCI_H
+#define PCI_CFG_SPACE_SIZE 256
+#define PCI_CFG_SPACE_EXP_SIZE 4096
+
/*
* Under PCI, each device has 256 bytes of configuration address space,
* of which the first 64 bytes are standardized as follows:
#define PCI_MIN_GNT 0x3e /* 8 bits */
#define PCI_MAX_LAT 0x3f /* 8 bits */
+#define PCI_INTERRUPT_LINE_DISABLE 0xff
+
/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
#define PCI_FIND_CAP_TTL 0x48
#define CAP_START_POS 0x40
+/* Extended Capabilities (PCI-X 2.0 and Express) */
+#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
+#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
+#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
+
+#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
+#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
+#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
+#define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
+#define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
+#define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
+#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
+#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
+#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
+#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
+#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
+#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
+#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
+#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
+#define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
+#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
+#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
+#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
+#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
+#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */
+#define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */
+#define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */
+#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */
+#define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
+#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
+#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
+#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
+
/* Include the ID list */
#include <pci_ids.h>
#define PCI_ANY_ID (~0)
struct pci_device_id {
- unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
+ unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
+ unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
+ unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
+ unsigned long driver_data; /* Data private to the driver */
};
struct pci_controller;
int indirect_type;
+ /*
+ * TODO(sjg@chromium.org): With driver model we use struct
+ * pci_controller for both the controller and any bridge devices
+ * attached to it. But there is only one region list and it is in the
+ * top-level controller.
+ *
+ * This could be changed so that struct pci_controller is only used
+ * for PCI controllers and a separate UCLASS (or perhaps
+ * UCLASS_PCI_GENERIC) is used for bridges.
+ */
struct pci_region regions[MAX_PCI_REGIONS];
int region_count;
#define pci_io_to_virt(dev, addr, len, map_flags) \
pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
+/* For driver model these are defined in macros in pci_compat.c */
extern int pci_hose_read_config_byte(struct pci_controller *hose,
pci_dev_t dev, int where, u8 *val);
extern int pci_hose_read_config_word(struct pci_controller *hose,
extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
int cap);
+int pci_find_next_ext_capability(struct pci_controller *hose,
+ pci_dev_t dev, int start, int cap);
+int pci_hose_find_ext_capability(struct pci_controller *hose,
+ pci_dev_t dev, int cap);
+
#ifdef CONFIG_PCI_FIXUP_DEV
extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
unsigned short vendor,
* */
u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
-/**
- * pciauto_setup_rom() - Set up access to a device ROM
- *
- * @hose: PCI hose to use
- * @dev: PCI device to adjust
- * @return 0 if done, -ve on error
- */
-int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev);
-
/**
* pci_hose_find_devices() - Find devices by vendor/device ID
*
/* Get access to a PCI bus' operations */
#define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
+/**
+ * pci_get_bdf() - Get the BDF value for a device
+ *
+ * @dev: Device to check
+ * @return bus/device/function value (see PCI_BDF())
+ */
+pci_dev_t pci_get_bdf(struct udevice *dev);
+
/**
* pci_bind_bus_devices() - scan a PCI bus and bind devices
*
int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
struct udevice **devp);
+/**
+ * pci_find_first_device() - return the first available PCI device
+ *
+ * This function and pci_find_first_device() allow iteration through all
+ * available PCI devices on all buses. Assuming there are any, this will
+ * return the first one.
+ *
+ * @devp: Set to the first available device, or NULL if no more are left
+ * or we got an error
+ * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
+ */
+int pci_find_first_device(struct udevice **devp);
+
+/**
+ * pci_find_next_device() - return the next available PCI device
+ *
+ * Finds the next available PCI device after the one supplied, or sets @devp
+ * to NULL if there are no more.
+ *
+ * @devp: On entry, the last device returned. Set to the next available
+ * device, or NULL if no more are left or we got an error
+ * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
+ */
+int pci_find_next_device(struct udevice **devp);
+
/**
* pci_get_ff() - Returns a mask for the given access size
*
int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
unsigned long value, enum pci_size_t size);
+/**
+ * Driver model PCI config access functions. Use these in preference to others
+ * when you have a valid device
+ */
+int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
+ enum pci_size_t size);
+
+int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep);
+int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep);
+int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep);
+
+int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
+ enum pci_size_t size);
+
+int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
+int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
+int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
+
/*
* The following functions provide access to the above without needing the
* size parameter. We are trying to encourage the use of the 8/16/32-style
return pci_read_config8(pcidev, offset, valuep);
}
-#endif
+/**
+ * struct dm_pci_emul_ops - PCI device emulator operations
+ */
+struct dm_pci_emul_ops {
+ /**
+ * get_devfn(): Check which device and function this emulators
+ *
+ * @dev: device to check
+ * @return the device and function this emulates, or -ve on error
+ */
+ int (*get_devfn)(struct udevice *dev);
+ /**
+ * read_config() - Read a PCI configuration value
+ *
+ * @dev: Emulated device to read from
+ * @offset: Byte offset within the device's configuration space
+ * @valuep: Place to put the returned value
+ * @size: Access size
+ * @return 0 if OK, -ve on error
+ */
+ int (*read_config)(struct udevice *dev, uint offset, ulong *valuep,
+ enum pci_size_t size);
+ /**
+ * write_config() - Write a PCI configuration value
+ *
+ * @dev: Emulated device to write to
+ * @offset: Byte offset within the device's configuration space
+ * @value: Value to write
+ * @size: Access size
+ * @return 0 if OK, -ve on error
+ */
+ int (*write_config)(struct udevice *dev, uint offset, ulong value,
+ enum pci_size_t size);
+ /**
+ * read_io() - Read a PCI I/O value
+ *
+ * @dev: Emulated device to read from
+ * @addr: I/O address to read
+ * @valuep: Place to put the returned value
+ * @size: Access size
+ * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
+ * other -ve value on error
+ */
+ int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
+ enum pci_size_t size);
+ /**
+ * write_io() - Write a PCI I/O value
+ *
+ * @dev: Emulated device to write from
+ * @addr: I/O address to write
+ * @value: Value to write
+ * @size: Access size
+ * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
+ * other -ve value on error
+ */
+ int (*write_io)(struct udevice *dev, unsigned int addr,
+ ulong value, enum pci_size_t size);
+ /**
+ * map_physmem() - Map a device into sandbox memory
+ *
+ * @dev: Emulated device to map
+ * @addr: Memory address, normally corresponding to a PCI BAR.
+ * The device should have been configured to have a BAR
+ * at this address.
+ * @lenp: On entry, the size of the area to map, On exit it is
+ * updated to the size actually mapped, which may be less
+ * if the device has less space
+ * @ptrp: Returns a pointer to the mapped address. The device's
+ * space can be accessed as @lenp bytes starting here
+ * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
+ * other -ve value on error
+ */
+ int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
+ unsigned long *lenp, void **ptrp);
+ /**
+ * unmap_physmem() - undo a memory mapping
+ *
+ * This must be called after map_physmem() to undo the mapping.
+ * Some devices can use this to check what has been written into
+ * their mapped memory and perform an operations they require on it.
+ * In this way, map/unmap can be used as a sort of handshake between
+ * the emulated device and its users.
+ *
+ * @dev: Emuated device to unmap
+ * @vaddr: Mapped memory address, as passed to map_physmem()
+ * @len: Size of area mapped, as returned by map_physmem()
+ * @return 0 if OK, -ve on error
+ */
+ int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
+ unsigned long len);
+};
+
+/* Get access to a PCI device emulator's operations */
+#define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)
+
+/**
+ * sandbox_pci_get_emul() - Get the emulation device for a PCI device
+ *
+ * Searches for a suitable emulator for the given PCI bus device
+ *
+ * @bus: PCI bus to search
+ * @find_devfn: PCI device and function address (PCI_DEVFN())
+ * @emulp: Returns emulated device if found
+ * @return 0 if found, -ENODEV if not found
+ */
+int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
+ struct udevice **emulp);
+
+#endif /* CONFIG_DM_PCI */
+
+/**
+ * PCI_DEVICE - macro used to describe a specific pci device
+ * @vend: the 16 bit PCI Vendor ID
+ * @dev: the 16 bit PCI Device ID
+ *
+ * This macro is used to create a struct pci_device_id that matches a
+ * specific device. The subvendor and subdevice fields will be set to
+ * PCI_ANY_ID.
+ */
+#define PCI_DEVICE(vend, dev) \
+ .vendor = (vend), .device = (dev), \
+ .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
+
+/**
+ * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
+ * @vend: the 16 bit PCI Vendor ID
+ * @dev: the 16 bit PCI Device ID
+ * @subvend: the 16 bit PCI Subvendor ID
+ * @subdev: the 16 bit PCI Subdevice ID
+ *
+ * This macro is used to create a struct pci_device_id that matches a
+ * specific device with subsystem information.
+ */
+#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
+ .vendor = (vend), .device = (dev), \
+ .subvendor = (subvend), .subdevice = (subdev)
+
+/**
+ * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
+ * @dev_class: the class, subclass, prog-if triple for this device
+ * @dev_class_mask: the class mask for this device
+ *
+ * This macro is used to create a struct pci_device_id that matches a
+ * specific PCI class. The vendor, device, subvendor, and subdevice
+ * fields will be set to PCI_ANY_ID.
+ */
+#define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
+ .class = (dev_class), .class_mask = (dev_class_mask), \
+ .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
+ .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
+
+/**
+ * PCI_VDEVICE - macro used to describe a specific pci device in short form
+ * @vend: the vendor name
+ * @dev: the 16 bit PCI Device ID
+ *
+ * This macro is used to create a struct pci_device_id that matches a
+ * specific PCI device. The subvendor, and subdevice fields will be set
+ * to PCI_ANY_ID. The macro allows the next field to follow as the device
+ * private data.
+ */
+
+#define PCI_VDEVICE(vend, dev) \
+ .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
+ .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
+
+/**
+ * struct pci_driver_entry - Matches a driver to its pci_device_id list
+ * @driver: Driver to use
+ * @match: List of match records for this driver, terminated by {}
+ */
+struct pci_driver_entry {
+ struct driver *driver;
+ const struct pci_device_id *match;
+};
+
+#define U_BOOT_PCI_DEVICE(__name, __match) \
+ ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
+ .driver = llsym(struct driver, __name, driver), \
+ .match = __match, \
+ }
#endif /* __ASSEMBLY__ */
#endif /* _PCI_H */
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