+#define SATA_PLL_BASE (CTRL_BASE + 0x0720)
+
+struct sata_pll {
+ unsigned int pllcfg0;
+ unsigned int pllcfg1;
+ unsigned int pllcfg2;
+ unsigned int pllcfg3;
+ unsigned int pllcfg4;
+ unsigned int pllstatus;
+ unsigned int rxstatus;
+ unsigned int txstatus;
+ unsigned int testcfg;
+};
+
+#define SEL_IN_FREQ (0x1 << 31)
+#define DIGCLRZ (0x1 << 30)
+#define ENDIGLDO (0x1 << 4)
+#define APLL_CP_CURR (0x1 << 3)
+#define ENBGSC_REF (0x1 << 2)
+#define ENPLLLDO (0x1 << 1)
+#define ENPLL (0x1 << 0)
+
+#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
+#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
+#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
+#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
+ ENPLLLDO | ENPLL)
+
+#define PLL_LOCK (0x1 << 0)
+
+#define ENSATAMODE (0x1 << 31)
+#define PLLREFSEL (0x1 << 30)
+#define MDIVINT (0x4b << 18)
+#define EN_CLKAUX (0x1 << 5)
+#define EN_CLK125M (0x1 << 4)
+#define EN_CLK100M (0x1 << 3)
+#define EN_CLK50M (0x1 << 2)
+
+#define SATA_PLLCFG1 (ENSATAMODE | \
+ PLLREFSEL | \
+ MDIVINT | \
+ EN_CLKAUX | \
+ EN_CLK125M | \
+ EN_CLK100M | \
+ EN_CLK50M)
+
+#define DIGLDO_EN_CAPLESSMODE (0x1 << 22)
+#define PLLDO_EN_LDO_STABLE (0x1 << 11)
+#define PLLDO_EN_BUF_CUR (0x1 << 7)
+#define PLLDO_EN_LP (0x1 << 6)
+#define PLLDO_CTRL_TRIM_1_4V (0x10 << 1)
+
+#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \
+ PLLDO_EN_LDO_STABLE | \
+ PLLDO_EN_BUF_CUR | \
+ PLLDO_EN_LP | \
+ PLLDO_CTRL_TRIM_1_4V)