help
If you want to build TPL as well as the normal image and SPL, say Y.
+config FIT
+ bool "Support Flattened Image Tree"
+ depends on !SPL_BUILD
+ help
+ This option allows to boot the new uImage structrure,
+ Flattened Image Tree. FIT is formally a FDT, which can include
+ images of various types (kernel, FDT blob, ramdisk, etc.)
+ in a single blob. To boot this new uImage structure,
+ pass the the address of the blob to the "bootm" command.
+
+config FIT_VERBOSE
+ bool "Display verbose messages on FIT boot"
+ depends on FIT
+
+config FIT_SIGNATURE
+ bool "Enabel signature verification of FIT uImages"
+ depends on FIT
+ help
+ This option enables signature verification of FIT uImages,
+ using a hash signed and verified using RSA.
+ See doc/uImage.FIT/signature.txt for more details.
+
config SYS_EXTRA_OPTIONS
string "Extra Options (DEPRECATED)"
depends on !SPL_BUILD
libs-y += lib/
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
libs-y += $(CPUDIR)/
-ifdef SOC
-libs-y += $(CPUDIR)/$(SOC)/
-endif
libs-$(CONFIG_OF_EMBED) += dts/
libs-y += arch/$(ARCH)/lib/
libs-y += fs/
endif
ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
+# We can't do this yet due to the need for binary blobs
+# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
+
# enable combined SPL/u-boot/dtb rules for tegra
ifneq ($(CONFIG_TEGRA),)
ifeq ($(CONFIG_SPL),y)
u-boot.hex u-boot.srec: u-boot FORCE
$(call if_changed,objcopy)
-OBJCOPYFLAGS_u-boot.bin := -O binary
+OBJCOPYFLAGS_u-boot.bin := -O binary \
+ $(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec)
binary_size_check: u-boot.bin FORCE
@file_size=$(shell wc -c u-boot.bin | awk '{print $$1}') ; \
$(call if_changed,mkimage)
@dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
+# x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including
+# reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in
+# the middle.
+ifneq ($(CONFIG_X86_RESET_VECTOR),)
+rom: u-boot.rom FORCE
+
+u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \
+ $(srctree)/board/$(BOARDDIR)/mrc.bin
+ $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) u-boot.tmp
+ if [ -n "$(CONFIG_HAVE_INTEL_ME)" ]; then \
+ $(objtree)/tools/ifdtool -D \
+ $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp; \
+ $(objtree)/tools/ifdtool \
+ -i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp; \
+ fi
+ $(objtree)/tools/ifdtool -w \
+ $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp
+ $(objtree)/tools/ifdtool -w \
+ $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin \
+ u-boot.tmp
+ $(objtree)/tools/ifdtool -w \
+ $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \
+ u-boot.tmp
+ mv u-boot.tmp $@
+
+OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
+u-boot-x86-16bit.bin: u-boot FORCE
+ $(call if_changed,objcopy)
+endif
+
ifneq ($(CONFIG_SUNXI),)
OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
--pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
CONFIG_CMD_EXT4 * ext4 command support
CONFIG_CMD_FS_GENERIC * filesystem commands (e.g. load, ls)
that work for multiple fs types
+ CONFIG_CMD_FS_UUID * Look up a filesystem UUID
CONFIG_CMD_SAVEENV saveenv
CONFIG_CMD_FDC * Floppy Disk Support
CONFIG_CMD_FAT * FAT command support
Enable auto completion of commands using TAB.
- CONFIG_SYS_HUSH_PARSER
-
- Define this variable to enable the "hush" shell (from
- Busybox) as command line interpreter, thus enabling
- powerful command line syntax like
- if...then...else...fi conditionals or `&&' and '||'
- constructs ("shell scripts").
-
- If undefined, you get the old, much simpler behaviour
- with a somewhat smaller memory footprint.
-
-
CONFIG_SYS_PROMPT_HUSH_PS2
This defines the secondary prompt string, which is
bool "Support bcm28155_ap"
select CPU_V7
-config TARGET_BCM958300K
- bool "Support bcm958300k"
+config TARGET_BCMCYGNUS
+ bool "Support bcmcygnus"
select CPU_V7
-config TARGET_BCM958622HR
- bool "Support bcm958622hr"
+config TARGET_BCMNSP
+ bool "Support bcmnsp"
select CPU_V7
config ARCH_EXYNOS
source "board/bluewater/snapper9260/Kconfig"
source "board/boundary/nitrogen6x/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
-source "board/broadcom/bcm958300k/Kconfig"
-source "board/broadcom/bcm958622hr/Kconfig"
+source "board/broadcom/bcmcygnus/Kconfig"
+source "board/broadcom/bcmnsp/Kconfig"
source "board/calao/sbc35_a9g20/Kconfig"
source "board/calao/tny_a9260/Kconfig"
source "board/calao/usb_a9263/Kconfig"
extra-y = start.o
obj-y = cpu.o
+
+obj-$(CONFIG_MX31) += mx31/
+obj-$(CONFIG_MX35) += mx35/
extra-y = start.o
obj-y = cpu.o
+
+obj-$(CONFIG_BCM2835) += bcm2835/
+obj-$(CONFIG_TNETV107X) += tnetv107x/
#define BIT(x) (1 << (x))
#define MAX_PREDIV 64
-#define MAX_POSTDIV 8
+#define MAX_POSTDIV 8UL
#define MAX_MULT 512
#define MAX_DIV (MAX_PREDIV * MAX_POSTDIV)
pllctl_reg_write(data->pll, ctl, tmp);
mult = data->pll_freq / fpll;
- for (mult = max(mult, 1); mult <= MAX_MULT; mult++) {
+ for (mult = max(mult, 1UL); mult <= MAX_MULT; mult++) {
div = (fpll * mult) / data->pll_freq;
if (div < 1 || div > MAX_DIV)
continue;
obj-y = interrupts.o cpu.o
obj-$(CONFIG_TEGRA) += tegra-common/
+obj-$(CONFIG_TEGRA20) += tegra20/
+obj-$(CONFIG_TEGRA30) += tegra30/
+obj-$(CONFIG_TEGRA114) += tegra114/
+obj-$(CONFIG_TEGRA124) += tegra124/
obj-y += cpu.o
obj-$(CONFIG_USE_IRQ) += interrupts.o
+
+obj-$(if $(filter a320,$(SOC)),y) += a320/
+obj-$(CONFIG_AT91FAMILY) += at91/
+obj-$(CONFIG_EP93XX) += ep93xx/
+obj-$(CONFIG_IMX) += imx/
+obj-$(CONFIG_KS8695) += ks8695/
+obj-$(CONFIG_S3C24X0) += s3c24x0/
extra-y :=
endif
endif
+
+obj-$(CONFIG_ARMADA100) += armada100/
+obj-$(CONFIG_AT91FAMILY) += at91/
+obj-$(CONFIG_ARCH_DAVINCI) += davinci/
+obj-$(CONFIG_KIRKWOOD) += kirkwood/
+obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
+obj-$(CONFIG_MB86R0x) += mb86r0x/
+obj-$(CONFIG_MX25) += mx25/
+obj-$(CONFIG_MX27) += mx27/
+obj-$(if $(filter mxs,$(SOC)),y) += mxs/
+obj-$(CONFIG_ARCH_NOMADIK) += nomadik/
+obj-$(CONFIG_ORION5X) += orion5x/
+obj-$(CONFIG_PANTHEON) += pantheon/
+obj-$(if $(filter spear,$(SOC)),y) += spear/
+obj-$(CONFIG_ARCH_VERSATILE) += versatile/
uint32_t powered_by_linreg = 0;
int adjust_up, tmp;
- new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
+ new_brownout = DIV_ROUND_CLOSEST(new_target - new_brownout,
+ cfg->step_mV);
cur_target = readl(cfg->reg);
cur_target &= cfg->trg_mask;
ifneq (,$(filter s5pc1xx exynos,$(SOC)))
obj-y += s5p-common/
endif
+
+obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
+obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/
+obj-$(CONFIG_AT91FAMILY) += at91/
+obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
+obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
+obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
+obj-$(CONFIG_ARCH_EXYNOS) += exynos/
+obj-$(CONFIG_ARCH_HIGHBANK) += highbank/
+obj-$(CONFIG_ARCH_KEYSTONE) += keystone/
+obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
+obj-$(if $(filter mx5,$(SOC)),y) += mx5/
+obj-$(CONFIG_MX6) += mx6/
+obj-$(CONFIG_OMAP34XX) += omap3/
+obj-$(CONFIG_OMAP44XX) += omap4/
+obj-$(CONFIG_OMAP54XX) += omap5/
+obj-$(CONFIG_RMOBILE) += rmobile/
+obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
+obj-$(CONFIG_SOCFPGA) += socfpga/
+obj-$(CONFIG_ARCH_SUNXI) += sunxi/
+obj-$(CONFIG_TEGRA20) += tegra20/
+obj-$(CONFIG_U8500) += u8500/
+obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/
+obj-$(CONFIG_VF610) += vf610/
+obj-$(CONFIG_ZYNQ) += zynq/
struct refclk *refclk_str_to_clk(const char *name);
-#define U8_MAX ((u8)~0U)
-#define U32_MAX ((u32)~0U)
-#define U64_MAX ((u64)~0U)
-
/* The common clock framework uses u8 to represent a parent index */
#define PARENT_COUNT_MAX ((u32)U8_MAX)
return 1;
for (i = 1; i <= loops; i++) {
- const unsigned int effective_div = max(min(input_rate / i /
- target_rate, cap), 1);
+ const unsigned int effective_div =
+ max(min(input_rate / i / target_rate, cap), 1U);
const unsigned int effective_rate = input_rate / i /
effective_div;
const int error = target_rate - effective_rate;
}
for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
- todo = min(uboot_size - upto, (1 << 15));
+ todo = min(uboot_size - upto, (unsigned int)(1 << 15));
spi_rx_tx(regs, todo, (void *)(uboot_addr),
(void *)(SPI_FLASH_UBOOT_POS), i);
}
*/
/* calculate SR2_WTCNT_VALUE */
- sys_rate = DIV_ROUND(V_OSCK, 1000000);
- clk_cycles = DIV_ROUND(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate);
- sr2_cnt = DIV_ROUND(OMAP_ABB_SETTLING_TIME * 10, clk_cycles);
+ sys_rate = DIV_ROUND_CLOSEST(V_OSCK, 1000000);
+ clk_cycles = DIV_ROUND_CLOSEST(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate);
+ sr2_cnt = DIV_ROUND_CLOSEST(OMAP_ABB_SETTLING_TIME * 10, clk_cycles);
setbits_le32(setup,
sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1));
+++ /dev/null
-#
-# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-
-# necessary to create built-in.o
-obj- := __dummy__.o
+++ /dev/null
-#
-# (C) Copyright 2013-2014
-# NVIDIA Corporation <www.nvidia.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# necessary to create built-in.o
-obj- := __dummy__.o
writel(0, &dc->win.h_initial_dda);
writel(0, &dc->win.v_initial_dda);
- h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1);
- v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1);
+ h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
+ v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
val = h_dda << H_DDA_INC_SHIFT;
val |= v_dda << V_DDA_INC_SHIFT;
+++ /dev/null
-#
-# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-
-# necessary to create built-in.o
-obj- := __dummy__.o
obj-y += cache.o
obj-y += tlb.o
obj-y += transition.o
+
+obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
#define _ARMD1_CONFIG_H
#include <asm/arch/armada100.h>
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
/* default Dcache Line length for armada100 */
#define CONFIG_SYS_CACHELINE_SIZE 32
#define __AT91RM9200_H__
#define CONFIG_AT91FAMILY /* it's a member of AT91 family */
-#define CONFIG_ARM920T /* it's an ARM920T Core */
#define CONFIG_ARCH_CPU_INIT /* we need arch_cpu_init() for hw timers */
#define CONFIG_AT91_GPIO /* and require always gpio features */
/*
* defines to be used in other places
*/
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
/*
* defines to be used in other places
*/
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
/*
* defines to be used in other places
*/
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
/*
* defines to be used in other places
*/
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
/*
* defines to be used in other places
*/
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
#ifndef __AT91SAM9X5_H__
#define __AT91SAM9X5_H__
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 family */
/*
/*
* defines to be used in other places
*/
-#define CONFIG_ARMV7 /* ARM A5 Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
#endif /* CONFIG_KW88F6281 */
#include <asm/arch/soc.h>
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
#define CONFIG_SYS_CACHELINE_SIZE 32
/* default Dcache Line length for kirkwood */
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define _LPC32XX_CONFIG_H
/* Basic CPU architecture */
-#define CONFIG_ARM926EJS
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_NR_DRAM_BANKS_MAX 2
#include <asm/arch/pantheon.h>
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
/* default Dcache Line length for pantheon */
#define CONFIG_SYS_CACHELINE_SIZE 32
__weak void flush_cache(unsigned long start, unsigned long size)
{
-#if defined(CONFIG_ARM1136)
+#if defined(CONFIG_CPU_ARM1136)
#if !defined(CONFIG_SYS_ICACHE_OFF)
asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */
asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */
#endif
-#endif /* CONFIG_ARM1136 */
+#endif /* CONFIG_CPU_ARM1136 */
-#ifdef CONFIG_ARM926EJS
+#ifdef CONFIG_CPU_ARM926EJS
/* test and clean, page 2-23 of arm926ejs manual */
asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
/* disable write buffer as well (page 2-22) */
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-#endif /* CONFIG_ARM926EJS */
+#endif /* CONFIG_CPU_ARM926EJS */
return;
}
obj-y += interrupts.o
obj-$(CONFIG_PORTMUX_PIO) += portmux-pio.o
obj-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o
+
+obj-$(if $(filter at32ap700x,$(SOC)),y) += at32ap700x/
sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN));
rate = parent_rate;
} else {
- divider = min(255, divider / 2 - 1);
+ divider = min(255UL, divider / 2 - 1);
sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN) | SM_BIT(DIVEN)
| SM_BF(DIV, divider));
rate = parent_rate / (2 * (divider + 1));
inbound_len = emudat;
} else {
/* store the bytes */
- leftovers_len = min(4, inbound_len);
+ leftovers_len = min((size_t)4, inbound_len);
inbound_len -= leftovers_len;
leftovers = emudat;
}
*dshift = WDSIZE_P;
#endif
- *bpos = min(limit, ffs(ldst | lsrc | count)) - 1;
+ *bpos = min(limit, (unsigned long)ffs(ldst | lsrc | count)) - 1;
}
/* This version misbehaves for count values of 0 and 2^16+.
#ifdef PSIZE
/* The max memory DMA peripheral transfer size is 4 bytes. */
- dsize |= min(2, bpos) << PSIZE_P;
+ dsize |= min(2UL, bpos) << PSIZE_P;
#endif
/* Copy sram functions from sdram to sram */
extra-y = start.o
obj-y = cache.o
obj-y += cpu.o interrupts.o time.o
+
+obj-$(CONFIG_SOC_AU1X00) += au1x00/
#define readl(a) au_readl((long)(a))
#define writel(v,a) au_writel((v),(int)(a))
-#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
-
#define DEBUG
#ifdef DEBUG
#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
# SPDX-License-Identifier: GPL-2.0+
#
-# necessary to create built-in.o
-obj- := __dummy__.o
-
extra-y = start.o
+
+obj-$(if $(filter ag101,$(SOC)),y) += ag101/
+obj-$(if $(filter ag102,$(SOC)),y) += ag102/
#define readl(a) (*((volatile u32 *)(a)))
#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
-#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
-
#ifdef DEBUG
#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
#else
unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
u64 memsize = (u64)memsize_in_meg << 20;
- memsize = min(memsize, CONFIG_MAX_MEM_MAPPED);
+ memsize = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED);
memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM);
if (memsize)
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
/* If a dimm is installed in a particular slot ... */
if (dimm_populated[dimm_num] != SDRAM_NONE)
- t_wr_ns = max(t_wr_ns,
+ t_wr_ns = max(t_wr_ns, (unsigned long)
spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
}
else
sdram_ddr1 = false;
- t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
- t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
- t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
- t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
- t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
- t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
+ t_rcd_ns = max(t_rcd_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
+ t_rrd_ns = max(t_rrd_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
+ t_rp_ns = max(t_rp_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
+ t_ras_ns = max(t_ras_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 30));
+ t_rc_ns = max(t_rc_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 41));
+ t_rfc_ns = max(t_rfc_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 42));
}
}
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
/* If a dimm is installed in a particular slot ... */
if (dimm_populated[dimm_num] != SDRAM_NONE) {
- t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
- t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
- t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
+ t_wpc_ns = max(t_wtr_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
+ t_wtr_ns = max(t_wtr_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
+ t_rpc_ns = max(t_rpc_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
}
}
for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
/* If a dimm is installed in a particular slot ... */
if (dimm_populated[dimm_num] != SDRAM_NONE)
- ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
+ ecc = max(ecc,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11));
}
if (ecc == 0)
return;
#define readl(a) (*((volatile u32 *)(a)))
#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
-#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
-
#ifdef DEBUG
#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
#else
#endif
size = min(bootm_size, get_effective_memsize());
- size = min(size, CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE);
+ size = min(size, (ulong)CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE);
if (size < bootm_size) {
ulong base = bootmap_base + size;
return os_dirent_typename[OS_FILET_UNKNOWN];
}
-ssize_t os_get_filesize(const char *fname)
+int os_get_filesize(const char *fname, loff_t *size)
{
struct stat buf;
int ret;
ret = stat(fname, &buf);
if (ret)
return ret;
- return buf.st_size;
+ *size = buf.st_size;
+ return 0;
}
void os_putc(int ch)
{
struct sandbox_state *state = state_get_current();
int fd, ret;
- int size;
+ loff_t size;
- size = os_get_filesize(fname);
- if (size < 0)
- return -ENOENT;
+ ret = os_get_filesize(fname, &size);
+ if (ret < 0)
+ return ret;
if (size != state->ram_size)
return -ENOSPC;
fd = open(fname, O_RDONLY);
max_arg_len = 0;
for (i = 0; i < num_options; ++i)
- max_arg_len = max(strlen(sb_opt[i]->flag), max_arg_len);
+ max_arg_len = max((int)strlen(sb_opt[i]->flag), max_arg_len);
max_noarg_len = max_arg_len + 7;
for (i = 0; i < num_options; ++i) {
static int state_read_file(struct sandbox_state *state, const char *fname)
{
- int size;
+ loff_t size;
int ret;
int fd;
- size = os_get_filesize(fname);
- if (size < 0) {
+ ret = os_get_filesize(fname, &size);
+ if (ret < 0) {
printf("Cannot find sandbox state file '%s'\n", fname);
- return -ENOENT;
+ return ret;
}
state->state_fdt = os_malloc(size);
if (!state->state_fdt) {
config TARGET_COREBOOT
bool "Support coreboot"
+ help
+ This target is used for running U-Boot on top of Coreboot. In
+ this case Coreboot does the early inititalisation, and U-Boot
+ takes over once the RAM, video and CPU are fully running.
+ U-Boot is loaded as a fallback payload from Coreboot, in
+ Coreboot terminology. This method was used for the Chromebook
+ Pixel when launched.
+
+config TARGET_CHROMEBOOK_LINK
+ bool "Support Chromebook link"
+ help
+ This is the Chromebook Pixel released in 2013. It uses an Intel
+ i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
+ SDRAM. It has a Panther Point platform controller hub, PCIe
+ WiFi and Bluetooth. It also includes a 720p webcam, USB SD
+ reader, microphone and speakers, display port and 32GB SATA
+ solid state drive. There is a Chrome OS EC connected on LPC,
+ and it provides a 2560x1700 high resolution touch-enabled LCD
+ display.
endchoice
-source "board/chromebook-x86/coreboot/Kconfig"
+config RAMBASE
+ hex
+ default 0x100000
+
+config RAMTOP
+ hex
+ default 0x200000
+
+config XIP_ROM_SIZE
+ hex
+ default 0x10000
+
+config CPU_ADDR_BITS
+ int
+ default 36
+
+config HPET_ADDRESS
+ hex
+ default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
+
+config SMM_TSEG
+ bool
+ default n
+
+config SMM_TSEG_SIZE
+ hex
+
+config ROM_SIZE
+ hex
+ default 0x800000
+
+config HAVE_INTEL_ME
+ bool "Platform requires Intel Management Engine"
+ help
+ Newer higher-end devices have an Intel Management Engine (ME)
+ which is a very large binary blob (typically 1.5MB) which is
+ required for the platform to work. This enforces a particular
+ SPI flash format. You will need to supply the me.bin file in
+ your board directory.
+
+config X86_RAMTEST
+ bool "Perform a simple RAM test after SDRAM initialisation"
+ help
+ If there is something wrong with SDRAM then the platform will
+ often crash within U-Boot or the kernel. This option enables a
+ very simple RAM test that quickly checks whether the SDRAM seems
+ to work correctly. It is not exhaustive but can save time by
+ detecting obvious failures.
+
+source "arch/x86/cpu/ivybridge/Kconfig"
+
+source "board/coreboot/coreboot/Kconfig"
+
+source "board/google/chromebook_link/Kconfig"
endmenu
$(call cc-option, -mpreferred-stack-boundary=2)
PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86)
PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
-PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0
PLATFORM_CPPFLAGS += -march=i386 -m32
# Support generic board on x86
extra-y = start.o
obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
obj-y += interrupts.o cpu.o call64.o
+
+obj-$(CONFIG_SYS_COREBOOT) += coreboot/
+obj-$(CONFIG_PCI) += pci.o
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_SYS_COREBOOT) += car.o
-obj-$(CONFIG_SYS_COREBOOT) += coreboot.o
-obj-$(CONFIG_SYS_COREBOOT) += tables.o
-obj-$(CONFIG_SYS_COREBOOT) += ipchecksum.o
-obj-$(CONFIG_SYS_COREBOOT) += sdram.o
-obj-$(CONFIG_SYS_COREBOOT) += timestamp.o
+obj-y += car.o
+obj-y += coreboot.o
+obj-y += tables.o
+obj-y += ipchecksum.o
+obj-y += sdram.o
+obj-y += timestamp.o
obj-$(CONFIG_PCI) += pci.o
#include <ns16550.h>
#include <asm/msr.h>
#include <asm/cache.h>
+#include <asm/cpu.h>
#include <asm/io.h>
-#include <asm/arch-coreboot/tables.h>
-#include <asm/arch-coreboot/sysinfo.h>
+#include <asm/arch/tables.h>
+#include <asm/arch/sysinfo.h>
#include <asm/arch/timestamp.h>
DECLARE_GLOBAL_DATA_PTR;
-/*
- * Miscellaneous platform dependent initializations
- */
-int cpu_init_f(void)
+int arch_cpu_init(void)
{
int ret = get_coreboot_info(&lib_sysinfo);
- if (ret != 0)
+ if (ret != 0) {
printf("Failed to parse coreboot tables.\n");
+ return ret;
+ }
timestamp_init();
- return ret;
+ return x86_cpu_init_f();
}
int board_early_init_f(void)
return 0;
}
-void show_boot_progress(int val)
+int print_cpuinfo(void)
{
-#if MIN_PORT80_KCLOCKS_DELAY
- /*
- * Scale the time counter reading to avoid using 64 bit arithmetics.
- * Can't use get_timer() here becuase it could be not yet
- * initialized or even implemented.
- */
- if (!gd->arch.tsc_prev) {
- gd->arch.tsc_base_kclocks = rdtsc() / 1000;
- gd->arch.tsc_prev = 0;
- } else {
- uint32_t now;
-
- do {
- now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
- } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
- gd->arch.tsc_prev = now;
- }
-#endif
- outb(val, 0x80);
+ return default_print_cpuinfo();
}
int last_stage_init(void)
#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
-int board_final_cleanup(void)
+void board_final_cleanup(void)
{
/* Un-cache the ROM so the kernel has one
* more MTRR available.
/* Issue SMI to Coreboot to lock down ME and registers */
printf("Finalizing Coreboot\n");
outb(0xcb, 0xb2);
-
- return 0;
}
void panic_puts(const char *str)
*/
#include <compiler.h>
-#include <asm/arch-coreboot/ipchecksum.h>
+#include <asm/arch/ipchecksum.h>
unsigned short ipchksum(const void *vptr, unsigned long nbytes)
{
#include <pci.h>
#include <asm/pci.h>
-static struct pci_controller coreboot_hose;
-
static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
struct pci_config_table *table)
{
u8 secondary;
hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
- hose->last_busno = max(hose->last_busno, secondary);
+ hose->last_busno = max(hose->last_busno, (int)secondary);
pci_hose_scan_bus(hose, secondary);
}
{}
};
-void pci_init_board(void)
+void board_pci_setup_hose(struct pci_controller *hose)
{
- coreboot_hose.config_table = pci_coreboot_config_table;
- coreboot_hose.first_busno = 0;
- coreboot_hose.last_busno = 0;
-
- pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
- PCI_REGION_MEM);
- coreboot_hose.region_count = 1;
-
- pci_setup_type1(&coreboot_hose);
-
- pci_register_hose(&coreboot_hose);
+ hose->config_table = pci_coreboot_config_table;
+ hose->first_busno = 0;
+ hose->last_busno = 0;
- pci_hose_scan(&coreboot_hose);
+ pci_set_region(hose->regions + 0, 0x0, 0x0, 0xffffffff,
+ PCI_REGION_MEM);
+ hose->region_count = 1;
}
#include <asm/e820.h>
#include <asm/u-boot-x86.h>
#include <asm/global_data.h>
+#include <asm/init_helpers.h>
#include <asm/processor.h>
#include <asm/sections.h>
+#include <asm/zimage.h>
#include <asm/arch/sysinfo.h>
#include <asm/arch/tables.h>
{
int i;
- unsigned num_entries = min(lib_sysinfo.n_memranges, max_entries);
+ unsigned num_entries = min((unsigned)lib_sysinfo.n_memranges, max_entries);
if (num_entries < lib_sysinfo.n_memranges) {
printf("Warning: Limiting e820 map to %d entries.\n",
num_entries);
return (ulong)dest_addr;
}
-int dram_init_f(void)
+int dram_init(void)
{
int i;
phys_size_t ram_size = 0;
gd->ram_size = ram_size;
if (ram_size == 0)
return -1;
- return 0;
+
+ return calculate_relocation_address();
}
-int dram_init_banksize(void)
+void dram_init_banksize(void)
{
int i, j;
}
}
}
- return 0;
-}
-
-int dram_init(void)
-{
- return dram_init_banksize();
}
*/
#include <common.h>
-#include <asm/arch-coreboot/ipchecksum.h>
-#include <asm/arch-coreboot/sysinfo.h>
-#include <asm/arch-coreboot/tables.h>
+#include <asm/arch/ipchecksum.h>
+#include <asm/arch/sysinfo.h>
+#include <asm/arch/tables.h>
/*
* This needs to be in the .data section so that it's copied over during
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
+ * Part of this file is adapted from coreboot
+ * src/arch/x86/lib/cpu.c
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
#include <malloc.h>
#include <asm/control_regs.h>
#include <asm/cpu.h>
+#include <asm/post.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <asm/interrupt.h>
#include <linux/compiler.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* Constructor for a conventional segment GDT (or LDT) entry
* This is a macro so it can be used in initialisers
u32 ptr;
} __packed;
+struct cpu_device_id {
+ unsigned vendor;
+ unsigned device;
+};
+
+struct cpuinfo_x86 {
+ uint8_t x86; /* CPU family */
+ uint8_t x86_vendor; /* CPU vendor */
+ uint8_t x86_model;
+ uint8_t x86_mask;
+};
+
+/*
+ * List of cpu vendor strings along with their normalized
+ * id values.
+ */
+static struct {
+ int vendor;
+ const char *name;
+} x86_vendors[] = {
+ { X86_VENDOR_INTEL, "GenuineIntel", },
+ { X86_VENDOR_CYRIX, "CyrixInstead", },
+ { X86_VENDOR_AMD, "AuthenticAMD", },
+ { X86_VENDOR_UMC, "UMC UMC UMC ", },
+ { X86_VENDOR_NEXGEN, "NexGenDriven", },
+ { X86_VENDOR_CENTAUR, "CentaurHauls", },
+ { X86_VENDOR_RISE, "RiseRiseRise", },
+ { X86_VENDOR_TRANSMETA, "GenuineTMx86", },
+ { X86_VENDOR_TRANSMETA, "TransmetaCPU", },
+ { X86_VENDOR_NSC, "Geode by NSC", },
+ { X86_VENDOR_SIS, "SiS SiS SiS ", },
+};
+
+static const char *const x86_vendor_name[] = {
+ [X86_VENDOR_INTEL] = "Intel",
+ [X86_VENDOR_CYRIX] = "Cyrix",
+ [X86_VENDOR_AMD] = "AMD",
+ [X86_VENDOR_UMC] = "UMC",
+ [X86_VENDOR_NEXGEN] = "NexGen",
+ [X86_VENDOR_CENTAUR] = "Centaur",
+ [X86_VENDOR_RISE] = "Rise",
+ [X86_VENDOR_TRANSMETA] = "Transmeta",
+ [X86_VENDOR_NSC] = "NSC",
+ [X86_VENDOR_SIS] = "SiS",
+};
+
static void load_ds(u32 segment)
{
asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
return 0;
}
+/*
+ * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
+ * by the fact that they preserve the flags across the division of 5/2.
+ * PII and PPro exhibit this behavior too, but they have cpuid available.
+ */
+
+/*
+ * Perform the Cyrix 5/2 test. A Cyrix won't change
+ * the flags, while other 486 chips will.
+ */
+static inline int test_cyrix_52div(void)
+{
+ unsigned int test;
+
+ __asm__ __volatile__(
+ "sahf\n\t" /* clear flags (%eax = 0x0005) */
+ "div %b2\n\t" /* divide 5 by 2 */
+ "lahf" /* store flags into %ah */
+ : "=a" (test)
+ : "0" (5), "q" (2)
+ : "cc");
+
+ /* AH is 0x02 on Cyrix after the divide.. */
+ return (unsigned char) (test >> 8) == 0x02;
+}
+
+/*
+ * Detect a NexGen CPU running without BIOS hypercode new enough
+ * to have CPUID. (Thanks to Herbert Oppmann)
+ */
+
+static int deep_magic_nexgen_probe(void)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ " movw $0x5555, %%ax\n"
+ " xorw %%dx,%%dx\n"
+ " movw $2, %%cx\n"
+ " divw %%cx\n"
+ " movl $0, %%eax\n"
+ " jnz 1f\n"
+ " movl $1, %%eax\n"
+ "1:\n"
+ : "=a" (ret) : : "cx", "dx");
+ return ret;
+}
+
+static bool has_cpuid(void)
+{
+ return flag_is_changeable_p(X86_EFLAGS_ID);
+}
+
+static int build_vendor_name(char *vendor_name)
+{
+ struct cpuid_result result;
+ result = cpuid(0x00000000);
+ unsigned int *name_as_ints = (unsigned int *)vendor_name;
+
+ name_as_ints[0] = result.ebx;
+ name_as_ints[1] = result.edx;
+ name_as_ints[2] = result.ecx;
+
+ return result.eax;
+}
+
+static void identify_cpu(struct cpu_device_id *cpu)
+{
+ char vendor_name[16];
+ int i;
+
+ vendor_name[0] = '\0'; /* Unset */
+ cpu->device = 0; /* fix gcc 4.4.4 warning */
+
+ /* Find the id and vendor_name */
+ if (!has_cpuid()) {
+ /* Its a 486 if we can modify the AC flag */
+ if (flag_is_changeable_p(X86_EFLAGS_AC))
+ cpu->device = 0x00000400; /* 486 */
+ else
+ cpu->device = 0x00000300; /* 386 */
+ if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
+ memcpy(vendor_name, "CyrixInstead", 13);
+ /* If we ever care we can enable cpuid here */
+ }
+ /* Detect NexGen with old hypercode */
+ else if (deep_magic_nexgen_probe())
+ memcpy(vendor_name, "NexGenDriven", 13);
+ }
+ if (has_cpuid()) {
+ int cpuid_level;
+
+ cpuid_level = build_vendor_name(vendor_name);
+ vendor_name[12] = '\0';
+
+ /* Intel-defined flags: level 0x00000001 */
+ if (cpuid_level >= 0x00000001) {
+ cpu->device = cpuid_eax(0x00000001);
+ } else {
+ /* Have CPUID level 0 only unheard of */
+ cpu->device = 0x00000400;
+ }
+ }
+ cpu->vendor = X86_VENDOR_UNKNOWN;
+ for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
+ if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
+ cpu->vendor = x86_vendors[i].vendor;
+ break;
+ }
+ }
+}
+
+static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
+{
+ c->x86 = (tfms >> 8) & 0xf;
+ c->x86_model = (tfms >> 4) & 0xf;
+ c->x86_mask = tfms & 0xf;
+ if (c->x86 == 0xf)
+ c->x86 += (tfms >> 20) & 0xff;
+ if (c->x86 >= 0x6)
+ c->x86_model += ((tfms >> 16) & 0xF) << 4;
+}
+
int x86_cpu_init_f(void)
{
const u32 em_rst = ~X86_CR0_EM;
"movl %%eax, %%cr0\n" \
: : "i" (em_rst), "i" (mp_ne_set) : "eax");
+ /* identify CPU via cpuid and store the decoded info into gd->arch */
+ if (has_cpuid()) {
+ struct cpu_device_id cpu;
+ struct cpuinfo_x86 c;
+
+ identify_cpu(&cpu);
+ get_fms(&c, cpu.device);
+ gd->arch.x86 = c.x86;
+ gd->arch.x86_vendor = cpu.vendor;
+ gd->arch.x86_model = c.x86_model;
+ gd->arch.x86_mask = c.x86_mask;
+ gd->arch.x86_device = cpu.device;
+ }
+
return 0;
}
-int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
int x86_cpu_init_r(void)
{
"generate_gpf:\n"
"ljmp $0x70, $0x47114711\n");
-void __reset_cpu(ulong addr)
+__weak void reset_cpu(ulong addr)
{
printf("Resetting using x86 Triple Fault\n");
set_vector(13, generate_gpf); /* general protection fault handler */
set_vector(8, generate_gpf); /* double fault handler */
generate_gpf(); /* start the show */
}
-void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu")));
int dcache_status(void)
{
: "eax");
}
-static bool has_cpuid(void)
+static bool can_detect_long_mode(void)
{
- unsigned long flag;
-
- asm volatile("pushf\n" \
- "pop %%eax\n"
- "mov %%eax, %%ecx\n" /* ecx = flags */
- "xor %1, %%eax\n"
- "push %%eax\n"
- "popf\n" /* flags ^= $2 */
- "pushf\n"
- "pop %%eax\n" /* eax = flags */
- "push %%ecx\n"
- "popf\n" /* flags = ecx */
- "xor %%ecx, %%eax\n"
- "mov %%eax, %0"
- : "=r" (flag)
- : "i" (1 << 21)
- : "eax", "ecx", "memory");
+ return cpuid_eax(0x80000000) > 0x80000000UL;
+}
- return flag != 0;
+static bool has_long_mode(void)
+{
+ return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
}
-static bool can_detect_long_mode(void)
+int cpu_has_64bit(void)
{
- unsigned long flag;
+ return has_cpuid() && can_detect_long_mode() &&
+ has_long_mode();
+}
- asm volatile("mov $0x80000000, %%eax\n"
- "cpuid\n"
- "mov %%eax, %0"
- : "=r" (flag)
- :
- : "eax", "ebx", "ecx", "edx", "memory");
+const char *cpu_vendor_name(int vendor)
+{
+ const char *name;
+ name = "<invalid cpu vendor>";
+ if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
+ (x86_vendor_name[vendor] != 0))
+ name = x86_vendor_name[vendor];
- return flag > 0x80000000UL;
+ return name;
}
-static bool has_long_mode(void)
+char *cpu_get_name(char *name)
{
- unsigned long flag;
+ unsigned int *name_as_ints = (unsigned int *)name;
+ struct cpuid_result regs;
+ char *ptr;
+ int i;
- asm volatile("mov $0x80000001, %%eax\n"
- "cpuid\n"
- "mov %%edx, %0"
- : "=r" (flag)
- :
- : "eax", "ebx", "ecx", "edx", "memory");
+ /* This bit adds up to 48 bytes */
+ for (i = 0; i < 3; i++) {
+ regs = cpuid(0x80000002 + i);
+ name_as_ints[i * 4 + 0] = regs.eax;
+ name_as_ints[i * 4 + 1] = regs.ebx;
+ name_as_ints[i * 4 + 2] = regs.ecx;
+ name_as_ints[i * 4 + 3] = regs.edx;
+ }
+ name[CPU_MAX_NAME_LEN - 1] = '\0';
- return flag & (1 << 29) ? true : false;
-}
+ /* Skip leading spaces. */
+ ptr = name;
+ while (*ptr == ' ')
+ ptr++;
-int cpu_has_64bit(void)
-{
- return has_cpuid() && can_detect_long_mode() &&
- has_long_mode();
+ return ptr;
}
-int print_cpuinfo(void)
+int default_print_cpuinfo(void)
{
- printf("CPU: %s\n", cpu_has_64bit() ? "x86_64" : "x86");
+ printf("CPU: %s, vendor %s, device %xh\n",
+ cpu_has_64bit() ? "x86_64" : "x86",
+ cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
return 0;
}
return -EFAULT;
}
+
+void show_boot_progress(int val)
+{
+#if MIN_PORT80_KCLOCKS_DELAY
+ /*
+ * Scale the time counter reading to avoid using 64 bit arithmetics.
+ * Can't use get_timer() here becuase it could be not yet
+ * initialized or even implemented.
+ */
+ if (!gd->arch.tsc_prev) {
+ gd->arch.tsc_base_kclocks = rdtsc() / 1000;
+ gd->arch.tsc_prev = 0;
+ } else {
+ uint32_t now;
+
+ do {
+ now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
+ } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
+ gd->arch.tsc_prev = now;
+ }
+#endif
+ outb(val, POST_PORT);
+}
"pushl $"#x"\n" \
"jmp irq_common_entry\n"
-void dump_regs(struct irq_regs *regs)
+static void dump_regs(struct irq_regs *regs)
{
unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
unsigned long d0, d1, d2, d3, d6, d7;
--- /dev/null
+#
+# From Coreboot src/northbridge/intel/sandybridge/Kconfig
+#
+# Copyright (C) 2010 Google Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+
+config NORTHBRIDGE_INTEL_SANDYBRIDGE
+ bool
+ select CACHE_MRC_BIN
+ select CPU_INTEL_MODEL_206AX
+
+config NORTHBRIDGE_INTEL_IVYBRIDGE
+ bool
+ select CACHE_MRC_BIN
+ select CPU_INTEL_MODEL_306AX
+
+if NORTHBRIDGE_INTEL_SANDYBRIDGE
+
+config VGA_BIOS_ID
+ string
+ default "8086,0106"
+
+config CACHE_MRC_SIZE_KB
+ int
+ default 256
+
+config MRC_CACHE_BASE
+ hex
+ default 0xff800000
+
+config MRC_CACHE_LOCATION
+ hex
+ depends on !CHROMEOS
+ default 0x1ec000
+
+config MRC_CACHE_SIZE
+ hex
+ depends on !CHROMEOS
+ default 0x10000
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xff7f0000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x10000
+
+endif
+
+if NORTHBRIDGE_INTEL_IVYBRIDGE
+
+config VGA_BIOS_ID
+ string
+ default "8086,0166"
+
+config EXTERNAL_MRC_BLOB
+ bool
+ default n
+
+config CACHE_MRC_SIZE_KB
+ int
+ default 512
+
+config MRC_CACHE_BASE
+ hex
+ default 0xff800000
+
+config MRC_CACHE_LOCATION
+ hex
+ depends on !CHROMEOS
+ default 0x370000
+
+config MRC_CACHE_SIZE
+ hex
+ depends on !CHROMEOS
+ default 0x10000
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xff7e0000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x20000
+
+endif
+
+if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE
+
+config HAVE_MRC
+ bool "Add a System Agent binary"
+ help
+ Select this option to add a System Agent binary to
+ the resulting U-Boot image. MRC stands for Memory Reference Code.
+ It is a binary blob which U-Boot uses to set up SDRAM.
+
+ Note: Without this binary U-Boot will not be able to set up its
+ SDRAM so will not boot.
+
+config DCACHE_RAM_MRC_VAR_SIZE
+ hex
+ default 0x4000
+ help
+ This is the amount of CAR (Cache as RAM) reserved for use by the
+ memory reference code. This should be set to 16KB (0x4000 hex)
+ so that MRC has enough space to run.
+
+config MRC_FILE
+ string "Intel System Agent path and filename"
+ depends on HAVE_MRC
+ default "systemagent-ivybridge.bin" if NORTHBRIDGE_INTEL_IVYBRIDGE
+ default "systemagent-sandybridge.bin" if NORTHBRIDGE_INTEL_SANDYBRIDGE
+ help
+ The path and filename of the file to use as System Agent
+ binary.
+
+config CPU_SPECIFIC_OPTIONS
+ def_bool y
+ select SMM_TSEG
+ select ARCH_BOOTBLOCK_X86_32
+ select ARCH_ROMSTAGE_X86_32
+ select ARCH_RAMSTAGE_X86_32
+ select SMP
+ select SSE2
+ select UDELAY_LAPIC
+ select CPU_MICROCODE_IN_CBFS
+ select TSC_SYNC_MFENCE
+ select HAVE_INTEL_ME
+ select X86_RAMTEST
+
+config SMM_TSEG_SIZE
+ hex
+ default 0x800000
+
+config ENABLE_VMX
+ bool "Enable VMX for virtualization"
+ default n
+ help
+ Virtual Machine Extensions are provided in many x86 CPUs. These
+ provide various facilities for allowing a host OS to provide an
+ environment where potentially several guest OSes have only
+ limited access to the underlying hardware. This is achieved
+ without resorting to software trapping and/or instruction set
+ emulation (which would be very slow).
+
+ Intel's implementation of this is called VT-x. This option enables
+ VT-x this so that the OS that is booted by U-Boot can make use of
+ these facilities. If this option is not enabled, then the host OS
+ will be unable to support virtualisation, or it will run very
+ slowly.
+
+endif
+
+config CPU_INTEL_SOCKET_RPGA989
+ bool
+
+if CPU_INTEL_SOCKET_RPGA989
+
+config SOCKET_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select MMX
+ select SSE
+ select CACHE_AS_RAM
+
+config CACHE_MRC_BIN
+ bool
+ default n
+
+endif
--- /dev/null
+#
+# Copyright (c) 2014 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += car.o
+obj-y += cpu.o
+obj-y += early_init.o
+obj-y += early_me.o
+obj-y += lpc.o
+obj-y += me_status.o
+obj-y += microcode_intel.o
+obj-y += pci.o
+obj-y += report_platform.o
+obj-y += sdram.o
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/mtrr.h>
+#include <asm/post.h>
+#include <asm/processor-flags.h>
+
+#define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
+#define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
+
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+
+/* Cache 4GB - MRC_SIZE_KB for MRC */
+#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
+#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)
+#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
+
+#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
+
+#define NOEVICTMOD_MSR 0x2e0
+
+ /*
+ * Note: ebp must not be touched in this code as it holds the BIST
+ * value (built-in self test). We preserve this value until it can
+ * be written to global_data when CAR is ready for use.
+ */
+.globl car_init
+car_init:
+ post_code(POST_CAR_START)
+
+ /* Send INIT IPI to all excluding ourself */
+ movl $0x000C4500, %eax
+ movl $0xFEE00300, %esi
+ movl %eax, (%esi)
+
+ post_code(POST_CAR_SIPI)
+ /* Zero out all fixed range and variable range MTRRs */
+ movl $mtrr_table, %esi
+ movl $((mtrr_table_end - mtrr_table) / 2), %edi
+ xorl %eax, %eax
+ xorl %edx, %edx
+clear_mtrrs:
+ movw (%esi), %bx
+ movzx %bx, %ecx
+ wrmsr
+ add $2, %esi
+ dec %edi
+ jnz clear_mtrrs
+
+ post_code(POST_CAR_MTRR)
+ /* Configure the default memory type to uncacheable */
+ movl $MTRRdefType_MSR, %ecx
+ rdmsr
+ andl $(~0x00000cff), %eax
+ wrmsr
+
+ post_code(POST_CAR_UNCACHEABLE)
+ /* Set Cache-as-RAM base address */
+ movl $(MTRR_PHYS_BASE_MSR(0)), %ecx
+ movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
+ xorl %edx, %edx
+ wrmsr
+
+ post_code(POST_CAR_BASE_ADDRESS)
+ /* Set Cache-as-RAM mask */
+ movl $(MTRR_PHYS_MASK_MSR(0)), %ecx
+ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $CPU_PHYSMASK_HI, %edx
+ wrmsr
+
+ post_code(POST_CAR_MASK)
+
+ /* Enable MTRR */
+ movl $MTRRdefType_MSR, %ecx
+ rdmsr
+ orl $MTRRdefTypeEn, %eax
+ wrmsr
+
+ /* Enable cache (CR0.CD = 0, CR0.NW = 0) */
+ movl %cr0, %eax
+ andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax
+ invd
+ movl %eax, %cr0
+
+ /* enable the 'no eviction' mode */
+ movl $NOEVICTMOD_MSR, %ecx
+ rdmsr
+ orl $1, %eax
+ andl $~2, %eax
+ wrmsr
+
+ /* Clear the cache memory region. This will also fill up the cache */
+ movl $CACHE_AS_RAM_BASE, %esi
+ movl %esi, %edi
+ movl $(CACHE_AS_RAM_SIZE / 4), %ecx
+ xorl %eax, %eax
+ rep stosl
+
+ /* enable the 'no eviction run' state */
+ movl $NOEVICTMOD_MSR, %ecx
+ rdmsr
+ orl $3, %eax
+ wrmsr
+
+ post_code(POST_CAR_FILL)
+ /* Enable Cache-as-RAM mode by disabling cache */
+ movl %cr0, %eax
+ orl $X86_CR0_CD, %eax
+ movl %eax, %cr0
+
+ /* Enable cache for our code in Flash because we do XIP here */
+ movl $MTRR_PHYS_BASE_MSR(1), %ecx
+ xorl %edx, %edx
+ movl $car_init_ret, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+ orl $MTRR_TYPE_WRPROT, %eax
+ wrmsr
+
+ movl $MTRR_PHYS_MASK_MSR(1), %ecx
+ movl $CPU_PHYSMASK_HI, %edx
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ wrmsr
+
+ post_code(POST_CAR_ROM_CACHE)
+#ifdef CONFIG_CACHE_MRC_BIN
+ /* Enable caching for ram init code to run faster */
+ movl $MTRR_PHYS_BASE_MSR(2), %ecx
+ movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
+ xorl %edx, %edx
+ wrmsr
+ movl $MTRR_PHYS_MASK_MSR(2), %ecx
+ movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
+ movl $CPU_PHYSMASK_HI, %edx
+ wrmsr
+#endif
+
+ post_code(POST_CAR_MRC_CACHE)
+ /* Enable cache */
+ movl %cr0, %eax
+ andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax
+ movl %eax, %cr0
+
+ post_code(POST_CAR_CPU_CACHE)
+
+ /* All CPUs need to be in Wait for SIPI state */
+wait_for_sipi:
+ movl (%esi), %eax
+ bt $12, %eax
+ jc wait_for_sipi
+
+ /* return */
+ jmp car_init_ret
+
+mtrr_table:
+ /* Fixed MTRRs */
+ .word 0x250, 0x258, 0x259
+ .word 0x268, 0x269, 0x26A
+ .word 0x26B, 0x26C, 0x26D
+ .word 0x26E, 0x26F
+ /* Variable MTRRs */
+ .word 0x200, 0x201, 0x202, 0x203
+ .word 0x204, 0x205, 0x206, 0x207
+ .word 0x208, 0x209, 0x20A, 0x20B
+ .word 0x20C, 0x20D, 0x20E, 0x20F
+ .word 0x210, 0x211, 0x212, 0x213
+mtrr_table_end:
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * Some portions from coreboot src/mainboard/google/link/romstage.c
+ * and src/cpu/intel/model_206ax/bootblock.c
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <asm/cpu.h>
+#include <asm/io.h>
+#include <asm/lapic.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
+#include <asm/pci.h>
+#include <asm/post.h>
+#include <asm/processor.h>
+#include <asm/arch/model_206ax.h>
+#include <asm/arch/microcode.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/sandybridge.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev)
+{
+ /* Enable port 80 POST on LPC */
+ pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
+ clrbits_le32(RCB_REG(GCS), 4);
+}
+
+/*
+ * Enable Prefetching and Caching.
+ */
+static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev)
+{
+ u8 reg8;
+
+ pci_hose_read_config_byte(hose, dev, 0xdc, ®8);
+ reg8 &= ~(3 << 2);
+ reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+ pci_hose_write_config_byte(hose, dev, 0xdc, reg8);
+}
+
+static void set_var_mtrr(
+ unsigned reg, unsigned base, unsigned size, unsigned type)
+
+{
+ /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+ /* FIXME: It only support 4G less range */
+ wrmsr(MTRRphysBase_MSR(reg), base | type, 0);
+ wrmsr(MTRRphysMask_MSR(reg), ~(size - 1) | MTRRphysMaskValid,
+ (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1);
+}
+
+static void enable_rom_caching(void)
+{
+ disable_caches();
+ set_var_mtrr(1, 0xffc00000, 4 << 20, MTRR_TYPE_WRPROT);
+ enable_caches();
+
+ /* Enable Variable MTRRs */
+ wrmsr(MTRRdefType_MSR, 0x800, 0);
+}
+
+static int set_flex_ratio_to_tdp_nominal(void)
+{
+ msr_t flex_ratio, msr;
+ u8 nominal_ratio;
+
+ /* Minimum CPU revision for configurable TDP support */
+ if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
+ return -EINVAL;
+
+ /* Check for Flex Ratio support */
+ flex_ratio = msr_read(MSR_FLEX_RATIO);
+ if (!(flex_ratio.lo & FLEX_RATIO_EN))
+ return -EINVAL;
+
+ /* Check for >0 configurable TDPs */
+ msr = msr_read(MSR_PLATFORM_INFO);
+ if (((msr.hi >> 1) & 3) == 0)
+ return -EINVAL;
+
+ /* Use nominal TDP ratio for flex ratio */
+ msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+ nominal_ratio = msr.lo & 0xff;
+
+ /* See if flex ratio is already set to nominal TDP ratio */
+ if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
+ return 0;
+
+ /* Set flex ratio to nominal TDP ratio */
+ flex_ratio.lo &= ~0xff00;
+ flex_ratio.lo |= nominal_ratio << 8;
+ flex_ratio.lo |= FLEX_RATIO_LOCK;
+ msr_write(MSR_FLEX_RATIO, flex_ratio);
+
+ /* Set flex ratio in soft reset data register bits 11:6 */
+ clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
+ (nominal_ratio & 0x3f) << 6);
+
+ /* Set soft reset control to use register value */
+ setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
+
+ /* Issue warm reset, will be "CPU only" due to soft reset data */
+ outb(0x0, PORT_RESET);
+ outb(0x6, PORT_RESET);
+ cpu_hlt();
+
+ /* Not reached */
+ return -EINVAL;
+}
+
+static void set_spi_speed(void)
+{
+ u32 fdod;
+
+ /* Observe SPI Descriptor Component Section 0 */
+ writel(0x1000, RCB_REG(SPI_DESC_COMP0));
+
+ /* Extract the1 Write/Erase SPI Frequency from descriptor */
+ fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));
+ fdod >>= 24;
+ fdod &= 7;
+
+ /* Set Software Sequence frequency to match */
+ clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
+}
+
+int arch_cpu_init(void)
+{
+ const void *blob = gd->fdt_blob;
+ struct pci_controller *hose;
+ int node;
+ int ret;
+
+ post_code(POST_CPU_INIT);
+ timer_set_base(rdtsc());
+
+ ret = x86_cpu_init_f();
+ if (ret)
+ return ret;
+
+ ret = pci_early_init_hose(&hose);
+ if (ret)
+ return ret;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
+ if (node < 0)
+ return -ENOENT;
+ ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV);
+ if (ret)
+ return ret;
+
+ enable_spi_prefetch(hose, PCH_LPC_DEV);
+
+ /* This is already done in start.S, but let's do it in C */
+ enable_port80_on_lpc(hose, PCH_LPC_DEV);
+
+ /* already done in car.S */
+ if (false)
+ enable_rom_caching();
+
+ set_spi_speed();
+
+ /*
+ * We should do as little as possible before the serial console is
+ * up. Perhaps this should move to later. Our next lot of init
+ * happens in print_cpuinfo() when we have a console
+ */
+ ret = set_flex_ratio_to_tdp_nominal();
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int enable_smbus(void)
+{
+ pci_dev_t dev;
+ uint16_t value;
+
+ /* Set the SMBus device statically. */
+ dev = PCI_BDF(0x0, 0x1f, 0x3);
+
+ /* Check to make sure we've got the right device. */
+ value = pci_read_config16(dev, 0x0);
+ if (value != 0x8086) {
+ printf("SMBus controller not found\n");
+ return -ENOSYS;
+ }
+
+ /* Set SMBus I/O base. */
+ pci_write_config32(dev, SMB_BASE,
+ SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+
+ /* Set SMBus enable. */
+ pci_write_config8(dev, HOSTC, HST_EN);
+
+ /* Set SMBus I/O space enable. */
+ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
+
+ /* Disable interrupt generation. */
+ outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+
+ /* Clear any lingering errors, so transactions can run. */
+ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+ debug("SMBus controller enabled\n");
+
+ return 0;
+}
+
+#define PCH_EHCI0_TEMP_BAR0 0xe8000000
+#define PCH_EHCI1_TEMP_BAR0 0xe8000400
+#define PCH_XHCI_TEMP_BAR0 0xe8001000
+
+/*
+ * Setup USB controller MMIO BAR to prevent the reference code from
+ * resetting the controller.
+ *
+ * The BAR will be re-assigned during device enumeration so these are only
+ * temporary.
+ *
+ * This is used to speed up the resume path.
+ */
+static void enable_usb_bar(void)
+{
+ pci_dev_t usb0 = PCH_EHCI1_DEV;
+ pci_dev_t usb1 = PCH_EHCI2_DEV;
+ pci_dev_t usb3 = PCH_XHCI_DEV;
+ u32 cmd;
+
+ /* USB Controller 1 */
+ pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
+ PCH_EHCI0_TEMP_BAR0);
+ cmd = pci_read_config32(usb0, PCI_COMMAND);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config32(usb0, PCI_COMMAND, cmd);
+
+ /* USB Controller 1 */
+ pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
+ PCH_EHCI1_TEMP_BAR0);
+ cmd = pci_read_config32(usb1, PCI_COMMAND);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config32(usb1, PCI_COMMAND, cmd);
+
+ /* USB3 Controller */
+ pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
+ PCH_XHCI_TEMP_BAR0);
+ cmd = pci_read_config32(usb3, PCI_COMMAND);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config32(usb3, PCI_COMMAND, cmd);
+}
+
+static int report_bist_failure(void)
+{
+ if (gd->arch.bist != 0) {
+ printf("BIST failed: %08x\n", gd->arch.bist);
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
+ char processor_name[CPU_MAX_NAME_LEN];
+ const char *name;
+ uint32_t pm1_cnt;
+ uint16_t pm1_sts;
+ int ret;
+
+ /* Halt if there was a built in self test failure */
+ ret = report_bist_failure();
+ if (ret)
+ return ret;
+
+ enable_lapic();
+
+ ret = microcode_update_intel();
+ if (ret && ret != -ENOENT && ret != -EEXIST)
+ return ret;
+
+ /* Enable upper 128bytes of CMOS */
+ writel(1 << 2, RCB_REG(RC));
+
+ /* TODO: cmos_post_init() */
+ if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) {
+ debug("soft reset detected\n");
+ boot_mode = PEI_BOOT_SOFT_RESET;
+
+ /* System is not happy after keyboard reset... */
+ debug("Issuing CF9 warm reset\n");
+ outb(0x6, 0xcf9);
+ cpu_hlt();
+ }
+
+ /* Early chipset init required before RAM init can work */
+ sandybridge_early_init(SANDYBRIDGE_MOBILE);
+
+ /* Check PM1_STS[15] to see if we are waking from Sx */
+ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+ /* Read PM1_CNT[12:10] to determine which Sx state */
+ pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+ if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+ debug("Resume from S3 detected.\n");
+ boot_mode = PEI_BOOT_RESUME;
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
+#else
+ debug("Resume from S3 detected, but disabled.\n");
+#endif
+ } else {
+ /*
+ * TODO: An indication of life might be possible here (e.g.
+ * keyboard light)
+ */
+ }
+ post_code(POST_EARLY_INIT);
+
+ /* Enable SPD ROMs and DDR-III DRAM */
+ ret = enable_smbus();
+ if (ret)
+ return ret;
+
+ /* Prepare USB controller early in S3 resume */
+ if (boot_mode == PEI_BOOT_RESUME)
+ enable_usb_bar();
+
+ gd->arch.pei_boot_mode = boot_mode;
+
+ /* TODO: Move this to the board or driver */
+ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
+ pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+
+ /* Print processor name */
+ name = cpu_get_name(processor_name);
+ printf("CPU: %s\n", name);
+
+ post_code(POST_CPU_INFO);
+
+ return 0;
+}
--- /dev/null
+/*
+ * From Coreboot
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 Google Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/sandybridge.h>
+
+static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev)
+{
+ /* Setting up Southbridge. In the northbridge code. */
+ debug("Setting up static southbridge registers\n");
+ pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
+
+ pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1);
+ pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
+
+ debug("Disabling watchdog reboot\n");
+ setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
+ outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
+
+ /* Set up all hardcoded northbridge BARs */
+ debug("Setting up static registers\n");
+ pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1);
+ pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
+ pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1);
+ pci_write_config32(pch_dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32);
+ /* 64MB - busses 0-63 */
+ pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
+ pci_write_config32(pch_dev, PCIEXBAR + 4,
+ (0LL + DEFAULT_PCIEXBAR) >> 32);
+ pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1);
+ pci_write_config32(pch_dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
+
+ /* Set C0000-FFFFF to access RAM on both reads and writes */
+ pci_write_config8(pch_dev, PAM0, 0x30);
+ pci_write_config8(pch_dev, PAM1, 0x33);
+ pci_write_config8(pch_dev, PAM2, 0x33);
+ pci_write_config8(pch_dev, PAM3, 0x33);
+ pci_write_config8(pch_dev, PAM4, 0x33);
+ pci_write_config8(pch_dev, PAM5, 0x33);
+ pci_write_config8(pch_dev, PAM6, 0x33);
+}
+
+static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
+{
+ u32 reg32;
+ u16 reg16;
+ u8 reg8;
+
+ reg16 = pci_read_config16(video_dev, PCI_DEVICE_ID);
+ switch (reg16) {
+ case 0x0102: /* GT1 Desktop */
+ case 0x0106: /* GT1 Mobile */
+ case 0x010a: /* GT1 Server */
+ case 0x0112: /* GT2 Desktop */
+ case 0x0116: /* GT2 Mobile */
+ case 0x0122: /* GT2 Desktop >=1.3GHz */
+ case 0x0126: /* GT2 Mobile >=1.3GHz */
+ case 0x0156: /* IvyBridge */
+ case 0x0166: /* IvyBridge */
+ break;
+ default:
+ debug("Graphics not supported by this CPU/chipset\n");
+ return;
+ }
+
+ debug("Initialising Graphics\n");
+
+ /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
+ reg16 = pci_read_config16(pch_dev, GGC);
+ reg16 &= ~0x00f8;
+ reg16 |= 1 << 3;
+ /* Program GTT memory by setting GGC[9:8] = 2MB */
+ reg16 &= ~0x0300;
+ reg16 |= 2 << 8;
+ /* Enable VGA decode */
+ reg16 &= ~0x0002;
+ pci_write_config16(pch_dev, GGC, reg16);
+
+ /* Enable 256MB aperture */
+ reg8 = pci_read_config8(video_dev, MSAC);
+ reg8 &= ~0x06;
+ reg8 |= 0x02;
+ pci_write_config8(video_dev, MSAC, reg8);
+
+ /* Erratum workarounds */
+ reg32 = readl(MCHBAR_REG(0x5f00));
+ reg32 |= (1 << 9) | (1 << 10);
+ writel(reg32, MCHBAR_REG(0x5f00));
+
+ /* Enable SA Clock Gating */
+ reg32 = readl(MCHBAR_REG(0x5f00));
+ writel(reg32 | 1, MCHBAR_REG(0x5f00));
+
+ /* GPU RC6 workaround for sighting 366252 */
+ reg32 = readl(MCHBAR_REG(0x5d14));
+ reg32 |= (1 << 31);
+ writel(reg32, MCHBAR_REG(0x5d14));
+
+ /* VLW */
+ reg32 = readl(MCHBAR_REG(0x6120));
+ reg32 &= ~(1 << 0);
+ writel(reg32, MCHBAR_REG(0x6120));
+
+ reg32 = readl(MCHBAR_REG(0x5418));
+ reg32 |= (1 << 4) | (1 << 5);
+ writel(reg32, MCHBAR_REG(0x5418));
+}
+
+void sandybridge_early_init(int chipset_type)
+{
+ pci_dev_t pch_dev = PCH_DEV;
+ pci_dev_t video_dev = PCH_VIDEO_DEV;
+ pci_dev_t lpc_dev = PCH_LPC_DEV;
+ u32 capid0_a;
+ u8 reg8;
+
+ /* Device ID Override Enable should be done very early */
+ capid0_a = pci_read_config32(pch_dev, 0xe4);
+ if (capid0_a & (1 << 10)) {
+ reg8 = pci_read_config8(pch_dev, 0xf3);
+ reg8 &= ~7; /* Clear 2:0 */
+
+ if (chipset_type == SANDYBRIDGE_MOBILE)
+ reg8 |= 1; /* Set bit 0 */
+
+ pci_write_config8(pch_dev, 0xf3, reg8);
+ }
+
+ /* Setup all BARs required for early PCIe and raminit */
+ sandybridge_setup_bars(pch_dev, lpc_dev);
+
+ /* Device Enable */
+ pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
+
+ sandybridge_setup_graphics(pch_dev, video_dev);
+}
--- /dev/null
+/*
+ * From Coreboot src/southbridge/intel/bd82x6x/early_me.c
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/pci.h>
+#include <asm/processor.h>
+#include <asm/arch/me.h>
+#include <asm/arch/pch.h>
+#include <asm/io.h>
+
+static const char *const me_ack_values[] = {
+ [ME_HFS_ACK_NO_DID] = "No DID Ack received",
+ [ME_HFS_ACK_RESET] = "Non-power cycle reset",
+ [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset",
+ [ME_HFS_ACK_S3] = "Go to S3",
+ [ME_HFS_ACK_S4] = "Go to S4",
+ [ME_HFS_ACK_S5] = "Go to S5",
+ [ME_HFS_ACK_GBL_RESET] = "Global Reset",
+ [ME_HFS_ACK_CONTINUE] = "Continue to boot"
+};
+
+static inline void pci_read_dword_ptr(void *ptr, int offset)
+{
+ u32 dword;
+
+ dword = pci_read_config32(PCH_ME_DEV, offset);
+ memcpy(ptr, &dword, sizeof(dword));
+}
+
+static inline void pci_write_dword_ptr(void *ptr, int offset)
+{
+ u32 dword = 0;
+ memcpy(&dword, ptr, sizeof(dword));
+ pci_write_config32(PCH_ME_DEV, offset, dword);
+}
+
+void intel_early_me_status(void)
+{
+ struct me_hfs hfs;
+ struct me_gmes gmes;
+
+ pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+ pci_read_dword_ptr(&gmes, PCI_ME_GMES);
+
+ intel_me_status(&hfs, &gmes);
+}
+
+int intel_early_me_init(void)
+{
+ int count;
+ struct me_uma uma;
+ struct me_hfs hfs;
+
+ debug("Intel ME early init\n");
+
+ /* Wait for ME UMA SIZE VALID bit to be set */
+ for (count = ME_RETRY; count > 0; --count) {
+ pci_read_dword_ptr(&uma, PCI_ME_UMA);
+ if (uma.valid)
+ break;
+ udelay(ME_DELAY);
+ }
+ if (!count) {
+ printf("ERROR: ME is not ready!\n");
+ return -EBUSY;
+ }
+
+ /* Check for valid firmware */
+ pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+ if (hfs.fpt_bad) {
+ printf("WARNING: ME has bad firmware\n");
+ return -EBADF;
+ }
+
+ debug("Intel ME firmware is ready\n");
+
+ return 0;
+}
+
+int intel_early_me_uma_size(void)
+{
+ struct me_uma uma;
+
+ pci_read_dword_ptr(&uma, PCI_ME_UMA);
+ if (uma.valid) {
+ debug("ME: Requested %uMB UMA\n", uma.size);
+ return uma.size;
+ }
+
+ debug("ME: Invalid UMA size\n");
+ return -EINVAL;
+}
+
+static inline void set_global_reset(int enable)
+{
+ u32 etr3;
+
+ etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
+
+ /* Clear CF9 Without Resume Well Reset Enable */
+ etr3 &= ~ETR3_CWORWRE;
+
+ /* CF9GR indicates a Global Reset */
+ if (enable)
+ etr3 |= ETR3_CF9GR;
+ else
+ etr3 &= ~ETR3_CF9GR;
+
+ pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
+}
+
+int intel_early_me_init_done(u8 status)
+{
+ u8 reset;
+ int count;
+ u32 mebase_l, mebase_h;
+ struct me_hfs hfs;
+ struct me_did did = {
+ .init_done = ME_INIT_DONE,
+ .status = status
+ };
+
+ /* MEBASE from MESEG_BASE[35:20] */
+ mebase_l = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L);
+ mebase_h = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H);
+ mebase_h &= 0xf;
+ did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
+
+ /* Send message to ME */
+ debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n",
+ status, did.uma_base);
+
+ pci_write_dword_ptr(&did, PCI_ME_H_GS);
+
+ /* Must wait for ME acknowledgement */
+ for (count = ME_RETRY; count > 0; --count) {
+ pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+ if (hfs.bios_msg_ack)
+ break;
+ udelay(ME_DELAY);
+ }
+ if (!count) {
+ printf("ERROR: ME failed to respond\n");
+ return -1;
+ }
+
+ /* Return the requested BIOS action */
+ debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
+
+ /* Check status after acknowledgement */
+ intel_early_me_status();
+
+ reset = 0;
+ switch (hfs.ack_data) {
+ case ME_HFS_ACK_CONTINUE:
+ /* Continue to boot */
+ return 0;
+ case ME_HFS_ACK_RESET:
+ /* Non-power cycle reset */
+ set_global_reset(0);
+ reset = 0x06;
+ break;
+ case ME_HFS_ACK_PWR_CYCLE:
+ /* Power cycle reset */
+ set_global_reset(0);
+ reset = 0x0e;
+ break;
+ case ME_HFS_ACK_GBL_RESET:
+ /* Global reset */
+ set_global_reset(1);
+ reset = 0x0e;
+ break;
+ case ME_HFS_ACK_S3:
+ case ME_HFS_ACK_S4:
+ case ME_HFS_ACK_S5:
+ break;
+ }
+
+ /* Perform the requested reset */
+ if (reset) {
+ outb(reset, 0xcf9);
+ cpu_hlt();
+ }
+ return -1;
+}
--- /dev/null
+/*
+ * From coreboot southbridge/intel/bd82x6x/lpc.c
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <pci.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+int lpc_early_init(const void *blob, int node, pci_dev_t dev)
+{
+ struct reg_info {
+ u32 base;
+ u32 size;
+ } values[4], *ptr;
+ int count;
+ int i;
+
+ count = fdtdec_get_int_array_count(blob, node, "gen-dec",
+ (u32 *)values, sizeof(values) / sizeof(u32));
+ if (count < 0)
+ return -EINVAL;
+
+ /* Set COM1/COM2 decode range */
+ pci_write_config16(dev, LPC_IO_DEC, 0x0010);
+
+ /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
+ pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+ GAMEL_LPC_EN | COMA_LPC_EN);
+
+ /* Write all registers but use 0 if we run out of data */
+ count = count * sizeof(u32) / sizeof(values[0]);
+ for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
+ u32 reg = 0;
+
+ if (i < count)
+ reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
+ pci_write_config32(dev, LPC_GENX_DEC(i), reg);
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * From Coreboot src/southbridge/intel/bd82x6x/me_status.c
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/arch/me.h>
+
+/* HFS1[3:0] Current Working State Values */
+static const char *const me_cws_values[] = {
+ [ME_HFS_CWS_RESET] = "Reset",
+ [ME_HFS_CWS_INIT] = "Initializing",
+ [ME_HFS_CWS_REC] = "Recovery",
+ [ME_HFS_CWS_NORMAL] = "Normal",
+ [ME_HFS_CWS_WAIT] = "Platform Disable Wait",
+ [ME_HFS_CWS_TRANS] = "OP State Transition",
+ [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In"
+};
+
+/* HFS1[8:6] Current Operation State Values */
+static const char *const me_opstate_values[] = {
+ [ME_HFS_STATE_PREBOOT] = "Preboot",
+ [ME_HFS_STATE_M0_UMA] = "M0 with UMA",
+ [ME_HFS_STATE_M3] = "M3 without UMA",
+ [ME_HFS_STATE_M0] = "M0 without UMA",
+ [ME_HFS_STATE_BRINGUP] = "Bring up",
+ [ME_HFS_STATE_ERROR] = "M0 without UMA but with error"
+};
+
+/* HFS[19:16] Current Operation Mode Values */
+static const char *const me_opmode_values[] = {
+ [ME_HFS_MODE_NORMAL] = "Normal",
+ [ME_HFS_MODE_DEBUG] = "Debug",
+ [ME_HFS_MODE_DIS] = "Soft Temporary Disable",
+ [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper",
+ [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message"
+};
+
+/* HFS[15:12] Error Code Values */
+static const char *const me_error_values[] = {
+ [ME_HFS_ERROR_NONE] = "No Error",
+ [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure",
+ [ME_HFS_ERROR_IMAGE] = "Image Failure",
+ [ME_HFS_ERROR_DEBUG] = "Debug Failure"
+};
+
+/* GMES[31:28] ME Progress Code */
+static const char *const me_progress_values[] = {
+ [ME_GMES_PHASE_ROM] = "ROM Phase",
+ [ME_GMES_PHASE_BUP] = "BUP Phase",
+ [ME_GMES_PHASE_UKERNEL] = "uKernel Phase",
+ [ME_GMES_PHASE_POLICY] = "Policy Module",
+ [ME_GMES_PHASE_MODULE] = "Module Loading",
+ [ME_GMES_PHASE_UNKNOWN] = "Unknown",
+ [ME_GMES_PHASE_HOST] = "Host Communication"
+};
+
+/* GMES[27:24] Power Management Event */
+static const char *const me_pmevent_values[] = {
+ [0x00] = "Clean Moff->Mx wake",
+ [0x01] = "Moff->Mx wake after an error",
+ [0x02] = "Clean global reset",
+ [0x03] = "Global reset after an error",
+ [0x04] = "Clean Intel ME reset",
+ [0x05] = "Intel ME reset due to exception",
+ [0x06] = "Pseudo-global reset",
+ [0x07] = "S0/M0->Sx/M3",
+ [0x08] = "Sx/M3->S0/M0",
+ [0x09] = "Non-power cycle reset",
+ [0x0a] = "Power cycle reset through M3",
+ [0x0b] = "Power cycle reset through Moff",
+ [0x0c] = "Sx/Mx->Sx/Moff"
+};
+
+/* Progress Code 0 states */
+static const char *const me_progress_rom_values[] = {
+ [0x00] = "BEGIN",
+ [0x06] = "DISABLE"
+};
+
+/* Progress Code 1 states */
+static const char *const me_progress_bup_values[] = {
+ [0x00] = "Initialization starts",
+ [0x01] = "Disable the host wake event",
+ [0x04] = "Flow determination start process",
+ [0x08] = "Error reading/matching the VSCC table in the descriptor",
+ [0x0a] = "Check to see if straps say ME DISABLED",
+ [0x0b] = "Timeout waiting for PWROK",
+ [0x0d] = "Possibly handle BUP manufacturing override strap",
+ [0x11] = "Bringup in M3",
+ [0x12] = "Bringup in M0",
+ [0x13] = "Flow detection error",
+ [0x15] = "M3 clock switching error",
+ [0x18] = "M3 kernel load",
+ [0x1c] = "T34 missing - cannot program ICC",
+ [0x1f] = "Waiting for DID BIOS message",
+ [0x20] = "Waiting for DID BIOS message failure",
+ [0x21] = "DID reported an error",
+ [0x22] = "Enabling UMA",
+ [0x23] = "Enabling UMA error",
+ [0x24] = "Sending DID Ack to BIOS",
+ [0x25] = "Sending DID Ack to BIOS error",
+ [0x26] = "Switching clocks in M0",
+ [0x27] = "Switching clocks in M0 error",
+ [0x28] = "ME in temp disable",
+ [0x32] = "M0 kernel load",
+};
+
+/* Progress Code 3 states */
+static const char *const me_progress_policy_values[] = {
+ [0x00] = "Entery into Policy Module",
+ [0x03] = "Received S3 entry",
+ [0x04] = "Received S4 entry",
+ [0x05] = "Received S5 entry",
+ [0x06] = "Received UPD entry",
+ [0x07] = "Received PCR entry",
+ [0x08] = "Received NPCR entry",
+ [0x09] = "Received host wake",
+ [0x0a] = "Received AC<>DC switch",
+ [0x0b] = "Received DRAM Init Done",
+ [0x0c] = "VSCC Data not found for flash device",
+ [0x0d] = "VSCC Table is not valid",
+ [0x0e] = "Flash Partition Boundary is outside address space",
+ [0x0f] = "ME cannot access the chipset descriptor region",
+ [0x10] = "Required VSCC values for flash parts do not match",
+};
+
+void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes)
+{
+ /* Check Current States */
+ debug("ME: FW Partition Table : %s\n",
+ hfs->fpt_bad ? "BAD" : "OK");
+ debug("ME: Bringup Loader Failure : %s\n",
+ hfs->ft_bup_ld_flr ? "YES" : "NO");
+ debug("ME: Firmware Init Complete : %s\n",
+ hfs->fw_init_complete ? "YES" : "NO");
+ debug("ME: Manufacturing Mode : %s\n",
+ hfs->mfg_mode ? "YES" : "NO");
+ debug("ME: Boot Options Present : %s\n",
+ hfs->boot_options_present ? "YES" : "NO");
+ debug("ME: Update In Progress : %s\n",
+ hfs->update_in_progress ? "YES" : "NO");
+ debug("ME: Current Working State : %s\n",
+ me_cws_values[hfs->working_state]);
+ debug("ME: Current Operation State : %s\n",
+ me_opstate_values[hfs->operation_state]);
+ debug("ME: Current Operation Mode : %s\n",
+ me_opmode_values[hfs->operation_mode]);
+ debug("ME: Error Code : %s\n",
+ me_error_values[hfs->error_code]);
+ debug("ME: Progress Phase : %s\n",
+ me_progress_values[gmes->progress_code]);
+ debug("ME: Power Management Event : %s\n",
+ me_pmevent_values[gmes->current_pmevent]);
+
+ debug("ME: Progress Phase State : ");
+ switch (gmes->progress_code) {
+ case ME_GMES_PHASE_ROM: /* ROM Phase */
+ debug("%s", me_progress_rom_values[gmes->current_state]);
+ break;
+
+ case ME_GMES_PHASE_BUP: /* Bringup Phase */
+ if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) &&
+ me_progress_bup_values[gmes->current_state])
+ debug("%s",
+ me_progress_bup_values[gmes->current_state]);
+ else
+ debug("0x%02x", gmes->current_state);
+ break;
+
+ case ME_GMES_PHASE_POLICY: /* Policy Module Phase */
+ if (gmes->current_state <
+ ARRAY_SIZE(me_progress_policy_values) &&
+ me_progress_policy_values[gmes->current_state])
+ debug("%s",
+ me_progress_policy_values[gmes->current_state]);
+ else
+ debug("0x%02x", gmes->current_state);
+ break;
+
+ case ME_GMES_PHASE_HOST: /* Host Communication Phase */
+ if (!gmes->current_state)
+ debug("Host communication established");
+ else
+ debug("0x%02x", gmes->current_state);
+ break;
+
+ default:
+ debug("Unknown 0x%02x", gmes->current_state);
+ }
+ debug("\n");
+}
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ * Copyright (C) 2000 Ronald G. Minnich
+ *
+ * Microcode update for Intel PIII and later CPUs
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <asm/cpu.h>
+#include <asm/msr.h>
+#include <asm/processor.h>
+
+/**
+ * struct microcode_update - standard microcode header from Intel
+ *
+ * We read this information out of the device tree and use it to determine
+ * whether the update is applicable or not. We also use the same structure
+ * to read information from the CPU.
+ */
+struct microcode_update {
+ uint header_version;
+ uint update_revision;
+ uint date_code;
+ uint processor_signature;
+ uint checksum;
+ uint loader_revision;
+ uint processor_flags;
+ const void *data;
+ int size;
+};
+
+static int microcode_decode_node(const void *blob, int node,
+ struct microcode_update *update)
+{
+ update->data = fdt_getprop(blob, node, "data", &update->size);
+ if (!update->data)
+ return -EINVAL;
+
+ update->header_version = fdtdec_get_int(blob, node,
+ "intel,header-version", 0);
+ update->update_revision = fdtdec_get_int(blob, node,
+ "intel,update-revision", 0);
+ update->date_code = fdtdec_get_int(blob, node,
+ "intel,date-code", 0);
+ update->processor_signature = fdtdec_get_int(blob, node,
+ "intel.processor-signature", 0);
+ update->checksum = fdtdec_get_int(blob, node, "intel,checksum", 0);
+ update->loader_revision = fdtdec_get_int(blob, node,
+ "loader-revision", 0);
+ update->processor_flags = fdtdec_get_int(blob, node,
+ "processor-flags", 0);
+
+ return 0;
+}
+
+static uint32_t microcode_read_rev(void)
+{
+ /*
+ * Some Intel CPUs can be very finicky about the CPUID sequence used.
+ * So this is implemented in assembly so that it works reliably.
+ */
+ uint32_t low, high;
+
+ asm volatile (
+ "xorl %%eax, %%eax\n"
+ "xorl %%edx, %%edx\n"
+ "movl $0x8b, %%ecx\n"
+ "wrmsr\n"
+ "movl $0x01, %%eax\n"
+ "cpuid\n"
+ "movl $0x8b, %%ecx\n"
+ "rdmsr\n"
+ : /* outputs */
+ "=a" (low), "=d" (high)
+ : /* inputs */
+ : /* clobbers */
+ "ebx", "ecx"
+ );
+
+ return high;
+}
+
+static void microcode_read_cpu(struct microcode_update *cpu)
+{
+ /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */
+ unsigned int x86_model, x86_family;
+ struct cpuid_result result;
+ uint32_t low, high;
+
+ wrmsr(0x8b, 0, 0);
+ result = cpuid(1);
+ rdmsr(0x8b, low, cpu->update_revision);
+ x86_model = (result.eax >> 4) & 0x0f;
+ x86_family = (result.eax >> 8) & 0x0f;
+ cpu->processor_signature = result.eax;
+
+ cpu->processor_flags = 0;
+ if ((x86_model >= 5) || (x86_family > 6)) {
+ rdmsr(0x17, low, high);
+ cpu->processor_flags = 1 << ((high >> 18) & 7);
+ }
+ debug("microcode: sig=%#x pf=%#x revision=%#x\n",
+ cpu->processor_signature, cpu->processor_flags,
+ cpu->update_revision);
+}
+
+/* Get a microcode update from the device tree and apply it */
+int microcode_update_intel(void)
+{
+ struct microcode_update cpu, update;
+ const void *blob = gd->fdt_blob;
+ int count;
+ int node;
+ int ret;
+
+ microcode_read_cpu(&cpu);
+ node = 0;
+ count = 0;
+ do {
+ node = fdtdec_next_compatible(blob, node,
+ COMPAT_INTEL_MICROCODE);
+ if (node < 0) {
+ debug("%s: Found %d updates\n", __func__, count);
+ return count ? 0 : -ENOENT;
+ }
+
+ ret = microcode_decode_node(blob, node, &update);
+ if (ret) {
+ debug("%s: Unable to decode update: %d\n", __func__,
+ ret);
+ return ret;
+ }
+ if (update.processor_signature == cpu.processor_signature &&
+ (update.processor_flags & cpu.processor_flags)) {
+ debug("%s: Update already exists\n", __func__);
+ return -EEXIST;
+ }
+
+ wrmsr(0x79, (ulong)update.data, 0);
+ debug("microcode: updated to revision 0x%x date=%04x-%02x-%02x\n",
+ microcode_read_rev(), update.date_code & 0xffff,
+ (update.date_code >> 24) & 0xff,
+ (update.date_code >> 16) & 0xff);
+ count++;
+ } while (1);
+}
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008,2009
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+
+static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
+ struct pci_config_table *table)
+{
+ u8 secondary;
+
+ hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
+ if (secondary != 0)
+ pci_hose_scan_bus(hose, secondary);
+}
+
+static struct pci_config_table pci_ivybridge_config_table[] = {
+ /* vendor, device, class, bus, dev, func */
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
+ {}
+};
+
+void board_pci_setup_hose(struct pci_controller *hose)
+{
+ hose->config_table = pci_ivybridge_config_table;
+ hose->first_busno = 0;
+ hose->last_busno = 0;
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 0,
+ CONFIG_PCI_MEM_BUS,
+ CONFIG_PCI_MEM_PHYS,
+ CONFIG_PCI_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI IO space */
+ pci_set_region(hose->regions + 1,
+ CONFIG_PCI_IO_BUS,
+ CONFIG_PCI_IO_PHYS,
+ CONFIG_PCI_IO_SIZE,
+ PCI_REGION_IO);
+
+ pci_set_region(hose->regions + 2,
+ CONFIG_PCI_PREF_BUS,
+ CONFIG_PCI_PREF_PHYS,
+ CONFIG_PCI_PREF_SIZE,
+ PCI_REGION_PREFETCH);
+
+ hose->region_count = 3;
+}
--- /dev/null
+/*
+ * From Coreboot src/northbridge/intel/sandybridge/report_platform.c
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/cpu.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+static void report_cpu_info(void)
+{
+ char cpu_string[CPU_MAX_NAME_LEN], *cpu_name;
+ const char *mode[] = {"NOT ", ""};
+ struct cpuid_result cpuidr;
+ int vt, txt, aes;
+ u32 index;
+
+ index = 0x80000000;
+ cpuidr = cpuid(index);
+ if (cpuidr.eax < 0x80000004) {
+ strcpy(cpu_string, "Platform info not available");
+ cpu_name = cpu_string;
+ } else {
+ cpu_name = cpu_get_name(cpu_string);
+ }
+
+ cpuidr = cpuid(1);
+ debug("CPU id(%x): %s\n", cpuidr.eax, cpu_name);
+ aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
+ txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
+ vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
+ debug("AES %ssupported, TXT %ssupported, VT %ssupported\n",
+ mode[aes], mode[txt], mode[vt]);
+}
+
+/* The PCI id name match comes from Intel document 472178 */
+static struct {
+ u16 dev_id;
+ const char *dev_name;
+} pch_table[] = {
+ {0x1E41, "Desktop Sample"},
+ {0x1E42, "Mobile Sample"},
+ {0x1E43, "SFF Sample"},
+ {0x1E44, "Z77"},
+ {0x1E45, "H71"},
+ {0x1E46, "Z75"},
+ {0x1E47, "Q77"},
+ {0x1E48, "Q75"},
+ {0x1E49, "B75"},
+ {0x1E4A, "H77"},
+ {0x1E53, "C216"},
+ {0x1E55, "QM77"},
+ {0x1E56, "QS77"},
+ {0x1E58, "UM77"},
+ {0x1E57, "HM77"},
+ {0x1E59, "HM76"},
+ {0x1E5D, "HM75"},
+ {0x1E5E, "HM70"},
+ {0x1E5F, "NM70"},
+};
+
+static void report_pch_info(void)
+{
+ const char *pch_type = "Unknown";
+ int i;
+ u16 dev_id;
+ uint8_t rev_id;
+
+ dev_id = pci_read_config16(PCH_LPC_DEV, 2);
+ for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
+ if (pch_table[i].dev_id == dev_id) {
+ pch_type = pch_table[i].dev_name;
+ break;
+ }
+ }
+ rev_id = pci_read_config8(PCH_LPC_DEV, 8);
+ debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id,
+ rev_id);
+}
+
+void report_platform_info(void)
+{
+ report_cpu_info();
+ report_pch_info();
+}
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * Portions from Coreboot mainboard/google/link/romstage.c
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/gpio.h>
+#include <asm/global_data.h>
+#include <asm/pci.h>
+#include <asm/arch/me.h>
+#include <asm/arch/pei_data.h>
+#include <asm/arch/pch.h>
+#include <asm/post.h>
+#include <asm/arch/sandybridge.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This function looks for the highest region of memory lower than 4GB which
+ * has enough space for U-Boot where U-Boot is aligned on a page boundary.
+ * It overrides the default implementation found elsewhere which simply
+ * picks the end of ram, wherever that may be. The location of the stack,
+ * the relocation address, and how far U-Boot is moved by relocation are
+ * set in the global data structure.
+ */
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ struct memory_info *info = &gd->arch.meminfo;
+ uintptr_t dest_addr = 0;
+ struct memory_area *largest = NULL;
+ int i;
+
+ /* Find largest area of memory below 4GB */
+
+ for (i = 0; i < info->num_areas; i++) {
+ struct memory_area *area = &info->area[i];
+
+ if (area->start >= 1ULL << 32)
+ continue;
+ if (!largest || area->size > largest->size)
+ largest = area;
+ }
+
+ /* If no suitable area was found, return an error. */
+ assert(largest);
+ if (!largest || largest->size < (2 << 20))
+ panic("No available memory found for relocation");
+
+ dest_addr = largest->start + largest->size;
+
+ return (ulong)dest_addr;
+}
+
+void dram_init_banksize(void)
+{
+ struct memory_info *info = &gd->arch.meminfo;
+ int num_banks;
+ int i;
+
+ for (i = 0, num_banks = 0; i < info->num_areas; i++) {
+ struct memory_area *area = &info->area[i];
+
+ if (area->start >= 1ULL << 32)
+ continue;
+ gd->bd->bi_dram[num_banks].start = area->start;
+ gd->bd->bi_dram[num_banks].size = area->size;
+ num_banks++;
+ }
+}
+
+static const char *const ecc_decoder[] = {
+ "inactive",
+ "active on IO",
+ "disabled on IO",
+ "active"
+};
+
+/*
+ * Dump in the log memory controller configuration as read from the memory
+ * controller registers.
+ */
+static void report_memory_config(void)
+{
+ u32 addr_decoder_common, addr_decode_ch[2];
+ int i;
+
+ addr_decoder_common = readl(MCHBAR_REG(0x5000));
+ addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
+ addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
+
+ debug("memcfg DDR3 clock %d MHz\n",
+ (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100);
+ debug("memcfg channel assignment: A: %d, B % d, C % d\n",
+ addr_decoder_common & 3,
+ (addr_decoder_common >> 2) & 3,
+ (addr_decoder_common >> 4) & 3);
+
+ for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
+ u32 ch_conf = addr_decode_ch[i];
+ debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
+ debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
+ debug(" enhanced interleave mode %s\n",
+ ((ch_conf >> 22) & 1) ? "on" : "off");
+ debug(" rank interleave %s\n",
+ ((ch_conf >> 21) & 1) ? "on" : "off");
+ debug(" DIMMA %d MB width x%d %s rank%s\n",
+ ((ch_conf >> 0) & 0xff) * 256,
+ ((ch_conf >> 19) & 1) ? 16 : 8,
+ ((ch_conf >> 17) & 1) ? "dual" : "single",
+ ((ch_conf >> 16) & 1) ? "" : ", selected");
+ debug(" DIMMB %d MB width x%d %s rank%s\n",
+ ((ch_conf >> 8) & 0xff) * 256,
+ ((ch_conf >> 20) & 1) ? 16 : 8,
+ ((ch_conf >> 18) & 1) ? "dual" : "single",
+ ((ch_conf >> 16) & 1) ? ", selected" : "");
+ }
+}
+
+static void post_system_agent_init(struct pei_data *pei_data)
+{
+ /* If PCIe init is skipped, set the PEG clock gating */
+ if (!pei_data->pcie_init)
+ setbits_le32(MCHBAR_REG(0x7010), 1);
+}
+
+static asmlinkage void console_tx_byte(unsigned char byte)
+{
+#ifdef DEBUG
+ putc(byte);
+#endif
+}
+
+/**
+ * Find the PEI executable in the ROM and execute it.
+ *
+ * @param pei_data: configuration data for UEFI PEI reference code
+ */
+int sdram_initialise(struct pei_data *pei_data)
+{
+ unsigned version;
+ const char *data;
+ uint16_t done;
+ int ret;
+
+ report_platform_info();
+
+ /* Wait for ME to be ready */
+ ret = intel_early_me_init();
+ if (ret)
+ return ret;
+ ret = intel_early_me_uma_size();
+ if (ret < 0)
+ return ret;
+
+ debug("Starting UEFI PEI System Agent\n");
+
+ /* If MRC data is not found we cannot continue S3 resume. */
+ if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
+ debug("Giving up in sdram_initialize: No MRC data\n");
+ outb(0x6, PORT_RESET);
+ cpu_hlt();
+ }
+
+ /* Pass console handler in pei_data */
+ pei_data->tx_byte = console_tx_byte;
+
+ debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
+
+ data = (char *)CONFIG_X86_MRC_START;
+ if (data) {
+ int rv;
+ int (*func)(struct pei_data *);
+
+ debug("Calling MRC at %p\n", data);
+ post_code(POST_PRE_MRC);
+ func = (int (*)(struct pei_data *))data;
+ rv = func(pei_data);
+ post_code(POST_MRC);
+ if (rv) {
+ switch (rv) {
+ case -1:
+ printf("PEI version mismatch.\n");
+ break;
+ case -2:
+ printf("Invalid memory frequency.\n");
+ break;
+ default:
+ printf("MRC returned %x.\n", rv);
+ }
+ printf("Nonzero MRC return value.\n");
+ return -EFAULT;
+ }
+ } else {
+ printf("UEFI PEI System Agent not found.\n");
+ return -ENOSYS;
+ }
+
+#if CONFIG_USBDEBUG
+ /* mrc.bin reconfigures USB, so reinit it to have debug */
+ early_usbdebug_init();
+#endif
+
+ version = readl(MCHBAR_REG(0x5034));
+ debug("System Agent Version %d.%d.%d Build %d\n",
+ version >> 24 , (version >> 16) & 0xff,
+ (version >> 8) & 0xff, version & 0xff);
+
+ /*
+ * Send ME init done for SandyBridge here. This is done inside the
+ * SystemAgent binary on IvyBridge
+ */
+ done = pci_read_config32(PCH_DEV, PCI_DEVICE_ID);
+ done &= BASE_REV_MASK;
+ if (BASE_REV_SNB == done)
+ intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
+ else
+ intel_early_me_status();
+
+ post_system_agent_init(pei_data);
+ report_memory_config();
+
+ return 0;
+}
+
+static int copy_spd(struct pei_data *peid)
+{
+ const int gpio_vector[] = {41, 42, 43, 10, -1};
+ int spd_index;
+ const void *blob = gd->fdt_blob;
+ int node, spd_node;
+ int ret, i;
+
+ for (i = 0; ; i++) {
+ if (gpio_vector[i] == -1)
+ break;
+ ret = gpio_requestf(gpio_vector[i], "spd_id%d", i);
+ if (ret) {
+ debug("%s: Could not request gpio %d\n", __func__,
+ gpio_vector[i]);
+ return ret;
+ }
+ }
+ spd_index = gpio_get_values_as_int(gpio_vector);
+ debug("spd index %d\n", spd_index);
+ node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD);
+ if (node < 0) {
+ printf("SPD data not found.\n");
+ return -ENOENT;
+ }
+
+ for (spd_node = fdt_first_subnode(blob, node);
+ spd_node > 0;
+ spd_node = fdt_next_subnode(blob, spd_node)) {
+ const char *data;
+ int len;
+
+ if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index)
+ continue;
+ data = fdt_getprop(blob, spd_node, "data", &len);
+ if (len < sizeof(peid->spd_data[0])) {
+ printf("Missing SPD data\n");
+ return -EINVAL;
+ }
+
+ debug("Using SDRAM SPD data for '%s'\n",
+ fdt_get_name(blob, spd_node, NULL));
+ memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
+ break;
+ }
+
+ if (spd_node < 0) {
+ printf("No SPD data found for index %d\n", spd_index);
+ return -ENOENT;
+ }
+
+ return 0;
+}
+
+/**
+ * add_memory_area() - Add a new usable memory area to our list
+ *
+ * Note: @start and @end must not span the first 4GB boundary
+ *
+ * @info: Place to store memory info
+ * @start: Start of this memory area
+ * @end: End of this memory area + 1
+ */
+static int add_memory_area(struct memory_info *info,
+ uint64_t start, uint64_t end)
+{
+ struct memory_area *ptr;
+
+ if (info->num_areas == CONFIG_NR_DRAM_BANKS)
+ return -ENOSPC;
+
+ ptr = &info->area[info->num_areas];
+ ptr->start = start;
+ ptr->size = end - start;
+ info->total_memory += ptr->size;
+ if (ptr->start < (1ULL << 32))
+ info->total_32bit_memory += ptr->size;
+ debug("%d: memory %llx size %llx, total now %llx / %llx\n",
+ info->num_areas, ptr->start, ptr->size,
+ info->total_32bit_memory, info->total_memory);
+ info->num_areas++;
+
+ return 0;
+}
+
+/**
+ * sdram_find() - Find available memory
+ *
+ * This is a bit complicated since on x86 there are system memory holes all
+ * over the place. We create a list of available memory blocks
+ */
+static int sdram_find(pci_dev_t dev)
+{
+ struct memory_info *info = &gd->arch.meminfo;
+ uint32_t tseg_base, uma_size, tolud;
+ uint64_t tom, me_base, touud;
+ uint64_t uma_memory_base = 0;
+ uint64_t uma_memory_size;
+ unsigned long long tomk;
+ uint16_t ggc;
+
+ /* Total Memory 2GB example:
+ *
+ * 00000000 0000MB-1992MB 1992MB RAM (writeback)
+ * 7c800000 1992MB-2000MB 8MB TSEG (SMRR)
+ * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached)
+ * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached)
+ * 7f200000 2034MB TOLUD
+ * 7f800000 2040MB MEBASE
+ * 7f800000 2040MB-2048MB 8MB ME UMA (uncached)
+ * 80000000 2048MB TOM
+ * 100000000 4096MB-4102MB 6MB RAM (writeback)
+ *
+ * Total Memory 4GB example:
+ *
+ * 00000000 0000MB-2768MB 2768MB RAM (writeback)
+ * ad000000 2768MB-2776MB 8MB TSEG (SMRR)
+ * ad800000 2776MB-2778MB 2MB GFX GTT (uncached)
+ * ada00000 2778MB-2810MB 32MB GFX UMA (uncached)
+ * afa00000 2810MB TOLUD
+ * ff800000 4088MB MEBASE
+ * ff800000 4088MB-4096MB 8MB ME UMA (uncached)
+ * 100000000 4096MB TOM
+ * 100000000 4096MB-5374MB 1278MB RAM (writeback)
+ * 14fe00000 5368MB TOUUD
+ */
+
+ /* Top of Upper Usable DRAM, including remap */
+ touud = pci_read_config32(dev, TOUUD+4);
+ touud <<= 32;
+ touud |= pci_read_config32(dev, TOUUD);
+
+ /* Top of Lower Usable DRAM */
+ tolud = pci_read_config32(dev, TOLUD);
+
+ /* Top of Memory - does not account for any UMA */
+ tom = pci_read_config32(dev, 0xa4);
+ tom <<= 32;
+ tom |= pci_read_config32(dev, 0xa0);
+
+ debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);
+
+ /* ME UMA needs excluding if total memory <4GB */
+ me_base = pci_read_config32(dev, 0x74);
+ me_base <<= 32;
+ me_base |= pci_read_config32(dev, 0x70);
+
+ debug("MEBASE %llx\n", me_base);
+
+ /* TODO: Get rid of all this shifting by 10 bits */
+ tomk = tolud >> 10;
+ if (me_base == tolud) {
+ /* ME is from MEBASE-TOM */
+ uma_size = (tom - me_base) >> 10;
+ /* Increment TOLUD to account for ME as RAM */
+ tolud += uma_size << 10;
+ /* UMA starts at old TOLUD */
+ uma_memory_base = tomk * 1024ULL;
+ uma_memory_size = uma_size * 1024ULL;
+ debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10);
+ }
+
+ /* Graphics memory comes next */
+ ggc = pci_read_config16(dev, GGC);
+ if (!(ggc & 2)) {
+ debug("IGD decoded, subtracting ");
+
+ /* Graphics memory */
+ uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
+ debug("%uM UMA", uma_size >> 10);
+ tomk -= uma_size;
+ uma_memory_base = tomk * 1024ULL;
+ uma_memory_size += uma_size * 1024ULL;
+
+ /* GTT Graphics Stolen Memory Size (GGMS) */
+ uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
+ tomk -= uma_size;
+ uma_memory_base = tomk * 1024ULL;
+ uma_memory_size += uma_size * 1024ULL;
+ debug(" and %uM GTT\n", uma_size >> 10);
+ }
+
+ /* Calculate TSEG size from its base which must be below GTT */
+ tseg_base = pci_read_config32(dev, 0xb8);
+ uma_size = (uma_memory_base - tseg_base) >> 10;
+ tomk -= uma_size;
+ uma_memory_base = tomk * 1024ULL;
+ uma_memory_size += uma_size * 1024ULL;
+ debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
+
+ debug("Available memory below 4GB: %lluM\n", tomk >> 10);
+
+ /* Report the memory regions */
+ add_memory_area(info, 1 << 20, 2 << 28);
+ add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
+ add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
+ add_memory_area(info, 1ULL << 32, touud);
+ /*
+ * If >= 4GB installed then memory from TOLUD to 4GB
+ * is remapped above TOM, TOUUD will account for both
+ */
+ if (touud > (1ULL << 32ULL)) {
+ debug("Available memory above 4GB: %lluM\n",
+ (touud >> 20) - 4096);
+ }
+
+ return 0;
+}
+
+static void rcba_config(void)
+{
+ /*
+ * GFX INTA -> PIRQA (MSI)
+ * D28IP_P3IP WLAN INTA -> PIRQB
+ * D29IP_E1P EHCI1 INTA -> PIRQD
+ * D26IP_E2P EHCI2 INTA -> PIRQF
+ * D31IP_SIP SATA INTA -> PIRQF (MSI)
+ * D31IP_SMIP SMBUS INTB -> PIRQH
+ * D31IP_TTIP THRT INTC -> PIRQA
+ * D27IP_ZIP HDA INTA -> PIRQA (MSI)
+ *
+ * TRACKPAD -> PIRQE (Edge Triggered)
+ * TOUCHSCREEN -> PIRQG (Edge Triggered)
+ */
+
+ /* Device interrupt pin register (board specific) */
+ writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+ (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP));
+ writel(NOINT << D30IP_PIP, RCB_REG(D30IP));
+ writel(INTA << D29IP_E1P, RCB_REG(D29IP));
+ writel(INTA << D28IP_P3IP, RCB_REG(D28IP));
+ writel(INTA << D27IP_ZIP, RCB_REG(D27IP));
+ writel(INTA << D26IP_E2P, RCB_REG(D26IP));
+ writel(NOINT << D25IP_LIP, RCB_REG(D25IP));
+ writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP));
+
+ /* Device interrupt route registers */
+ writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR));
+ writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR));
+ writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR));
+ writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR));
+ writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR));
+ writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR));
+ writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR));
+
+ /* Enable IOAPIC (generic) */
+ writew(0x0100, RCB_REG(OIC));
+ /* PCH BWG says to read back the IOAPIC enable register */
+ (void)readw(RCB_REG(OIC));
+
+ /* Disable unused devices (board specific) */
+ setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS);
+}
+
+int dram_init(void)
+{
+ struct pei_data pei_data __aligned(8) = {
+ .pei_version = PEI_VERSION,
+ .mchbar = DEFAULT_MCHBAR,
+ .dmibar = DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = CONFIG_HPET_ADDRESS,
+ .rcba = DEFAULT_RCBABASE,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .thermalbase = 0xfed08000,
+ .system_type = 0, /* 0 Mobile, 1 Desktop/Server */
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
+ .ec_present = 1,
+ .ddr3lv_support = 1,
+ /*
+ * 0 = leave channel enabled
+ * 1 = disable dimm 0 on channel
+ * 2 = disable dimm 1 on channel
+ * 3 = disable dimm 0+1 on channel
+ */
+ .dimm_channel0_disabled = 2,
+ .dimm_channel1_disabled = 2,
+ .max_ddr3_freq = 1600,
+ .usb_port_config = {
+ /*
+ * Empty and onboard Ports 0-7, set to un-used pin
+ * OC3
+ */
+ { 0, 3, 0x0000 }, /* P0= Empty */
+ { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */
+ { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */
+ { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */
+ { 0, 3, 0x0000 }, /* P4= Empty */
+ { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */
+ { 0, 3, 0x0000 }, /* P6= Empty */
+ { 0, 3, 0x0000 }, /* P7= Empty */
+ /*
+ * Empty and onboard Ports 8-13, set to un-used pin
+ * OC4
+ */
+ { 1, 4, 0x0040 }, /* P8= Camera (no OC) */
+ { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */
+ { 0, 4, 0x0000 }, /* P10= Empty */
+ { 0, 4, 0x0000 }, /* P11= Empty */
+ { 0, 4, 0x0000 }, /* P12= Empty */
+ { 0, 4, 0x0000 }, /* P13= Empty */
+ },
+ };
+ pci_dev_t dev = PCI_BDF(0, 0, 0);
+ int ret;
+
+ debug("Boot mode %d\n", gd->arch.pei_boot_mode);
+ debug("mcr_input %p\n", pei_data.mrc_input);
+ pei_data.boot_mode = gd->arch.pei_boot_mode;
+ ret = copy_spd(&pei_data);
+ if (!ret)
+ ret = sdram_initialise(&pei_data);
+ if (ret)
+ return ret;
+
+ rcba_config();
+ quick_ram_check();
+
+ writew(0xCAFE, MCHBAR_REG(SSKPD));
+
+ post_code(POST_DRAM);
+
+ ret = sdram_find(dev);
+ if (ret)
+ return ret;
+
+ gd->ram_size = gd->arch.meminfo.total_32bit_memory;
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008,2009
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <pci.h>
+#include <asm/pci.h>
+
+static struct pci_controller x86_hose;
+
+int pci_early_init_hose(struct pci_controller **hosep)
+{
+ struct pci_controller *hose;
+
+ hose = calloc(1, sizeof(struct pci_controller));
+ if (!hose)
+ return -ENOMEM;
+
+ board_pci_setup_hose(hose);
+ pci_setup_type1(hose);
+ gd->arch.hose = hose;
+ *hosep = hose;
+
+ return 0;
+}
+
+void pci_init_board(void)
+{
+ struct pci_controller *hose = &x86_hose;
+
+ /* Stop using the early hose */
+ gd->arch.hose = NULL;
+
+ board_pci_setup_hose(hose);
+ pci_setup_type1(hose);
+ pci_register_hose(hose);
+
+ hose->last_busno = pci_hose_scan(hose);
+}
+
+static struct pci_controller *get_hose(void)
+{
+ if (gd->arch.hose)
+ return gd->arch.hose;
+
+ return pci_bus_to_hose(0);
+}
+
+unsigned int pci_read_config8(pci_dev_t dev, unsigned where)
+{
+ uint8_t value;
+
+ pci_hose_read_config_byte(get_hose(), dev, where, &value);
+
+ return value;
+}
+
+unsigned int pci_read_config16(pci_dev_t dev, unsigned where)
+{
+ uint16_t value;
+
+ pci_hose_read_config_word(get_hose(), dev, where, &value);
+
+ return value;
+}
+
+unsigned int pci_read_config32(pci_dev_t dev, unsigned where)
+{
+ uint32_t value;
+
+ pci_hose_read_config_dword(get_hose(), dev, where, &value);
+
+ return value;
+}
+
+void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
+{
+ pci_hose_write_config_byte(get_hose(), dev, where, value);
+}
+
+void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
+{
+ pci_hose_write_config_word(get_hose(), dev, where, value);
+}
+
+void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
+{
+ pci_hose_write_config_dword(get_hose(), dev, where, value);
+}
#include <config.h>
#include <version.h>
#include <asm/global_data.h>
+#include <asm/post.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <generated/generic-asm-offsets.h>
*/
movw $GD_FLG_COLD_BOOT, %bx
1:
+ /* Save BIST */
+ movl %eax, %ebp
/* Load the segement registes to match the gdt loaded in start16.S */
movl $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax
jmp early_board_init
.globl early_board_init_ret
early_board_init_ret:
+ post_code(POST_START)
/* Initialise Cache-As-RAM */
jmp car_init
* We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM,
* or fully initialised SDRAM - we really don't care which)
* starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack
+ * and early malloc area. The MRC requires some space at the top.
+ *
+ * Stack grows down from top of CAR. We have:
+ *
+ * top-> CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE
+ * MRC area
+ * global_data
+ * x86 global descriptor table
+ * early malloc area
+ * stack
+ * bottom-> CONFIG_SYS_CAR_ADDR
*/
-
- /* Stack grows down from top of CAR */
- movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE), %esp
+ movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp
+#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
+ subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp
+#endif
/* Reserve space on stack for global data */
subl $GENERATED_GBL_DATA_SIZE, %esp
/* Align global data to 16-byte boundary */
andl $0xfffffff0, %esp
+ post_code(POST_START_STACK)
/* Zero the global data since it won't happen later */
xorl %eax, %eax
movl %esp, %edi
rep stosb
- /* Setup first parameter to setup_gdt */
+ /* Setup first parameter to setup_gdt, pointer to global_data */
movl %esp, %eax
/* Reserve space for global descriptor table */
subl $X86_GDT_SIZE, %esp
+ /* Align temporary global descriptor table to 16-byte boundary */
+ andl $0xfffffff0, %esp
+ movl %esp, %ecx
+
#if defined(CONFIG_SYS_MALLOC_F_LEN)
subl $CONFIG_SYS_MALLOC_F_LEN, %esp
movl %eax, %edx
addl $GD_MALLOC_BASE, %edx
movl %esp, (%edx)
#endif
-
- /* Align temporary global descriptor table to 16-byte boundary */
- andl $0xfffffff0, %esp
+ /* Store BIST */
+ movl %eax, %edx
+ addl $GD_BIST, %edx
+ movl %ebp, (%edx)
/* Set second parameter to setup_gdt */
- movl %esp, %edx
+ movl %ecx, %edx
/* Setup global descriptor table so gd->xyz works */
call setup_gdt
/* Set parameter to board_init_f() to boot flags */
+ post_code(POST_START_DONE)
xorl %eax, %eax
- movw %bx, %ax
/* Enter, U-boot! */
call board_init_f
.code16
.globl start16
start16:
+ /* Save BIST */
+ movl %eax, %ecx
+
/* Set the Cold Boot / Hard Reset flag */
movl $GD_FLG_COLD_BOOT, %ebx
- /*
- * First we let the BSP do some early initialization
- * this code have to map the flash to its final position
- */
- jmp board_init16
-.globl board_init16_ret
-board_init16_ret:
+ xorl %eax, %eax
+ movl %eax, %cr3 /* Invalidate TLB */
- /* Turn of cache (this might require a 486-class CPU) */
+ /* Turn off cache (this might require a 486-class CPU) */
movl %cr0, %eax
orl $(X86_CR0_NW | X86_CR0_CD), %eax
movl %eax, %cr0
/* Flush the prefetch queue */
jmp ff
ff:
- /* Finally jump to the 32bit initialization code */
+
+ /* Finally restore BIST and jump to the 32bit initialization code */
movw $code32start, %ax
movw %ax, %bp
+ movl %ecx, %eax
o32 cs ljmp *(%bp)
/* 48-bit far pointer */
dtb-y += link.dtb \
+ chromebook_link.dtb \
alex.dtb
targets += $(dtb-y)
--- /dev/null
+link.dts
\ No newline at end of file
gpioa {
compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
reg = <0 0x10>;
bank-name = "A";
};
gpiob {
compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
reg = <0x30 0x10>;
bank-name = "B";
};
gpioc {
compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
reg = <0x40 0x10>;
bank-name = "C";
};
chosen { };
memory { device_type = "memory"; reg = <0 0>; };
+ spd {
+ compatible = "memory-spd";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ elpida_4Gb_1600_x16 {
+ reg = <0>;
+ data = [92 10 0b 03 04 19 02 02
+ 03 52 01 08 0a 00 fe 00
+ 69 78 69 3c 69 11 18 81
+ 20 08 3c 3c 01 40 83 81
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 11 42 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 02 fe 00
+ 11 52 00 00 00 07 7f 37
+ 45 42 4a 32 30 55 47 36
+ 45 42 55 30 2d 47 4e 2d
+ 46 20 30 20 02 fe 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00];
+ };
+ samsung_4Gb_1600_1.35v_x16 {
+ reg = <1>;
+ data = [92 11 0b 03 04 19 02 02
+ 03 11 01 08 0a 00 fe 00
+ 69 78 69 3c 69 11 18 81
+ f0 0a 3c 3c 01 40 83 01
+ 00 80 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 11 02 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 80 ce 01
+ 00 00 00 00 00 00 6a 04
+ 4d 34 37 31 42 35 36 37
+ 34 42 48 30 2d 59 4b 30
+ 20 20 00 00 80 ce 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00];
+ };
+ micron_4Gb_1600_1.35v_x16 {
+ reg = <2>;
+ data = [92 11 0b 03 04 19 02 02
+ 03 11 01 08 0a 00 fe 00
+ 69 78 69 3c 69 11 18 81
+ 20 08 3c 3c 01 40 83 05
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 01 02 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 80 2c 00
+ 00 00 00 00 00 00 ad 75
+ 34 4b 54 46 32 35 36 36
+ 34 48 5a 2d 31 47 36 45
+ 31 20 45 31 80 2c 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff];
+ };
+ };
+
spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,lpc";
#address-cells = <1>;
#size-cells = <1>;
+ gen-dec = <0x800 0xfc 0x900 0xfc>;
cros-ec@200 {
compatible = "google,cros-ec";
reg = <0x204 1 0x200 1 0x880 0x80>;
};
};
};
+
+ microcode {
+ update@0 {
+#include "m12206a7_00000028.dtsi"
+ };
+ update@1 {
+#include "m12306a9_00000017.dtsi"
+ };
+ };
+
};
--- /dev/null
+/*
+ * Copyright (c) <1995-2013>, Intel Corporation.
+ * All rights reserved.
+ *
+ * Redistribution. Redistribution and use in binary form, without modification, are
+ * permitted provided that the following conditions are met:
+ * .Redistributions must reproduce the above copyright notice and the following
+ * disclaimer in the documentation and/or other materials provided with the
+ * distribution.
+ * Neither the name of Intel Corporation nor the names of its suppliers may be used
+ * to endorse or promote products derived from this software without specific prior
+ * written permission.
+ * .No reverse engineering, decompilation, or disassembly of this software is
+ * permitted.
+ * ."Binary form" includes any format commonly used for electronic conveyance
+ * which is a reversible, bit-exact translation of binary representation to ASCII or
+ * ISO text, for example, "uuencode."
+ *
+ * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x28>;
+intel,date-code = <0x04242012>;
+intel,processor-signature = <0x000206a7>;
+intel,checksum = <0xf3e9935d>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The 48-byte public header is omitted. */
+data = <
+ 0x00000000 0x000000a1 0x00020001 0x00000028
+ 0x00000000 0x00000000 0x20120423 0x000008f1
+ 0x00000001 0x000206a7 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000008f1 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x52b813ac 0xdb8994c7 0x70e9f6bb 0x9d6db2ff
+ 0xf4d70f5d 0x5b1eccf6 0xac59106f 0x0ae2e2c1
+ 0x1a7bbeb1 0x355a1d62 0x2e7eb594 0x09f8dea9
+ 0x432a49e4 0xbf520253 0xdafa4010 0x893a858a
+ 0x766e0efb 0xd91e196d 0x838bd2ef 0xe5146494
+ 0xd515f413 0x29704828 0xe85598b6 0xdcbe6c51
+ 0x88eabbfa 0xa1e8909f 0xd8931721 0x35386554
+ 0x089a78a7 0xd9914775 0xd4644748 0x1556a4dc
+ 0xf44448f6 0xd054d7db 0xf30f2b7d 0x5ae223d0
+ 0xcbbb48b0 0x5c8b0383 0x177de157 0x9c1e5f73
+ 0x2ec28289 0xd72a7b6c 0x823b6eb2 0x35e02171
+ 0xba8deae4 0x06f4d468 0x13dbafaa 0x72b419f1
+ 0x033385b5 0x05806920 0x4c6034cf 0x9bd117dc
+ 0x976e2d04 0x250330f0 0x7250b5e1 0x184980c2
+ 0x12a9d7d6 0x1bc808f9 0xae79994f 0xc6f87901
+ 0xc0e3132f 0x671491c5 0x236cad39 0x37889d9c
+ 0x67f7c3f3 0x964a6be5 0xbcced7da 0x57eeaa6e
+ 0x7bca1522 0x654fee4c 0x2a1ca5d9 0xa1803cf3
+ 0x00000011 0x8c316d2c 0x17603b7e 0x32e42981
+ 0xc26c1400 0xf0fbccb6 0xeab6b43a 0x11d456a5
+ 0x5b912d46 0x15195fe0 0x542f6db3 0x0b7f212e
+ 0x47718dd9 0x7c41b108 0x06c21111 0x4445d5ea
+ 0xb4fb8128 0xe07404a6 0x8d503da4 0x78fc7e44
+ 0xb9919656 0x9968c797 0x87f26ab0 0x23bb1af7
+ 0x1ec5d761 0x26f30d2c 0x7cdb747c 0xe4d42033
+ 0x8a5d4801 0x768aff57 0xbcfd5d11 0x7c853c2d
+ 0x231e6207 0x8b1988a6 0xd68fdb75 0x58dcb417
+ 0x44422ef9 0x2a186ebb 0x7d27e85f 0x36ac31f7
+ 0x1e487e77 0x2b0b8c37 0xd8ba682f 0x2cba791b
+ 0xe6d3dece 0x1b2c2a99 0x4e5decab 0xfbd313a3
+ 0xdbc78294 0x5a80cce7 0x2d8e0f0b 0xcf564f71
+ 0x073d1f37 0x25162870 0x96cdb85b 0x9c553048
+ 0x24eba740 0xfc0f352e 0x0c83be68 0x89b5076c
+ 0xc39c4355 0x6a4cf25c 0x2bbd2682 0xc524fdb9
+ 0x7ea19bae 0x191ad6f1 0xd3fbf3bf 0x21bf77fa
+ 0x8f77fec4 0x0f90f635 0xe55e165c 0x868d58c0
+ 0x966bc0ad 0x6c276364 0x9d8f7eff 0x4b7925d4
+ 0x8b2f9326 0x4ab7b47e 0x33a9087c 0xf31ab949
+ 0x69831dfb 0x4711a215 0x8128c1fa 0x8481c213
+ 0x7401b01b 0xfdcfdc50 0xd6b55266 0xae9b23ac
+ 0xfa2ad275 0xa225bb45 0x4dd720c4 0x760a20e6
+ 0x5f1223c9 0x2f334372 0x6e1dcdab 0xe8ee8638
+ 0x1c19ba8a 0xef9341c4 0x360aaa9d 0x90452ea9
+ 0x65852446 0xe9398fa3 0xbba6a631 0x1a3e90b9
+ 0xe2a73a56 0x6e8c0747 0x35c7c53d 0xcc1ac842
+ 0x183356af 0xb6e98608 0x987b43c2 0xa8a3cfd2
+ 0xc2c5fce0 0xcc3af64a 0xd6d3a291 0xe59ad1f5
+ 0x124ca513 0x9522b50a 0x25150477 0xa2eb5797
+ 0x7fc63626 0x648c48e3 0x9f5797ff 0x2307b84d
+ 0x980625a4 0xabc05983 0x24980807 0x773c4f99
+ 0x3407b872 0x07c3657a 0xa2cd9e48 0x49c1e6a8
+ 0xa881b84c 0xf804d72c 0xb5319d2a 0x3e39780f
+ 0x97518822 0x0acd54c2 0x0721a9ff 0x10e1d2fd
+ 0xa7b6db77 0x845b1a56 0xef00160e 0x6b41bfd5
+ 0xc994df0d 0xcf44a5ca 0x794b36a4 0xf9fdb127
+ 0x922a1366 0x822aa8a9 0x4b137bd5 0x5722a49f
+ 0x8933719a 0x17edc1a9 0x079d9538 0x21fae7d5
+ 0xe534fd73 0x9d3038d5 0x48c3a056 0x5b22d58a
+ 0x6f142866 0xf1d767cd 0xb51ad5a6 0x34a0ef85
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+ 0x20c4d2cf 0x8c80d4d3 0x61ebe382 0x788b74df
+ 0x11c56903 0x535889ba 0x0a9c7380 0xf9de2837
+ 0x09437fe7 0x1627c6b2 0xb943bdb8 0x69bc29b2
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+ 0x56b56b66 0xb0680941 0x623d38a9 0x2add07ad
+ 0xe583ba09 0x96f6532a 0x3eff4696 0x2a8a6b0b
+ 0x905b913b 0xafc01673 0xe871e006 0x2c2339ad
+ 0x248438e5 0x96d83e53 0xb3a75d6b 0x2258cf63
+ 0x69ff39bf 0x95727173 0xc3ac09d5 0xea8d2c06
+ 0x0e7c0a4b 0x144fcade 0x28a9a5a3 0x97c11ae8
+ 0x89865e3d 0x1640cd32 0xe3e551f8 0x1f7ba770
+ 0x6d23fb31 0x11eceae3 0xc8ccb8ee 0x46dd0bb0
+ 0xd01a46ff 0x0504adf5 0xec6e170e 0x2e3d7ac5
+ 0x70f893ac 0xaf9963db 0x061e283c 0xf0ad248f
+ 0x2fe97e19 0x881fd340 0xc686c9d5 0x88ea8ba5
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+ 0xe9166f3c 0x2d20777b 0x82a003ae 0x2c7ae0aa
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+ 0x35c5e2dc 0xc97b78fc 0x5db6db2a 0x80fe3414
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+ 0xd95b61ea 0x5528e8f5 0x4ecd325c 0x88ffdc0b
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+ 0x1ed8978b 0xa8849eda 0x8633b4a3 0xb8c858b5
+ 0xbe3c4375 0x28b9e84e 0xb2a26def 0x22f8f66b
+ 0x3a4aed99 0x0c4914ea 0xad103249 0xba5a5eff
+ 0x8a052461 0x26938899 0x915c6ed7 0xe6268ad9
+ 0x246e8c74 0x75f3c196 0xc3e725d6 0x92e02549
+ 0x1f78a5cb 0xeada57e5 0x40f14906 0x0215e49c
+ 0x57c06bae 0xc1896b87 0x0cd40a63 0x60741d80
+ 0x11a69899 0x80fed942 0x0497e115 0x56697b55
+ 0xba89c3d4 0x27d6b7c5 0xddff87b0 0xd3b1ff2f
+ 0x3160e528 0x9cca1286 0x13b4fdf1 0x38cdd907
+ 0xb50c4597 0x4c151714 0x1cab86c7 0x23126a3e
+ 0xe26e9749 0x289a0d0e 0xc4004640 0x9d33928d
+ 0x33b691a2 0x15ed6e6b 0x6e773980 0xadd59678
+ 0x188ba49f 0x08da4c6d 0x6d150d0b 0x0c6c7b98
+ 0xc8e1df7e 0xb8b1e692 0x5e89fd35 0xcb253d24
+ 0xfc6ee27c 0x8013de3d 0x1d38012b 0xe50a8f7b
+ 0x7d410ff1 0xceee4e9f 0x0e8094b6 0xaa1a5f57
+ 0xb395a551 0xbd62b2ae 0x5d7b34c8 0xbd2d6195
+ 0x33af4109 0x0769ff18 0x9c6cc123 0x78ee6eb6
+ 0x412644e7 0x70e0c6f4 0xf45d8fc6 0x0435f5af
+ 0xd43622b7 0x27409d5b 0x6dd04e8f 0x9f02ecf5
+ 0xca415f7d 0xc9f439c2 0x7198e539 0x20476b75
+ 0x3cdd8dd8 0xce17fbb0 0xa5bc115e 0xb0ee52c1
+ 0x0b074cfa 0xd26d4f99 0x3b43320b 0x230b680b
+ 0x9908f2d2 0xcbcb1952 0xf45a2f53 0x7b4564c6
+ 0xcf2fd983 0x414fe4b2 0x55ea7f11 0x63e8117d
+ 0xe8954052 0x7c2ea344 0x97a02aaf 0x6ca874c3
+ 0x1ae5b4ee 0x41754eae 0x6954abe0 0x115ddcda
+ 0x9a27968b 0x32a53e65 0xffe47b2f 0x4fe7e5a7
+ 0x6016dedc 0xb3c0893e 0x9626776d 0x5ec773f9
+ 0x1104e01c 0x1473cfb3 0x43b2cedf 0x8ca9d119
+ 0x7f1bc844 0xd8bb7387 0xba90d2ef 0x2bb0dcf4
+ 0x2340f124 0xa5bd514c 0x50afab05 0x718f5ad5
+ 0x7c03fad9 0x71d00d2d 0x1c31fdc2 0x4a938809
+ 0x40945ded 0x437f2a0d 0x83c10d64 0xd224c6ab
+ 0x0cd44481 0xb0040966 0x27fd6e7f 0x6ff45d4c
+ 0xab057ad1 0x8fa4e5d4 0xac50270c 0x6e4926ca
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+ 0xea8964ca 0x56766e60 0xdc3b8702 0xa93528d4
+ 0x28d7713d 0x42edf022 0x59774dd8 0x200ff942
+ 0xe7a4d769 0xd8c4ef5e 0xe177f715 0xe9d53cd6
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+ 0xdbf166a8 0x49700d85 0x0f85f98a 0xa7ca7a75
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+ 0xc7ca1ee0 0xe0c3b047 0x5e36e1bc 0x447a9141
+ 0xe24654df 0x9853a49b 0x6a29cedb 0x022f00dc
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+ 0xd649f4a5 0xbb0c81f9 0xc0ba93fd 0xc1b390f1
+ 0xda84e720 0x1aea0064 0xf3ee67e1 0xb874ef4a
+ 0x82467ce6 0x59abf506 0xafbf145a 0x9a4cf8a1
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+ 0xcb486570 0x17a9db23 0x3e6504f0 0x08684517
+ 0x2723ab28 0x7081b814 0x8a265a04 0x697e6d8b
+ 0x69b146dc 0x6434c182 0x27ec8101 0x864405c5
+ 0xfff86c9e 0x3052d8a6 0x23d283db 0x492970e8
+ 0xbc6c64c3 0x46d8f98b 0xe16e7ff3 0x731e4f82
+ 0xbd26b1af 0x6b30e6c1 0xff192fce 0x097e0bba
+ 0x49df63a5 0x2fdc3f01 0x50aae053 0x60177b8f
+ 0x1949eb85 0xa46084ce 0x9658f694 0xcb951fbc
+ 0xc53806d9 0x63a17d30 0x3b3f86c2 0x8a37aa6c
+ 0xedf8fe5c 0x87aee1d3 0x8c680126 0xfd8b27a6
+ 0x231fa106 0x69358c25 0x4502c348 0xc107861c
+ 0x46280e70 0xcf6067ac 0xf6a04ff3 0x3e488677
+ 0x6f3fb4c1 0xeec1f758 0x560e1c48 0xb604c06b
+ 0x69e34b1e 0x8ef41dec 0x854cea22 0x726581d7
+ 0x55ea91f3 0x38ae4053 0x5ff7389d 0x6952cbf6
+ 0x09aa0fc1 0xcccb1d50 0x5c1a633a 0xde1eba46
+ 0x797212d8 0xa943fb3d 0x6063a1a8 0xbe68ef36
+ 0x6ba0d5ba 0x0dbe2061 0x47711712 0x62679807
+ 0x6f34009e 0xe6fe8f18 0x66a6a64b 0x3f80f472
+ 0xe953d5e0 0xbcd8196a 0x086faad0 0x49da7f16
+ 0x7f2199a5 0x55af4af2 0x085b4d38 0x22e634bd
+ 0x6cff0416 0x343466f4 0xd121a7a6 0x6caa3942
+ 0xe4f365a2 0xd832eb0c 0x616728e5 0xcca4c71a
+ 0x4010cdc2 0xd0f1d1cb 0x5e695f89 0x27719206
+ 0x0ec92854 0x76144a1b 0x49808021 0x12457a1b
+ 0xdde7aa5c 0x8f1a077f 0x110a4a5a 0xb3a5ad31
+ 0xaacebf8f 0x66ff7f33 0xa2340971 0xfb4c7e82
+ 0x8dd536d7 0xafd2021a 0x72aa9c6e 0x22df6952
+ 0x83c4b4fb 0xba515555 0x93eee8f0 0x22d0ed5a
+ 0xbec05586 0x83828f28 0xe0d7f930 0xac0f0199
+ 0xef6d76f9 0xf56ebdf8 0xf67323c9 0x8b805745
+ 0xce5902c0 0xfa2ce3da 0x10f836dd 0xe1ac6d97
+ 0xa0e415ea 0xbb7c32ad 0xc421f3b0 0x8166e898
+ 0x74e7a73c 0xf454b82a 0x631369b1 0xe30ed23f
+ 0xdaa1c75b 0xe7c9c6a7 0x5f33c375 0x99c05187
+ 0xf2d6e6ae 0xcd2045b8 0x92ff3009 0x15082015
+ 0xd1a1580e 0xdce25f9b 0x21984a75 0xa9be5388
+ 0x099a5372 0x3ab9bcfa 0xdb9069aa 0x49a99be6
+ 0x42a9ee0b 0xfe32d832 0x24e11ad3 0xd16f596b
+ 0xb95982cc 0x754ab1c8 0x42ffa128 0x539e823d
+ 0x28e0f976 0x262ddfc0 0x2a16e7ad 0x49b5acd9
+ 0x931f3def 0xdc419b84 0x8412cc3c 0x81056cd9
+ 0x91933e1f 0x57710b15 0xa55d2696 0x87d88724
+ 0xd4fedfdc 0xcc3825c6 0x397f382f 0x80f9b6ba
+ 0xcdd6d59f 0x24b984d8 0x8f1c5bcf 0x25bcef1d
+ 0x00dc603a 0x76fd94c2 0xa267a7dc 0xa6e90a6a
+ 0x5c5916d6 0x065a52cf 0xa28d3263 0x9b17b72d
+ 0xb8436b48 0x1b1c2391 0x1fda3395 0xa6cecbcb
+ 0xbc4ec502 0x1766b590 0x5945fbd6 0x6a124405
+ 0xf92d06f2 0xe24694b7 0xf6befd08 0x8266cf5c
+ 0x03ed670a 0x5f98be62 0xf27b7e2e 0x598cf22c
+ 0x2e855591 0x879815fb 0x153799c6 0x3820faf6
+ 0x3d3a2cc6 0xdbb6dece 0x1a3c46b2 0x5031bdda
+ 0x47894c03 0xe43661fe 0x7a6ee548 0xa5ca9779
+ 0x6aa9e105 0xbc8505a3 0xa03b860a 0x448faeb9
+ 0x367de4a9 0xc9779c7d 0x6535ad8c 0x4b7fcacc
+ 0xb2db5c10 0x0ab41ec6 0xe528ab90 0x5e6f03da
+ 0x98bc76d3 0xf38df42e 0xea59b039 0x1c2eaa28
+ 0xca30dac5 0xdb0eb8c6 0x60063860 0x18823f8d
+ 0x164e2f28 0x7cbbe080 0x70a12315 0xb08f44d9
+ 0x5fbb9453 0x4bc62738 0x9fa15ffc 0xe4033ca1
+ 0xc9dfbc13 0x58245d7d 0x588113aa 0x8f5a6ac8
+ 0x92588a60 0x26330c74 0xb2aaf0e3 0x24ada1ea
+ 0xa9e973ae 0x624b73e7 0x4ef961db 0x95ede155
+ 0xf2bb86ff 0x96bc79d9 0x95cd646b 0x1c3af453
+ 0xf60fa711 0x10905115 0x0e24b740 0x169bb227
+ 0x34cee6f0 0x990980db 0x18d8ace5 0xd4c87504
+ 0x29515d32 0x2e5d9c04 0x87dffa60 0x12e815d1
+ 0x021db8e9 0x2c5a42fd 0x6e3a1a13 0x88889ab5
+ 0x3bc915a6 0x608919c5 0xd310a970 0xea8f3218
+ 0x949f55bc 0x9ed7aadd 0x6d990157 0x181f1c2f
+ 0xa940df64 0xf3be8c39 0x7ca2e699 0x7b4f07f9
+ 0x89e83fee 0xe66b9493 0x54fc3d17 0xa63d2d46
+ 0xd5e835d5 0x910e0144 0xecf67025 0x1fa6a93a
+ 0xe692dbca 0x466af681 0xc2bc808c 0xbb4ebd60
+ 0x74d5c729 0xa283ad25 0x1e66fa23 0x6d372988
+ 0x753c9fcb 0x1742efdb 0x5b68cf15 0x372a0e33
+ 0xaa3a7ebd 0xa0e944d5 0x95d5cbb4 0x4fb6020b
+ 0xced927b0 0xb2afea78 0xd0646b72 0x1622fad4
+ 0x4672c6b6 0x736ae4f8 0x8d46a4db 0x0e6a432e
+ 0xe0a30a98 0x4c2bcf4f 0xd87acedd 0x19682d7a
+ 0xf97c025c 0x55d8feb3 0xbcd4d2ff 0x236c6f9f
+ 0x8ba0246d 0x42812f73 0x327636f5 0xc92cd30a
+ 0x08a69d9d 0xc735a946 0x82eca01f 0xda0753a0
+ 0x7077b1d1 0x17b05834 0xfa24bc02 0xf49f4473
+ 0x8f9ac6b4 0xa880c630 0xf7457b4d 0xd5f829e4
+ 0x25c49a99 0x1176a997 0xbb2d2009 0x61d35764
+ 0xa322c752 0x6ef3ae02 0x5faae6f8 0x9a52acf1
+ 0x19176f43 0x43843b07 0x14efc471 0xee474403
+ 0x319c4857 0xa19adcf0 0xc0a466e1 0x02db14ad
+ 0xb7f211f3 0x72aa6ca6 0x0eb9bffe 0x48a6d284
+ 0x9a93a2ee 0xac09fc5f 0x92a62c4f 0xd34f0271
+ 0xffb348c7 0xf229b6e2 0xc68ec1ca 0x19577dbc
+ 0x069a10bf 0xf64ac347 0xf7c3c848 0x81975294
+ 0x6376e550 0x93b53440 0x8bb17daa 0xc4c64c07
+ 0xcaeff293 0xd51497b0 0x33da3565 0xa73d5def
+ 0x4bf4dcde 0xfb470fcd 0xca7db864 0x7ef17022
+ 0x47567363 0xd8fb8d74 0xa68c3c72 0x8202e4f3
+ 0x75bf1798 0x16a70fd2 0xcc3b697f 0xab9a1075
+ 0x13f56ef3 0x269d0302 0xcb655a43 0xc9a4de88
+ 0xfb8363de 0xff40f36d 0xd2555489 0x647a7995
+ 0xfd8eda6e 0xa3958c9a 0x20e029b4 0xbed3e225
+ 0xa7df5f17 0x63bc3c1a 0x337ecc9d 0x6c329508
+ 0x786aa47e 0x1db5b093 0xc0acd73b 0xf9587237
+ 0x243e5d40 0xd3623c3a 0x338c4740 0xb672140e
+ 0x43640a9b 0xb7ef3f6a 0x44151074 0x749bcc46
+ 0xfa1f103b 0x0fefb19e 0x58855538 0x138ad276
+ 0x2641fd80 0x297d99d0 0xfaa63ba2 0x00b6f11a
+ 0x3793fb6b 0x124763a1 0x8b9419ac 0x56abf9eb
+ 0xdbf83419 0x43570571 0x37299cd8 0x8b201e62
+ 0xa4058fa5 0xb320e91b 0xbe7d40b7 0x4eca3b2d
+ 0x8519c155 0xf4b17021 0x9e4c572a 0xdc1f9e16
+ 0x39a589a3 0xa6cfc7a8 0x5b986910 0x64e150e7
+ 0x60b6f2c1 0x02bacd3f 0x2f3b5a5c 0xc6f453a8
+ 0x15a87a7e 0x76104a14 0xafa2ef63 0x2cd48dbe
+ 0x3c7abddc 0xd786ea5a 0x4f65867a 0x355cda38
+ 0x2ae03d9e 0x4f11f6be 0xfc0a0034 0xde4ea602
+ 0x21ff83ea 0x0f12d913 0xedf4da28 0xc96d8fd1
+ 0xd7e82c3c 0xfec63bdc 0x37a456d7 0x3007e18c
+ 0x091a47b6 0x82f1c641 0x82219cce 0x3e7e6993
+ 0x7b3a2115 0x0b8e1a02 0x40f88213 0xfa2f9c21
+ >;
--- /dev/null
+/*
+ * Copyright (c) <1995-2013>, Intel Corporation.
+ * All rights reserved.
+ *
+ * Redistribution. Redistribution and use in binary form, without modification, are
+ * permitted provided that the following conditions are met:
+ * .Redistributions must reproduce the above copyright notice and the following
+ * disclaimer in the documentation and/or other materials provided with the
+ * distribution.
+ * Neither the name of Intel Corporation nor the names of its suppliers may be used
+ * to endorse or promote products derived from this software without specific prior
+ * written permission.
+ * .No reverse engineering, decompilation, or disassembly of this software is
+ * permitted.
+ * ."Binary form" includes any format commonly used for electronic conveyance
+ * which is a reversible, bit-exact translation of binary representation to ASCII or
+ * ISO text, for example, "uuencode."
+ *
+ * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x17>;
+intel,date-code = <0x01092013>;
+intel,processor-signature = <0x000306a9>;
+intel,checksum = <0x3546450b>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The 48-byte public header is omitted. */
+data = <
+ 0x00000000 0x000000a1 0x00020001 0x00000017
+ 0x00000000 0x00000000 0x20130107 0x00000a61
+ 0x00000001 0x000306a9 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x86c5b0d4 0xf6978804 0x7f4f5870 0x6319dc3c
+ 0xbb3b7d61 0x33cf9075 0xe8424658 0xf611a357
+ 0x5a3401db 0x42caecce 0xb4d8e75e 0xe6dbaf24
+ 0x7861b35f 0x6bd717bc 0x23b9b731 0x82ec1ac8
+ 0x20337b64 0x5396dbf1 0x59973bff 0x724bc7e9
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+ 0x39f77be7 0xa21b48c1 0x1ded01c1 0x5cf98c5f
+ 0x6e23d207 0xd7e7dadf 0x5932ed1a 0x2a729061
+ 0x29a89f4a 0xac0e8447 0x01ff4205 0x8b1456c6
+ 0x3fba0156 0x658c03f7 0x5c69f968 0xf6570582
+ 0x21bb0145 0x8683bf5b 0xa4b6eba5 0x4ccfe5cb
+ 0xd202898c 0xbd2411cc 0xc2fc702a 0x5c39b695
+ 0x87584ccf 0xeae3c735 0xc472b6f9 0x4249f637
+ 0x3fa89c0e 0xce5a8bd7 0xbb28138b 0xc080ecb1
+ 0x9cbf1916 0xd70424e9 0x75cc4ed1 0xa575f3e9
+ 0x1c571f68 0xe2906205 0xc26520cf 0xf9c1fc8e
+ 0x61c982de 0x1af6cfcc 0xaf397c9a 0x46830771
+ 0x623d98bb 0xda7b52fa 0x5a3c57d3 0xfa35d2f0
+ 0x4783df19 0x6ad07325 0x487406f4 0x3fae5152
+ 0x189137cb 0xd98a644e 0x17ffe880 0xeb6aa9f7
+ 0x67184e3e 0xe475734b 0x0f1113c2 0x39a4df47
+ 0xbf8f6ec9 0xe13a4d8b 0x63ec02f5 0xdfe7d75d
+ 0x1379034c 0x5db7314a 0xa9d9ad3e 0xfaaed8f2
+ 0xf0fb6074 0x12f27b84 0xc97a92bb 0xae5e3bb7
+ 0x5f7fc2bf 0x00cbc1f7 0x9360a4d9 0x3632ba04
+ 0xad044c83 0xeda13ec1 0x34a214c0 0xcf9c972a
+ 0x96352243 0xf1a35357 0x2d77bc30 0x8485bbad
+ 0x67fbaa99 0x8035b1a5 0x8ca763c0 0x109d7887
+ 0xa1c35cd8 0xdc79e308 0x4495404d 0x64419226
+ 0xacdcea08 0x9545c0ef 0x5493e09e 0x7fe16336
+ 0x41381aa2 0x5c344f46 0xb40cab9f 0xc43951c4
+ 0xd86e52a5 0xb141d934 0xd78efcff 0xf37ec320
+ 0xc184a45b 0xf4a57954 0xc8aed0bd 0xe602c15a
+ 0x71a6b48b 0xce837428 0x02733706 0xc4a4a044
+ 0xa75efb97 0xcb63d62e 0xd0580b5a 0xce499087
+ 0xc12bf4ca 0x9c995345 0x1d8adfbc 0xe62fd60e
+ 0xccbf5412 0x6161f8d0 0x64268e34 0x565d066b
+ 0x1896b63f 0x838f8f2a 0x1e314a00 0xac470276
+ 0x1879cfdf 0x4702d7f9 0x83b4d777 0x81fcb068
+ 0x1b6da94d 0xd075ed01 0x3c7734e8 0x56389a0b
+ 0x0743b9cd 0xb6b0bf0d 0x63107ab9 0x193172bc
+ 0xc7b84c8e 0x982ce2aa 0xb8e387a6 0xc264a4b0
+ 0x2ac6c802 0xb89ea335 0x052332a4 0x49932ecc
+ 0xb940f808 0xa7a09330 0x19f3f49d 0x7aef6b5a
+ 0x201d8ed0 0xf29aac4b 0x8ae2ac0f 0x998c1ca7
+ 0x665c3927 0xab4ef641 0xf136710d 0x9644ee9b
+ 0x34efae96 0x4c596035 0x8cfe8b3b 0x5d9f742e
+ 0xab2c63ca 0x017d864d 0xd0604d6e 0xab24eee0
+ 0x75916a9a 0xad0d1167 0xbeb47775 0x6ac822d1
+ 0x776907aa 0x9e9377f2 0x438c5d81 0xd70e9964
+ 0x1c09c914 0xab90e5cf 0x31cee523 0x26ba6ea7
+ 0xef00781d 0x622b886d 0x36a54031 0x88b1221c
+ 0x666333f5 0x60e1c93e 0x5e4d0e0a 0x3ee6ff69
+ 0xceb4c76b 0xa5deb4f8 0x0668ced8 0x30225378
+ 0x6697cf37 0xc5d9661d 0x089eab85 0x7684a876
+ 0x018a81af 0x221a7fb2 0x31d80de0 0x9f18ae90
+ 0xa29c9af0 0xc3e2b00f 0xda0edbab 0x7ee9cd2a
+ 0x3ab0f88e 0x02c58228 0x606fa7aa 0x7776cb0a
+ 0x4e8ad99c 0x3b527469 0x58123d62 0x4ce428d2
+ 0xee91a210 0x466ba2cc 0x043c57b9 0xaf7bdd43
+ 0x98e76fee 0x8f3eac1b 0x00dffd6c 0x6fcb1c6a
+ 0x5cb90573 0x485d4505 0x0df5418a 0x26eafe35
+ 0x0faddf3e 0x4e972930 0xe113c823 0xe45944d1
+ 0xa646077f 0xc1708ae5 0x6ba07c20 0xc7e4e234
+ 0xc6754ed5 0xbd6e85aa 0x8cc1756e 0x02afda29
+ 0x72809597 0x75b6f5a1 0x61141874 0x1774047f
+ 0x7a10afed 0xfac2c4ad 0x42cf5c99 0x24f0350e
+ 0x042f2864 0xfab55b67 0xc8ead5bc 0x914e9512
+ 0x77c8ef6b 0x8369aeb1 0x71bc947f 0x0c6b49d8
+ 0x8ddd0513 0x028ad10d 0x99a1b28f 0xe6cfbdc8
+ 0x7978b4a6 0x3ebbade8 0x9985f5cf 0x431f42f1
+ 0x004372b2 0x18b67f68 0x20111c21 0xbb6f77ff
+ 0x1783b030 0xa045d7d1 0x0e9c7e09 0x3ccbd95f
+ 0x0b84a2ed 0xf0ee3325 0x63f2e126 0x5ec4c67b
+ 0x2ca782cc 0xcaf20d04 0x8b59d515 0x3212aa33
+ 0x335ca0c3 0x6f9e0cdd 0x4d4bf189 0x44d2fa0c
+ 0x5abe9396 0x492794ee 0x10dcfcb1 0x9acda9bd
+ 0xe8aa2803 0x3f1b9605 0x3e2ecb5a 0x971bfa8a
+ 0xcbf141d2 0x0afafe10 0x2fc906a6 0xefad20c0
+ 0x9e922581 0xe69142cc 0xc9c0ba82 0xc069e640
+ 0xb99c08b6 0x4b62ca1f 0xf3c5767a 0x6ab088c7
+ 0x8f0f0c0b 0x6726f64a 0x9711a3cd 0x46462571
+ 0x3a58350e 0xa2561911 0xe24dfdfe 0x97443fdc
+ 0xf80540be 0x069978bf 0xb38a359b 0x8e574f62
+ 0x69aea75c 0xdc753fcb 0x2a74002c 0xced027b4
+ 0xda993254 0x03409b83 0xf827331d 0x75fb3271
+ 0x01ad839d 0x68520842 0xca65c45c 0x1a3db5a0
+ 0x91d37dd3 0x6168c0fb 0x935f5a08 0x002007c3
+ 0x42eb4760 0xdab3a804 0x72a6297e 0x905c32d9
+ 0x81abcfa9 0x1b21d04a 0x5a1289ae 0x424e7183
+ 0xc207906c 0x31fe9134 0x5eb2e5af 0xc9253fc7
+ 0xc32be24f 0xe5474cbd 0xeff6e1b0 0x710e5e69
+ 0xe6c4c538 0x96b5f1de 0x2abc9c35 0xddbd1a92
+ 0x8aca40d7 0xe359c238 0x954718f4 0x18b157e5
+ 0xeeed790e 0x6948a963 0x24e70bfb 0x4d681547
+ 0xf68369a7 0x5b54409a 0x1f0b787a 0xc2610047
+ 0x0f8bd269 0xd7c8c154 0x9dee62d9 0xd4738ed8
+ 0x1a66c6b1 0x5bad5a5b 0xb110311a 0xfaec6802
+ 0x6b750f2d 0xcbf8d0e0 0x11edaf4b 0xf64a07bb
+ 0x422e7c15 0xb1732663 0x1ff404f0 0x2d5052b0
+ 0x6e45356c 0x7e2201e8 0x7c5ebcd1 0x1cb4425a
+ 0xb1539a64 0xa2e4459f 0xcf1ade8a 0xfc476473
+ 0xf4147deb 0x2afbdd77 0xff01fabc 0x6597408a
+ 0x0951220b 0x6750f3ec 0x0a242763 0xf3d71c05
+ 0x84cb1c26 0xdb7a81bd 0x7aea1a5d 0x7e719a48
+ 0xc5c12fe1 0x0ce2e988 0x29ecc6f0 0x5ede901a
+ 0xda8399b1 0x31c05d6b 0xe1956aff 0x59ed7c3d
+ 0x60832637 0x9bcb7cac 0x63c530d1 0x14c677de
+ 0x9225ed18 0x065327c9 0xd1ff6a0e 0x5516517e
+ 0x53c6f5c2 0xed5983cf 0xaa1d18b9 0xbe300d7f
+ 0xadc525a7 0x07ea81b6 0xfc517a09 0x4ead3f86
+ 0x45435f41 0x2efa58df 0x02348ebc 0x30ed6783
+ 0x190b4fb9 0x85c55d6e 0xc9ed8896 0x416ee113
+ 0x9b3536d9 0x30577cc0 0xbc4b88c8 0xcda59612
+ 0xdfe2bd89 0xd60cde71 0x98843881 0xcc1f32f2
+ 0x18b3f643 0x671a14ca 0xd6482a47 0xac6a7d38
+ 0x1897da16 0x91b6fcb3 0xf199bb35 0xd38c00ba
+ 0xa8c946b6 0x52a1ad37 0xd38ed2d4 0xa1d6f81d
+ 0x5af6865b 0xebdb858f 0xb844b110 0x53201ea2
+ 0x08870945 0x10c869de 0x19849613 0xdb35d3ed
+ 0xd68ebd6e 0x1056fd48 0xf1a0e305 0xe3982ebd
+ 0x6f7cc391 0x5956374a 0xf414a5a2 0x325119ab
+ 0x99ee1f96 0x6f044bd9 0x8374805b 0xb55c366c
+ 0xa2c77051 0x68f199e5 0xd36a9714 0x878f847b
+ 0xec0394ae 0x86d0584b 0xf4df66b9 0x451cd039
+ 0xf4de06ae 0x35dd0554 0x818a342f 0xeefdbfc9
+ 0x5b4e9edd 0x22d9313a 0x3b710d60 0x6deaeb4c
+ 0xa9e26512 0x98d31867 0x3c2c2d61 0x7eb5ce41
+ 0x40890db6 0x7a3aa660 0x3ef4f306 0x7322881f
+ 0x49dac4d5 0x96efe685 0x27bb7f49 0xbb955283
+ 0x79c5f2b7 0xff599c28 0x28ee7f5e 0x9f324b73
+ 0x45edb7cf 0x39a8b79c 0xd0919c6e 0xe149b29d
+ 0x62f5f82e 0xebcfa23e 0xd4d68937 0x54270090
+ 0x958af0d4 0xa1e4e799 0xaf68ac19 0x82a84f4e
+ 0x50f67b84 0xd5e59629 0xf5fdf24c 0xab1d63c5
+ 0x30835807 0x431fce5f 0xe5f96f4d 0x3f6b4802
+ 0x14010be8 0xdca45ae5 0xc82709af 0xff76ce2c
+ 0x8b222c22 0x73a2d948 0xa8d59cea 0x8c31849e
+ 0x469c2e5f 0x3777ee84 0x5fdfa5da 0x02ef9bb2
+ 0x792d3194 0xbed63f21 0x0b6dc5f1 0xc9d7fe08
+ 0x6df7883d 0x366566cf 0xef772769 0x37826465
+ 0x1cdc3086 0xa69ff7b6 0x235012ea 0x292f7e75
+ 0x30bdd0fd 0xffdc9df1 0x95c6d570 0xec206204
+ 0xc6cd42cb 0xc0d6dfd9 0xb7a16b71 0x17fa527e
+ 0x295f2c79 0x990f9820 0x8b8f447d 0x193f9ad1
+ 0xebddb2af 0x5dd532eb 0xf1bbd8e8 0x3444a3f4
+ 0x18ccce93 0x05edeb4f 0xc4a6b935 0xba37aab0
+ 0x96076ba4 0x250dc2f7 0xc4093548 0x030e777d
+ 0x7ea40933 0x8da7b1dd 0x59c0b79f 0x807d437c
+ 0xf5233ddf 0x54c1983f 0xfc18771b 0xe74b85f0
+ 0xdbd725b5 0x70cdd153 0x4ffe300c 0xfda4bdae
+ 0xf4ac75d2 0x91c4e15a 0x34d92b97 0x16356a79
+ >;
#ifndef _X86_ARCH_GPIO_H_
#define _X86_ARCH_GPIO_H_
-struct ich6_bank_platdata {
- uint32_t base_addr;
- const char *bank_name;
-};
-
#endif /* _X86_ARCH_GPIO_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2014, Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_GPIO_H_
+#define _X86_ARCH_GPIO_H_
+
+#endif /* _X86_ARCH_GPIO_H_ */
--- /dev/null
+/*
+ * From Coreboot src/southbridge/intel/bd82x6x/me.h
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_INTEL_ME_H
+#define _ASM_INTEL_ME_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+#define ME_RETRY 100000 /* 1 second */
+#define ME_DELAY 10 /* 10 us */
+
+/*
+ * Management Engine PCI registers
+ */
+
+#define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */
+#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */
+
+#define PCI_ME_HFS 0x40
+#define ME_HFS_CWS_RESET 0
+#define ME_HFS_CWS_INIT 1
+#define ME_HFS_CWS_REC 2
+#define ME_HFS_CWS_NORMAL 5
+#define ME_HFS_CWS_WAIT 6
+#define ME_HFS_CWS_TRANS 7
+#define ME_HFS_CWS_INVALID 8
+#define ME_HFS_STATE_PREBOOT 0
+#define ME_HFS_STATE_M0_UMA 1
+#define ME_HFS_STATE_M3 4
+#define ME_HFS_STATE_M0 5
+#define ME_HFS_STATE_BRINGUP 6
+#define ME_HFS_STATE_ERROR 7
+#define ME_HFS_ERROR_NONE 0
+#define ME_HFS_ERROR_UNCAT 1
+#define ME_HFS_ERROR_IMAGE 3
+#define ME_HFS_ERROR_DEBUG 4
+#define ME_HFS_MODE_NORMAL 0
+#define ME_HFS_MODE_DEBUG 2
+#define ME_HFS_MODE_DIS 3
+#define ME_HFS_MODE_OVER_JMPR 4
+#define ME_HFS_MODE_OVER_MEI 5
+#define ME_HFS_BIOS_DRAM_ACK 1
+#define ME_HFS_ACK_NO_DID 0
+#define ME_HFS_ACK_RESET 1
+#define ME_HFS_ACK_PWR_CYCLE 2
+#define ME_HFS_ACK_S3 3
+#define ME_HFS_ACK_S4 4
+#define ME_HFS_ACK_S5 5
+#define ME_HFS_ACK_GBL_RESET 6
+#define ME_HFS_ACK_CONTINUE 7
+
+struct me_hfs {
+ u32 working_state:4;
+ u32 mfg_mode:1;
+ u32 fpt_bad:1;
+ u32 operation_state:3;
+ u32 fw_init_complete:1;
+ u32 ft_bup_ld_flr:1;
+ u32 update_in_progress:1;
+ u32 error_code:4;
+ u32 operation_mode:4;
+ u32 reserved:4;
+ u32 boot_options_present:1;
+ u32 ack_data:3;
+ u32 bios_msg_ack:4;
+} __packed;
+
+#define PCI_ME_UMA 0x44
+
+struct me_uma {
+ u32 size:6;
+ u32 reserved_1:10;
+ u32 valid:1;
+ u32 reserved_0:14;
+ u32 set_to_one:1;
+} __packed;
+
+#define PCI_ME_H_GS 0x4c
+#define ME_INIT_DONE 1
+#define ME_INIT_STATUS_SUCCESS 0
+#define ME_INIT_STATUS_NOMEM 1
+#define ME_INIT_STATUS_ERROR 2
+
+struct me_did {
+ u32 uma_base:16;
+ u32 reserved:8;
+ u32 status:4;
+ u32 init_done:4;
+} __packed;
+
+#define PCI_ME_GMES 0x48
+#define ME_GMES_PHASE_ROM 0
+#define ME_GMES_PHASE_BUP 1
+#define ME_GMES_PHASE_UKERNEL 2
+#define ME_GMES_PHASE_POLICY 3
+#define ME_GMES_PHASE_MODULE 4
+#define ME_GMES_PHASE_UNKNOWN 5
+#define ME_GMES_PHASE_HOST 6
+
+struct me_gmes {
+ u32 bist_in_prog:1;
+ u32 icc_prog_sts:2;
+ u32 invoke_mebx:1;
+ u32 cpu_replaced_sts:1;
+ u32 mbp_rdy:1;
+ u32 mfs_failure:1;
+ u32 warm_rst_req_for_df:1;
+ u32 cpu_replaced_valid:1;
+ u32 reserved_1:2;
+ u32 fw_upd_ipu:1;
+ u32 reserved_2:4;
+ u32 current_state:8;
+ u32 current_pmevent:4;
+ u32 progress_code:4;
+} __packed;
+
+#define PCI_ME_HERES 0xbc
+#define PCI_ME_EXT_SHA1 0x00
+#define PCI_ME_EXT_SHA256 0x02
+#define PCI_ME_HER(x) (0xc0+(4*(x)))
+
+struct me_heres {
+ u32 extend_reg_algorithm:4;
+ u32 reserved:26;
+ u32 extend_feature_present:1;
+ u32 extend_reg_valid:1;
+} __packed;
+
+/*
+ * Management Engine MEI registers
+ */
+
+#define MEI_H_CB_WW 0x00
+#define MEI_H_CSR 0x04
+#define MEI_ME_CB_RW 0x08
+#define MEI_ME_CSR_HA 0x0c
+
+struct mei_csr {
+ u32 interrupt_enable:1;
+ u32 interrupt_status:1;
+ u32 interrupt_generate:1;
+ u32 ready:1;
+ u32 reset:1;
+ u32 reserved:3;
+ u32 buffer_read_ptr:8;
+ u32 buffer_write_ptr:8;
+ u32 buffer_depth:8;
+} __packed;
+
+#define MEI_ADDRESS_CORE 0x01
+#define MEI_ADDRESS_AMT 0x02
+#define MEI_ADDRESS_RESERVED 0x03
+#define MEI_ADDRESS_WDT 0x04
+#define MEI_ADDRESS_MKHI 0x07
+#define MEI_ADDRESS_ICC 0x08
+#define MEI_ADDRESS_THERMAL 0x09
+
+#define MEI_HOST_ADDRESS 0
+
+struct mei_header {
+ u32 client_address:8;
+ u32 host_address:8;
+ u32 length:9;
+ u32 reserved:6;
+ u32 is_complete:1;
+} __packed;
+
+#define MKHI_GROUP_ID_CBM 0x00
+#define MKHI_GROUP_ID_FWCAPS 0x03
+#define MKHI_GROUP_ID_MDES 0x08
+#define MKHI_GROUP_ID_GEN 0xff
+
+#define MKHI_GLOBAL_RESET 0x0b
+
+#define MKHI_FWCAPS_GET_RULE 0x02
+
+#define MKHI_MDES_ENABLE 0x09
+
+#define MKHI_GET_FW_VERSION 0x02
+#define MKHI_END_OF_POST 0x0c
+#define MKHI_FEATURE_OVERRIDE 0x14
+
+struct mkhi_header {
+ u32 group_id:8;
+ u32 command:7;
+ u32 is_response:1;
+ u32 reserved:8;
+ u32 result:8;
+} __packed;
+
+struct me_fw_version {
+ u16 code_minor;
+ u16 code_major;
+ u16 code_build_number;
+ u16 code_hot_fix;
+ u16 recovery_minor;
+ u16 recovery_major;
+ u16 recovery_build_number;
+ u16 recovery_hot_fix;
+} __packed;
+
+
+#define HECI_EOP_STATUS_SUCCESS 0x0
+#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
+
+#define CBM_RR_GLOBAL_RESET 0x01
+
+#define GLOBAL_RESET_BIOS_MRC 0x01
+#define GLOBAL_RESET_BIOS_POST 0x02
+#define GLOBAL_RESET_MEBX 0x03
+
+struct me_global_reset {
+ u8 request_origin;
+ u8 reset_type;
+} __packed;
+
+enum me_bios_path {
+ ME_NORMAL_BIOS_PATH,
+ ME_S3WAKE_BIOS_PATH,
+ ME_ERROR_BIOS_PATH,
+ ME_RECOVERY_BIOS_PATH,
+ ME_DISABLE_BIOS_PATH,
+ ME_FIRMWARE_UPDATE_BIOS_PATH,
+};
+
+struct __packed mbp_fw_version_name {
+ u32 major_version:16;
+ u32 minor_version:16;
+ u32 hotfix_version:16;
+ u32 build_version:16;
+};
+
+struct __packed mbp_icc_profile {
+ u8 num_icc_profiles;
+ u8 icc_profile_soft_strap;
+ u8 icc_profile_index;
+ u8 reserved;
+ u32 register_lock_mask[3];
+};
+
+struct __packed mefwcaps_sku {
+ u32 full_net:1;
+ u32 std_net:1;
+ u32 manageability:1;
+ u32 small_business:1;
+ u32 l3manageability:1;
+ u32 intel_at:1;
+ u32 intel_cls:1;
+ u32 reserved:3;
+ u32 intel_mpc:1;
+ u32 icc_over_clocking:1;
+ u32 pavp:1;
+ u32 reserved_1:4;
+ u32 ipv6:1;
+ u32 kvm:1;
+ u32 och:1;
+ u32 vlan:1;
+ u32 tls:1;
+ u32 reserved_4:1;
+ u32 wlan:1;
+ u32 reserved_5:8;
+};
+
+struct __packed tdt_state_flag {
+ u16 lock_state:1;
+ u16 authenticate_module:1;
+ u16 s3authentication:1;
+ u16 flash_wear_out:1;
+ u16 flash_variable_security:1;
+ u16 wwan3gpresent:1;
+ u16 wwan3goob:1;
+ u16 reserved:9;
+};
+
+struct __packed tdt_state_info {
+ u8 state;
+ u8 last_theft_trigger;
+ struct tdt_state_flag flags;
+};
+
+struct __packed platform_type_rule_data {
+ u32 platform_target_usage_type:4;
+ u32 platform_target_market_type:2;
+ u32 super_sku:1;
+ u32 reserved:1;
+ u32 intel_me_fw_image_type:4;
+ u32 platform_brand:4;
+ u32 reserved_1:16;
+};
+
+struct __packed mbp_fw_caps {
+ struct mefwcaps_sku fw_capabilities;
+ u8 available;
+};
+
+struct __packed mbp_rom_bist_data {
+ u16 device_id;
+ u16 fuse_test_flags;
+ u32 umchid[4];
+};
+
+struct __packed mbp_platform_key {
+ u32 key[8];
+};
+
+struct __packed mbp_plat_type {
+ struct platform_type_rule_data rule_data;
+ u8 available;
+};
+
+struct __packed me_bios_payload {
+ struct mbp_fw_version_name fw_version_name;
+ struct mbp_fw_caps fw_caps_sku;
+ struct mbp_rom_bist_data rom_bist_data;
+ struct mbp_platform_key platform_key;
+ struct mbp_plat_type fw_plat_type;
+ struct mbp_icc_profile icc_profile;
+ struct tdt_state_info at_state;
+ u32 mfsintegrity;
+};
+
+struct __packed mbp_header {
+ u32 mbp_size:8;
+ u32 num_entries:8;
+ u32 rsvd:16;
+};
+
+struct __packed mbp_item_header {
+ u32 app_id:8;
+ u32 item_id:8;
+ u32 length:8;
+ u32 rsvd:8;
+};
+
+struct __packed me_fwcaps {
+ u32 id;
+ u8 length;
+ struct mefwcaps_sku caps_sku;
+ u8 reserved[3];
+};
+
+/* Defined in me_status.c for both romstage and ramstage */
+void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
+
+void intel_early_me_status(void);
+int intel_early_me_init(void);
+int intel_early_me_uma_size(void);
+int intel_early_me_init_done(u8 status);
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MICROCODE_H
+#define __ASM_ARCH_MICROCODE_H
+
+/**
+ * microcode_update_intel() - Apply microcode updates
+ *
+ * Applies any microcode updates in the device tree.
+ *
+ * @return 0 if OK, -EEXIST if the updates were already applied, -ENOENT if
+ * not updates were found, -EINVAL if an update was invalid
+ */
+int microcode_update_intel(void);
+
+#endif
--- /dev/null
+/*
+ * From Coreboot file of the same name
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_MODEL_206AX_H
+#define _ASM_ARCH_MODEL_206AX_H
+
+/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
+#define SANDYBRIDGE_BCLK 100
+
+#define CPUID_VMX (1 << 5)
+#define CPUID_SMX (1 << 6)
+#define MSR_FEATURE_CONFIG 0x13c
+#define MSR_FLEX_RATIO 0x194
+#define FLEX_RATIO_LOCK (1 << 20)
+#define FLEX_RATIO_EN (1 << 16)
+#define IA32_PLATFORM_DCA_CAP 0x1f8
+#define IA32_MISC_ENABLE 0x1a0
+#define MSR_TEMPERATURE_TARGET 0x1a2
+#define IA32_PERF_CTL 0x199
+#define IA32_THERM_INTERRUPT 0x19b
+#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
+#define ENERGY_POLICY_PERFORMANCE 0
+#define ENERGY_POLICY_NORMAL 6
+#define ENERGY_POLICY_POWERSAVE 15
+#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
+#define MSR_LT_LOCK_MEMORY 0x2e7
+#define IA32_MC0_STATUS 0x401
+
+#define MSR_PIC_MSG_CONTROL 0x2e
+#define PLATFORM_INFO_SET_TDP (1 << 29)
+
+#define MSR_MISC_PWR_MGMT 0x1aa
+#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
+#define MSR_TURBO_RATIO_LIMIT 0x1ad
+#define MSR_POWER_CTL 0x1fc
+
+#define MSR_PKGC3_IRTL 0x60a
+#define MSR_PKGC6_IRTL 0x60b
+#define MSR_PKGC7_IRTL 0x60c
+#define IRTL_VALID (1 << 15)
+#define IRTL_1_NS (0 << 10)
+#define IRTL_32_NS (1 << 10)
+#define IRTL_1024_NS (2 << 10)
+#define IRTL_32768_NS (3 << 10)
+#define IRTL_1048576_NS (4 << 10)
+#define IRTL_33554432_NS (5 << 10)
+#define IRTL_RESPONSE_MASK (0x3ff)
+
+/* long duration in low dword, short duration in high dword */
+#define PKG_POWER_LIMIT_MASK 0x7fff
+#define PKG_POWER_LIMIT_EN (1 << 15)
+#define PKG_POWER_LIMIT_CLAMP (1 << 16)
+#define PKG_POWER_LIMIT_TIME_SHIFT 17
+#define PKG_POWER_LIMIT_TIME_MASK 0x7f
+
+#define MSR_PP0_CURRENT_CONFIG 0x601
+#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */
+#define MSR_PP1_CURRENT_CONFIG 0x602
+#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */
+#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */
+#define MSR_PKG_POWER_SKU_UNIT 0x606
+#define MSR_PKG_POWER_SKU 0x614
+
+#define IVB_CONFIG_TDP_MIN_CPUID 0x306a2
+#define MSR_CONFIG_TDP_NOMINAL 0x648
+#define MSR_CONFIG_TDP_LEVEL1 0x649
+#define MSR_CONFIG_TDP_LEVEL2 0x64a
+#define MSR_CONFIG_TDP_CONTROL 0x64b
+#define MSR_TURBO_ACTIVATION_RATIO 0x64c
+
+/* P-state configuration */
+#define PSS_MAX_ENTRIES 8
+#define PSS_RATIO_STEP 2
+#define PSS_LATENCY_TRANSITION 10
+#define PSS_LATENCY_BUSMASTER 10
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * From Coreboot src/southbridge/intel/bd82x6x/pch.h
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_PCH_H
+#define _ASM_ARCH_PCH_H
+
+#include <pci.h>
+
+#define DEFAULT_GPIOBASE 0x0480
+#define DEFAULT_PMBASE 0x0500
+
+#define SMBUS_IO_BASE 0x0400
+
+#define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0)
+#define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0)
+#define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0)
+#define PCH_ME_DEV PCI_BDF(0, 0x16, 0)
+#define PCH_PCIE_DEV_SLOT 28
+
+#define PCH_DEV PCI_BDF(0, 0, 0)
+#define PCH_VIDEO_DEV PCI_BDF(0, 2, 0)
+
+/* PCI Configuration Space (D31:F0): LPC */
+#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
+
+#define GEN_PMCON_1 0xa0
+#define GEN_PMCON_2 0xa2
+#define GEN_PMCON_3 0xa4
+#define ETR3 0xac
+#define ETR3_CWORWRE (1 << 18)
+#define ETR3_CF9GR (1 << 20)
+
+#define PMBASE 0x40
+#define ACPI_CNTL 0x44
+#define BIOS_CNTL 0xDC
+#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
+#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
+#define GPIO_ROUT 0xb8
+
+#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
+#define LPC_EN 0x82 /* LPC IF Enables Register */
+#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
+#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
+#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
+#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
+#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
+#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
+#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
+#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
+#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
+#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */
+#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
+#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
+#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
+#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
+#define LPC_GENX_DEC(x) (0x84 + 4 * (x))
+
+/* PCI Configuration Space (D31:F3): SMBus */
+#define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3)
+#define SMB_BASE 0x20
+#define HOSTC 0x40
+#define SMB_RCV_SLVA 0x09
+
+/* HOSTC bits */
+#define I2C_EN (1 << 2)
+#define SMB_SMI_EN (1 << 1)
+#define HST_EN (1 << 0)
+
+/* SMBus I/O bits. */
+#define SMBHSTSTAT 0x0
+#define SMBHSTCTL 0x2
+#define SMBHSTCMD 0x3
+#define SMBXMITADD 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBBLKDAT 0x7
+#define SMBTRNSADD 0x9
+#define SMBSLVDATA 0xa
+#define SMLINK_PIN_CTL 0xe
+#define SMBUS_PIN_CTL 0xf
+
+#define SMBUS_TIMEOUT (10 * 1000 * 100)
+
+
+/* Root Complex Register Block */
+#define DEFAULT_RCBA 0xfed1c000
+#define RCB_REG(reg) (DEFAULT_RCBA + (reg))
+
+#define PCH_RCBA_BASE 0xf0
+
+#define VCH 0x0000 /* 32bit */
+#define VCAP1 0x0004 /* 32bit */
+#define VCAP2 0x0008 /* 32bit */
+#define PVC 0x000c /* 16bit */
+#define PVS 0x000e /* 16bit */
+
+#define V0CAP 0x0010 /* 32bit */
+#define V0CTL 0x0014 /* 32bit */
+#define V0STS 0x001a /* 16bit */
+
+#define V1CAP 0x001c /* 32bit */
+#define V1CTL 0x0020 /* 32bit */
+#define V1STS 0x0026 /* 16bit */
+
+#define RCTCL 0x0100 /* 32bit */
+#define ESD 0x0104 /* 32bit */
+#define ULD 0x0110 /* 32bit */
+#define ULBA 0x0118 /* 64bit */
+
+#define RP1D 0x0120 /* 32bit */
+#define RP1BA 0x0128 /* 64bit */
+#define RP2D 0x0130 /* 32bit */
+#define RP2BA 0x0138 /* 64bit */
+#define RP3D 0x0140 /* 32bit */
+#define RP3BA 0x0148 /* 64bit */
+#define RP4D 0x0150 /* 32bit */
+#define RP4BA 0x0158 /* 64bit */
+#define HDD 0x0160 /* 32bit */
+#define HDBA 0x0168 /* 64bit */
+#define RP5D 0x0170 /* 32bit */
+#define RP5BA 0x0178 /* 64bit */
+#define RP6D 0x0180 /* 32bit */
+#define RP6BA 0x0188 /* 64bit */
+
+#define RPC 0x0400 /* 32bit */
+#define RPFN 0x0404 /* 32bit */
+
+#define TRSR 0x1e00 /* 8bit */
+#define TRCR 0x1e10 /* 64bit */
+#define TWDR 0x1e18 /* 64bit */
+
+#define IOTR0 0x1e80 /* 64bit */
+#define IOTR1 0x1e88 /* 64bit */
+#define IOTR2 0x1e90 /* 64bit */
+#define IOTR3 0x1e98 /* 64bit */
+
+#define TCTL 0x3000 /* 8bit */
+
+#define NOINT 0
+#define INTA 1
+#define INTB 2
+#define INTC 3
+#define INTD 4
+
+#define DIR_IDR 12 /* Interrupt D Pin Offset */
+#define DIR_ICR 8 /* Interrupt C Pin Offset */
+#define DIR_IBR 4 /* Interrupt B Pin Offset */
+#define DIR_IAR 0 /* Interrupt A Pin Offset */
+
+#define PIRQA 0
+#define PIRQB 1
+#define PIRQC 2
+#define PIRQD 3
+#define PIRQE 4
+#define PIRQF 5
+#define PIRQG 6
+#define PIRQH 7
+
+/* IO Buffer Programming */
+#define IOBPIRI 0x2330
+#define IOBPD 0x2334
+#define IOBPS 0x2338
+#define IOBPS_RW_BX ((1 << 9)|(1 << 10))
+#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
+#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
+
+#define D31IP 0x3100 /* 32bit */
+#define D31IP_TTIP 24 /* Thermal Throttle Pin */
+#define D31IP_SIP2 20 /* SATA Pin 2 */
+#define D31IP_SMIP 12 /* SMBUS Pin */
+#define D31IP_SIP 8 /* SATA Pin */
+#define D30IP 0x3104 /* 32bit */
+#define D30IP_PIP 0 /* PCI Bridge Pin */
+#define D29IP 0x3108 /* 32bit */
+#define D29IP_E1P 0 /* EHCI #1 Pin */
+#define D28IP 0x310c /* 32bit */
+#define D28IP_P8IP 28 /* PCI Express Port 8 */
+#define D28IP_P7IP 24 /* PCI Express Port 7 */
+#define D28IP_P6IP 20 /* PCI Express Port 6 */
+#define D28IP_P5IP 16 /* PCI Express Port 5 */
+#define D28IP_P4IP 12 /* PCI Express Port 4 */
+#define D28IP_P3IP 8 /* PCI Express Port 3 */
+#define D28IP_P2IP 4 /* PCI Express Port 2 */
+#define D28IP_P1IP 0 /* PCI Express Port 1 */
+#define D27IP 0x3110 /* 32bit */
+#define D27IP_ZIP 0 /* HD Audio Pin */
+#define D26IP 0x3114 /* 32bit */
+#define D26IP_E2P 0 /* EHCI #2 Pin */
+#define D25IP 0x3118 /* 32bit */
+#define D25IP_LIP 0 /* GbE LAN Pin */
+#define D22IP 0x3124 /* 32bit */
+#define D22IP_KTIP 12 /* KT Pin */
+#define D22IP_IDERIP 8 /* IDE-R Pin */
+#define D22IP_MEI2IP 4 /* MEI #2 Pin */
+#define D22IP_MEI1IP 0 /* MEI #1 Pin */
+#define D20IP 0x3128 /* 32bit */
+#define D20IP_XHCIIP 0
+#define D31IR 0x3140 /* 16bit */
+#define D30IR 0x3142 /* 16bit */
+#define D29IR 0x3144 /* 16bit */
+#define D28IR 0x3146 /* 16bit */
+#define D27IR 0x3148 /* 16bit */
+#define D26IR 0x314c /* 16bit */
+#define D25IR 0x3150 /* 16bit */
+#define D22IR 0x315c /* 16bit */
+#define D20IR 0x3160 /* 16bit */
+#define OIC 0x31fe /* 16bit */
+
+#define SPI_FREQ_SWSEQ 0x3893
+#define SPI_DESC_COMP0 0x38b0
+#define SPI_FREQ_WR_ERA 0x38b4
+#define SOFT_RESET_CTRL 0x38f4
+#define SOFT_RESET_DATA 0x38f8
+
+#define DIR_ROUTE(a, b, c, d) \
+ (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
+ ((b) << DIR_IBR) | ((a) << DIR_IAR))
+
+#define RC 0x3400 /* 32bit */
+#define HPTC 0x3404 /* 32bit */
+#define GCS 0x3410 /* 32bit */
+#define BUC 0x3414 /* 32bit */
+#define PCH_DISABLE_GBE (1 << 5)
+#define FD 0x3418 /* 32bit */
+#define DISPBDF 0x3424 /* 16bit */
+#define FD2 0x3428 /* 32bit */
+#define CG 0x341c /* 32bit */
+
+/* Function Disable 1 RCBA 0x3418 */
+#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
+#define PCH_DISABLE_P2P (1 << 1)
+#define PCH_DISABLE_SATA1 (1 << 2)
+#define PCH_DISABLE_SMBUS (1 << 3)
+#define PCH_DISABLE_HD_AUDIO (1 << 4)
+#define PCH_DISABLE_EHCI2 (1 << 13)
+#define PCH_DISABLE_LPC (1 << 14)
+#define PCH_DISABLE_EHCI1 (1 << 15)
+#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
+#define PCH_DISABLE_THERMAL (1 << 24)
+#define PCH_DISABLE_SATA2 (1 << 25)
+#define PCH_DISABLE_XHCI (1 << 27)
+
+/* Function Disable 2 RCBA 0x3428 */
+#define PCH_DISABLE_KT (1 << 4)
+#define PCH_DISABLE_IDER (1 << 3)
+#define PCH_DISABLE_MEI2 (1 << 2)
+#define PCH_DISABLE_MEI1 (1 << 1)
+#define PCH_ENABLE_DBDF (1 << 0)
+
+/* ICH7 GPIOBASE */
+#define GPIO_USE_SEL 0x00
+#define GP_IO_SEL 0x04
+#define GP_LVL 0x0c
+#define GPO_BLINK 0x18
+#define GPI_INV 0x2c
+#define GPIO_USE_SEL2 0x30
+#define GP_IO_SEL2 0x34
+#define GP_LVL2 0x38
+#define GPIO_USE_SEL3 0x40
+#define GP_IO_SEL3 0x44
+#define GP_LVL3 0x48
+#define GP_RST_SEL1 0x60
+#define GP_RST_SEL2 0x64
+#define GP_RST_SEL3 0x68
+
+/* ICH7 PMBASE */
+#define PM1_STS 0x00
+#define WAK_STS (1 << 15)
+#define PCIEXPWAK_STS (1 << 14)
+#define PRBTNOR_STS (1 << 11)
+#define RTC_STS (1 << 10)
+#define PWRBTN_STS (1 << 8)
+#define GBL_STS (1 << 5)
+#define BM_STS (1 << 4)
+#define TMROF_STS (1 << 0)
+#define PM1_EN 0x02
+#define PCIEXPWAK_DIS (1 << 14)
+#define RTC_EN (1 << 10)
+#define PWRBTN_EN (1 << 8)
+#define GBL_EN (1 << 5)
+#define TMROF_EN (1 << 0)
+#define PM1_CNT 0x04
+#define SLP_EN (1 << 13)
+#define SLP_TYP (7 << 10)
+#define SLP_TYP_S0 0
+#define SLP_TYP_S1 1
+#define SLP_TYP_S3 5
+#define SLP_TYP_S4 6
+#define SLP_TYP_S5 7
+#define GBL_RLS (1 << 2)
+#define BM_RLD (1 << 1)
+#define SCI_EN (1 << 0)
+#define PM1_TMR 0x08
+#define PROC_CNT 0x10
+#define LV2 0x14
+#define LV3 0x15
+#define LV4 0x16
+#define PM2_CNT 0x50 /* mobile only */
+#define GPE0_STS 0x20
+#define PME_B0_STS (1 << 13)
+#define PME_STS (1 << 11)
+#define BATLOW_STS (1 << 10)
+#define PCI_EXP_STS (1 << 9)
+#define RI_STS (1 << 8)
+#define SMB_WAK_STS (1 << 7)
+#define TCOSCI_STS (1 << 6)
+#define SWGPE_STS (1 << 2)
+#define HOT_PLUG_STS (1 << 1)
+#define GPE0_EN 0x28
+#define PME_B0_EN (1 << 13)
+#define PME_EN (1 << 11)
+#define TCOSCI_EN (1 << 6)
+#define SMI_EN 0x30
+#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */
+#define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */
+#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */
+#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */
+#define MCSMI_EN (1 << 11) /* Trap microcontroller range access */
+#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */
+#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */
+#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */
+#define SLP_SMI_EN (1 << 4) /* Write SLP_EN in PM1_CNT asserts SMI# */
+#define LEGACY_USB_EN (1 << 3) /* Legacy USB circuit SMI logic */
+#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */
+#define EOS (1 << 1) /* End of SMI (deassert SMI#) */
+#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */
+#define SMI_STS 0x34
+#define ALT_GP_SMI_EN 0x38
+#define ALT_GP_SMI_STS 0x3a
+#define GPE_CNTL 0x42
+#define DEVACT_STS 0x44
+#define SS_CNT 0x50
+#define C3_RES 0x54
+#define TCO1_STS 0x64
+#define DMISCI_STS (1 << 9)
+#define TCO2_STS 0x66
+
+/**
+ * lpc_early_init() - set up LPC serial ports and other early things
+ *
+ * @blob: Device tree blob
+ * @node: Offset of LPC node
+ * @dev: PCH PCI device containing the LPC
+ * @return 0 if OK, -ve on error
+ */
+int lpc_early_init(const void *blob, int node, pci_dev_t dev);
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2011, Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef ASM_ARCH_PEI_DATA_H
+#define ASM_ARCH_PEI_DATA_H
+
+struct pch_usb3_controller_settings {
+ /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */
+ uint16_t mode;
+ /* 4 bit mask, 1: switchable, 0: not switchable */
+ uint16_t hs_port_switch_mask;
+ /* 0: No xHCI preOS driver, 1: xHCI preOS driver */
+ uint16_t preboot_support;
+ /* 0: Disable, 1: Enable */
+ uint16_t xhci_streams;
+};
+
+typedef asmlinkage void (*tx_byte_func)(unsigned char byte);
+
+#define PEI_VERSION 6
+
+struct __packed pei_data {
+ uint32_t pei_version;
+ uint32_t mchbar;
+ uint32_t dmibar;
+ uint32_t epbar;
+ uint32_t pciexbar;
+ uint16_t smbusbar;
+ uint32_t wdbbar;
+ uint32_t wdbsize;
+ uint32_t hpet_address;
+ uint32_t rcba;
+ uint32_t pmbase;
+ uint32_t gpiobase;
+ uint32_t thermalbase;
+ uint32_t system_type; /* 0 Mobile, 1 Desktop/Server */
+ uint32_t tseg_size;
+ uint8_t spd_addresses[4];
+ uint8_t ts_addresses[4];
+ int boot_mode;
+ int ec_present;
+ int gbe_enable;
+ /*
+ * 0 = leave channel enabled
+ * 1 = disable dimm 0 on channel
+ * 2 = disable dimm 1 on channel
+ * 3 = disable dimm 0+1 on channel
+ */
+ int dimm_channel0_disabled;
+ int dimm_channel1_disabled;
+ /* Seed values saved in CMOS */
+ uint32_t scrambler_seed;
+ uint32_t scrambler_seed_s3;
+ /* Data read from flash and passed into MRC */
+ unsigned char *mrc_input;
+ unsigned int mrc_input_len;
+ /* Data from MRC that should be saved to flash */
+ unsigned char *mrc_output;
+ unsigned int mrc_output_len;
+ /*
+ * Max frequency DDR3 could be ran at. Could be one of four values:
+ * 800, 1067, 1333, 1600
+ */
+ uint32_t max_ddr3_freq;
+ /*
+ * USB Port Configuration:
+ * [0] = enable
+ * [1] = overcurrent pin
+ * [2] = length
+ *
+ * Ports 0-7 can be mapped to OC0-OC3
+ * Ports 8-13 can be mapped to OC4-OC7
+ *
+ * Port Length
+ * MOBILE:
+ * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude)
+ * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude)
+ * DESKTOP:
+ * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude)
+ * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude)
+ * < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude)
+ */
+ uint16_t usb_port_config[16][3];
+ /* See the usb3 struct above for details */
+ struct pch_usb3_controller_settings usb3;
+ /*
+ * SPD data array for onboard RAM. Specify address 0xf0,
+ * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in
+ * spd_address for a given "DIMM".
+ */
+ uint8_t spd_data[4][256];
+ tx_byte_func tx_byte;
+ int ddr3lv_support;
+ /*
+ * pcie_init needs to be set to 1 to have the system agent initialise
+ * PCIe. Note: This should only be required if your system has Gen3
+ * devices and it will increase your boot time by at least 100ms.
+ */
+ int pcie_init;
+ /*
+ * N mode functionality. Leave this setting at 0.
+ * 0 Auto
+ * 1 1N
+ * 2 2N
+ */
+ int nmode;
+ /*
+ * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows
+ * for DIMM SPD data to specify whether double-rate is required for
+ * extended operating temperature range.
+ * 0 Enable double rate based upon temperature thresholds
+ * 1 Normal rate
+ * 2 Always enable double rate
+ */
+ int ddr_refresh_rate_config;
+};
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * From Coreboot file of the same name
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ACH_ASM_SANDYBRIDGE_H
+#define _ACH_ASM_SANDYBRIDGE_H
+
+/* Chipset types */
+#define SANDYBRIDGE_MOBILE 0
+#define SANDYBRIDGE_DESKTOP 1
+#define SANDYBRIDGE_SERVER 2
+
+/* Device ID for SandyBridge and IvyBridge */
+#define BASE_REV_SNB 0x00
+#define BASE_REV_IVB 0x50
+#define BASE_REV_MASK 0x50
+
+/* SandyBridge CPU stepping */
+#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */
+#define SNB_STEP_D1 (BASE_REV_SNB + 6)
+#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */
+
+/* IvyBridge CPU stepping */
+#define IVB_STEP_A0 (BASE_REV_IVB + 0)
+#define IVB_STEP_B0 (BASE_REV_IVB + 2)
+#define IVB_STEP_C0 (BASE_REV_IVB + 4)
+#define IVB_STEP_K0 (BASE_REV_IVB + 5)
+#define IVB_STEP_D0 (BASE_REV_IVB + 6)
+
+/* Intel Enhanced Debug region must be 4MB */
+#define IED_SIZE 0x400000
+
+/* Northbridge BARs */
+#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
+#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
+#define DEFAULT_RCBABASE 0xfed1c000
+/* 4 KB per PCIe device */
+#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
+
+/* Device 0:0.0 PCI configuration space (Host Bridge) */
+#define EPBAR 0x40
+#define MCHBAR 0x48
+#define PCIEXBAR 0x60
+#define DMIBAR 0x68
+#define X60BAR 0x60
+
+#define GGC 0x50 /* GMCH Graphics Control */
+
+#define DEVEN 0x54 /* Device Enable */
+#define DEVEN_PEG60 (1 << 13)
+#define DEVEN_IGD (1 << 4)
+#define DEVEN_PEG10 (1 << 3)
+#define DEVEN_PEG11 (1 << 2)
+#define DEVEN_PEG12 (1 << 1)
+#define DEVEN_HOST (1 << 0)
+
+#define PAM0 0x80
+#define PAM1 0x81
+#define PAM2 0x82
+#define PAM3 0x83
+#define PAM4 0x84
+#define PAM5 0x85
+#define PAM6 0x86
+
+#define LAC 0x87 /* Legacy Access Control */
+#define SMRAM 0x88 /* System Management RAM Control */
+#define D_OPEN (1 << 6)
+#define D_CLS (1 << 5)
+#define D_LCK (1 << 4)
+#define G_SMRAME (1 << 3)
+#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
+
+#define TOM 0xa0
+#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
+#define TSEG 0xb8 /* TSEG base */
+#define TOLUD 0xbc /* Top of Low Used Memory */
+
+#define SKPAD 0xdc /* Scratchpad Data */
+
+/* Device 0:1.0 PCI configuration space (PCI Express) */
+#define BCTRL1 0x3e /* 16bit */
+
+/* Device 0:2.0 PCI configuration space (Graphics Device) */
+
+#define MSAC 0x62 /* Multi Size Aperture Control */
+#define SWSCI 0xe8 /* SWSCI enable */
+#define ASLS 0xfc /* OpRegion Base */
+
+/*
+ * MCHBAR
+ */
+#define MCHBAR_REG(reg) (DEFAULT_RCBA + (reg))
+
+#define SSKPD 0x5d14 /* 16bit (scratchpad) */
+#define BIOS_RESET_CPL 0x5da8 /* 8bit */
+
+void report_platform_info(void);
+
+void sandybridge_early_init(int chipset_type);
+
+#endif
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+#define asmlinkage __attribute__((regparm(0)))
#endif
/*
* Copyright (c) 2014 The Chromium OS Authors.
*
+ * Part of this file is adapted from coreboot
+ * src/arch/x86/include/arch/cpu.h and
+ * src/arch/x86/lib/cpu.c
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __X86_CPU_H
-#define __X86_CPU_H
+#ifndef _ASM_CPU_H
+#define _ASM_CPU_H
+
+enum {
+ X86_VENDOR_INVALID = 0,
+ X86_VENDOR_INTEL,
+ X86_VENDOR_CYRIX,
+ X86_VENDOR_AMD,
+ X86_VENDOR_UMC,
+ X86_VENDOR_NEXGEN,
+ X86_VENDOR_CENTAUR,
+ X86_VENDOR_RISE,
+ X86_VENDOR_TRANSMETA,
+ X86_VENDOR_NSC,
+ X86_VENDOR_SIS,
+ X86_VENDOR_ANY = 0xfe,
+ X86_VENDOR_UNKNOWN = 0xff
+};
+
+struct cpuid_result {
+ uint32_t eax;
+ uint32_t ebx;
+ uint32_t ecx;
+ uint32_t edx;
+};
+
+/*
+ * Generic CPUID function
+ */
+static inline struct cpuid_result cpuid(int op)
+{
+ struct cpuid_result result;
+ asm volatile(
+ "mov %%ebx, %%edi;"
+ "cpuid;"
+ "mov %%ebx, %%esi;"
+ "mov %%edi, %%ebx;"
+ : "=a" (result.eax),
+ "=S" (result.ebx),
+ "=c" (result.ecx),
+ "=d" (result.edx)
+ : "0" (op)
+ : "edi");
+ return result;
+}
+
+/*
+ * Generic Extended CPUID function
+ */
+static inline struct cpuid_result cpuid_ext(int op, unsigned ecx)
+{
+ struct cpuid_result result;
+ asm volatile(
+ "mov %%ebx, %%edi;"
+ "cpuid;"
+ "mov %%ebx, %%esi;"
+ "mov %%edi, %%ebx;"
+ : "=a" (result.eax),
+ "=S" (result.ebx),
+ "=c" (result.ecx),
+ "=d" (result.edx)
+ : "0" (op), "2" (ecx)
+ : "edi");
+ return result;
+}
+
+/*
+ * CPUID functions returning a single datum
+ */
+static inline unsigned int cpuid_eax(unsigned int op)
+{
+ unsigned int eax;
+
+ __asm__("mov %%ebx, %%edi;"
+ "cpuid;"
+ "mov %%edi, %%ebx;"
+ : "=a" (eax)
+ : "0" (op)
+ : "ecx", "edx", "edi");
+ return eax;
+}
+
+static inline unsigned int cpuid_ebx(unsigned int op)
+{
+ unsigned int eax, ebx;
+
+ __asm__("mov %%ebx, %%edi;"
+ "cpuid;"
+ "mov %%ebx, %%esi;"
+ "mov %%edi, %%ebx;"
+ : "=a" (eax), "=S" (ebx)
+ : "0" (op)
+ : "ecx", "edx", "edi");
+ return ebx;
+}
+
+static inline unsigned int cpuid_ecx(unsigned int op)
+{
+ unsigned int eax, ecx;
- /**
+ __asm__("mov %%ebx, %%edi;"
+ "cpuid;"
+ "mov %%edi, %%ebx;"
+ : "=a" (eax), "=c" (ecx)
+ : "0" (op)
+ : "edx", "edi");
+ return ecx;
+}
+
+static inline unsigned int cpuid_edx(unsigned int op)
+{
+ unsigned int eax, edx;
+
+ __asm__("mov %%ebx, %%edi;"
+ "cpuid;"
+ "mov %%edi, %%ebx;"
+ : "=a" (eax), "=d" (edx)
+ : "0" (op)
+ : "ecx", "edi");
+ return edx;
+}
+
+/* Standard macro to see if a specific flag is changeable */
+static inline int flag_is_changeable_p(uint32_t flag)
+{
+ uint32_t f1, f2;
+
+ asm(
+ "pushfl\n\t"
+ "pushfl\n\t"
+ "popl %0\n\t"
+ "movl %0,%1\n\t"
+ "xorl %2,%0\n\t"
+ "pushl %0\n\t"
+ "popfl\n\t"
+ "pushfl\n\t"
+ "popl %0\n\t"
+ "popfl\n\t"
+ : "=&r" (f1), "=&r" (f2)
+ : "ir" (flag));
+ return ((f1^f2) & flag) != 0;
+}
+
+/**
* cpu_enable_paging_pae() - Enable PAE-paging
*
- * @pdpt: Value to set in cr3 (PDPT or PML4T)
+ * @cr3: Value to set in cr3 (PDPT or PML4T)
*/
void cpu_enable_paging_pae(ulong cr3);
*/
int cpu_has_64bit(void);
+/**
+ * cpu_vendor_name() - Get CPU vendor name
+ *
+ * @vendor: CPU vendor enumeration number
+ *
+ * @return: Address to hold the CPU vendor name string
+ */
+const char *cpu_vendor_name(int vendor);
+
+#define CPU_MAX_NAME_LEN 49
+
+/**
+ * cpu_get_name() - Get the name of the current cpu
+ *
+ * @name: Place to put name, which must be CPU_MAX_NAME_LEN bytes including
+ * @return pointer to name, which will likely be a few bytes after the start
+ * of @name
+ * \0 terminator
+ */
+char *cpu_get_name(char *name);
+
/**
* cpu_call64() - Jump to a 64-bit Linux kernel (internal function)
*
#ifndef __ASSEMBLY__
+enum pei_boot_mode_t {
+ PEI_BOOT_NONE = 0,
+ PEI_BOOT_SOFT_RESET,
+ PEI_BOOT_RESUME,
+
+};
+
+struct memory_area {
+ uint64_t start;
+ uint64_t size;
+};
+
+struct memory_info {
+ int num_areas;
+ uint64_t total_memory;
+ uint64_t total_32bit_memory;
+ struct memory_area area[CONFIG_NR_DRAM_BANKS];
+};
+
/* Architecture-specific global data */
struct arch_global_data {
struct global_data *gd_addr; /* Location of Global Data */
+ uint8_t x86; /* CPU family */
+ uint8_t x86_vendor; /* CPU vendor */
+ uint8_t x86_model;
+ uint8_t x86_mask;
+ uint32_t x86_device;
uint64_t tsc_base; /* Initial value returned by rdtsc() */
uint32_t tsc_base_kclocks; /* Initial tsc as a kclocks value */
uint32_t tsc_prev; /* For show_boot_progress() */
+ uint32_t tsc_mhz; /* TSC frequency in MHz */
void *new_fdt; /* Relocated FDT */
+ uint32_t bist; /* Built-in self test value */
+ struct pci_controller *hose; /* PCI hose for early use */
+ enum pei_boot_mode_t pei_boot_mode;
+ const struct pch_gpio_map *gpio_map; /* board GPIO map */
+ struct memory_info meminfo; /* Memory information */
};
#endif
/*
* Copyright (c) 2012, Google Inc. All rights reserved.
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _X86_GPIO_H_
#define _X86_GPIO_H_
+#include <linux/compiler.h>
#include <asm/arch/gpio.h>
#include <asm-generic/gpio.h>
+struct ich6_bank_platdata {
+ uint32_t base_addr;
+ const char *bank_name;
+};
+
+#define GPIO_MODE_NATIVE 0
+#define GPIO_MODE_GPIO 1
+#define GPIO_MODE_NONE 1
+
+#define GPIO_DIR_OUTPUT 0
+#define GPIO_DIR_INPUT 1
+
+#define GPIO_NO_INVERT 0
+#define GPIO_INVERT 1
+
+#define GPIO_LEVEL_LOW 0
+#define GPIO_LEVEL_HIGH 1
+
+#define GPIO_NO_BLINK 0
+#define GPIO_BLINK 1
+
+#define GPIO_RESET_PWROK 0
+#define GPIO_RESET_RSMRST 1
+
+struct pch_gpio_set1 {
+ u32 gpio0:1;
+ u32 gpio1:1;
+ u32 gpio2:1;
+ u32 gpio3:1;
+ u32 gpio4:1;
+ u32 gpio5:1;
+ u32 gpio6:1;
+ u32 gpio7:1;
+ u32 gpio8:1;
+ u32 gpio9:1;
+ u32 gpio10:1;
+ u32 gpio11:1;
+ u32 gpio12:1;
+ u32 gpio13:1;
+ u32 gpio14:1;
+ u32 gpio15:1;
+ u32 gpio16:1;
+ u32 gpio17:1;
+ u32 gpio18:1;
+ u32 gpio19:1;
+ u32 gpio20:1;
+ u32 gpio21:1;
+ u32 gpio22:1;
+ u32 gpio23:1;
+ u32 gpio24:1;
+ u32 gpio25:1;
+ u32 gpio26:1;
+ u32 gpio27:1;
+ u32 gpio28:1;
+ u32 gpio29:1;
+ u32 gpio30:1;
+ u32 gpio31:1;
+} __packed;
+
+struct pch_gpio_set2 {
+ u32 gpio32:1;
+ u32 gpio33:1;
+ u32 gpio34:1;
+ u32 gpio35:1;
+ u32 gpio36:1;
+ u32 gpio37:1;
+ u32 gpio38:1;
+ u32 gpio39:1;
+ u32 gpio40:1;
+ u32 gpio41:1;
+ u32 gpio42:1;
+ u32 gpio43:1;
+ u32 gpio44:1;
+ u32 gpio45:1;
+ u32 gpio46:1;
+ u32 gpio47:1;
+ u32 gpio48:1;
+ u32 gpio49:1;
+ u32 gpio50:1;
+ u32 gpio51:1;
+ u32 gpio52:1;
+ u32 gpio53:1;
+ u32 gpio54:1;
+ u32 gpio55:1;
+ u32 gpio56:1;
+ u32 gpio57:1;
+ u32 gpio58:1;
+ u32 gpio59:1;
+ u32 gpio60:1;
+ u32 gpio61:1;
+ u32 gpio62:1;
+ u32 gpio63:1;
+} __packed;
+
+struct pch_gpio_set3 {
+ u32 gpio64:1;
+ u32 gpio65:1;
+ u32 gpio66:1;
+ u32 gpio67:1;
+ u32 gpio68:1;
+ u32 gpio69:1;
+ u32 gpio70:1;
+ u32 gpio71:1;
+ u32 gpio72:1;
+ u32 gpio73:1;
+ u32 gpio74:1;
+ u32 gpio75:1;
+} __packed;
+
+/*
+ * This hilariously complex structure came from Coreboot. The
+ * setup_pch_gpios() function uses it. It could be move to device tree, or
+ * adjust to use masks instead of bitfields.
+ */
+struct pch_gpio_map {
+ struct {
+ const struct pch_gpio_set1 *mode;
+ const struct pch_gpio_set1 *direction;
+ const struct pch_gpio_set1 *level;
+ const struct pch_gpio_set1 *reset;
+ const struct pch_gpio_set1 *invert;
+ const struct pch_gpio_set1 *blink;
+ } set1;
+ struct {
+ const struct pch_gpio_set2 *mode;
+ const struct pch_gpio_set2 *direction;
+ const struct pch_gpio_set2 *level;
+ const struct pch_gpio_set2 *reset;
+ } set2;
+ struct {
+ const struct pch_gpio_set3 *mode;
+ const struct pch_gpio_set3 *direction;
+ const struct pch_gpio_set3 *level;
+ const struct pch_gpio_set3 *reset;
+ } set3;
+};
+
+void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
+
#endif /* _X86_GPIO_H_ */
#define PIT_CMD_MODE4 0x08 /* Select mode 4 */
#define PIT_CMD_MODE5 0x0A /* Select mode 5 */
+/* The clock frequency of the i8253/i8254 PIT */
+#define PIT_TICK_RATE 1193182ul
+
#endif
int init_cache_f_r(void);
int init_bd_struct_r(void);
int init_func_spi(void);
-int find_fdt(void);
-int prepare_fdt(void);
#endif /* !_INIT_HELPERS_H_ */
#define memcpy_fromio(a,b,c) memcpy((a),(b),(c))
#define memcpy_toio(a,b,c) memcpy((a),(b),(c))
+#define write_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
+#define read_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
+
+#define write_le64(a, v) write_arch(q, le64, a, v)
+#define write_le32(a, v) write_arch(l, le32, a, v)
+#define write_le16(a, v) write_arch(w, le16, a, v)
+
+#define read_le64(a) read_arch(q, le64, a)
+#define read_le32(a) read_arch(l, le32, a)
+#define read_le16(a) read_arch(w, le16, a)
+
+#define write_be32(a, v) write_arch(l, be32, a, v)
+#define write_be16(a, v) write_arch(w, be16, a, v)
+
+#define read_be32(a) read_arch(l, be32, a)
+#define read_be16(a) read_arch(w, be16, a)
+
+#define write_8(a, v) __raw_writeb(v, a)
+#define read_8(a) __raw_readb(a)
+
+#define clrbits(type, addr, clear) \
+ write_##type((addr), read_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+ write_##type((addr), read_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+ write_##type((addr), (read_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
/*
* ISA space is 'always mapped' on a typical x86 system, no need to
* explicitly ioremap() it. The fact that the ISA IO space is mapped
--- /dev/null
+/*
+ * From Coreboot file of same name
+ *
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ARCH_ASM_LAPIC_H
+#define _ARCH_ASM_LAPIC_H
+
+#include <asm/io.h>
+#include <asm/lapic_def.h>
+#include <asm/msr.h>
+#include <asm/processor.h>
+
+static inline __attribute__((always_inline))
+ unsigned long lapic_read(unsigned long reg)
+{
+ return readl(LAPIC_DEFAULT_BASE + reg);
+}
+
+static inline __attribute__((always_inline))
+ void lapic_write(unsigned long reg, unsigned long val)
+{
+ writel(val, LAPIC_DEFAULT_BASE + reg);
+}
+
+static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void)
+{
+ do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY);
+}
+
+static inline void enable_lapic(void)
+{
+ msr_t msr;
+
+ msr = msr_read(LAPIC_BASE_MSR);
+ msr.hi &= 0xffffff00;
+ msr.lo &= 0x000007ff;
+ msr.lo |= LAPIC_DEFAULT_BASE | (1 << 11);
+ msr_write(LAPIC_BASE_MSR, msr);
+}
+
+static inline void disable_lapic(void)
+{
+ msr_t msr;
+
+ msr = msr_read(LAPIC_BASE_MSR);
+ msr.lo &= ~(1 << 11);
+ msr_write(LAPIC_BASE_MSR, msr);
+}
+
+static inline __attribute__((always_inline)) unsigned long lapicid(void)
+{
+ return lapic_read(LAPIC_ID) >> 24;
+}
+
+#endif
--- /dev/null
+/*
+ * Taken from the Coreboot file of the same name
+ *
+ * (C) Copyright 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_LAPIC_DEF_H
+#define _ASM_LAPIC_DEF_H
+
+#define LAPIC_BASE_MSR 0x1B
+#define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8)
+#define LAPIC_BASE_MSR_ENABLE (1 << 11)
+#define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000
+
+#define LOCAL_APIC_ADDR 0xfee00000
+#define LAPIC_DEFAULT_BASE LOCAL_APIC_ADDR
+
+#define LAPIC_ID 0x020
+#define LAPIC_LVR 0x030
+#define LAPIC_TASKPRI 0x80
+#define LAPIC_TPRI_MASK 0xFF
+#define LAPIC_ARBID 0x090
+#define LAPIC_RRR 0x0C0
+#define LAPIC_SVR 0x0f0
+#define LAPIC_SPIV 0x0f0
+#define LAPIC_SPIV_ENABLE 0x100
+#define LAPIC_ESR 0x280
+#define LAPIC_ESR_SEND_CS 0x00001
+#define LAPIC_ESR_RECV_CS 0x00002
+#define LAPIC_ESR_SEND_ACC 0x00004
+#define LAPIC_ESR_RECV_ACC 0x00008
+#define LAPIC_ESR_SENDILL 0x00020
+#define LAPIC_ESR_RECVILL 0x00040
+#define LAPIC_ESR_ILLREGA 0x00080
+#define LAPIC_ICR 0x300
+#define LAPIC_DEST_SELF 0x40000
+#define LAPIC_DEST_ALLINC 0x80000
+#define LAPIC_DEST_ALLBUT 0xC0000
+#define LAPIC_ICR_RR_MASK 0x30000
+#define LAPIC_ICR_RR_INVALID 0x00000
+#define LAPIC_ICR_RR_INPROG 0x10000
+#define LAPIC_ICR_RR_VALID 0x20000
+#define LAPIC_INT_LEVELTRIG 0x08000
+#define LAPIC_INT_ASSERT 0x04000
+#define LAPIC_ICR_BUSY 0x01000
+#define LAPIC_DEST_LOGICAL 0x00800
+#define LAPIC_DM_FIXED 0x00000
+#define LAPIC_DM_LOWEST 0x00100
+#define LAPIC_DM_SMI 0x00200
+#define LAPIC_DM_REMRD 0x00300
+#define LAPIC_DM_NMI 0x00400
+#define LAPIC_DM_INIT 0x00500
+#define LAPIC_DM_STARTUP 0x00600
+#define LAPIC_DM_EXTINT 0x00700
+#define LAPIC_VECTOR_MASK 0x000FF
+#define LAPIC_ICR2 0x310
+#define GET_LAPIC_DEST_FIELD(x) (((x) >> 24) & 0xFF)
+#define SET_LAPIC_DEST_FIELD(x) ((x) << 24)
+#define LAPIC_LVTT 0x320
+#define LAPIC_LVTPC 0x340
+#define LAPIC_LVT0 0x350
+#define LAPIC_LVT_TIMER_BASE_MASK (0x3 << 18)
+#define GET_LAPIC_TIMER_BASE(x) (((x) >> 18) & 0x3)
+#define SET_LAPIC_TIMER_BASE(x) (((x) << 18))
+#define LAPIC_TIMER_BASE_CLKIN 0x0
+#define LAPIC_TIMER_BASE_TMBASE 0x1
+#define LAPIC_TIMER_BASE_DIV 0x2
+#define LAPIC_LVT_TIMER_PERIODIC (1 << 17)
+#define LAPIC_LVT_MASKED (1 << 16)
+#define LAPIC_LVT_LEVEL_TRIGGER (1 << 15)
+#define LAPIC_LVT_REMOTE_IRR (1 << 14)
+#define LAPIC_INPUT_POLARITY (1 << 13)
+#define LAPIC_SEND_PENDING (1 << 12)
+#define LAPIC_LVT_RESERVED_1 (1 << 11)
+#define LAPIC_DELIVERY_MODE_MASK (7 << 8)
+#define LAPIC_DELIVERY_MODE_FIXED (0 << 8)
+#define LAPIC_DELIVERY_MODE_NMI (4 << 8)
+#define LAPIC_DELIVERY_MODE_EXTINT (7 << 8)
+#define GET_LAPIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7)
+#define SET_LAPIC_DELIVERY_MODE(x, y) (((x) & ~0x700)|((y) << 8))
+#define LAPIC_MODE_FIXED 0x0
+#define LAPIC_MODE_NMI 0x4
+#define LAPIC_MODE_EXINT 0x7
+#define LAPIC_LVT1 0x360
+#define LAPIC_LVTERR 0x370
+#define LAPIC_TMICT 0x380
+#define LAPIC_TMCCT 0x390
+#define LAPIC_TDCR 0x3E0
+#define LAPIC_TDR_DIV_TMBASE (1 << 2)
+#define LAPIC_TDR_DIV_1 0xB
+#define LAPIC_TDR_DIV_2 0x0
+#define LAPIC_TDR_DIV_4 0x1
+#define LAPIC_TDR_DIV_8 0x2
+#define LAPIC_TDR_DIV_16 0x3
+#define LAPIC_TDR_DIV_32 0x8
+#define LAPIC_TDR_DIV_64 0x9
+#define LAPIC_TDR_DIV_128 0xA
+
+#endif
return native_wrmsr_safe_regs(regs);
}
+typedef struct msr_t {
+ uint32_t lo;
+ uint32_t hi;
+} msr_t;
+
+static inline struct msr_t msr_read(unsigned msr_num)
+{
+ struct msr_t msr;
+
+ rdmsr(msr_num, msr.lo, msr.hi);
+
+ return msr;
+}
+
+static inline void msr_write(unsigned msr_num, msr_t msr)
+{
+ wrmsr(msr_num, msr.lo, msr.hi);
+}
+
#define rdtscl(low) \
((low) = (u32)__native_read_tsc())
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * From Coreboot file of the same name
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_MTRR_H
+#define _ASM_MTRR_H
+
+/* These are the region types */
+#define MTRR_TYPE_UNCACHEABLE 0
+#define MTRR_TYPE_WRCOMB 1
+/*#define MTRR_TYPE_ 2*/
+/*#define MTRR_TYPE_ 3*/
+#define MTRR_TYPE_WRTHROUGH 4
+#define MTRR_TYPE_WRPROT 5
+#define MTRR_TYPE_WRBACK 6
+#define MTRR_NUM_TYPES 7
+
+#define MTRRcap_MSR 0x0fe
+#define MTRRdefType_MSR 0x2ff
+
+#define MTRRdefTypeEn (1 << 11)
+#define MTRRdefTypeFixEn (1 << 10)
+
+#define SMRRphysBase_MSR 0x1f2
+#define SMRRphysMask_MSR 0x1f3
+
+#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
+#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
+
+#define MTRRphysMaskValid (1 << 11)
+
+#define NUM_FIXED_RANGES 88
+#define RANGES_PER_FIXED_MTRR 8
+#define MTRRfix64K_00000_MSR 0x250
+#define MTRRfix16K_80000_MSR 0x258
+#define MTRRfix16K_A0000_MSR 0x259
+#define MTRRfix4K_C0000_MSR 0x268
+#define MTRRfix4K_C8000_MSR 0x269
+#define MTRRfix4K_D0000_MSR 0x26a
+#define MTRRfix4K_D8000_MSR 0x26b
+#define MTRRfix4K_E0000_MSR 0x26c
+#define MTRRfix4K_E8000_MSR 0x26d
+#define MTRRfix4K_F0000_MSR 0x26e
+#define MTRRfix4K_F8000_MSR 0x26f
+
+#if !defined(__ASSEMBLER__)
+
+/*
+ * The MTRR code has some side effects that the callers should be aware for.
+ * 1. The call sequence matters. x86_setup_mtrrs() calls
+ * x86_setup_fixed_mtrrs_no_enable() then enable_fixed_mtrrs() (equivalent
+ * of x86_setup_fixed_mtrrs()) then x86_setup_var_mtrrs(). If the callers
+ * want to call the components of x86_setup_mtrrs() because of other
+ * rquirements the ordering should still preserved.
+ * 2. enable_fixed_mtrr() will enable both variable and fixed MTRRs because
+ * of the nature of the global MTRR enable flag. Therefore, all direct
+ * or indirect callers of enable_fixed_mtrr() should ensure that the
+ * variable MTRR MSRs do not contain bad ranges.
+ * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling
+ * the caching of the ROM. However, it is set to uncacheable (UC). It
+ * is the responsiblity of the caller to enable it by calling
+ * x86_mtrr_enable_rom_caching().
+ */
+void x86_setup_mtrrs(void);
+/*
+ * x86_setup_var_mtrrs() parameters:
+ * address_bits - number of physical address bits supported by cpu
+ * above4gb - 2 means dynamically detect number of variable MTRRs available.
+ * non-zero means handle memory ranges above 4GiB.
+ * 0 means ignore memory ranges above 4GiB
+ */
+void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb);
+void enable_fixed_mtrr(void);
+void x86_setup_fixed_mtrrs(void);
+/* Set up fixed MTRRs but do not enable them. */
+void x86_setup_fixed_mtrrs_no_enable(void);
+int x86_mtrr_check(void);
+/* ROM caching can be used after variable MTRRs are set up. Beware that
+ * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on
+ * one's IO hole size and WRCOMB resources. Be sure to check the console
+ * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that
+ * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the
+ * rom caching will be disabled if all threads run the MTRR code. Therefore,
+ * one needs to call x86_mtrr_enable_rom_caching() after all threads of the
+ * same core have run the MTRR code. */
+#if CONFIG_CACHE_ROM
+void x86_mtrr_enable_rom_caching(void);
+void x86_mtrr_disable_rom_caching(void);
+/* Return the variable range MTRR index of the ROM cache. */
+long x86_mtrr_rom_cache_var_index(void);
+#else
+static inline void x86_mtrr_enable_rom_caching(void) {}
+static inline void x86_mtrr_disable_rom_caching(void) {}
+static inline long x86_mtrr_rom_cache_var_index(void) { return -1; }
+#endif /* CONFIG_CACHE_ROM */
+
+#endif
+
+#if !defined(CONFIG_RAMTOP)
+# error "CONFIG_RAMTOP not defined"
+#endif
+
+#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
+# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
+#endif
+
+#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0)
+# error "CONFIG_CACHE_ROM_SIZE is not a power of 2"
+#endif
+
+#define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12)
+
+#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
+# error "CONFIG_RAMTOP must be a power of 2"
+#endif
+
+#endif
#define DEFINE_PCI_DEVICE_TABLE(_table) \
const struct pci_device_id _table[]
+struct pci_controller;
+
void pci_setup_type1(struct pci_controller *hose);
+
+/**
+ * board_pci_setup_hose() - Set up the PCI hose
+ *
+ * This is called by the common x86 PCI code to set up the PCI controller
+ * hose. It may be called when no memory/BSS is available so should just
+ * store things in 'hose' and not in BSS variables.
+ */
+void board_pci_setup_hose(struct pci_controller *hose);
+
+/**
+ * pci_early_init_hose() - Set up PCI host before relocation
+ *
+ * This allocates memory for, sets up and returns the PCI hose. It can be
+ * called before relocation. The hose will be stored in gd->arch.hose for
+ * later use, but will become invalid one DRAM is available.
+ */
+int pci_early_init_hose(struct pci_controller **hosep);
+
+/*
+ * Simple PCI access routines - these work from either the early PCI hose
+ * or the 'real' one, created after U-Boot has memory available
+ */
+unsigned int pci_read_config8(pci_dev_t dev, unsigned where);
+unsigned int pci_read_config16(pci_dev_t dev, unsigned where);
+unsigned int pci_read_config32(pci_dev_t dev, unsigned where);
+
+void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value);
+void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value);
+void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value);
+
#endif
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _post_h
+#define _post_h
+
+/* port to use for post codes */
+#define POST_PORT 0x80
+
+/* post codes which represent various stages of init */
+#define POST_START 0x1e
+#define POST_CAR_START 0x1f
+#define POST_CAR_SIPI 0x20
+#define POST_CAR_MTRR 0x21
+#define POST_CAR_UNCACHEABLE 0x22
+#define POST_CAR_BASE_ADDRESS 0x23
+#define POST_CAR_MASK 0x24
+#define POST_CAR_FILL 0x25
+#define POST_CAR_ROM_CACHE 0x26
+#define POST_CAR_MRC_CACHE 0x27
+#define POST_CAR_CPU_CACHE 0x28
+#define POST_START_STACK 0x29
+#define POST_START_DONE 0x2a
+#define POST_CPU_INIT 0x2b
+#define POST_EARLY_INIT 0x2c
+#define POST_CPU_INFO 0x2d
+#define POST_PRE_MRC 0x2e
+#define POST_MRC 0x2f
+#define POST_DRAM 0x2f
+
+#define POST_RAM_FAILURE 0xea
+
+/* Output a post code using al - value must be 0 to 0xff */
+#ifdef __ASSEMBLY__
+#define post_code(value) \
+ movb $value, %al; \
+ outb %al, $POST_PORT
+#else
+#include <asm/io.h>
+
+static inline void post_code(int code)
+{
+ outb(code, POST_PORT);
+}
+#endif
+
+#endif
#define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE)
+#ifndef __ASSEMBLY__
+
+#define PORT_RESET 0xcf9
+
+static inline __attribute__((always_inline)) void cpu_hlt(void)
+{
+ asm("hlt");
+}
+
+static inline ulong cpu_get_sp(void)
+{
+ ulong result;
+
+ asm volatile(
+ "mov %%esp, %%eax"
+ : "=a" (result));
+ return result;
+}
+
+#endif /* __ASSEMBLY__ */
+
#endif
#define _U_BOOT_I386_H_ 1
/* cpu/.../cpu.c */
+int arch_cpu_init(void);
int x86_cpu_init_r(void);
int cpu_init_r(void);
int x86_cpu_init_f(void);
void timer_set_base(uint64_t base);
int pcat_timer_init(void);
-/* Architecture specific - can be in arch/x86/cpu/, arch/x86/lib/, or $(BOARD)/ */
-int dram_init_f(void);
+/* Architecture specific DRAM init */
+int dram_init(void);
/* cpu/.../interrupts.c */
int cpu_init_interrupts(void);
/* board/.../... */
int dram_init(void);
+int cleanup_before_linux(void);
+int x86_cleanup_before_linux(void);
+void x86_enable_caches(void);
+void x86_disable_caches(void);
+int x86_init_cache(void);
+void reset_cpu(ulong addr);
+ulong board_get_usable_ram_top(ulong total_size);
+void dram_init_banksize(void);
+int default_print_cpuinfo(void);
+
void setup_pcat_compatibility(void);
void isa_unmap_rom(u32 addr);
void timer_set_tsc_base(uint64_t new_base);
uint64_t timer_get_tsc(void);
+void quick_ram_check(void);
+
#endif /* _U_BOOT_I386_H_ */
obj-$(CONFIG_PCI) += pci_type1.o
obj-y += relocate.o
obj-y += physmem.o
+obj-$(CONFIG_X86_RAMTEST) += ramtest.o
obj-y += string.o
obj-$(CONFIG_SYS_X86_TSC_TIMER) += tsc_timer.o
obj-$(CONFIG_VIDEO_VGA) += video.o
puts("ready\n");
return 0;
}
-
-int find_fdt(void)
-{
-#ifdef CONFIG_OF_EMBED
- /* Get a pointer to the FDT */
- gd->fdt_blob = __dtb_dt_begin;
-#elif defined CONFIG_OF_SEPARATE
- /* FDT is at end of image */
- gd->fdt_blob = (ulong *)&_end;
-#endif
- /* Allow the early environment to override the fdt address */
- gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
- (uintptr_t)gd->fdt_blob);
-
- return 0;
-}
-
-int prepare_fdt(void)
-{
- /* For now, put this check after the console is ready */
- if (fdtdec_prepare_fdt()) {
- panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
- "doc/README.fdt-control");
- }
-
- return 0;
-}
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * From Coreboot src/lib/ramtest.c
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/post.h>
+
+static void write_phys(unsigned long addr, u32 value)
+{
+#if CONFIG_SSE2
+ asm volatile(
+ "movnti %1, (%0)"
+ : /* outputs */
+ : "r" (addr), "r" (value) /* inputs */
+ : /* clobbers */
+ );
+#else
+ writel(value, addr);
+#endif
+}
+
+static u32 read_phys(unsigned long addr)
+{
+ return readl(addr);
+}
+
+static void phys_memory_barrier(void)
+{
+#if CONFIG_SSE2
+ /* Needed for movnti */
+ asm volatile(
+ "sfence"
+ :
+ :
+ : "memory"
+ );
+#else
+ asm volatile(""
+ :
+ :
+ : "memory");
+#endif
+}
+
+void quick_ram_check(void)
+{
+ int fail = 0;
+ u32 backup;
+
+ backup = read_phys(CONFIG_RAMBASE);
+ write_phys(CONFIG_RAMBASE, 0x55555555);
+ phys_memory_barrier();
+ if (read_phys(CONFIG_RAMBASE) != 0x55555555)
+ fail = 1;
+ write_phys(CONFIG_RAMBASE, 0xaaaaaaaa);
+ phys_memory_barrier();
+ if (read_phys(CONFIG_RAMBASE) != 0xaaaaaaaa)
+ fail = 1;
+ write_phys(CONFIG_RAMBASE, 0x00000000);
+ phys_memory_barrier();
+ if (read_phys(CONFIG_RAMBASE) != 0x00000000)
+ fail = 1;
+ write_phys(CONFIG_RAMBASE, 0xffffffff);
+ phys_memory_barrier();
+ if (read_phys(CONFIG_RAMBASE) != 0xffffffff)
+ fail = 1;
+
+ write_phys(CONFIG_RAMBASE, backup);
+ if (fail) {
+ post_code(POST_RAM_FAILURE);
+ panic("RAM INIT FAILURE!\n");
+ }
+ phys_memory_barrier();
+}
/*
* Copyright (c) 2012 The Chromium OS Authors.
*
+ * TSC calibration codes are adapted from Linux kernel
+ * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/msr.h>
#include <asm/u-boot-x86.h>
+/* CPU reference clock frequency: in KHz */
+#define FREQ_83 83200
+#define FREQ_100 99840
+#define FREQ_133 133200
+#define FREQ_166 166400
+
+#define MAX_NUM_FREQS 8
+
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * According to Intel 64 and IA-32 System Programming Guide,
+ * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
+ * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
+ * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
+ * so we need manually differentiate SoC families. This is what the
+ * field msr_plat does.
+ */
+struct freq_desc {
+ u8 x86_family; /* CPU family */
+ u8 x86_model; /* model */
+ /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
+ u8 msr_plat;
+ u32 freqs[MAX_NUM_FREQS];
+};
+
+static struct freq_desc freq_desc_tables[] = {
+ /* PNW */
+ { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
+ /* CLV+ */
+ { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
+ /* TNG */
+ { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
+ /* VLV2 */
+ { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
+ /* Ivybridge */
+ { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },
+ /* ANN */
+ { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
+};
+
+static int match_cpu(u8 family, u8 model)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
+ if ((family == freq_desc_tables[i].x86_family) &&
+ (model == freq_desc_tables[i].x86_model))
+ return i;
+ }
+
+ return -1;
+}
+
+/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
+#define id_to_freq(cpu_index, freq_id) \
+ (freq_desc_tables[cpu_index].freqs[freq_id])
+
+/*
+ * Do MSR calibration only for known/supported CPUs.
+ *
+ * Returns the calibration value or 0 if MSR calibration failed.
+ */
+static unsigned long try_msr_calibrate_tsc(void)
+{
+ u32 lo, hi, ratio, freq_id, freq;
+ unsigned long res;
+ int cpu_index;
+
+ cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
+ if (cpu_index < 0)
+ return 0;
+
+ if (freq_desc_tables[cpu_index].msr_plat) {
+ rdmsr(MSR_PLATFORM_INFO, lo, hi);
+ ratio = (lo >> 8) & 0x1f;
+ } else {
+ rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
+ ratio = (hi >> 8) & 0x1f;
+ }
+ debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
+
+ if (!ratio)
+ goto fail;
+
+ if (freq_desc_tables[cpu_index].msr_plat == 2) {
+ /* TODO: Figure out how best to deal with this */
+ freq = FREQ_100;
+ debug("Using frequency: %u KHz\n", freq);
+ } else {
+ /* Get FSB FREQ ID */
+ rdmsr(MSR_FSB_FREQ, lo, hi);
+ freq_id = lo & 0x7;
+ freq = id_to_freq(cpu_index, freq_id);
+ debug("Resolved frequency ID: %u, frequency: %u KHz\n",
+ freq_id, freq);
+ }
+ if (!freq)
+ goto fail;
+
+ /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
+ res = freq * ratio / 1000;
+ debug("TSC runs at %lu MHz\n", res);
+
+ return res;
+
+fail:
+ debug("Fast TSC calibration using MSR failed\n");
+ return 0;
+}
+
+/*
+ * This reads the current MSB of the PIT counter, and
+ * checks if we are running on sufficiently fast and
+ * non-virtualized hardware.
+ *
+ * Our expectations are:
+ *
+ * - the PIT is running at roughly 1.19MHz
+ *
+ * - each IO is going to take about 1us on real hardware,
+ * but we allow it to be much faster (by a factor of 10) or
+ * _slightly_ slower (ie we allow up to a 2us read+counter
+ * update - anything else implies a unacceptably slow CPU
+ * or PIT for the fast calibration to work.
+ *
+ * - with 256 PIT ticks to read the value, we have 214us to
+ * see the same MSB (and overhead like doing a single TSC
+ * read per MSB value etc).
+ *
+ * - We're doing 2 reads per loop (LSB, MSB), and we expect
+ * them each to take about a microsecond on real hardware.
+ * So we expect a count value of around 100. But we'll be
+ * generous, and accept anything over 50.
+ *
+ * - if the PIT is stuck, and we see *many* more reads, we
+ * return early (and the next caller of pit_expect_msb()
+ * then consider it a failure when they don't see the
+ * next expected value).
+ *
+ * These expectations mean that we know that we have seen the
+ * transition from one expected value to another with a fairly
+ * high accuracy, and we didn't miss any events. We can thus
+ * use the TSC value at the transitions to calculate a pretty
+ * good value for the TSC frequencty.
+ */
+static inline int pit_verify_msb(unsigned char val)
+{
+ /* Ignore LSB */
+ inb(0x42);
+ return inb(0x42) == val;
+}
+
+static inline int pit_expect_msb(unsigned char val, u64 *tscp,
+ unsigned long *deltap)
+{
+ int count;
+ u64 tsc = 0, prev_tsc = 0;
+
+ for (count = 0; count < 50000; count++) {
+ if (!pit_verify_msb(val))
+ break;
+ prev_tsc = tsc;
+ tsc = rdtsc();
+ }
+ *deltap = rdtsc() - prev_tsc;
+ *tscp = tsc;
+
+ /*
+ * We require _some_ success, but the quality control
+ * will be based on the error terms on the TSC values.
+ */
+ return count > 5;
+}
+
+/*
+ * How many MSB values do we want to see? We aim for
+ * a maximum error rate of 500ppm (in practice the
+ * real error is much smaller), but refuse to spend
+ * more than 50ms on it.
+ */
+#define MAX_QUICK_PIT_MS 50
+#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
+
+static unsigned long quick_pit_calibrate(void)
+{
+ int i;
+ u64 tsc, delta;
+ unsigned long d1, d2;
+
+ /* Set the Gate high, disable speaker */
+ outb((inb(0x61) & ~0x02) | 0x01, 0x61);
+
+ /*
+ * Counter 2, mode 0 (one-shot), binary count
+ *
+ * NOTE! Mode 2 decrements by two (and then the
+ * output is flipped each time, giving the same
+ * final output frequency as a decrement-by-one),
+ * so mode 0 is much better when looking at the
+ * individual counts.
+ */
+ outb(0xb0, 0x43);
+
+ /* Start at 0xffff */
+ outb(0xff, 0x42);
+ outb(0xff, 0x42);
+
+ /*
+ * The PIT starts counting at the next edge, so we
+ * need to delay for a microsecond. The easiest way
+ * to do that is to just read back the 16-bit counter
+ * once from the PIT.
+ */
+ pit_verify_msb(0);
+
+ if (pit_expect_msb(0xff, &tsc, &d1)) {
+ for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
+ if (!pit_expect_msb(0xff-i, &delta, &d2))
+ break;
+
+ /*
+ * Iterate until the error is less than 500 ppm
+ */
+ delta -= tsc;
+ if (d1+d2 >= delta >> 11)
+ continue;
+
+ /*
+ * Check the PIT one more time to verify that
+ * all TSC reads were stable wrt the PIT.
+ *
+ * This also guarantees serialization of the
+ * last cycle read ('d2') in pit_expect_msb.
+ */
+ if (!pit_verify_msb(0xfe - i))
+ break;
+ goto success;
+ }
+ }
+ debug("Fast TSC calibration failed\n");
+ return 0;
+
+success:
+ /*
+ * Ok, if we get here, then we've seen the
+ * MSB of the PIT decrement 'i' times, and the
+ * error has shrunk to less than 500 ppm.
+ *
+ * As a result, we can depend on there not being
+ * any odd delays anywhere, and the TSC reads are
+ * reliable (within the error).
+ *
+ * kHz = ticks / time-in-seconds / 1000;
+ * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
+ * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
+ */
+ delta *= PIT_TICK_RATE;
+ delta /= (i*256*1000);
+ debug("Fast TSC calibration using PIT\n");
+ return delta / 1000;
+}
+
void timer_set_base(u64 base)
{
gd->arch.tsc_base = base;
return now_tick - gd->arch.tsc_base;
}
-#define PLATFORM_INFO_MSR 0xce
-
/* Get the speed of the TSC timer in MHz */
unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void)
{
- u32 ratio;
- u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
+ unsigned long fast_calibrate;
+
+ if (gd->arch.tsc_mhz)
+ return gd->arch.tsc_mhz;
+
+ fast_calibrate = try_msr_calibrate_tsc();
+ if (!fast_calibrate) {
+
+ fast_calibrate = quick_pit_calibrate();
+ if (!fast_calibrate)
+ panic("TSC frequency is ZERO");
+ }
- /* 100MHz times Max Non Turbo ratio */
- ratio = (platform_info >> 8) & 0xff;
- return 100 * ratio;
+ gd->arch.tsc_mhz = fast_calibrate;
+ return fast_calibrate;
}
unsigned long get_tbclk(void)
--- /dev/null
+BCM11130 BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcm28155_ap/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm11130_defconfig
--- /dev/null
+BCM11130_NAND BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcm28155_ap/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm11130_nand_defconfig
--- /dev/null
+BCM911360_ENTPHN-NS BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm911360_entphn-ns_defconfig
--- /dev/null
+BCM911360_ENTPHN BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm911360_entphn_defconfig
--- /dev/null
+BCM911360K BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm911360k_defconfig
--- /dev/null
+BCM958300K-NS BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm958300k-ns_defconfig
-Broadcom: Cygnus
+BCM958300K BOARD
M: Steve Rae <srae@broadcom.com>
S: Maintained
-F: board/broadcom/bcm958300k/
+F: board/broadcom/bcmcygnus/
F: include/configs/bcm_ep_board.h
F: configs/bcm958300k_defconfig
--- /dev/null
+BCM958305K BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm958305k_defconfig
-Broadcom: Northstar Plus
+BCM958622HR BOARD
M: Steve Rae <srae@broadcom.com>
S: Maintained
-F: board/broadcom/bcm958622hr/
+F: board/broadcom/bcmnsp/
F: include/configs/bcm_ep_board.h
F: configs/bcm958622hr_defconfig
return status;
}
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+}
+
+void smp_kick_all_cpus(void)
+{
+}
+
+void smp_waitloop(unsigned previous_address)
+{
+}
+#endif
-if TARGET_BCM958300K
+if TARGET_BCMCYGNUS
config SYS_BOARD
default "bcm_ep"
-if TARGET_BCM958622HR
+if TARGET_BCMNSP
config SYS_BOARD
default "bcm_ep"
default "coreboot"
config SYS_VENDOR
- default "chromebook-x86"
+ default "coreboot"
config SYS_SOC
default "coreboot"
COREBOOT BOARD
M: Simon Glass <sjg@chromium.org>
S: Maintained
-F: board/chromebook-x86/coreboot/
+F: board/coreboot/coreboot/
F: include/configs/coreboot.h
F: configs/coreboot-x86_defconfig
{
*(.vectors)
arch/arm/cpu/arm926ejs/start.o (.text*)
- arch/arm/cpu/arm926ejs/davinci/built-in.o (.text*)
+ arch/arm/cpu/arm926ejs/built-in.o (.text*)
drivers/mtd/nand/built-in.o (.text*)
*(.text*)
#include <image.h>
#include <asm/byteorder.h>
#include <fat.h>
+#include <flash.h>
#include <part.h>
#include "auto_update.h"
#define MAX_LOADSZ 0x1c00000
/* externals */
-extern int fat_register_device(block_dev_desc_t *, int);
-extern int file_fat_detectfs(void);
-extern long file_fat_read(const char *, void *, unsigned long);
long do_fat_read (const char *filename, void *buffer,
unsigned long maxsize, int dols);
-extern int flash_sect_erase(ulong, ulong);
-extern int flash_sect_protect (int, ulong, ulong);
-extern int flash_write (char *, ulong, ulong);
extern block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
e.date[3] & 0x80 ? "PM" : "");
/* Show MAC addresses */
- for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) {
+ for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
u8 *p = e.mac[i];
*/
for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
- p, min((sizeof(e) - i), 8));
+ p, min((int)(sizeof(e) - i), 8));
if (ret)
break;
udelay(5000); /* 5ms write cycle timing */
memset(e.mac[8], 0xff, 6);
#endif
- for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) {
+ for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) &&
memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
char ethaddr[18];
tmp_buf);
if (!n)
goto failure;
- result = min(size, blk_len - ofs);
+ result = min(size, (int)(blk_len - ofs));
memcpy(dst, tmp_buf + ofs, result);
dst += result;
size -= result;
src_buf = buf;
for (ptr = (uint8_t *)src_buf, i = 20; i > 0;
i -= data_size, ptr += data_size)
- memcpy(ptr, data, min(i, data_size));
+ memcpy(ptr, data,
+ min_t(size_t, i, data_size));
}
}
bin_func(dst_reg->digest, src_buf, 20);
struct key_program header;
uint32_t crc;
uint8_t buf[12];
- int i;
+ loff_t i;
if (fs_set_blk_dev(ifname, dev_part_str, fs_type))
goto failure;
- i = fs_read(path, (ulong)buf, 0, 12);
+ if (fs_read(path, (ulong)buf, 0, 12, &i) < 0)
+ goto failure;
if (i < 12)
goto failure;
header.magic = get_unaligned_be32(buf);
goto failure;
if (fs_set_blk_dev(ifname, dev_part_str, fs_type))
goto failure;
- i = fs_read(path, (ulong)result, 0,
- sizeof(struct key_program) + header.code_size);
+ if (fs_read(path, (ulong)result, 0,
+ sizeof(struct key_program) + header.code_size, &i) < 0)
+ goto failure;
if (i <= 0)
goto failure;
*result = header;
const char *image_path = "/ccdm.itb";
char *mac_path = NULL;
ulong image_addr;
- size_t image_size;
+ loff_t image_size;
uint32_t err;
printf("CCDM S2\n");
image_addr = (ulong)get_image_location();
if (fs_set_blk_dev("mmc", mmcdev, FS_TYPE_EXT))
goto failure;
- image_size = fs_read(image_path, image_addr, 0, 0);
+ if (fs_read(image_path, image_addr, 0, 0, &image_size) < 0)
+ goto failure;
if (image_size <= 0)
goto failure;
- printf("CCDM image found on %s, %d bytes\n", mmcdev, image_size);
+ printf("CCDM image found on %s, %lld bytes\n", mmcdev, image_size);
hmac_blob = load_key_chunk("mmc", mmcdev, FS_TYPE_EXT, mac_path);
if (!hmac_blob) {
--- /dev/null
+if TARGET_CHROMEBOOK_LINK
+
+config SYS_BOARD
+ default "chromebook_link"
+
+config SYS_VENDOR
+ default "google"
+
+config SYS_SOC
+ default "ivybridge"
+
+config SYS_CONFIG_NAME
+ default "chromebook_link"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_INTEL_SOCKET_RPGA989
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SOUTHBRIDGE_INTEL_C216
+ select HAVE_ACPI_RESUME
+ select MARK_GRAPHICS_MEM_WRCOMB
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config EARLY_POST_CROS_EC
+ bool "Enable early post to Chrome OS EC"
+ default y
+
+endif
--- /dev/null
+CHROMEBOOK LINK BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/google/chromebook_link/
+F: include/configs/chromebook_link.h
+F: configs/chromebook_link_defconfig
--- /dev/null
+#
+# Copyright (c) 2011 The Chromium OS Authors.
+# (C) Copyright 2008
+# Graeme Russ, graeme.russ@gmail.com.
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += link.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+
+int arch_early_init_r(void)
+{
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ return 0;
+}
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */
+ .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */
+ .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */
+ .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */
+ .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */
+ .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */
+ .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */
+ .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */
+ .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */
+ .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */
+ .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */
+ .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */
+ .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */
+ .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio1 = GPIO_LEVEL_HIGH,
+ .gpio6 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio7 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio12 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+ .gpio15 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */
+ .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */
+ .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */
+ .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */
+ .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */
+ .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio36 = GPIO_DIR_OUTPUT,
+ .gpio41 = GPIO_DIR_INPUT,
+ .gpio42 = GPIO_DIR_INPUT,
+ .gpio43 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio36 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_map link_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ },
+};
+
+int board_early_init_f(void)
+{
+ ich_gpio_set_gpio_map(&link_gpio_map);
+
+ return 0;
+}
--- /dev/null
+#
+# Copyright (c) 2014 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += early_init.o
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+ /* Enable post codes to EC */
+#ifdef CONFIG_EARLY_POST_CROS_EC
+ mov $0x1b, %ecx
+ rdmsr
+ and $0x100, %eax
+ test %eax, %eax
+ je 1f
+
+ mov $0x8000f8f0, %eax
+ mov $0xcf8, %dx
+ out %eax, (%dx)
+ mov $0xfed1c001, %eax
+ mov $0xcfc, %dx
+ out %eax, (%dx)
+ mov $0xfed1f410, %esp
+ mov (%esp), %eax
+ and $0xfffffffb, %eax
+ mov %eax, (%esp)
+1:
+#endif
+ jmp early_board_init_ret
void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
/* print up to 8 characters of the string */
- for (i = 0; i < min(strlen(str), 8); i++) {
+ for (i = 0; i < min((int)strlen(str), 8); i++) {
__raw_writel(str[i], reg);
reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
}
menu "Command line interface"
depends on !SPL_BUILD
+config HUSH_PARSER
+ bool "Use hush shell"
+ select SYS_HUSH_PARSER
+ help
+ This option enables the "hush" shell (from Busybox) as command line
+ interpreter, thus enabling powerful command line syntax like
+ if...then...else...fi conditionals or `&&' and '||'
+ constructs ("shell scripts").
+
+ If disabled, you get the old, much simpler behaviour with a somewhat
+ smaller memory footprint.
+
+config SYS_HUSH_PARSER
+ bool
+ help
+ Backward compatibility.
+
+comment "Commands"
+
+menu "Info commands"
+
+config CMD_BDI
+ bool "bdinfo"
+ help
+ Print board info
+
+config CMD_CONSOLE
+ bool "coninfo"
+ help
+ Print console devices and information.
+
+config CMD_LICENSE
+ bool "license"
+ help
+ Print GPL license text
+
+endmenu
+
+menu "Boot commands"
+
+config CMD_BOOTD
+ bool "bootd"
+ help
+ Run the command stored in the environment "bootcmd", i.e.
+ "bootd" does the same thing as "run bootcmd".
+
config CMD_BOOTM
- bool "Enable bootm command"
+ bool "bootm"
default y
help
Boot an application image from the memory.
-config CMD_CRC32
- bool "Enable crc32 command"
+config CMD_GO
+ bool "go"
default y
help
- Compute CRC32.
+ Start an application at a given address.
+
+config CMD_RUN
+ bool "run"
+ help
+ Run the command in the given environment variable.
+
+config CMD_IMI
+ bool "iminfo"
+ help
+ Print header information for application image.
+
+config CMD_IMLS
+ bool "imls"
+ help
+ List all images found in flash
+
+config CMD_XIMG
+ bool "imxtract"
+ help
+ Extract a part of a multi-image.
+
+endmenu
+
+menu "Environment commands"
config CMD_EXPORTENV
- bool "Enable env export command"
+ bool "env export"
default y
help
Export environments.
config CMD_IMPORTENV
- bool "Enable env import command"
+ bool "env import"
default y
help
Import environments.
-config CMD_GO
- bool "Enable go command"
+config CMD_EDITENV
+ bool "editenv"
+ help
+ Edit environment variable.
+
+config CMD_SAVEENV
+ bool "saveenv"
+ help
+ Run the command in the given environment variable.
+
+endmenu
+
+menu "Memory commands"
+
+config CMD_MEMORY
+ bool "md, mm, nm, mw, cp, cmp, base, loop"
+ help
+ Memeory commands.
+ md - memory display
+ mm - memory modify (auto-incrementing address)
+ nm - memory modify (constant address)
+ mw - memory write (fill)
+ cp - memory copy
+ cmp - memory compare
+ base - print or set address offset
+ loop - initinite loop on address range
+
+config CMD_CRC32
+ bool "crc32"
default y
help
- Start an application at a given address.
+ Compute CRC32.
+
+config LOOPW
+ bool "loopw"
+ help
+ Infinite write loop on address range
+
+config CMD_MEMTEST
+ bool "crc32"
+ help
+ Simple RAM read/write test.
+
+config CMD_MX_CYCLIC
+ bool "mdc, mwc"
+ help
+ mdc - memory display cyclic
+ mwc - memory write cyclic
+
+config CMD_MEMINFO
+ bool "meminfo"
+ help
+ Display memory information.
+
+endmenu
+
+menu "Device access commands"
+
+config CMD_LOADB
+ bool "loadb"
+ help
+ Load a binary file over serial line.
+
+config CMD_LOADS
+ bool "loads"
+ help
+ Load an S-Record file over serial line
+
+config CMD_FLASH
+ bool "flinfo, erase, protect"
+ help
+ NOR flash support.
+ flinfo - print FLASH memory information
+ erase - FLASH memory
+ protect - enable or disable FLASH write protection
+
+config CMD_NAND
+ bool "nand"
+ help
+ NAND support.
+
+config CMD_SPI
+ bool "sspi"
+ help
+ SPI utility command.
+
+config CMD_I2C
+ bool "i2c"
+ help
+ I2C support.
+
+config CMD_USB
+ bool "usb"
+ help
+ USB support.
+
+config CMD_FPGA
+ bool "fpga"
+ help
+ FPGA support.
+
+endmenu
+
+
+menu "Shell scripting commands"
+
+config CMD_ECHO
+ bool "echo"
+ help
+ Echo args to console
+
+config CMD_ITEST
+ bool "itest"
+ help
+ Return true/false on integer compare.
+
+config CMD_SOURCE
+ bool "source"
+ help
+ Run script from memory
+
+endmenu
+
+menu "Network commands"
+
+config CMD_NET
+ bool "bootp, tftpboot"
+ help
+ Network commands.
+ bootp - boot image via network using BOOTP/TFTP protocol
+ tftpboot - boot image via network using TFTP protocol
+
+config CMD_TFTPPUT
+ bool "tftp put"
+ help
+ TFTP put command, for uploading files to a server
+
+config CMD_TFTPSRV
+ bool "tftpsrv"
+ help
+ Act as a TFTP server and boot the first received file
+
+config CMD_RARP
+ bool "rarpboot"
+ help
+ Boot image via network using RARP/TFTP protocol
+
+config CMD_DHCP
+ bool "dhcp"
+ help
+ Boot image via network using DHCP/TFTP protocol
+
+config CMD_NFS
+ bool "nfs"
+ help
+ Boot image via network using NFS protocol.
+
+config CMD_PING
+ bool "ping"
+ help
+ Send ICMP ECHO_REQUEST to network host
+
+config CMD_CDP
+ bool "cdp"
+ help
+ Perform CDP network configuration
+
+config CMD_SNTP
+ bool "sntp"
+ help
+ Synchronize RTC via network
+
+config CMD_DNS
+ bool "dns"
+ help
+ Lookup the IP of a hostname
+
+config CMD_DNS
+ bool "dns"
+ help
+ Lookup the IP of a hostname
+
+config CMD_LINK_LOCAL
+ bool "linklocal"
+ help
+ Acquire a network IP address using the link-local protocol
+
+endmenu
+
+menu "Misc commands"
+
+config CMD_TIME
+ bool "time"
+ help
+ Run commands and summarize execution time.
+
+# TODO: rename to CMD_SLEEP
+config CMD_MISC
+ bool "sleep"
+ help
+ Delay execution for some time
+
+config CMD_TIMER
+ bool "timer"
+ help
+ Access the system timer.
+
+config CMD_SETGETDCR
+ bool "getdcr, setdcr, getidcr, setidcr"
+ depends on 4xx
+ help
+ getdcr - Get an AMCC PPC 4xx DCR's value
+ setdcr - Set an AMCC PPC 4xx DCR's value
+ getidcr - Get a register value via indirect DCR addressing
+ setidcr - Set a register value via indirect DCR addressing
+
+endmenu
endmenu
obj-$(CONFIG_USB_STORAGE) += usb_storage.o
endif
obj-$(CONFIG_CMD_FASTBOOT) += cmd_fastboot.o
+obj-$(CONFIG_CMD_FS_UUID) += cmd_fs_uuid.o
obj-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o
obj-$(CONFIG_CMD_THOR_DOWNLOAD) += cmd_thordown.o
static int display_text_info(void)
{
#ifndef CONFIG_SANDBOX
- ulong bss_start, bss_end;
+ ulong bss_start, bss_end, text_base;
bss_start = (ulong)&__bss_start;
bss_end = (ulong)&__bss_end;
- debug("U-Boot code: %08X -> %08lX BSS: -> %08lX\n",
#ifdef CONFIG_SYS_TEXT_BASE
- CONFIG_SYS_TEXT_BASE, bss_start, bss_end);
+ text_base = CONFIG_SYS_TEXT_BASE;
#else
- CONFIG_SYS_MONITOR_BASE, bss_start, bss_end);
+ text_base = CONFIG_SYS_MONITOR_BASE;
#endif
+
+ debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
+ text_base, bss_start, bss_end);
#endif
#ifdef CONFIG_MODEM_SUPPORT
struct sandbox_state *state = state_get_current();
const char *fname = state->fdt_fname;
void *blob;
- ssize_t size;
+ loff_t size;
int err;
int fd;
return -EINVAL;
}
- size = os_get_filesize(fname);
- if (size < 0) {
+ err = os_get_filesize(fname, &size);
+ if (err < 0) {
printf("Failed to file FDT file '%s'\n", fname);
- return -ENOENT;
+ return err;
}
fd = os_open(fname, OS_O_RDONLY);
if (fd < 0) {
gd->irq_sp = gd->start_addr_sp;
# endif
#else
-# ifdef CONFIG_PPC
+# if defined(CONFIG_PPC) || defined(CONFIG_MIPS)
ulong *s;
# endif
s = (ulong *) gd->start_addr_sp;
*s = 0; /* Terminate back chain */
*++s = 0; /* NULL return address */
+# elif defined(CONFIG_MIPS)
+ /* Clear initial stack frame */
+ s = (ulong *) gd->start_addr_sp;
+ *s-- = 0;
+ *s-- = 0;
+ gd->start_addr_sp = (ulong) s;
# endif /* Architecture specific code */
return 0;
setup_mon_len,
setup_fdt,
trace_early_init,
+ initf_malloc,
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
/* TODO: can this go into arch_cpu_init()? */
probecpu,
#endif
arch_cpu_init, /* basic arch cpu dependent setup */
-#ifdef CONFIG_X86
- cpu_init_f, /* TODO(sjg@chromium.org): remove */
-# ifdef CONFIG_OF_CONTROL
- find_fdt, /* TODO(sjg@chromium.org): remove */
-# endif
-#endif
mark_bootstage,
#ifdef CONFIG_OF_CONTROL
fdtdec_check_fdt,
#endif
- initf_malloc,
initf_dm,
#if defined(CONFIG_BOARD_EARLY_INIT_F)
board_early_init_f,
#endif
#if defined(CONFIG_HARD_SPI)
init_func_spi,
-#endif
-#ifdef CONFIG_X86
- dram_init_f, /* configure available RAM banks */
- calculate_relocation_address,
#endif
announce_dram_init,
/* TODO: unify all these dram functions? */
-#ifdef CONFIG_ARM
+#if defined(CONFIG_ARM) || defined(CONFIG_X86)
dram_init, /* configure available RAM banks */
#endif
#if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
*/
bootline = getenv("bootargs");
if (bootline) {
- memcpy((void *) bootaddr, bootline,
- max(strlen(bootline), 255));
- flush_cache(bootaddr, max(strlen(bootline), 255));
+ memcpy((void *)bootaddr, bootline,
+ max(strlen(bootline), (size_t)255));
+ flush_cache(bootaddr, max(strlen(bootline), (size_t)255));
} else {
sprintf(build_buf, CONFIG_SYS_VXWORKS_BOOT_DEVICE);
tmp = getenv("bootfile");
CONFIG_SYS_VXWORKS_ADD_PARAMS);
#endif
- memcpy((void *) bootaddr, build_buf,
- max(strlen(build_buf), 255));
- flush_cache(bootaddr, max(strlen(build_buf), 255));
+ memcpy((void *)bootaddr, build_buf,
+ max(strlen(build_buf), (size_t)255));
+ flush_cache(bootaddr, max(strlen(build_buf), (size_t)255));
}
/*
#if defined(CONFIG_CMD_EXT4_WRITE)
int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc,
- char *const argv[])
+ char *const argv[])
{
- const char *filename = "/";
- int dev, part;
- unsigned long ram_address;
- unsigned long file_size;
- disk_partition_t info;
- block_dev_desc_t *dev_desc;
-
- if (argc < 6)
- return cmd_usage(cmdtp);
-
- part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1);
- if (part < 0)
- return 1;
-
- dev = dev_desc->dev;
-
- /* get the filename */
- filename = argv[4];
-
- /* get the address in hexadecimal format (string to int) */
- ram_address = simple_strtoul(argv[3], NULL, 16);
-
- /* get the filesize in hexadecimal format */
- file_size = simple_strtoul(argv[5], NULL, 16);
-
- /* set the device as block device */
- ext4fs_set_blk_dev(dev_desc, &info);
-
- /* mount the filesystem */
- if (!ext4fs_mount(info.size)) {
- printf("Bad ext4 partition %s %d:%d\n", argv[1], dev, part);
- goto fail;
- }
-
- /* start write */
- if (ext4fs_write(filename, (unsigned char *)ram_address, file_size)) {
- printf("** Error ext4fs_write() **\n");
- goto fail;
- }
- ext4fs_close();
-
- return 0;
-
-fail:
- ext4fs_close();
-
- return 1;
+ return do_save(cmdtp, flag, argc, argv, FS_TYPE_EXT);
}
-U_BOOT_CMD(ext4write, 6, 1, do_ext4_write,
- "create a file in the root directory",
- "<interface> <dev[:part]> <addr> <absolute filename path> [sizebytes]\n"
- " - create a file in / directory");
+U_BOOT_CMD(ext4write, 7, 1, do_ext4_write,
+ "create a file in the root directory",
+ "<interface> <dev[:part]> <addr> <absolute filename path>\n"
+ " [sizebytes] [file offset]\n"
+ " - create a file in / directory");
#endif
"<interface> <dev[:part]> [directory]\n"
" - list files from 'dev' on 'interface' in a 'directory'");
-U_BOOT_CMD(ext4load, 6, 0, do_ext4_load,
+U_BOOT_CMD(ext4load, 7, 0, do_ext4_load,
"load binary file from a Ext4 filesystem",
"<interface> [<dev[:part]> [addr [filename [bytes [pos]]]]]\n"
" - load binary file 'filename' from 'dev' on 'interface'\n"
static int do_fat_fswrite(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
- long size;
+ loff_t size;
+ int ret;
unsigned long addr;
unsigned long count;
block_dev_desc_t *dev_desc = NULL;
count = simple_strtoul(argv[5], NULL, 16);
buf = map_sysmem(addr, count);
- size = file_fat_write(argv[4], buf, count);
+ ret = file_fat_write(argv[4], buf, 0, count, &size);
unmap_sysmem(buf);
- if (size == -1) {
+ if (ret < 0) {
printf("\n** Unable to write \"%s\" from %s %d:%d **\n",
argv[4], argv[1], dev, part);
return 1;
}
- printf("%ld bytes written\n", size);
+ printf("%llu bytes written\n", size);
return 0;
}
" If 'pos' is 0 or omitted, the file is read from the start."
)
+static int do_save_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ return do_save(cmdtp, flag, argc, argv, FS_TYPE_ANY);
+}
+
+U_BOOT_CMD(
+ save, 7, 0, do_save_wrapper,
+ "save file to a filesystem",
+ "<interface> <dev[:part]> <addr> <filename> bytes [pos]\n"
+ " - Save binary file 'filename' to partition 'part' on device\n"
+ " type 'interface' instance 'dev' from addr 'addr' in memory.\n"
+ " 'bytes' gives the size to save in bytes and is mandatory.\n"
+ " 'pos' gives the file byte position to start writing to.\n"
+ " If 'pos' is 0 or omitted, the file is written from the start."
+)
+
static int do_ls_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
--- /dev/null
+/*
+ * cmd_fs_uuid.c -- fsuuid command
+ *
+ * Copyright (C) 2014, Bachmann electronic GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fs.h>
+
+static int do_fs_uuid_wrapper(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ return do_fs_uuid(cmdtp, flag, argc, argv, FS_TYPE_ANY);
+}
+
+U_BOOT_CMD(
+ fsuuid, 4, 1, do_fs_uuid_wrapper,
+ "Look up a filesystem UUID",
+ "<interface> <dev>:<part>\n"
+ " - print filesystem UUID\n"
+ "fsuuid <interface> <dev>:<part> <varname>\n"
+ " - set environment variable to filesystem UUID\n"
+);
#include <common.h>
#include <command.h>
#include <u-boot/md5.h>
+#include <asm/io.h>
/*
* Store the resulting sum to an address or variable
int verify = 0;
int ac;
char * const *av;
+ void *buf;
if (argc < 3)
return CMD_RET_USAGE;
addr = simple_strtoul(*av++, NULL, 16);
len = simple_strtoul(*av++, NULL, 16);
- md5_wd((unsigned char *) addr, len, output, CHUNKSZ_MD5);
+ buf = map_sysmem(addr, len);
+ md5_wd(buf, len, output, CHUNKSZ_MD5);
+ unmap_sysmem(buf);
if (!verify) {
printf("md5 for %08lx ... %08lx ==> ", addr, addr + len - 1);
unsigned long addr, len;
unsigned int i;
u8 output[16];
+ void *buf;
if (argc < 3)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[1], NULL, 16);
len = simple_strtoul(argv[2], NULL, 16);
- md5_wd((unsigned char *) addr, len, output, CHUNKSZ_MD5);
+ buf = map_sysmem(addr, len);
+ md5_wd(buf, len, output, CHUNKSZ_MD5);
+ unmap_sysmem(buf);
+
printf("md5 for %08lx ... %08lx ==> ", addr, addr + len - 1);
for (i = 0; i < 16; i++)
printf("%02x", output[i]);
*/
void pciinfo(int BusNum, int ShortPCIListing)
{
+ struct pci_controller *hose = pci_bus_to_hose(BusNum);
int Device;
int Function;
unsigned char HeaderType;
unsigned short VendorID;
pci_dev_t dev;
+ if (!hose)
+ return;
+
printf("Scanning PCI devices on bus %d\n", BusNum);
if (ShortPCIListing) {
dev = PCI_BDF(BusNum, Device, Function);
+ if (pci_skip_dev(hose, dev))
+ continue;
+
pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
continue;
static struct spi_flash *flash;
-
/*
* This function computes the length argument for the erase command.
* The length on which the command is to operate can be given in two forms:
{
/* less accurate but avoids overflow */
if (len >= ((unsigned int) -1) / 1024)
- return len / (max(get_timer(start_ms) / 1024, 1));
+ return len / (max(get_timer(start_ms) / 1024, 1UL));
else
- return 1024 * len / max(get_timer(start_ms), 1);
+ return 1024 * len / max(get_timer(start_ms), 1UL);
}
static int do_spi_flash_probe(int argc, char * const argv[])
ulong last_update = get_timer(0);
for (; buf < end && !err_oper; buf += todo, offset += todo) {
- todo = min(end - buf, flash->sector_size);
+ todo = min_t(size_t, end - buf, flash->sector_size);
if (get_timer(last_update) > 100) {
printf(" \rUpdating, %zu%% %lu B/s",
100 - (end - buf) / scale,
for (i = 0; i < len; i++) {
if (vbuf[i] != 0xff) {
printf("Check failed at %d\n", i);
- print_buffer(i, vbuf + i, 1, min(len - i, 0x40), 0);
+ print_buffer(i, vbuf + i, 1,
+ min_t(uint, len - i, 0x40), 0);
return -1;
}
}
for (i = 0; i < len; i++) {
if (buf[i] != vbuf[i]) {
printf("Verify failed at %d, good data:\n", i);
- print_buffer(i, buf + i, 1, min(len - i, 0x40), 0);
+ print_buffer(i, buf + i, 1,
+ min_t(uint, len - i, 0x40), 0);
printf("Bad data:\n");
- print_buffer(i, vbuf + i, 1, min(len - i, 0x40), 0);
+ print_buffer(i, vbuf + i, 1,
+ min_t(uint, len - i, 0x40), 0);
return -1;
}
}
disk_partition_t info;
int dev, part;
int err;
+ loff_t size;
err = env_export(&env_new);
if (err)
return 1;
}
- err = file_fat_write(FAT_ENV_FILE, (void *)&env_new, sizeof(env_t));
+ err = file_fat_write(FAT_ENV_FILE, (void *)&env_new, 0, sizeof(env_t),
+ &size);
if (err == -1) {
printf("\n** Unable to write \"%s\" from %s%d:%d **\n",
FAT_ENV_FILE, FAT_ENV_INTERFACE, dev, part);
u_char *char_ptr;
blocksize = nand_info[0].erasesize;
- len = min(blocksize, CONFIG_ENV_SIZE);
+ len = min(blocksize, (size_t)CONFIG_ENV_SIZE);
while (amount_saved < CONFIG_ENV_SIZE && offset < end) {
if (nand_block_isbad(&nand_info[0], offset)) {
if (!blocksize)
return 1;
- len = min(blocksize, CONFIG_ENV_SIZE);
+ len = min(blocksize, (size_t)CONFIG_ENV_SIZE);
while (amount_loaded < CONFIG_ENV_SIZE && offset < end) {
if (nand_block_isbad(&nand_info[0], offset)) {
*/
int fdt_alloc_phandle(void *blob)
{
- int offset, phandle = 0;
+ int offset;
+ uint32_t phandle = 0;
for (offset = fdt_next_node(blob, -1, NULL); offset >= 0;
offset = fdt_next_node(blob, offset, NULL)) {
else
return;
- *axis = max(0, axis_alignment);
+ *axis = max(0, (int)axis_alignment);
}
#endif
void lcd_position_cursor(unsigned col, unsigned row)
{
- console_col = min(col, CONSOLE_COLS - 1);
- console_row = min(row, CONSOLE_ROWS - 1);
+ console_col = min_t(short, col, CONSOLE_COLS - 1);
+ console_row = min_t(short, row, CONSOLE_ROWS - 1);
}
int lcd_get_pixel_width(void)
break;
#endif
default:
- debug("SPL: Un-supported Boot Device\n");
+#if defined(CONFIG_SPL_SERIAL_SUPPORT) && defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+ printf("SPL: Unsupported Boot Device %d\n", boot_device);
+#endif
hang();
}
{
s32 err;
struct image_header *header;
- int filelen;
+ loff_t filelen, actlen;
disk_partition_t part_info = {};
header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
goto end;
}
- filelen = err = ext4fs_open(filename);
+ err = ext4fs_open(filename, &filelen);
if (err < 0) {
puts("spl: ext4fs_open failed\n");
goto end;
}
- err = ext4fs_read((char *)header, sizeof(struct image_header));
+ err = ext4fs_read((char *)header, sizeof(struct image_header), &actlen);
if (err <= 0) {
puts("spl: ext4fs_read failed\n");
goto end;
spl_parse_image_header(header);
- err = ext4fs_read((char *)spl_image.load_addr, filelen);
+ err = ext4fs_read((char *)spl_image.load_addr, filelen, &actlen);
end:
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition)
{
int err;
- int filelen;
+ __maybe_unused loff_t filelen, actlen;
disk_partition_t part_info = {};
__maybe_unused char *file;
#if defined(CONFIG_SPL_ENV_SUPPORT) && defined(CONFIG_SPL_OS_BOOT)
file = getenv("falcon_args_file");
if (file) {
- filelen = err = ext4fs_open(file);
+ err = ext4fs_open(file, &filelen);
if (err < 0) {
puts("spl: ext4fs_open failed\n");
goto defaults;
}
- err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen);
+ err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, &actlen);
if (err <= 0) {
printf("spl: error reading image %s, err - %d, falling back to default\n",
file, err);
defaults:
#endif
- filelen = err = ext4fs_open(CONFIG_SPL_FS_LOAD_ARGS_NAME);
+ err = ext4fs_open(CONFIG_SPL_FS_LOAD_ARGS_NAME, &filelen);
if (err < 0)
puts("spl: ext4fs_open failed\n");
- err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen);
+ err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, &actlen);
if (err <= 0) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: error reading image %s, err - %d\n",
}
descriptor = (struct usb_hub_descriptor *)buffer;
- length = min(descriptor->bLength, sizeof(struct usb_hub_descriptor));
+ length = min_t(int, descriptor->bLength,
+ sizeof(struct usb_hub_descriptor));
if (usb_get_hub_descriptor(dev, buffer, length) < 0) {
debug("usb_hub_configure: failed to get hub " \
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="SYS_MMC_ENV_DEV=0"
+CONFIG_ARM=y
+CONFIG_TARGET_BCM28155_AP=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ARM=y
+CONFIG_TARGET_BCM28155_AP=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000,ARMV7_NONSEC"
+CONFIG_ARM=y
+CONFIG_TARGET_BCMCYGNUS=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000"
+CONFIG_ARM=y
+CONFIG_TARGET_BCMCYGNUS=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
+CONFIG_ARM=y
+CONFIG_TARGET_BCMCYGNUS=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000,ARMV7_NONSEC"
+CONFIG_ARM=y
+CONFIG_TARGET_BCMCYGNUS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
CONFIG_ARM=y
-CONFIG_TARGET_BCM958300K=y
+CONFIG_TARGET_BCMCYGNUS=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
+CONFIG_ARM=y
+CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000"
CONFIG_ARM=y
-CONFIG_TARGET_BCM958622HR=y
+CONFIG_TARGET_BCMNSP=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
+CONFIG_X86=y
+CONFIG_TARGET_CHROMEBOOK_LINK=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_SEPARATE=y
+CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
+CONFIG_HAVE_MRC=y
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
--- /dev/null
+Intel LPC Device Binding
+========================
+
+The device tree node which describes the operation of the Intel Low Pin
+Count device is as follows:
+
+Required properties :
+- compatible = "intel,lpc"
+- gen-dec : Specifies the values for the gen-dec registers. Up to four cell
+ pairs can be provided - the first of each pair is the base address and
+ the second is the size. These are written into the GENx_DEC registers of
+ the LPC device
+
+
+Example
+-------
+
+lpc {
+ compatible = "intel,lpc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ gen-dec = <0x800 0xfc 0x900 0xfc>;
+};
u16 now_blocks; /* number of blocks per iteration */
u32 transfer_size; /* number of bytes per iteration */
- now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
+ now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
transfer_size = ATA_SECT_SIZE * now_blocks;
if (transfer_size > user_buffer_size) {
u16 word;
if (init_done == 1 && dev < sata_info.maxport)
- return 1;
+ return 0;
init_done = 1;
#ifdef CONFIG_SYS_FSL_DDR4
/* tXP=max(4nCK, 6ns) */
- int txp = max(mclk_ps * 4, 6000); /* unit=ps */
+ int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
trwt_mclk = 2;
twrt_mclk = 1;
act_pd_exit_mclk = picos_to_mclk(txp);
* MRS_CYC = max(tMRD, tMOD)
* tMRD = 8nCK, tMOD = max(24nCK, 15ns)
*/
- tmrd_mclk = max(24, picos_to_mclk(15000));
+ tmrd_mclk = max(24U, picos_to_mclk(15000));
#elif defined(CONFIG_SYS_FSL_DDR3)
unsigned int data_rate = get_ddr_freq(0);
int txp;
* spec has not the tAXPD, we use
* tAXPD=1, need design to confirm.
*/
- txp = max(mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
+ txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
tmrd_mclk = 4;
/* set the turnaround time */
#ifdef CONFIG_SYS_FSL_DDR4
refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8;
wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
- acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4);
- wrtord_mclk = max(2, picos_to_mclk(2500));
+ acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4U);
+ wrtord_mclk = max(2U, picos_to_mclk(2500));
if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
else
wr_data_delay = popts->write_data_delay;
#ifdef CONFIG_SYS_FSL_DDR4
cpo = 0;
- cke_pls = max(3, picos_to_mclk(5000));
+ cke_pls = max(3U, picos_to_mclk(5000));
#elif defined(CONFIG_SYS_FSL_DDR3)
/*
* cke pulse = max(3nCK, 7.5ns) for DDR3-800
* max(3nCK, 5.625ns) for DDR3-1066, 1333
* max(3nCK, 5ns) for DDR3-1600, 1866, 2133
*/
- cke_pls = max(3, picos_to_mclk(mclk_ps > 1870 ? 7500 :
+ cke_pls = max(3U, picos_to_mclk(mclk_ps > 1870 ? 7500 :
(mclk_ps > 1245 ? 5625 : 5000)));
#else
cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
unsigned int txpr, tcksre, tcksrx;
unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
- txpr = max(5, picos_to_mclk(common_dimm->trfc1_ps + 10000));
- tcksre = max(5, picos_to_mclk(10000));
- tcksrx = max(5, picos_to_mclk(10000));
+ txpr = max(5U, picos_to_mclk(common_dimm->trfc1_ps + 10000));
+ tcksre = max(5U, picos_to_mclk(10000));
+ tcksrx = max(5U, picos_to_mclk(10000));
par_lat = 0;
cs_to_cmd = 0;
}
acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
- wrtord_bg = max(4, picos_to_mclk(7500));
+ wrtord_bg = max(4U, picos_to_mclk(7500));
if (popts->otf_burst_chop_en)
wrtord_bg += 2;
* Find minimum tckmax_ps to find fastest slow speed,
* i.e., this is the slowest the whole system can go.
*/
- tckmax_ps = min(tckmax_ps, dimm_params[i].tckmax_ps);
+ tckmax_ps = min(tckmax_ps,
+ (unsigned int)dimm_params[i].tckmax_ps);
#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
- taamin_ps = max(taamin_ps, dimm_params[i].taa_ps);
+ taamin_ps = max(taamin_ps,
+ (unsigned int)dimm_params[i].taa_ps);
#endif
- tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
- trcd_ps = max(trcd_ps, dimm_params[i].trcd_ps);
- trp_ps = max(trp_ps, dimm_params[i].trp_ps);
- tras_ps = max(tras_ps, dimm_params[i].tras_ps);
+ tckmin_x_ps = max(tckmin_x_ps,
+ (unsigned int)dimm_params[i].tckmin_x_ps);
+ trcd_ps = max(trcd_ps, (unsigned int)dimm_params[i].trcd_ps);
+ trp_ps = max(trp_ps, (unsigned int)dimm_params[i].trp_ps);
+ tras_ps = max(tras_ps, (unsigned int)dimm_params[i].tras_ps);
#ifdef CONFIG_SYS_FSL_DDR4
- trfc1_ps = max(trfc1_ps, dimm_params[i].trfc1_ps);
- trfc2_ps = max(trfc2_ps, dimm_params[i].trfc2_ps);
- trfc4_ps = max(trfc4_ps, dimm_params[i].trfc4_ps);
- trrds_ps = max(trrds_ps, dimm_params[i].trrds_ps);
- trrdl_ps = max(trrdl_ps, dimm_params[i].trrdl_ps);
- tccdl_ps = max(tccdl_ps, dimm_params[i].tccdl_ps);
+ trfc1_ps = max(trfc1_ps,
+ (unsigned int)dimm_params[i].trfc1_ps);
+ trfc2_ps = max(trfc2_ps,
+ (unsigned int)dimm_params[i].trfc2_ps);
+ trfc4_ps = max(trfc4_ps,
+ (unsigned int)dimm_params[i].trfc4_ps);
+ trrds_ps = max(trrds_ps,
+ (unsigned int)dimm_params[i].trrds_ps);
+ trrdl_ps = max(trrdl_ps,
+ (unsigned int)dimm_params[i].trrdl_ps);
+ tccdl_ps = max(tccdl_ps,
+ (unsigned int)dimm_params[i].tccdl_ps);
#else
- twr_ps = max(twr_ps, dimm_params[i].twr_ps);
- twtr_ps = max(twtr_ps, dimm_params[i].twtr_ps);
- trfc_ps = max(trfc_ps, dimm_params[i].trfc_ps);
- trrd_ps = max(trrd_ps, dimm_params[i].trrd_ps);
- trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps);
+ twr_ps = max(twr_ps, (unsigned int)dimm_params[i].twr_ps);
+ twtr_ps = max(twtr_ps, (unsigned int)dimm_params[i].twtr_ps);
+ trfc_ps = max(trfc_ps, (unsigned int)dimm_params[i].trfc_ps);
+ trrd_ps = max(trrd_ps, (unsigned int)dimm_params[i].trrd_ps);
+ trtp_ps = max(trtp_ps, (unsigned int)dimm_params[i].trtp_ps);
#endif
- trc_ps = max(trc_ps, dimm_params[i].trc_ps);
+ trc_ps = max(trc_ps, (unsigned int)dimm_params[i].trc_ps);
#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
- tis_ps = max(tis_ps, dimm_params[i].tis_ps);
- tih_ps = max(tih_ps, dimm_params[i].tih_ps);
- tds_ps = max(tds_ps, dimm_params[i].tds_ps);
- tdh_ps = max(tdh_ps, dimm_params[i].tdh_ps);
- tqhs_ps = max(tqhs_ps, dimm_params[i].tqhs_ps);
+ tis_ps = max(tis_ps, (unsigned int)dimm_params[i].tis_ps);
+ tih_ps = max(tih_ps, (unsigned int)dimm_params[i].tih_ps);
+ tds_ps = max(tds_ps, (unsigned int)dimm_params[i].tds_ps);
+ tdh_ps = max(tdh_ps, (unsigned int)dimm_params[i].tdh_ps);
+ tqhs_ps = max(tqhs_ps, (unsigned int)dimm_params[i].tqhs_ps);
/*
* Find maximum tdqsq_max_ps to find slowest.
*
* FIXME: is finding the slowest value the correct
* strategy for this parameter?
*/
- tdqsq_max_ps = max(tdqsq_max_ps, dimm_params[i].tdqsq_max_ps);
+ tdqsq_max_ps = max(tdqsq_max_ps,
+ (unsigned int)dimm_params[i].tdqsq_max_ps);
#endif
refresh_rate_ps = max(refresh_rate_ps,
- dimm_params[i].refresh_rate_ps);
+ (unsigned int)dimm_params[i].refresh_rate_ps);
/* extended_op_srt is either 0 or 1, 0 having priority */
extended_op_srt = min(extended_op_srt,
- dimm_params[i].extended_op_srt);
+ (unsigned int)dimm_params[i].extended_op_srt);
}
outpdimm->ndimms_present = number_of_dimms - temp1;
i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
ret = i2c_read(i2c_address, 0, 1,
(uchar *)((ulong)spd + 256),
- min(256, sizeof(generic_spd_eeprom_t) - 256));
+ min(256,
+ (int)sizeof(generic_spd_eeprom_t) - 256));
}
#else
ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
readn = 0;
while (size > 0) {
/* get chunk that can be read */
- chunk = min(size, dfu->b_left);
+ chunk = min((long)size, dfu->b_left);
/* consume */
if (chunk > 0) {
memcpy(buf, dfu->i_buf, chunk);
unsigned long ts; /* Timestamp */
u32 isr_status, swap;
u32 partialbit = 0;
- u32 blocksize;
- u32 pos = 0;
+ loff_t blocksize, actread;
+ loff_t pos = 0;
int fstype;
char *interface, *dev_part, *filename;
if (fs_set_blk_dev(interface, dev_part, fstype))
return FPGA_FAIL;
- if (fs_read(filename, (u32) buf, pos, blocksize) < 0)
+ if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
return FPGA_FAIL;
if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
return FPGA_FAIL;
if (bsize > blocksize) {
- if (fs_read(filename, (u32) buf, pos, blocksize) < 0)
+ if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
return FPGA_FAIL;
} else {
- if (fs_read(filename, (u32) buf, pos, bsize) < 0)
+ if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0)
return FPGA_FAIL;
}
} while (bsize > blocksize);
return 0;
}
+/*
+ * get a number comprised of multiple GPIO values. gpio_num_array points to
+ * the array of gpio pin numbers to scan, terminated by -1.
+ */
+unsigned gpio_get_values_as_int(const int *gpio_num_array)
+{
+ int gpio;
+ unsigned bitmask = 1;
+ unsigned vector = 0;
+
+ while (bitmask &&
+ ((gpio = *gpio_num_array++) != -1)) {
+ if (gpio_get_value(gpio))
+ vector |= bitmask;
+ bitmask <<= 1;
+ }
+ return vector;
+}
+
/* We need to renumber the GPIOs when any driver is probed/removed */
static int gpio_renumber(struct udevice *removed_dev)
{
#include <pci.h>
#include <asm/gpio.h>
#include <asm/io.h>
+#include <asm/pci.h>
+#ifdef CONFIG_X86_RESET_VECTOR
+#include <asm/arch/pch.h>
+#define SUPPORT_GPIO_SETUP
+#endif
#define GPIO_PER_BANK 32
uint32_t lvl;
};
+#ifdef SUPPORT_GPIO_SETUP
+static void setup_pch_gpios(const struct pch_gpio_map *gpio)
+{
+ u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
+
+ /* GPIO Set 1 */
+ if (gpio->set1.level)
+ outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
+ if (gpio->set1.mode)
+ outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
+ if (gpio->set1.direction)
+ outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
+ if (gpio->set1.reset)
+ outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
+ if (gpio->set1.invert)
+ outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
+ if (gpio->set1.blink)
+ outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
+
+ /* GPIO Set 2 */
+ if (gpio->set2.level)
+ outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
+ if (gpio->set2.mode)
+ outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
+ if (gpio->set2.direction)
+ outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
+ if (gpio->set2.reset)
+ outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
+
+ /* GPIO Set 3 */
+ if (gpio->set3.level)
+ outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
+ if (gpio->set3.mode)
+ outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
+ if (gpio->set3.direction)
+ outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
+ if (gpio->set3.reset)
+ outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
+}
+
+/* TODO: Move this to device tree, or platform data */
+void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
+{
+ gd->arch.gpio_map = map;
+}
+#endif /* SUPPORT_GPIO_SETUP */
+
static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
{
struct ich6_bank_platdata *plat = dev_get_platdata(dev);
pci_dev = PCI_BDF(0, 0x1f, 0);
/* Is the device present? */
- pci_read_config_word(pci_dev, PCI_VENDOR_ID, &tmpword);
+ tmpword = pci_read_config16(pci_dev, PCI_VENDOR_ID);
if (tmpword != PCI_VENDOR_ID_INTEL) {
debug("%s: wrong VendorID\n", __func__);
return -ENODEV;
}
- pci_read_config_word(pci_dev, PCI_DEVICE_ID, &tmpword);
+ tmpword = pci_read_config16(pci_dev, PCI_DEVICE_ID);
debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword);
/*
* We'd like to validate the Device ID too, but pretty much any
*/
/* I/O should already be enabled (it's a RO bit). */
- pci_read_config_word(pci_dev, PCI_COMMAND, &tmpword);
+ tmpword = pci_read_config16(pci_dev, PCI_COMMAND);
if (!(tmpword & PCI_COMMAND_IO)) {
debug("%s: device IO not enabled\n", __func__);
return -ENODEV;
}
/* Header Type must be normal (bits 6-0 only; see spec.) */
- pci_read_config_byte(pci_dev, PCI_HEADER_TYPE, &tmpbyte);
+ tmpbyte = pci_read_config8(pci_dev, PCI_HEADER_TYPE);
if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) {
debug("%s: invalid Header type\n", __func__);
return -ENODEV;
}
/* Base Class must be a bridge device */
- pci_read_config_byte(pci_dev, PCI_CLASS_CODE, &tmpbyte);
+ tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_CODE);
if (tmpbyte != PCI_CLASS_CODE_BRIDGE) {
debug("%s: invalid class\n", __func__);
return -ENODEV;
}
/* Sub Class must be ISA */
- pci_read_config_byte(pci_dev, PCI_CLASS_SUB_CODE, &tmpbyte);
+ tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE);
if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) {
debug("%s: invalid subclass\n", __func__);
return -ENODEV;
}
/* Programming Interface must be 0x00 (no others exist) */
- pci_read_config_byte(pci_dev, PCI_CLASS_PROG, &tmpbyte);
+ tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_PROG);
if (tmpbyte != 0x00) {
debug("%s: invalid interface type\n", __func__);
return -ENODEV;
* that it was unused (or undocumented). Check that it looks
* okay: not all ones or zeros, and mapped to I/O space (bit 0).
*/
- pci_read_config_dword(pci_dev, PCI_CFG_GPIOBASE, &tmplong);
+ tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
if (tmplong == 0x00000000 || tmplong == 0xffffffff ||
!(tmplong & 0x00000001)) {
debug("%s: unexpected GPIOBASE value\n", __func__);
return 0;
}
-int ich6_gpio_probe(struct udevice *dev)
+static int ich6_gpio_probe(struct udevice *dev)
{
struct ich6_bank_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev->uclass_priv;
struct ich6_bank_priv *bank = dev_get_priv(dev);
+#ifdef SUPPORT_GPIO_SETUP
+ if (gd->arch.gpio_map) {
+ setup_pch_gpios(gd->arch.gpio_map);
+ gd->arch.gpio_map = NULL;
+ }
+#endif
uc_priv->gpio_count = GPIO_PER_BANK;
uc_priv->bank_name = plat->bank_name;
bank->use_sel = plat->base_addr;
return 0;
}
-int ich6_gpio_request(struct udevice *dev, unsigned offset, const char *label)
+static int ich6_gpio_request(struct udevice *dev, unsigned offset,
+ const char *label)
{
struct ich6_bank_priv *bank = dev_get_priv(dev);
u32 tmplong;
static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
unsigned int i2c_clk, unsigned int speed)
{
- unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);
+ unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX);
/*
* We want to choose an FDR/DFSR that generates an I2C bus speed that
return -1;
}
- len = min(p[1], din_len);
+ len = min((int)p[1], din_len);
cros_ec_dump_data("in", -1, p, len + 3);
/* Response code is first byte of message */
relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
1000000000) + 2 * (relax + 1) - 1;
- strobe_prog = DIV_ROUND(ipg_clk * BV_TIMING_STROBE_PROG_US, 1000000) +
- 2 * (relax + 1) - 1;
+ strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US,
+ 1000000) + 2 * (relax + 1) - 1;
timing = BF(strobe_read, TIMING_STROBE_READ) |
BF(relax, TIMING_RELAX) |
#endif
cfg->cfg.f_min = 400000;
- cfg->cfg.f_max = min(gd->arch.sdhc_clk, 52000000);
+ cfg->cfg.f_max = min(gd->arch.sdhc_clk, (u32)52000000);
cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
while (len) {
/* The controller has data ready */
if (readl(®s->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) {
- size = min(len, PXAMMC_FIFO_SIZE);
+ size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
len -= size;
size /= 4;
while (len) {
/* The controller is ready to receive data */
if (readl(®s->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) {
- size = min(len, PXAMMC_FIFO_SIZE);
+ size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
len -= size;
size /= 4;
while (size--)
writel(*buf++, ®s->txfifo);
- if (min(len, PXAMMC_FIFO_SIZE) < 32)
+ if (min(len, (uint32_t)PXAMMC_FIFO_SIZE) < 32)
writel(MMC_PRTBUF_BUF_PART_FULL, ®s->prtbuf);
}
if (ret < 0)
return ret;
- readlen = min(page_size - column, size);
+ readlen = min(page_size - column, (int)size);
memcpy(dst, page_buffer, readlen);
column = 0;
int ret;
while (size > 0) {
- todo = min(size, sizeof(sandbox_sf_0xff));
+ todo = min(size, (int)sizeof(sandbox_sf_0xff));
ret = os_write(sbsf->fd, sandbox_sf_0xff, todo);
if (ret != todo)
return ret;
return ret;
#endif
byte_addr = offset % page_size;
- chunk_len = min(len - actual, page_size - byte_addr);
+ chunk_len = min(len - actual, (size_t)(page_size - byte_addr));
if (flash->spi->max_write_size)
- chunk_len = min(chunk_len, flash->spi->max_write_size);
+ chunk_len = min(chunk_len,
+ (size_t)flash->spi->max_write_size);
spi_flash_addr(write_addr, cmd);
len = strlen(s);
while (len) {
- int send_len = min(len, sizeof(input_buffer));
+ int send_len = min(len, (int)sizeof(input_buffer));
nc_send_packet(s, send_len);
len -= send_len;
s += send_len;
bdf < PCI_BDF(bus + 1, 0, 0);
#endif
bdf += PCI_BDF(0, 0, 1)) {
+ if (pci_skip_dev(hose, bdf))
+ continue;
+
if (!PCI_FUNC(bdf)) {
pci_read_config_byte(bdf,
PCI_HEADER_TYPE,
#endif
#ifdef CONFIG_PCI_PNP
- sub_bus = max(pciauto_config_device(hose, dev), sub_bus);
+ sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
+ sub_bus);
#else
cfg = pci_find_config(hose, class, vendor, device,
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
if (cfg) {
cfg->config_device(hose, dev, cfg);
- sub_bus = max(sub_bus, hose->current_busno);
+ sub_bus = max(sub_bus,
+ (unsigned int)hose->current_busno);
}
#endif
n = pci_hose_scan_bus(hose, hose->current_busno);
/* figure out the deepest we've gone for this leg */
- sub_bus = max(n, sub_bus);
+ sub_bus = max((unsigned int)n, sub_bus);
pciauto_postscan_setup_bridge(hose, dev, sub_bus);
sub_bus = hose->current_busno;
DECLARE_GLOBAL_DATA_PTR;
-/* The currently-selected console serial device */
-struct udevice *cur_dev __attribute__ ((section(".data")));
-
/*
* Table with supported baudrates (defined in config_xyz.h)
*/
static void serial_find_console_or_panic(void)
{
+ struct udevice *dev;
+
#ifdef CONFIG_OF_CONTROL
int node;
node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path");
if (node < 0)
node = fdtdec_get_alias_node(gd->fdt_blob, "console");
- if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &cur_dev))
+ if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &dev)) {
+ gd->cur_serial_dev = dev;
return;
+ }
/*
* If the console is not marked to be bound before relocation, bind
* it anyway.
*/
if (node > 0 &&
- !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &cur_dev)) {
- if (!device_probe(cur_dev))
+ !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &dev)) {
+ if (!device_probe(dev)) {
+ gd->cur_serial_dev = dev;
return;
- cur_dev = NULL;
+ }
}
#endif
/*
#else
#define INDEX 0
#endif
- if (uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &cur_dev) &&
- uclass_get_device(UCLASS_SERIAL, INDEX, &cur_dev) &&
- (uclass_first_device(UCLASS_SERIAL, &cur_dev) || !cur_dev))
+ if (uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &dev) &&
+ uclass_get_device(UCLASS_SERIAL, INDEX, &dev) &&
+ (uclass_first_device(UCLASS_SERIAL, &dev) || !dev))
panic("No serial driver found");
#undef INDEX
+ gd->cur_serial_dev = dev;
}
/* Called prior to relocation */
void serial_putc(char ch)
{
- _serial_putc(cur_dev, ch);
+ _serial_putc(gd->cur_serial_dev, ch);
}
void serial_puts(const char *str)
{
- _serial_puts(cur_dev, str);
+ _serial_puts(gd->cur_serial_dev, str);
}
int serial_getc(void)
{
- return _serial_getc(cur_dev);
+ return _serial_getc(gd->cur_serial_dev);
}
int serial_tstc(void)
{
- return _serial_tstc(cur_dev);
+ return _serial_tstc(gd->cur_serial_dev);
}
void serial_setbrg(void)
{
- struct dm_serial_ops *ops = serial_get_ops(cur_dev);
+ struct dm_serial_ops *ops = serial_get_ops(gd->cur_serial_dev);
if (ops->setbrg)
- ops->setbrg(cur_dev, gd->baudrate);
+ ops->setbrg(gd->cur_serial_dev, gd->baudrate);
}
void serial_stdio_init(void)
space_avail =
current_urb->buffer_length -
current_urb->actual_length;
- popnum = min(space_avail, buf->size);
+ popnum = min(space_avail, (int)buf->size);
if (popnum == 0)
break;
spi_cs_deactivate(slave);
return 0;
}
- buf_len = 2 * cmd_len + min(data_len, max_tran_len);
+ buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len);
len = cmd_len + data_len;
rx_offset = cmd_len;
buffer = (unsigned char *)malloc(buf_len);
if (data_in)
din = buffer + rx_offset;
dout = buffer;
- tran_len = min(data_len , max_tran_len);
+ tran_len = min(data_len, (size_t)max_tran_len);
num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4);
num_bytes = (tran_len + cmd_len) % 4;
fsl->data_len = tran_len + cmd_len;
tmp = reg_read(®s->rxdata);
data = cpu_to_be32(tmp);
debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
- cnt = min(nbytes, sizeof(data));
+ cnt = min_t(u32, nbytes, sizeof(data));
if (din) {
memcpy(din, &data, cnt);
din += cnt;
speed = slave->max_hz;
if (spi->max_hz) {
if (speed)
- speed = min(speed, spi->max_hz);
+ speed = min(speed, (int)spi->max_hz);
else
speed = spi->max_hz;
}
* changes to zero exactly after the last byte is fed into the
* FIFO.
*/
- count = min(burst, len - offset - 1);
+ count = min((u32)burst, len - offset - 1);
while (count--)
tpm_write_byte(data[offset++],
&lpc_tpm_dev[locality].data);
if (!gadget_is_dualspeed(gadget))
break;
device_qual(cdev);
- value = min(w_length,
- sizeof(struct usb_qualifier_descriptor));
+ value = min_t(int, w_length,
+ sizeof(struct usb_qualifier_descriptor));
break;
case USB_DT_OTHER_SPEED_CONFIG:
if (!gadget_is_dualspeed(gadget))
UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d",
urb->buffer, urb->buffer_length, urb->actual_length);
- last = min(urb->actual_length - endpoint->sent,
- endpoint->tx_packetSize);
+ last = min_t(u32, urb->actual_length - endpoint->sent,
+ endpoint->tx_packetSize);
if (last) {
u8 *cp = urb->buffer + endpoint->sent;
if (!urb || !urb->actual_length)
return -1;
- n = min(urb->actual_length - endpoint->sent, endpoint->tx_packetSize);
+ n = min_t(unsigned int, urb->actual_length - endpoint->sent,
+ endpoint->tx_packetSize);
if (n <= 0)
return -1;
u32 ep_num = ep_index(ep);
buf = req->req.buf + req->req.actual;
- length = min(req->req.length - req->req.actual,
- ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket);
+ length = min_t(u32, req->req.length - req->req.actual,
+ ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket);
ep->len = length;
ep->dma_buf = buf;
case 0:
switch (wValue & 0xff00) {
case 0x0100: /* device descriptor */
- len = min3(txlen, sizeof(root_hub_dev_des), wLength);
+ len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
memcpy(buffer, root_hub_dev_des, len);
break;
case 0x0200: /* configuration descriptor */
- len = min3(txlen, sizeof(root_hub_config_des), wLength);
+ len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
memcpy(buffer, root_hub_config_des, len);
break;
case 0x0300: /* string descriptors */
switch (wValue & 0xff) {
case 0x00:
- len = min3(txlen, sizeof(root_hub_str_index0),
- wLength);
+ len = min3(txlen, (int)sizeof(root_hub_str_index0),
+ (int)wLength);
memcpy(buffer, root_hub_str_index0, len);
break;
case 0x01:
- len = min3(txlen, sizeof(root_hub_str_index1),
- wLength);
+ len = min3(txlen, (int)sizeof(root_hub_str_index1),
+ (int)wLength);
memcpy(buffer, root_hub_str_index1, len);
break;
}
data[10] = data[9];
}
- len = min3(txlen, data[0], wLength);
+ len = min3(txlen, (int)data[0], (int)wLength);
memcpy(buffer, data, len);
break;
default:
}
mdelay(1);
- len = min3(srclen, le16_to_cpu(req->length), length);
+ len = min3(srclen, (int)le16_to_cpu(req->length), length);
if (srcptr != NULL && len > 0)
memcpy(buffer, srcptr, len);
else
/* ------------------------------------------------------------------------- */
-#define ALIGN(x,a) (((x)+(a)-1UL)&~((a)-1UL))
-#define min_t(type,x,y) \
- ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
-
-/* ------------------------------------------------------------------------- */
-
static int isp116x_reset(struct isp116x *isp116x);
/* --- Debugging functions ------------------------------------------------- */
#include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */
#endif
-#if defined(CONFIG_ARM920T) || \
+#if defined(CONFIG_CPU_ARM920T) || \
defined(CONFIG_S3C24X0) || \
defined(CONFIG_440EP) || \
defined(CONFIG_PCI_OHCI) || \
#define OHCI_CONTROL_INIT \
(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-#define min_t(type, x, y) \
- ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
-
#ifdef CONFIG_PCI_OHCI
static struct pci_device_id ohci_pci_ids[] = {
{0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
#define OHCI_CONTROL_INIT \
(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-#define min_t(type, x, y) \
- ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
-
#undef DEBUG
#ifdef DEBUG
#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
return -1; /* fail */
}
-/* based on usb_ohci.c */
-#define min_t(type, x, y) \
- ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
/*-------------------------------------------------------------------------*
* Virtual Root Hub
*-------------------------------------------------------------------------*/
union xhci_trb *event, int length)
{
udev->act_len = min(length, length -
- EVENT_TRB_LEN(le32_to_cpu(event->trans_event.transfer_len)));
+ (int)EVENT_TRB_LEN(le32_to_cpu(event->trans_event.transfer_len)));
switch (GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len))) {
case COMP_SUCCESS:
debug("scrlen = %d\n req->length = %d\n",
srclen, le16_to_cpu(req->length));
- len = min(srclen, le16_to_cpu(req->length));
+ len = min(srclen, (int)le16_to_cpu(req->length));
if (srcptr != NULL && len > 0)
memcpy(buffer, srcptr, len);
((readb(&musbr->power) & MUSB_POWER_HSMODE) \
>> MUSB_POWER_HSMODE_SHIFT)
-#define min_t(type, x, y) \
- ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
-
/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
/* destination of request */
#define DPRINT(x...) do{}while(0)
#endif
-#ifndef min_t
-#define min_t(type,x,y) \
- ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
-#endif
-
#define MAX_MAPPED_VRAM (2048*2048*4)
#define MIN_MAPPED_VRAM (1024*768*1)
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
if (x == BMP_ALIGN_CENTER)
- x = max(0, (VIDEO_VISIBLE_COLS - width) / 2);
+ x = max(0, (int)(VIDEO_VISIBLE_COLS - width) / 2);
else if (x < 0)
- x = max(0, VIDEO_VISIBLE_COLS - width + x + 1);
+ x = max(0, (int)(VIDEO_VISIBLE_COLS - width + x + 1));
if (y == BMP_ALIGN_CENTER)
- y = max(0, (VIDEO_VISIBLE_ROWS - height) / 2);
+ y = max(0, (int)(VIDEO_VISIBLE_ROWS - height) / 2);
else if (y < 0)
- y = max(0, VIDEO_VISIBLE_ROWS - height + y + 1);
+ y = max(0, (int)(VIDEO_VISIBLE_ROWS - height + y + 1));
#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
/*
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
if (x == BMP_ALIGN_CENTER)
- x = max(0, (VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH) / 2);
+ x = max(0, (int)(VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH) / 2);
else if (x < 0)
- x = max(0, VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH + x + 1);
+ x = max(0, (int)(VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH + x + 1));
if (y == BMP_ALIGN_CENTER)
- y = max(0, (VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT) / 2);
+ y = max(0, (int)(VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT) / 2);
else if (y < 0)
- y = max(0, VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT + y + 1);
+ y = max(0, (int)(VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT + y + 1));
#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
dest = (unsigned char *)screen + (y * width + x) * VIDEO_PIXEL_SIZE;
* we need to adjust the logo height
*/
if (video_logo_ypos == BMP_ALIGN_CENTER)
- video_logo_height += max(0, (VIDEO_VISIBLE_ROWS - \
+ video_logo_height += max(0, (int)(VIDEO_VISIBLE_ROWS -
VIDEO_LOGO_HEIGHT) / 2);
else if (video_logo_ypos > 0)
video_logo_height += video_logo_ypos;
debug(" <" LBAFU ", %d, %d>\n", sector, byte_offset, byte_len);
if (byte_offset != 0) {
+ int readlen;
/* read first part which isn't aligned with start of sector */
if (ext4fs_block_dev_desc->
block_read(ext4fs_block_dev_desc->dev,
printf(" ** ext2fs_devread() read error **\n");
return 0;
}
- memcpy(buf, sec_buf + byte_offset,
- min(ext4fs_block_dev_desc->blksz
- - byte_offset, byte_len));
- buf += min(ext4fs_block_dev_desc->blksz
- - byte_offset, byte_len);
- byte_len -= min(ext4fs_block_dev_desc->blksz
- - byte_offset, byte_len);
+ readlen = min((int)ext4fs_block_dev_desc->blksz - byte_offset,
+ byte_len);
+ memcpy(buf, sec_buf + byte_offset, readlen);
+ buf += readlen;
+ byte_len -= readlen;
sector++;
}
{
unsigned int fpos = 0;
int status;
+ loff_t actread;
struct ext2fs_node *diro = (struct ext2fs_node *) dir;
#ifdef DEBUG
status = ext4fs_read_file(diro, fpos,
sizeof(struct ext2_dirent),
- (char *) &dirent);
- if (status < 1)
+ (char *)&dirent, &actread);
+ if (status < 0)
return 0;
if (dirent.namelen != 0) {
status = ext4fs_read_file(diro,
fpos +
sizeof(struct ext2_dirent),
- dirent.namelen, filename);
- if (status < 1)
+ dirent.namelen, filename,
+ &actread);
+ if (status < 0)
return 0;
fdiro = zalloc(sizeof(struct ext2fs_node));
printf("< ? > ");
break;
}
- printf("%10d %s\n",
- __le32_to_cpu(fdiro->inode.size),
+ printf("%10u %s\n",
+ __le32_to_cpu(fdiro->inode.size),
filename);
}
free(fdiro);
char *symlink;
struct ext2fs_node *diro = node;
int status;
+ loff_t actread;
if (!diro->inode_read) {
status = ext4fs_read_inode(diro->data, diro->ino, &diro->inode);
} else {
status = ext4fs_read_file(diro, 0,
__le32_to_cpu(diro->inode.size),
- symlink);
+ symlink, &actread);
if (status == 0) {
free(symlink);
return 0;
return 1;
}
-int ext4fs_open(const char *filename)
+int ext4fs_open(const char *filename, loff_t *len)
{
struct ext2fs_node *fdiro = NULL;
int status;
- int len;
if (ext4fs_root == NULL)
return -1;
if (status == 0)
goto fail;
}
- len = __le32_to_cpu(fdiro->inode.size);
+ *len = __le32_to_cpu(fdiro->inode.size);
ext4fs_file = fdiro;
- return len;
+ return 0;
fail:
ext4fs_free_node(fdiro, &ext4fs_root->diropen);
int ext4fs_read_inode(struct ext2_data *data, int ino,
struct ext2_inode *inode);
-int ext4fs_read_file(struct ext2fs_node *node, int pos,
- unsigned int len, char *buf);
+int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, loff_t len,
+ char *buf, loff_t *actread);
int ext4fs_find_file(const char *path, struct ext2fs_node *rootnode,
struct ext2fs_node **foundnode, int expecttype);
int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name,
return -1;
}
+
+int ext4_write_file(const char *filename, void *buf, loff_t offset,
+ loff_t len, loff_t *actwrite)
+{
+ int ret;
+
+ if (offset != 0) {
+ printf("** Cannot support non-zero offset **\n");
+ return -1;
+ }
+
+ /* mount the filesystem */
+ if (!ext4fs_mount(0)) {
+ printf("** Error Bad ext4 partition **\n");
+ goto fail;
+ }
+
+ ret = ext4fs_write(filename, buf, len);
+
+ if (ret) {
+ printf("** Error ext4fs_write() **\n");
+ goto fail;
+ }
+ ext4fs_close();
+
+ return 0;
+
+fail:
+ ext4fs_close();
+
+ return -1;
+}
* Optimized read file API : collects and defers contiguous sector
* reads into one potentially more efficient larger sequential read action
*/
-int ext4fs_read_file(struct ext2fs_node *node, int pos,
- unsigned int len, char *buf)
+int ext4fs_read_file(struct ext2fs_node *node, loff_t pos,
+ loff_t len, char *buf, loff_t *actread)
{
struct ext_filesystem *fs = get_fs();
int i;
previous_block_number = -1;
}
- return len;
+ *actread = len;
+ return 0;
}
int ext4fs_ls(const char *dirname)
int ext4fs_exists(const char *filename)
{
- int file_len;
+ loff_t file_len;
+ int ret;
- file_len = ext4fs_open(filename);
- return file_len >= 0;
+ ret = ext4fs_open(filename, &file_len);
+ return ret == 0;
}
-int ext4fs_size(const char *filename)
+int ext4fs_size(const char *filename, loff_t *size)
{
- return ext4fs_open(filename);
+ return ext4fs_open(filename, size);
}
-int ext4fs_read(char *buf, unsigned len)
+int ext4fs_read(char *buf, loff_t len, loff_t *actread)
{
if (ext4fs_root == NULL || ext4fs_file == NULL)
return 0;
- return ext4fs_read_file(ext4fs_file, 0, len, buf);
+ return ext4fs_read_file(ext4fs_file, 0, len, buf, actread);
}
int ext4fs_probe(block_dev_desc_t *fs_dev_desc,
return 0;
}
-int ext4_read_file(const char *filename, void *buf, int offset, int len)
+int ext4_read_file(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *len_read)
{
- int file_len;
- int len_read;
+ loff_t file_len;
+ int ret;
if (offset != 0) {
printf("** Cannot support non-zero offset **\n");
return -1;
}
- file_len = ext4fs_open(filename);
- if (file_len < 0) {
+ ret = ext4fs_open(filename, &file_len);
+ if (ret < 0) {
printf("** File not found %s **\n", filename);
return -1;
}
if (len == 0)
len = file_len;
- len_read = ext4fs_read(buf, len);
+ return ext4fs_read(buf, len, len_read);
+}
- return len_read;
+int ext4fs_uuid(char *uuid_str)
+{
+ if (ext4fs_root == NULL)
+ return -1;
+
+#ifdef CONFIG_LIB_UUID
+ uuid_bin_to_str((unsigned char *)ext4fs_root->sblock.unique_id,
+ uuid_str, UUID_STR_FORMAT_STD);
+
+ return 0;
+#else
+ return -ENOSYS;
+#endif
}
/*
* Read at most 'maxsize' bytes from 'pos' in the file associated with 'dentptr'
* into 'buffer'.
- * Return the number of bytes read or -1 on fatal errors.
+ * Update the number of bytes read in *gotsize or return -1 on fatal errors.
*/
__u8 get_contents_vfatname_block[MAX_CLUSTSIZE]
__aligned(ARCH_DMA_MINALIGN);
-static long
-get_contents(fsdata *mydata, dir_entry *dentptr, unsigned long pos,
- __u8 *buffer, unsigned long maxsize)
+static int get_contents(fsdata *mydata, dir_entry *dentptr, loff_t pos,
+ __u8 *buffer, loff_t maxsize, loff_t *gotsize)
{
- unsigned long filesize = FAT2CPU32(dentptr->size), gotsize = 0;
+ loff_t filesize = FAT2CPU32(dentptr->size);
unsigned int bytesperclust = mydata->clust_size * mydata->sect_size;
__u32 curclust = START(dentptr);
__u32 endclust, newclust;
- unsigned long actsize;
+ loff_t actsize;
- debug("Filesize: %ld bytes\n", filesize);
+ *gotsize = 0;
+ debug("Filesize: %llu bytes\n", filesize);
if (pos >= filesize) {
- debug("Read position past EOF: %lu\n", pos);
- return gotsize;
+ debug("Read position past EOF: %llu\n", pos);
+ return 0;
}
if (maxsize > 0 && filesize > pos + maxsize)
filesize = pos + maxsize;
- debug("%ld bytes\n", filesize);
+ debug("%llu bytes\n", filesize);
actsize = bytesperclust;
if (CHECK_CLUST(curclust, mydata->fatsize)) {
debug("curclust: 0x%x\n", curclust);
debug("Invalid FAT entry\n");
- return gotsize;
+ return 0;
}
actsize += bytesperclust;
}
/* align to beginning of next cluster if any */
if (pos) {
- actsize = min(filesize, bytesperclust);
+ actsize = min(filesize, (loff_t)bytesperclust);
if (get_cluster(mydata, curclust, get_contents_vfatname_block,
(int)actsize) != 0) {
printf("Error reading cluster\n");
filesize -= actsize;
actsize -= pos;
memcpy(buffer, get_contents_vfatname_block + pos, actsize);
- gotsize += actsize;
+ *gotsize += actsize;
if (!filesize)
- return gotsize;
+ return 0;
buffer += actsize;
curclust = get_fatent(mydata, curclust);
if (CHECK_CLUST(curclust, mydata->fatsize)) {
debug("curclust: 0x%x\n", curclust);
debug("Invalid FAT entry\n");
- return gotsize;
+ return 0;
}
}
if (CHECK_CLUST(newclust, mydata->fatsize)) {
debug("curclust: 0x%x\n", newclust);
debug("Invalid FAT entry\n");
- return gotsize;
+ return 0;
}
endclust = newclust;
actsize += bytesperclust;
printf("Error reading cluster\n");
return -1;
}
- gotsize += actsize;
- return gotsize;
+ *gotsize += actsize;
+ return 0;
getit:
if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) {
printf("Error reading cluster\n");
return -1;
}
- gotsize += (int)actsize;
+ *gotsize += (int)actsize;
filesize -= actsize;
buffer += actsize;
if (CHECK_CLUST(curclust, mydata->fatsize)) {
debug("curclust: 0x%x\n", curclust);
printf("Invalid FAT entry\n");
- return gotsize;
+ return 0;
}
actsize = bytesperclust;
endclust = curclust;
}
if (doit) {
if (dirc == ' ') {
- printf(" %8ld %s%c\n",
- (long)FAT2CPU32(dentptr->size),
+ printf(" %8u %s%c\n",
+ FAT2CPU32(dentptr->size),
l_name,
dirc);
} else {
if (doit) {
if (dirc == ' ') {
- printf(" %8ld %s%c\n",
- (long)FAT2CPU32(dentptr->size),
+ printf(" %8u %s%c\n",
+ FAT2CPU32(dentptr->size),
s_name, dirc);
} else {
printf(" %s%c\n",
__u8 do_fat_read_at_block[MAX_CLUSTSIZE]
__aligned(ARCH_DMA_MINALIGN);
-long
-do_fat_read_at(const char *filename, unsigned long pos, void *buffer,
- unsigned long maxsize, int dols, int dogetsize)
+int do_fat_read_at(const char *filename, loff_t pos, void *buffer,
+ loff_t maxsize, int dols, int dogetsize, loff_t *size)
{
char fnamecopy[2048];
boot_sector bs;
__u32 cursect;
int idx, isdir = 0;
int files = 0, dirs = 0;
- long ret = -1;
+ int ret = -1;
int firsttime;
__u32 root_cluster = 0;
int rootdir_size = 0;
}
if (doit) {
if (dirc == ' ') {
- printf(" %8ld %s%c\n",
- (long)FAT2CPU32(dentptr->size),
+ printf(" %8u %s%c\n",
+ FAT2CPU32(dentptr->size),
l_name,
dirc);
} else {
}
if (doit) {
if (dirc == ' ') {
- printf(" %8ld %s%c\n",
- (long)FAT2CPU32(dentptr->size),
+ printf(" %8u %s%c\n",
+ FAT2CPU32(dentptr->size),
s_name, dirc);
} else {
printf(" %s%c\n",
if (dols == LS_ROOT) {
printf("\n%d file(s), %d dir(s)\n\n",
files, dirs);
- ret = 0;
+ *size = 0;
}
goto exit;
}
if (get_dentfromdir(mydata, startsect, subname, dentptr,
isdir ? 0 : dols) == NULL) {
if (dols && !isdir)
- ret = 0;
+ *size = 0;
goto exit;
}
subname = nextname;
}
- if (dogetsize)
- ret = FAT2CPU32(dentptr->size);
- else
- ret = get_contents(mydata, dentptr, pos, buffer, maxsize);
- debug("Size: %d, got: %ld\n", FAT2CPU32(dentptr->size), ret);
+ if (dogetsize) {
+ *size = FAT2CPU32(dentptr->size);
+ ret = 0;
+ } else {
+ ret = get_contents(mydata, dentptr, pos, buffer, maxsize, size);
+ }
+ debug("Size: %u, got: %llu\n", FAT2CPU32(dentptr->size), *size);
exit:
free(mydata->fatbuf);
return ret;
}
-long
-do_fat_read(const char *filename, void *buffer, unsigned long maxsize, int dols)
+int do_fat_read(const char *filename, void *buffer, loff_t maxsize, int dols,
+ loff_t *actread)
{
- return do_fat_read_at(filename, 0, buffer, maxsize, dols, 0);
+ return do_fat_read_at(filename, 0, buffer, maxsize, dols, 0, actread);
}
int file_fat_detectfs(void)
int file_fat_ls(const char *dir)
{
- return do_fat_read(dir, NULL, 0, LS_YES);
+ loff_t size;
+
+ return do_fat_read(dir, NULL, 0, LS_YES, &size);
}
int fat_exists(const char *filename)
{
- int sz;
- sz = do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1);
- return sz >= 0;
+ int ret;
+ loff_t size;
+
+ ret = do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1, &size);
+ return ret == 0;
}
-int fat_size(const char *filename)
+int fat_size(const char *filename, loff_t *size)
{
- return do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1);
+ return do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1, size);
}
-long file_fat_read_at(const char *filename, unsigned long pos, void *buffer,
- unsigned long maxsize)
+int file_fat_read_at(const char *filename, loff_t pos, void *buffer,
+ loff_t maxsize, loff_t *actread)
{
printf("reading %s\n", filename);
- return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO, 0);
+ return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO, 0,
+ actread);
}
-long file_fat_read(const char *filename, void *buffer, unsigned long maxsize)
+int file_fat_read(const char *filename, void *buffer, int maxsize)
{
- return file_fat_read_at(filename, 0, buffer, maxsize);
+ loff_t actread;
+ int ret;
+
+ ret = file_fat_read_at(filename, 0, buffer, maxsize, &actread);
+ if (ret)
+ return ret;
+ else
+ return actread;
}
-int fat_read_file(const char *filename, void *buf, int offset, int len)
+int fat_read_file(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *actread)
{
- int len_read;
+ int ret;
- len_read = file_fat_read_at(filename, offset, buf, len);
- if (len_read == -1) {
+ ret = file_fat_read_at(filename, offset, buf, len, actread);
+ if (ret)
printf("** Unable to read file %s **\n", filename);
- return -1;
- }
- return len_read;
+ return ret;
}
void fat_close(void)
/*
* Write at most 'maxsize' bytes from 'buffer' into
* the file associated with 'dentptr'
- * Return the number of bytes read or -1 on fatal errors.
+ * Update the number of bytes written in *gotsize and return 0
+ * or return -1 on fatal errors.
*/
static int
set_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer,
- unsigned long maxsize)
+ loff_t maxsize, loff_t *gotsize)
{
- unsigned long filesize = FAT2CPU32(dentptr->size), gotsize = 0;
+ loff_t filesize = FAT2CPU32(dentptr->size);
unsigned int bytesperclust = mydata->clust_size * mydata->sect_size;
__u32 curclust = START(dentptr);
__u32 endclust = 0, newclust = 0;
- unsigned long actsize;
+ loff_t actsize;
- debug("Filesize: %ld bytes\n", filesize);
+ *gotsize = 0;
+ debug("Filesize: %llu bytes\n", filesize);
if (maxsize > 0 && filesize > maxsize)
filesize = maxsize;
- debug("%ld bytes\n", filesize);
+ debug("%llu bytes\n", filesize);
actsize = bytesperclust;
endclust = curclust;
if (CHECK_CLUST(newclust, mydata->fatsize)) {
debug("curclust: 0x%x\n", newclust);
debug("Invalid FAT entry\n");
- return gotsize;
+ return 0;
}
endclust = newclust;
actsize += bytesperclust;
}
/* set remaining bytes */
- gotsize += (int)actsize;
+ *gotsize += actsize;
filesize -= actsize;
buffer += actsize;
actsize = filesize;
debug("error: writing cluster\n");
return -1;
}
- gotsize += actsize;
+ *gotsize += actsize;
/* Mark end of file in FAT */
if (mydata->fatsize == 16)
newclust = 0xfffffff;
set_fatent_value(mydata, endclust, newclust);
- return gotsize;
+ return 0;
getit:
if (set_cluster(mydata, curclust, buffer, (int)actsize) != 0) {
debug("error: writing cluster\n");
return -1;
}
- gotsize += (int)actsize;
+ *gotsize += actsize;
filesize -= actsize;
buffer += actsize;
if (CHECK_CLUST(curclust, mydata->fatsize)) {
debug("curclust: 0x%x\n", curclust);
debug("Invalid FAT entry\n");
- return gotsize;
+ return 0;
}
actsize = bytesperclust;
curclust = endclust = newclust;
* exceed the size of the block device
* Return -1 when overflow occurs, otherwise return 0
*/
-static int check_overflow(fsdata *mydata, __u32 clustnum, unsigned long size)
+static int check_overflow(fsdata *mydata, __u32 clustnum, loff_t size)
{
__u32 startsect, sect_num;
return NULL;
}
-static int do_fat_write(const char *filename, void *buffer,
- unsigned long size)
+static int do_fat_write(const char *filename, void *buffer, loff_t size,
+ loff_t *actwrite)
{
dir_entry *dentptr, *retdent;
__u32 startsect;
int cursect;
int ret = -1, name_len;
char l_filename[VFAT_MAXLEN_BYTES];
- int write_size = size;
+ *actwrite = size;
dir_curclust = 0;
if (read_bootsectandvi(&bs, &volinfo, &mydata->fatsize)) {
ret = check_overflow(mydata, start_cluster, size);
if (ret) {
- printf("Error: %ld overflow\n", size);
+ printf("Error: %llu overflow\n", size);
goto exit;
}
goto exit;
}
- ret = set_contents(mydata, retdent, buffer, size);
+ ret = set_contents(mydata, retdent, buffer, size, actwrite);
if (ret < 0) {
printf("Error: writing contents\n");
goto exit;
}
- write_size = ret;
- debug("attempt to write 0x%x bytes\n", write_size);
+ debug("attempt to write 0x%llx bytes\n", *actwrite);
/* Flush fat buffer */
ret = flush_fat_buffer(mydata);
ret = check_overflow(mydata, start_cluster, size);
if (ret) {
- printf("Error: %ld overflow\n", size);
+ printf("Error: %llu overflow\n", size);
goto exit;
}
fill_dentry(mydata, empty_dentptr, filename,
start_cluster, size, 0x20);
- ret = set_contents(mydata, empty_dentptr, buffer, size);
+ ret = set_contents(mydata, empty_dentptr, buffer, size,
+ actwrite);
if (ret < 0) {
printf("Error: writing contents\n");
goto exit;
}
- write_size = ret;
- debug("attempt to write 0x%x bytes\n", write_size);
+ debug("attempt to write 0x%llx bytes\n", *actwrite);
/* Flush fat buffer */
ret = flush_fat_buffer(mydata);
exit:
free(mydata->fatbuf);
- return ret < 0 ? ret : write_size;
+ return ret;
}
-int file_fat_write(const char *filename, void *buffer, unsigned long maxsize)
+int file_fat_write(const char *filename, void *buffer, loff_t offset,
+ loff_t maxsize, loff_t *actwrite)
{
+ if (offset != 0) {
+ printf("Error: non zero offset is currently not suported.\n");
+ return -1;
+ }
+
printf("writing %s\n", filename);
- return do_fat_write(filename, buffer, maxsize);
+ return do_fat_write(filename, buffer, maxsize, actwrite);
}
return filesystems[current_filesystem].ls(arg);
}
-long
-file_read(const char *filename, void *buffer, unsigned long maxsize)
+int file_read(const char *filename, void *buffer, int maxsize)
{
char fullpath[1024];
const char *arg;
*/
#include <config.h>
+#include <errno.h>
#include <common.h>
#include <part.h>
#include <ext4fs.h>
return 0;
}
-static inline int fs_size_unsupported(const char *filename)
+static inline int fs_size_unsupported(const char *filename, loff_t *size)
{
return -1;
}
static inline int fs_read_unsupported(const char *filename, void *buf,
- int offset, int len)
+ loff_t offset, loff_t len,
+ loff_t *actread)
{
return -1;
}
static inline int fs_write_unsupported(const char *filename, void *buf,
- int offset, int len)
+ loff_t offset, loff_t len,
+ loff_t *actwrite)
{
return -1;
}
{
}
+static inline int fs_uuid_unsupported(char *uuid_str)
+{
+ return -1;
+}
+
struct fstype_info {
int fstype;
/*
disk_partition_t *fs_partition);
int (*ls)(const char *dirname);
int (*exists)(const char *filename);
- int (*size)(const char *filename);
- int (*read)(const char *filename, void *buf, int offset, int len);
- int (*write)(const char *filename, void *buf, int offset, int len);
+ int (*size)(const char *filename, loff_t *size);
+ int (*read)(const char *filename, void *buf, loff_t offset,
+ loff_t len, loff_t *actread);
+ int (*write)(const char *filename, void *buf, loff_t offset,
+ loff_t len, loff_t *actwrite);
void (*close)(void);
+ int (*uuid)(char *uuid_str);
};
static struct fstype_info fstypes[] = {
.exists = fat_exists,
.size = fat_size,
.read = fat_read_file,
+#ifdef CONFIG_FAT_WRITE
+ .write = file_fat_write,
+#else
.write = fs_write_unsupported,
+#endif
+ .uuid = fs_uuid_unsupported,
},
#endif
#ifdef CONFIG_FS_EXT4
.exists = ext4fs_exists,
.size = ext4fs_size,
.read = ext4_read_file,
+#ifdef CONFIG_CMD_EXT4_WRITE
+ .write = ext4_write_file,
+#else
.write = fs_write_unsupported,
+#endif
+ .uuid = ext4fs_uuid,
},
#endif
#ifdef CONFIG_SANDBOX
.size = sandbox_fs_size,
.read = fs_read_sandbox,
.write = fs_write_sandbox,
+ .uuid = fs_uuid_unsupported,
},
#endif
{
.size = fs_size_unsupported,
.read = fs_read_unsupported,
.write = fs_write_unsupported,
+ .uuid = fs_uuid_unsupported,
},
};
fs_type = FS_TYPE_ANY;
}
+int fs_uuid(char *uuid_str)
+{
+ struct fstype_info *info = fs_get_info(fs_type);
+
+ return info->uuid(uuid_str);
+}
+
int fs_ls(const char *dirname)
{
int ret;
return ret;
}
-int fs_size(const char *filename)
+int fs_size(const char *filename, loff_t *size)
{
int ret;
struct fstype_info *info = fs_get_info(fs_type);
- ret = info->size(filename);
+ ret = info->size(filename, size);
fs_close();
return ret;
}
-int fs_read(const char *filename, ulong addr, int offset, int len)
+int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len,
+ loff_t *actread)
{
struct fstype_info *info = fs_get_info(fs_type);
void *buf;
* means read the whole file.
*/
buf = map_sysmem(addr, len);
- ret = info->read(filename, buf, offset, len);
+ ret = info->read(filename, buf, offset, len, actread);
unmap_sysmem(buf);
/* If we requested a specific number of bytes, check we got it */
- if (ret >= 0 && len && ret != len) {
+ if (ret == 0 && len && *actread != len) {
printf("** Unable to read file %s **\n", filename);
ret = -1;
}
return ret;
}
-int fs_write(const char *filename, ulong addr, int offset, int len)
+int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len,
+ loff_t *actwrite)
{
struct fstype_info *info = fs_get_info(fs_type);
void *buf;
int ret;
buf = map_sysmem(addr, len);
- ret = info->write(filename, buf, offset, len);
+ ret = info->write(filename, buf, offset, len, actwrite);
unmap_sysmem(buf);
- if (ret >= 0 && ret != len) {
+ if (ret < 0 && len != *actwrite) {
printf("** Unable to write file %s **\n", filename);
ret = -1;
}
int do_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
int fstype)
{
- int size;
+ loff_t size;
if (argc != 4)
return CMD_RET_USAGE;
if (fs_set_blk_dev(argv[1], argv[2], fstype))
return 1;
- size = fs_size(argv[3]);
- if (size < 0)
+ if (fs_size(argv[3], &size) < 0)
return CMD_RET_FAILURE;
setenv_hex("filesize", size);
unsigned long addr;
const char *addr_str;
const char *filename;
- unsigned long bytes;
- unsigned long pos;
- int len_read;
+ loff_t bytes;
+ loff_t pos;
+ loff_t len_read;
+ int ret;
unsigned long time;
char *ep;
pos = 0;
time = get_timer(0);
- len_read = fs_read(filename, addr, pos, bytes);
+ ret = fs_read(filename, addr, pos, bytes, &len_read);
time = get_timer(time);
- if (len_read <= 0)
+ if (ret < 0)
return 1;
- printf("%d bytes read in %lu ms", len_read, time);
+ printf("%llu bytes read in %lu ms", len_read, time);
if (time > 0) {
puts(" (");
print_size(len_read / time * 1000, "/s");
{
unsigned long addr;
const char *filename;
- unsigned long bytes;
- unsigned long pos;
- int len;
+ loff_t bytes;
+ loff_t pos;
+ loff_t len;
+ int ret;
unsigned long time;
if (argc < 6 || argc > 7)
if (fs_set_blk_dev(argv[1], argv[2], fstype))
return 1;
- filename = argv[3];
- addr = simple_strtoul(argv[4], NULL, 16);
+ addr = simple_strtoul(argv[3], NULL, 16);
+ filename = argv[4];
bytes = simple_strtoul(argv[5], NULL, 16);
if (argc >= 7)
pos = simple_strtoul(argv[6], NULL, 16);
pos = 0;
time = get_timer(0);
- len = fs_write(filename, addr, pos, bytes);
+ ret = fs_write(filename, addr, pos, bytes, &len);
time = get_timer(time);
- if (len <= 0)
+ if (ret < 0)
return 1;
- printf("%d bytes written in %lu ms", len, time);
+ printf("%llu bytes written in %lu ms", len, time);
if (time > 0) {
puts(" (");
print_size(len / time * 1000, "/s");
return 0;
}
+
+int do_fs_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+ int fstype)
+{
+ int ret;
+ char uuid[37];
+ memset(uuid, 0, sizeof(uuid));
+
+ if (argc < 3 || argc > 4)
+ return CMD_RET_USAGE;
+
+ if (fs_set_blk_dev(argv[1], argv[2], fstype))
+ return 1;
+
+ ret = fs_uuid(uuid);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ if (argc == 4)
+ setenv(argv[3], uuid);
+ else
+ printf("%s\n", uuid);
+
+ return CMD_RET_SUCCESS;
+}
return 0;
}
-long sandbox_fs_read_at(const char *filename, unsigned long pos,
- void *buffer, unsigned long maxsize)
+int sandbox_fs_read_at(const char *filename, loff_t pos, void *buffer,
+ loff_t maxsize, loff_t *actread)
{
- ssize_t size;
+ loff_t size;
int fd, ret;
fd = os_open(filename, OS_O_RDONLY);
os_close(fd);
return ret;
}
- if (!maxsize)
- maxsize = os_get_filesize(filename);
+ if (!maxsize) {
+ ret = os_get_filesize(filename, &size);
+ if (ret) {
+ os_close(fd);
+ return ret;
+ }
+
+ maxsize = size;
+ }
+
size = os_read(fd, buffer, maxsize);
os_close(fd);
- return size;
+ if (size < 0) {
+ ret = -1;
+ } else {
+ ret = 0;
+ *actread = size;
+ }
+
+ return ret;
}
-long sandbox_fs_write_at(const char *filename, unsigned long pos,
- void *buffer, unsigned long towrite)
+int sandbox_fs_write_at(const char *filename, loff_t pos, void *buffer,
+ loff_t towrite, loff_t *actwrite)
{
ssize_t size;
int fd, ret;
size = os_write(fd, buffer, towrite);
os_close(fd);
- return size;
+ if (size == -1) {
+ ret = -1;
+ } else {
+ ret = 0;
+ *actwrite = size;
+ }
+
+ return ret;
}
int sandbox_fs_ls(const char *dirname)
int sandbox_fs_exists(const char *filename)
{
- ssize_t sz;
+ loff_t size;
+ int ret;
- sz = os_get_filesize(filename);
- return sz >= 0;
+ ret = os_get_filesize(filename, &size);
+ return ret == 0;
}
-int sandbox_fs_size(const char *filename)
+int sandbox_fs_size(const char *filename, loff_t *size)
{
- return os_get_filesize(filename);
+ return os_get_filesize(filename, size);
}
void sandbox_fs_close(void)
{
}
-int fs_read_sandbox(const char *filename, void *buf, int offset, int len)
+int fs_read_sandbox(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *actread)
{
- int len_read;
+ int ret;
- len_read = sandbox_fs_read_at(filename, offset, buf, len);
- if (len_read == -1) {
+ ret = sandbox_fs_read_at(filename, offset, buf, len, actread);
+ if (ret)
printf("** Unable to read file %s **\n", filename);
- return -1;
- }
- return len_read;
+ return ret;
}
-int fs_write_sandbox(const char *filename, void *buf, int offset, int len)
+int fs_write_sandbox(const char *filename, void *buf, loff_t offset,
+ loff_t len, loff_t *actwrite)
{
- int len_written;
+ int ret;
- len_written = sandbox_fs_write_at(filename, offset, buf, len);
- if (len_written == -1) {
+ ret = sandbox_fs_write_at(filename, offset, buf, len, actwrite);
+ if (ret)
printf("** Unable to write file %s **\n", filename);
- return -1;
- }
- return len_written;
+ return ret;
}
#define MAX_LFS_FILESIZE 0x7fffffffffffffffUL
#endif
-#define INT_MAX ((int)(~0U>>1))
-#define INT_MIN (-INT_MAX - 1)
-#define LLONG_MAX ((long long)(~0ULL>>1))
-
/*
* These are the fs-independent mount-flags: up to 32 flags are supported
*/
unsigned long malloc_limit; /* limit address */
unsigned long malloc_ptr; /* current address */
#endif
+ struct udevice *cur_serial_dev; /* current serial device */
struct arch_global_data arch; /* architecture-specific data */
} gd_t;
#endif
int gpio_lookup_name(const char *name, struct udevice **devp,
unsigned int *offsetp, unsigned int *gpiop);
-int name_to_gpio(const char *name);
+/**
+ * get_gpios() - Turn the values of a list of GPIOs into an integer
+ *
+ * This puts the value of the first GPIO into bit 0, the second into bit 1,
+ * etc. then returns the resulting integer.
+ *
+ * @gpio_list: List of GPIOs to collect
+ * @return resulting integer value
+ */
+unsigned gpio_get_values_as_int(const int *gpio_list);
#endif /* _ASM_GENERIC_GPIO_H_ */
#include <linux/stringify.h>
#include <asm/ptrace.h>
#include <stdarg.h>
+#include <linux/kernel.h>
#if defined(CONFIG_PCI) && defined(CONFIG_4xx)
#include <pci.h>
#endif
#define _DEBUG 0
#endif
+#ifndef pr_fmt
+#define pr_fmt(fmt) fmt
+#endif
+
/*
* Output a debug text when condition "cond" is met. The "cond" should be
* computed by a preprocessor in the best case, allowing for the best
* optimization.
*/
-#define debug_cond(cond, fmt, args...) \
- do { \
- if (cond) \
- printf(fmt, ##args); \
+#define debug_cond(cond, fmt, args...) \
+ do { \
+ if (cond) \
+ printf(pr_fmt(fmt), ##args); \
} while (0)
#define debug(fmt, args...) \
__assert_fail(#x, __FILE__, __LINE__, __func__); })
#define error(fmt, args...) do { \
- printf("ERROR: " fmt "\nat %s:%d/%s()\n", \
+ printf("ERROR: " pr_fmt(fmt) "\nat %s:%d/%s()\n", \
##args, __FILE__, __LINE__, __func__); \
} while (0)
# endif
#endif
-/*
- * General Purpose Utilities
- */
-#define min(X, Y) \
- ({ typeof(X) __x = (X); \
- typeof(Y) __y = (Y); \
- (__x < __y) ? __x : __y; })
-
-#define max(X, Y) \
- ({ typeof(X) __x = (X); \
- typeof(Y) __y = (Y); \
- (__x > __y) ? __x : __y; })
-
-#define min3(X, Y, Z) \
- ({ typeof(X) __x = (X); \
- typeof(Y) __y = (Y); \
- typeof(Z) __z = (Z); \
- __x < __y ? (__x < __z ? __x : __z) : \
- (__y < __z ? __y : __z); })
-
-#define max3(X, Y, Z) \
- ({ typeof(X) __x = (X); \
- typeof(Y) __y = (Y); \
- typeof(Z) __z = (Z); \
- __x > __y ? (__x > __z ? __x : __z) : \
- (__y > __z ? __y : __z); })
-
-/*
- * Return the absolute value of a number.
- *
- * This handles unsigned and signed longs, ints, shorts and chars. For all
- * input types abs() returns a signed long.
- *
- * For 64-bit types, use abs64()
- */
-#define abs(x) ({ \
- long ret; \
- if (sizeof(x) == sizeof(long)) { \
- long __x = (x); \
- ret = (__x < 0) ? -__x : __x; \
- } else { \
- int __x = (x); \
- ret = (__x < 0) ? -__x : __x; \
- } \
- ret; \
- })
-
-#define abs64(x) ({ \
- s64 __x = (x); \
- (__x < 0) ? -__x : __x; \
- })
-
#if defined(CONFIG_ENV_IS_EMBEDDED)
#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
#elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \
#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
#endif
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @ptr: the pointer to the member.
- * @type: the type of the container struct this is embedded in.
- * @member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({ \
- const typeof( ((type *)0)->member ) *__mptr = (ptr); \
- (type *)( (char *)__mptr - offsetof(type,member) );})
-
/*
* Function Prototypes
*/
#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README.
#endif
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
#define ROUND(a,b) (((a) + (b) - 1) & ~((b) - 1))
-#define DIV_ROUND(n,d) (((n) + ((d)/2)) / (d))
-#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
-#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
-
-/*
- * Divide positive or negative dividend by positive divisor and round
- * to closest integer. Result is undefined for negative divisors and
- * for negative dividends if the divisor variable type is unsigned.
- */
-#define DIV_ROUND_CLOSEST(x, divisor)( \
-{ \
- typeof(x) __x = x; \
- typeof(divisor) __d = divisor; \
- (((typeof(x))-1) > 0 || \
- ((typeof(divisor))-1) > 0 || (__x) > 0) ? \
- (((__x) + ((__d) / 2)) / (__d)) : \
- (((__x) - ((__d) / 2)) / (__d)); \
-} \
-)
-
-#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
-#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
/*
* ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture. It
* Usage of this macro shall be avoided or used with extreme care!
*/
#define DEFINE_ALIGN_BUFFER(type, name, size, align) \
- static char __##name[roundup(size * sizeof(type), align)] \
+ static char __##name[ALIGN(size * sizeof(type), align)] \
__aligned(align); \
\
static type *name = (type *)__##name
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T /* This is an ARM920T Core */
-#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */
#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */
#define CONFIG_VCMA9 /* on a MPL VCMA9 Board */
#define CONFIG_MACH_TYPE MACH_TYPE_MPL_VCMA9 /* Machine type */
/*
* SoC configurations
*/
-#define CONFIG_ARM926EJS /* this is an ARM926EJS CPU */
-#define CONFIG_MX27 /* in a Freescale i.MX27 Chip */
+#define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */
#define CONFIG_MACH_TYPE 1698 /* APF27 */
#define CONFIG_SYS_GENERIC_BOARD
#define __ARMADILLO_800EVA_H
#undef DEBUG
-#define CONFIG_ARMV7
#define CONFIG_R8A7740
#define CONFIG_RMOBILE_BOARD_STRING "Armadillo-800EVA Board\n"
#define CONFIG_SH_GPIO_PFC
#include <linux/sizes.h>
#include <asm/arch/sysmap.h>
-/* Architecture, CPU, chip, mach, etc */
-#define CONFIG_ARMV7
+/* CPU, chip, mach, etc */
#define CONFIG_KONA
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_GENERIC_BOARD
#include <asm/arch/configs.h>
-/* Architecture, CPU, chip, etc */
-#define CONFIG_ARMV7
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_GENERIC_BOARD
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_CALIMAIN
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SOC_DM365
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_CAR_ADDR 0xff7e0000
+#define CONFIG_SYS_CAR_SIZE (128 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (1 << 20)
+#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000
+#define CONFIG_SYS_X86_START16 0xfffff800
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_X86_RESET_VECTOR
+#define CONFIG_NR_DRAM_BANKS 8
+#define CONFIG_X86_MRC_START 0xfffa0000
+#define CONFIG_CACHE_MRC_SIZE_KB 512
+
+#define CONFIG_COREBOOT_SERIAL
+
+#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
+
+/*
+ * These common x86 features are not yet supported, but are added in
+ * follow-on patches in this series. Add undefs here to avoid every patch
+ * having to put things back into x86-common.h
+ */
+#undef CONFIG_VIDEO
+#undef CONFIG_CFB_CONSOLE
+#undef CONFIG_ICH_SPI
+#undef CONFIG_SPI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_SF
+#undef CONFIG_USB_EHCI
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_SCSI
+
+#define CONFIG_PCI_MEM_BUS 0xe0000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_PREF_BUS 0xd0000000
+#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
+#define CONFIG_PCI_PREF_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x1000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0xefff
+
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
+ "stdout=vga,serial\0" \
+ "stderr=vga,serial\0"
+
+#endif /* __CONFIG_H */
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <asm/ibmpc.h>
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <configs/x86-common.h>
+
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_SYS_COREBOOT
-#define CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_LAST_STAGE_INIT
-#define CONFIG_SYS_VSNPRINTF
-#define CONFIG_ZBOOT_32
-#define CONFIG_PHYSMEM
#define CONFIG_SYS_EARLY_PCI_INIT
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DM
-#define CONFIG_CMD_DM
-#define CONFIG_DM_GPIO
-#define CONFIG_DM_SERIAL
+#define CONFIG_SYS_CAR_ADDR 0x19200000
+#define CONFIG_SYS_CAR_SIZE (16 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_LMB
-#define CONFIG_OF_LIBFDT
+#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
+#define CONFIG_TRACE_EARLY
+#define CONFIG_TRACE_EARLY_ADDR 0x01400000
#define CONFIG_BOOTSTAGE
#define CONFIG_BOOTSTAGE_REPORT
#define CONFIG_BOOTSTAGE_STASH_SIZE 0x7fc
#define CONFIG_BOOTSTAGE_USER_COUNT 60
-#define CONFIG_LZO
-#define CONFIG_FIT
-#undef CONFIG_ZLIB
-#undef CONFIG_GZIP
-#define CONFIG_SYS_BOOTM_LEN (16 << 20)
-
-/*-----------------------------------------------------------------------
- * Watchdog Configuration
- */
-#undef CONFIG_WATCHDOG
-#undef CONFIG_HW_WATCHDOG
-
-/* SATA AHCI storage */
-
-#define CONFIG_SCSI_AHCI
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
-#define CONFIG_SYS_64BIT_LBA
-#define CONFIG_SATA_INTEL 1
#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
{PCI_VENDOR_ID_INTEL, \
{PCI_VENDOR_ID_INTEL, \
PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
-/* Generic TPM interfaced through LPC bus */
-#define CONFIG_TPM
-#define CONFIG_TPM_TIS_LPC
-#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000
-
-/*-----------------------------------------------------------------------
- * Real Time Clock Configuration
- */
-#define CONFIG_RTC_MC146818
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
-#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS
-
-/*-----------------------------------------------------------------------
- * Serial Configuration
- */
#define CONFIG_COREBOOT_SERIAL
-#define CONFIG_SYS_NS16550
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
- 9600, 19200, 38400, 115200}
-#define CONFIG_SYS_NS16550_PORT_MAPPED
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
"stdout=vga,serial,cbmem\0" \
"stderr=vga,serial,cbmem\0"
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_CBMEM_CONSOLE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_COMMAND_HISTORY
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
-
-#define CONFIG_SUPPORT_VFAT
-/************************************************************
- * ATAPI support (experimental)
- ************************************************************/
-#define CONFIG_ATAPI
-
-/************************************************************
- * DISK Partition support
- ************************************************************/
-#define CONFIG_EFI_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION /* Experimental */
-
-#define CONFIG_CMD_PART
-#define CONFIG_CMD_CBFS
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_PARTITION_UUIDS
-
-/*-----------------------------------------------------------------------
- * Video Configuration
- */
-#define CONFIG_VIDEO
#define CONFIG_VIDEO_COREBOOT
-#define CONFIG_VIDEO_SW_CURSOR
-#define VIDEO_FB_16BPP_WORD_SWAP
-#define CONFIG_I8042_KBD
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-/* x86 GPIOs are accessed through a PCI device */
-#define CONFIG_INTEL_ICH6_GPIO
-
-/*-----------------------------------------------------------------------
- * Command line configuration.
- */
-#include <config_cmd_default.h>
+#define CONFIG_NR_DRAM_BANKS 4
#define CONFIG_TRACE
#define CONFIG_CMD_TRACE
#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
-#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
-#define CONFIG_TRACE_EARLY
-#define CONFIG_TRACE_EARLY_ADDR 0x01400000
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ECHO
-#undef CONFIG_CMD_FLASH
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_GPIO
-#define CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#define CONFIG_CMD_IO
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ITEST
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_SETGETDCR
-#define CONFIG_CMD_SOURCE
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_GETTIME
-#define CONFIG_CMD_XIMG
-#define CONFIG_CMD_SCSI
-
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-
-#define CONFIG_CMD_ZBOOT
-#define CONFIG_CMD_ELF
#define CONFIG_BOOTDELAY 2
-#define CONFIG_BOOTARGS \
- "root=/dev/sdb3 init=/sbin/init rootwait ro"
-#define CONFIG_BOOTCOMMAND \
- "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
-
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE 512
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + \
- 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000
-#define CONFIG_SYS_MEMTEST_END 0x01000000
-#define CONFIG_SYS_LOAD_ADDR 0x20000000
-
-/*-----------------------------------------------------------------------
- * SDRAM Configuration
- */
-#define CONFIG_NR_DRAM_BANKS 4
-
-/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
-#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
-#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
-#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
-#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
-
-/*-----------------------------------------------------------------------
- * CPU Features
- */
-
-#define CONFIG_SYS_X86_TSC_TIMER
-#define CONFIG_SYS_PCAT_INTERRUPTS
-#define CONFIG_SYS_PCAT_TIMER
-#define CONFIG_SYS_NUM_IRQS 16
-
-/*-----------------------------------------------------------------------
- * Memory organization:
- * 32kB Stack
- * 16kB Cache-As-RAM @ 0x19200000
- * 256kB Monitor
- * (128kB + Environment Sector Size) malloc pool
- */
-#define CONFIG_SYS_STACK_SIZE (32 * 1024)
-#define CONFIG_SYS_CAR_ADDR 0x19200000
-#define CONFIG_SYS_CAR_SIZE (16 * 1024)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (0x20000 + 128 * 1024)
-#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/*-----------------------------------------------------------------------
- * FLASH configuration
- */
-#define CONFIG_ICH_SPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SPI_FLASH_GIGADEVICE
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SF_TEST
-#define CONFIG_CMD_SPI
-#define CONFIG_SPI
-
-/*-----------------------------------------------------------------------
- * Environment configuration
- */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE 0x01000
-
-/*-----------------------------------------------------------------------
- * PCI configuration
- */
-#define CONFIG_PCI
#define CONFIG_CROS_EC
#define CONFIG_CROS_EC_LPC
#define CONFIG_CMD_CROS_EC
#define CONFIG_ARCH_EARLY_INIT_R
-/*-----------------------------------------------------------------------
- * USB configuration
- */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_PCI
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_USB_EVENT_POLL
-
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_USB_ETHER_SMSC95XX
-#define CONFIG_TFTP_TSIZE
-#define CONFIG_CMD_DHCP
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-#define CONFIG_CMD_USB
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_STD_DEVICES_SETTINGS
-
#endif /* __CONFIG_H */
#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
-#define CONFIG_ARM920T
#define CONFIG_AT91RM9200
#define CONFIG_CPUAT91
#define USE_920T_MMU
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_DA830_EVM
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA830 /* TI DA830 SoC */
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SOC_DM355
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SOC_DM355 /* DM355 based board */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SOC_DM365
#define CONFIG_SKIP_LOWLEVEL_INIT
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU */
/* Clock rates detection */
#ifndef __ASSEMBLY__
/*===================*/
/* SoC Configuration */
/*===================*/
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SOC_DM644X
/*===================*/
/* SoC Configuration */
/*===================*/
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SOC_DM644X
#define CONFIG_SYS_USE_NAND
#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SOC_DM644X
/*===================*/
/* SoC Configuration */
/*===================*/
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SOC_DM644X
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#endif
/* High-level configuration options */
-#define CONFIG_ARM920T 1 /* This is an ARM920T core... */
-#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */
+#define CONFIG_EP93XX 1 /* This is a Cirrus Logic 93xx SoC */
#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */
#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */
*/
#define CONFIG_MARVELL 1
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
#define CONFIG_FEROCEON 1 /* CPU Core subversion */
#define CONFIG_88F5182 1 /* SOC Name */
#define CONFIG_MACH_EDMINIV2 1 /* Machine type */
/*
* SoC Configuration
*/
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
#define CONFIG_MX35
#define CONFIG_SYS_DCACHE_OFF
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_HAWK
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ sizeof(CONFIG_SYS_PROMPT)+16)
/*
* SoC Configuration
*/
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_MX27
#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
-#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31 1 /* This is a mx31 */
#define CONFIG_MX31_CLK32 32000
#define CONFIG_DISPLAY_CPUINFO
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
-#define CONFIG_MX31 /* in a mx31 */
+#define CONFIG_MX31 /* This is a mx31 */
#define CONFIG_MX31_CLK32 32000
#define CONFIG_DISPLAY_CPUINFO
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_MB86R0x_IOCLK get_bus_freq(0)
#define CONFIG_SYS_TEXT_BASE 0x10000000
-#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_SYS_THUMB_BUILD
/* SoC Configuration */
-#define CONFIG_ARMV7
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_TEXT_BASE 0x0c001000
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE \
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE \
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
-#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31 1 /* This is a mx31 */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
-#define CONFIG_MX31 /* in a mx31 */
+#define CONFIG_MX31 /* This is a mx31 */
#define CONFIG_SYS_GENERIC_BOARD
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
#define CONFIG_MX35
#define CONFIG_DISPLAY_CPUINFO
#include <nomadik.h>
-#define CONFIG_ARM926EJS
#define CONFIG_NOMADIK_8815 /* cpu variant */
#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
-#define CONFIG_MX31 /* in a mx31 */
+#define CONFIG_MX31 /* This is a mx31 */
#define CONFIG_QONG
#define CONFIG_DISPLAY_CPUINFO
/* Architecture, CPU, etc.*/
#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_ARM1176
#define CONFIG_BCM2835
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_FS_FAT
+#define CONFIG_FAT_WRITE
#define CONFIG_FS_EXT4
#define CONFIG_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#define CONFIG_HOST_MAX_DEVICES 4
#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_MD5SUM
#define CONFIG_SYS_VSNPRINTF
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */
-#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */
+#define CONFIG_IMX 1 /* This is a Motorola MC9328MXL Chip */
#define CONFIG_SCB9328 1 /* on a scb9328tronix board */
#define CONFIG_IMX_SERIAL
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T /* This is an ARM920T Core */
-#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */
#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */
#define CONFIG_SMDK2410 /* on a SAMSUNG SMDK2410 Board */
/* Virtual target or real hardware */
#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_ARMV7
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SOCFPGA
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP_GPIO
#include <asm/arch/clock.h>
/* Architecture, CPU, etc */
-#define CONFIG_ARM1176
#define CONFIG_TNETV107X
#define CONFIG_TNETV107X_EVM
#define CONFIG_TNETV107X_WATCHDOG
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136
#define CONFIG_MX31
#define CONFIG_DISPLAY_CPUINFO
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
-#define CONFIG_VERSATILE 1 /* in Versatile Platform Board */
+#define CONFIG_VERSATILE 1 /* This is Versatile Platform Board */
#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */
#define CONFIG_SYS_MEMTEST_START 0x100000
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
#define CONFIG_MX35
#define CONFIG_MX35_HCLK_FREQ 24000000
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/ibmpc.h>
+
+#ifndef __CONFIG_X86_COMMON_H
+#define __CONFIG_X86_COMMON_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_SYS_VSNPRINTF
+#define CONFIG_ZBOOT_32
+#define CONFIG_PHYSMEM
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_DM
+#define CONFIG_CMD_DM
+#define CONFIG_DM_GPIO
+#define CONFIG_DM_SERIAL
+
+#define CONFIG_LMB
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_LZO
+#define CONFIG_FIT
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+#define CONFIG_SYS_BOOTM_LEN (16 << 20)
+
+/* SATA AHCI storage */
+
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SATA_INTEL
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_LIBATA
+#define CONFIG_SYS_64BIT_LBA
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
+/* Generic TPM interfaced through LPC bus */
+#define CONFIG_TPM
+#define CONFIG_TPM_TIS_LPC
+#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000
+
+/*-----------------------------------------------------------------------
+ * Real Time Clock Configuration
+ */
+#define CONFIG_RTC_MC146818
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
+#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS
+
+/*-----------------------------------------------------------------------
+ * Serial Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
+ 9600, 19200, 38400, 115200}
+#define CONFIG_SYS_NS16550_PORT_MAPPED
+
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_STDIO_DEREGISTER
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_SUPPORT_VFAT
+/************************************************************
+ * ATAPI support (experimental)
+ ************************************************************/
+#define CONFIG_ATAPI
+
+/************************************************************
+ * DISK Partition support
+ ************************************************************/
+#define CONFIG_EFI_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION /* Experimental */
+
+#define CONFIG_CMD_PART
+#define CONFIG_CMD_CBFS
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_PARTITION_UUIDS
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* x86 GPIOs are accessed through a PCI device */
+#define CONFIG_INTEL_ICH6_GPIO
+
+/*-----------------------------------------------------------------------
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ECHO
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_IO
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ITEST
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_GETTIME
+#define CONFIG_CMD_XIMG
+#define CONFIG_CMD_SCSI
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_CMD_ZBOOT
+#define CONFIG_CMD_ELF
+
+#define CONFIG_BOOTARGS \
+ "root=/dev/sdb3 init=/sbin/init rootwait ro"
+#define CONFIG_BOOTCOMMAND \
+ "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + \
+ 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x01000000
+#define CONFIG_SYS_LOAD_ADDR 0x20000000
+
+/*-----------------------------------------------------------------------
+ * Video Configuration
+ */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SW_CURSOR
+#define VIDEO_FB_16BPP_WORD_SWAP
+#define CONFIG_I8042_KBD
+#define CONFIG_CFB_CONSOLE
+
+/*-----------------------------------------------------------------------
+ * CPU Features
+ */
+
+#define CONFIG_SYS_X86_TSC_TIMER
+#define CONFIG_SYS_PCAT_INTERRUPTS
+#define CONFIG_SYS_PCAT_TIMER
+#define CONFIG_SYS_NUM_IRQS 16
+
+#define CONFIG_SYS_STACK_SIZE (32 * 1024)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN 0x200000
+#define CONFIG_SYS_MALLOC_F_LEN (2 << 10)
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/*-----------------------------------------------------------------------
+ * FLASH configuration
+ */
+#define CONFIG_ICH_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_GIGADEVICE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SF_TEST
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI
+
+/*-----------------------------------------------------------------------
+ * Environment configuration
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x01000
+
+/*-----------------------------------------------------------------------
+ * PCI configuration
+ */
+#define CONFIG_PCI
+
+/*-----------------------------------------------------------------------
+ * USB configuration
+ */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_PCI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_TFTP_TSIZE
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+#define CONFIG_CMD_USB
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_STD_DEVICES_SETTINGS
+
+#endif /* __CONFIG_H */
#include <asm/arch/imx-regs.h>
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_MX25
#define CONFIG_SYS_TEXT_BASE 0xA0000000
#ifndef __CONFIG_ZYNQ_COMMON_H
#define __CONFIG_ZYNQ_COMMON_H
-/* High Level configuration Options */
-#define CONFIG_ARMV7
-
/* CPU clock */
#ifndef CONFIG_CPU_FREQ_HZ
# define CONFIG_CPU_FREQ_HZ 800000000
void ext4fs_deinit(void);
int ext4fs_filename_check(char *filename);
int ext4fs_write(const char *fname, unsigned char *buffer,
- unsigned long sizebytes);
+ unsigned long sizebytes);
+int ext4_write_file(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *actwrite);
#endif
struct ext_filesystem *get_fs(void);
-int ext4fs_open(const char *filename);
-int ext4fs_read(char *buf, unsigned len);
+int ext4fs_open(const char *filename, loff_t *len);
+int ext4fs_read(char *buf, loff_t len, loff_t *actread);
int ext4fs_mount(unsigned part_length);
void ext4fs_close(void);
void ext4fs_reinit_global(void);
int ext4fs_ls(const char *dirname);
int ext4fs_exists(const char *filename);
-int ext4fs_size(const char *filename);
+int ext4fs_size(const char *filename, loff_t *size);
void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot);
int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf);
void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
long int read_allocated_block(struct ext2_inode *inode, int fileblock);
int ext4fs_probe(block_dev_desc_t *fs_dev_desc,
disk_partition_t *fs_partition);
-int ext4_read_file(const char *filename, void *buf, int offset, int len);
+int ext4_read_file(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *actread);
int ext4_read_superblock(char *buffer);
+int ext4fs_uuid(char *uuid_str);
#endif
typedef int (file_detectfs_func)(void);
typedef int (file_ls_func)(const char *dir);
-typedef long (file_read_func)(const char *filename, void *buffer,
- unsigned long maxsize);
+typedef int (file_read_func)(const char *filename, void *buffer,
+ int maxsize);
struct filesystem {
file_detectfs_func *detect;
int file_fat_detectfs(void);
int file_fat_ls(const char *dir);
int fat_exists(const char *filename);
-int fat_size(const char *filename);
-long file_fat_read_at(const char *filename, unsigned long pos, void *buffer,
- unsigned long maxsize);
-long file_fat_read(const char *filename, void *buffer, unsigned long maxsize);
+int fat_size(const char *filename, loff_t *size);
+int file_fat_read_at(const char *filename, loff_t pos, void *buffer,
+ loff_t maxsize, loff_t *actread);
+int file_fat_read(const char *filename, void *buffer, int maxsize);
const char *file_getfsname(int idx);
int fat_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
int fat_register_device(block_dev_desc_t *dev_desc, int part_no);
-int file_fat_write(const char *filename, void *buffer, unsigned long maxsize);
-int fat_read_file(const char *filename, void *buf, int offset, int len);
+int file_fat_write(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *actwrite);
+int fat_read_file(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *actread);
void fat_close(void);
#endif /* _FAT_H_ */
COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */
COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */
COMPAT_INTEL_LPC, /* Intel Low Pin Count I/F */
+ COMPAT_INTEL_MICROCODE, /* Intel microcode update */
+ COMPAT_MEMORY_SPD, /* Memory SPD information */
COMPAT_COUNT,
};
int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
u32 *array, int count);
+/**
+ * Look up a property in a node and return its contents in an integer
+ * array of given length. The property must exist but may have less data that
+ * expected (4*count bytes). It may have more, but this will be ignored.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param prop_name name of property to find
+ * @param array array to fill with data
+ * @param count number of array elements
+ * @return number of array elements if ok, or -FDT_ERR_NOTFOUND if the
+ * property is not found
+ */
+int fdtdec_get_int_array_count(const void *blob, int node,
+ const char *prop_name, u32 *array, int count);
+
/**
* Look up a property in a node and return a pointer to its contents as a
* unsigned int array of given length. The property must have at least enough
int fs_exists(const char *filename);
/*
- * Determine a file's size
+ * fs_size - Determine a file's size
*
- * Returns the file's size in bytes, or a negative value if it doesn't exist.
+ * @filename: Name of the file
+ * @size: Size of file
+ * @return 0 if ok with valid *size, negative on error
*/
-int fs_size(const char *filename);
+int fs_size(const char *filename, loff_t *size);
/*
- * Read file "filename" from the partition previously set by fs_set_blk_dev(),
- * to address "addr", starting at byte offset "offset", and reading "len"
- * bytes. "offset" may be 0 to read from the start of the file. "len" may be
- * 0 to read the entire file. Note that not all filesystem types support
- * either/both offset!=0 or len!=0.
+ * fs_read - Read file from the partition previously set by fs_set_blk_dev()
+ * Note that not all filesystem types support either/both offset!=0 or len!=0.
*
- * Returns number of bytes read on success. Returns <= 0 on error.
+ * @filename: Name of file to read from
+ * @addr: The address to read into
+ * @offset: The offset in file to read from
+ * @len: The number of bytes to read. Maybe 0 to read entire file
+ * @actread: Returns the actual number of bytes read
+ * @return 0 if ok with valid *actread, -1 on error conditions
*/
-int fs_read(const char *filename, ulong addr, int offset, int len);
+int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len,
+ loff_t *actread);
/*
- * Write file "filename" to the partition previously set by fs_set_blk_dev(),
- * from address "addr", starting at byte offset "offset", and writing "len"
- * bytes. "offset" may be 0 to write to the start of the file. Note that not
- * all filesystem types support offset!=0.
+ * fs_write - Write file to the partition previously set by fs_set_blk_dev()
+ * Note that not all filesystem types support offset!=0.
*
- * Returns number of bytes read on success. Returns <= 0 on error.
+ * @filename: Name of file to read from
+ * @addr: The address to read into
+ * @offset: The offset in file to read from. Maybe 0 to write to start of file
+ * @len: The number of bytes to write
+ * @actwrite: Returns the actual number of bytes written
+ * @return 0 if ok with valid *actwrite, -1 on error conditions
*/
-int fs_write(const char *filename, ulong addr, int offset, int len);
+int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len,
+ loff_t *actwrite);
/*
* Common implementation for various filesystem commands, optionally limited
int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
int fstype);
+/*
+ * Determine the UUID of the specified filesystem and print it. Optionally it is
+ * possible to store the UUID directly in env.
+ */
+int do_fs_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+ int fstype);
+
#endif /* _FS_H */
#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
-/*
- * ..and if you can't take the strict
- * types, you can specify one yourself.
- *
- * Or not use min/max at all, of course.
- */
-#define min_t(type,x,y) \
- ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
-#define max_t(type,x,y) \
- ({ type __x = (x); type __y = (y); __x > __y ? __x: __y; })
-
#ifndef BUG
#define BUG() do { \
printf("U-Boot BUG at %s:%d!\n", __FILE__, __LINE__); \
#define PAGE_SIZE 4096
-/**
- * upper_32_bits - return MSB bits 32-63 of a number if little endian, or
- * return MSB bits 0-31 of a number if big endian.
- * @n: the number we're accessing
- *
- * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
- * the "right shift count >= width of type" warning when that quantity is
- * 32-bits.
- */
-#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
-
-/**
- * lower_32_bits - return LSB bits 0-31 of a number if little endian, or
- * return LSB bits 32-63 of a number if big endian.
- * @n: the number we're accessing
- */
-#define lower_32_bits(n) ((u32)(n))
-
/* drivers/char/random.c */
#define get_random_bytes(...)
#define ENOTSUPP 524 /* Operation is not supported */
-/* from include/linux/kernel.h */
-/*
- * This looks more complex than it should be. But we need to
- * get the type for the ~ right in round_down (it needs to be
- * as wide as the result!), and we want to evaluate the macro
- * arguments just once each.
- */
-#define __round_mask(x, y) ((__typeof__(x))((y)-1))
-#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1)
-#define round_down(x, y) ((x) & ~__round_mask(x, y))
-
/* module */
#define THIS_MODULE 0
#define try_module_get(...) 1
#define blocking_notifier_call_chain(...) 0
-/*
- * Multiplies an integer by a fraction, while avoiding unnecessary
- * overflow or loss of precision.
- */
-#define mult_frac(x, numer, denom)( \
-{ \
- typeof(x) quot = (x) / (denom); \
- typeof(x) rem = (x) % (denom); \
- (quot * (numer)) + ((rem * (numer)) / (denom)); \
-} \
-)
-
#define __initdata
#define late_initcall(...)
#define cond_resched() do { } while (0)
#define yield() do { } while (0)
-#define INT_MAX ((int)(~0U>>1))
-
#define __user
#define __init
#define __exit
--- /dev/null
+#ifndef _LINUX_KERNEL_H
+#define _LINUX_KERNEL_H
+
+
+#include <linux/types.h>
+
+#define USHRT_MAX ((u16)(~0U))
+#define SHRT_MAX ((s16)(USHRT_MAX>>1))
+#define SHRT_MIN ((s16)(-SHRT_MAX - 1))
+#define INT_MAX ((int)(~0U>>1))
+#define INT_MIN (-INT_MAX - 1)
+#define UINT_MAX (~0U)
+#define LONG_MAX ((long)(~0UL>>1))
+#define LONG_MIN (-LONG_MAX - 1)
+#define ULONG_MAX (~0UL)
+#define LLONG_MAX ((long long)(~0ULL>>1))
+#define LLONG_MIN (-LLONG_MAX - 1)
+#define ULLONG_MAX (~0ULL)
+#define SIZE_MAX (~(size_t)0)
+
+#define U8_MAX ((u8)~0U)
+#define S8_MAX ((s8)(U8_MAX>>1))
+#define S8_MIN ((s8)(-S8_MAX - 1))
+#define U16_MAX ((u16)~0U)
+#define S16_MAX ((s16)(U16_MAX>>1))
+#define S16_MIN ((s16)(-S16_MAX - 1))
+#define U32_MAX ((u32)~0U)
+#define S32_MAX ((s32)(U32_MAX>>1))
+#define S32_MIN ((s32)(-S32_MAX - 1))
+#define U64_MAX ((u64)~0ULL)
+#define S64_MAX ((s64)(U64_MAX>>1))
+#define S64_MIN ((s64)(-S64_MAX - 1))
+
+#define STACK_MAGIC 0xdeadbeef
+
+#define REPEAT_BYTE(x) ((~0ul / 0xff) * (x))
+
+#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
+#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
+#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a)))
+#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0)
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/*
+ * This looks more complex than it should be. But we need to
+ * get the type for the ~ right in round_down (it needs to be
+ * as wide as the result!), and we want to evaluate the macro
+ * arguments just once each.
+ */
+#define __round_mask(x, y) ((__typeof__(x))((y)-1))
+#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1)
+#define round_down(x, y) ((x) & ~__round_mask(x, y))
+
+#define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f))
+#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
+
+#if BITS_PER_LONG == 32
+# define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP_ULL(ll, d)
+#else
+# define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP(ll,d)
+#endif
+
+/* The `const' in roundup() prevents gcc-3.3 from calling __divdi3 */
+#define roundup(x, y) ( \
+{ \
+ const typeof(y) __y = y; \
+ (((x) + (__y - 1)) / __y) * __y; \
+} \
+)
+#define rounddown(x, y) ( \
+{ \
+ typeof(x) __x = (x); \
+ __x - (__x % (y)); \
+} \
+)
+
+/*
+ * Divide positive or negative dividend by positive divisor and round
+ * to closest integer. Result is undefined for negative divisors and
+ * for negative dividends if the divisor variable type is unsigned.
+ */
+#define DIV_ROUND_CLOSEST(x, divisor)( \
+{ \
+ typeof(x) __x = x; \
+ typeof(divisor) __d = divisor; \
+ (((typeof(x))-1) > 0 || \
+ ((typeof(divisor))-1) > 0 || (__x) > 0) ? \
+ (((__x) + ((__d) / 2)) / (__d)) : \
+ (((__x) - ((__d) / 2)) / (__d)); \
+} \
+)
+
+/*
+ * Multiplies an integer by a fraction, while avoiding unnecessary
+ * overflow or loss of precision.
+ */
+#define mult_frac(x, numer, denom)( \
+{ \
+ typeof(x) quot = (x) / (denom); \
+ typeof(x) rem = (x) % (denom); \
+ (quot * (numer)) + ((rem * (numer)) / (denom)); \
+} \
+)
+
+/**
+ * upper_32_bits - return bits 32-63 of a number
+ * @n: the number we're accessing
+ *
+ * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
+ * the "right shift count >= width of type" warning when that quantity is
+ * 32-bits.
+ */
+#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * lower_32_bits - return bits 0-31 of a number
+ * @n: the number we're accessing
+ */
+#define lower_32_bits(n) ((u32)(n))
+
+/*
+ * abs() handles unsigned and signed longs, ints, shorts and chars. For all
+ * input types abs() returns a signed long.
+ * abs() should not be used for 64-bit types (s64, u64, long long) - use abs64()
+ * for those.
+ */
+#define abs(x) ({ \
+ long ret; \
+ if (sizeof(x) == sizeof(long)) { \
+ long __x = (x); \
+ ret = (__x < 0) ? -__x : __x; \
+ } else { \
+ int __x = (x); \
+ ret = (__x < 0) ? -__x : __x; \
+ } \
+ ret; \
+ })
+
+#define abs64(x) ({ \
+ s64 __x = (x); \
+ (__x < 0) ? -__x : __x; \
+ })
+
+/*
+ * min()/max()/clamp() macros that also do
+ * strict type-checking.. See the
+ * "unnecessary" pointer comparison.
+ */
+#define min(x, y) ({ \
+ typeof(x) _min1 = (x); \
+ typeof(y) _min2 = (y); \
+ (void) (&_min1 == &_min2); \
+ _min1 < _min2 ? _min1 : _min2; })
+
+#define max(x, y) ({ \
+ typeof(x) _max1 = (x); \
+ typeof(y) _max2 = (y); \
+ (void) (&_max1 == &_max2); \
+ _max1 > _max2 ? _max1 : _max2; })
+
+#define min3(x, y, z) min((typeof(x))min(x, y), z)
+#define max3(x, y, z) max((typeof(x))max(x, y), z)
+
+/**
+ * min_not_zero - return the minimum that is _not_ zero, unless both are zero
+ * @x: value1
+ * @y: value2
+ */
+#define min_not_zero(x, y) ({ \
+ typeof(x) __x = (x); \
+ typeof(y) __y = (y); \
+ __x == 0 ? __y : ((__y == 0) ? __x : min(__x, __y)); })
+
+/**
+ * clamp - return a value clamped to a given range with strict typechecking
+ * @val: current value
+ * @lo: lowest allowable value
+ * @hi: highest allowable value
+ *
+ * This macro does strict typechecking of lo/hi to make sure they are of the
+ * same type as val. See the unnecessary pointer comparisons.
+ */
+#define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
+
+/*
+ * ..and if you can't take the strict
+ * types, you can specify one yourself.
+ *
+ * Or not use min/max/clamp at all, of course.
+ */
+#define min_t(type, x, y) ({ \
+ type __min1 = (x); \
+ type __min2 = (y); \
+ __min1 < __min2 ? __min1: __min2; })
+
+#define max_t(type, x, y) ({ \
+ type __max1 = (x); \
+ type __max2 = (y); \
+ __max1 > __max2 ? __max1: __max2; })
+
+/**
+ * clamp_t - return a value clamped to a given range using a given type
+ * @type: the type of variable to use
+ * @val: current value
+ * @lo: minimum allowable value
+ * @hi: maximum allowable value
+ *
+ * This macro does no typechecking and uses temporary variables of type
+ * 'type' to make all the comparisons.
+ */
+#define clamp_t(type, val, lo, hi) min_t(type, max_t(type, val, lo), hi)
+
+/**
+ * clamp_val - return a value clamped to a given range using val's type
+ * @val: current value
+ * @lo: minimum allowable value
+ * @hi: maximum allowable value
+ *
+ * This macro does no typechecking and uses temporary variables of whatever
+ * type the input argument 'val' is. This is useful when val is an unsigned
+ * type and min and max are literals that will otherwise be assigned a signed
+ * integer type.
+ */
+#define clamp_val(val, lo, hi) clamp_t(typeof(val), val, lo, hi)
+
+
+/*
+ * swap - swap value of @a and @b
+ */
+#define swap(a, b) \
+ do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @ptr: the pointer to the member.
+ * @type: the type of the container struct this is embedded in.
+ * @member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({ \
+ const typeof( ((type *)0)->member ) *__mptr = (ptr); \
+ (type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif
* Get the size of a file
*
* @param fname Filename to check
- * @return size of file, or -1 if an error ocurred
+ * @param size size of file is returned if no error
+ * @return 0 on success or -1 if an error ocurred
*/
-ssize_t os_get_filesize(const char *fname);
+int os_get_filesize(const char *fname, loff_t *size);
/**
* Write a character to the controlling OS terminal
extern struct pci_controller* pci_bus_to_hose(int bus);
extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
+extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
extern int pci_hose_scan(struct pci_controller *hose);
extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
int sandbox_fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
-long sandbox_fs_read_at(const char *filename, unsigned long pos,
- void *buffer, unsigned long maxsize);
+int sandbox_fs_read_at(const char *filename, loff_t pos, void *buffer,
+ loff_t maxsize, loff_t *actread);
+int sandbox_fs_write_at(const char *filename, loff_t pos, void *buffer,
+ loff_t maxsize, loff_t *actwrite);
void sandbox_fs_close(void);
int sandbox_fs_ls(const char *dirname);
int sandbox_fs_exists(const char *filename);
-int sandbox_fs_size(const char *filename);
-int fs_read_sandbox(const char *filename, void *buf, int offset, int len);
-int fs_write_sandbox(const char *filename, void *buf, int offset, int len);
+int sandbox_fs_size(const char *filename, loff_t *size);
+int fs_read_sandbox(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *actread);
+int fs_write_sandbox(const char *filename, void *buf, loff_t offset,
+ loff_t len, loff_t *actwrite);
#endif
#ifdef CONFIG_SYS_MALLOC_F_LEN
DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base));
#endif
+#ifdef CONFIG_X86
+ DEFINE(GD_BIST, offsetof(struct global_data, arch.bist));
+#endif
#if defined(CONFIG_ARM)
COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
COMPAT(PARADE_PS8625, "parade,ps8625"),
COMPAT(COMPAT_INTEL_LPC, "intel,lpc"),
+ COMPAT(INTEL_MICROCODE, "intel,microcode"),
+ COMPAT(MEMORY_SPD, "memory-spd"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
return err;
}
+int fdtdec_get_int_array_count(const void *blob, int node,
+ const char *prop_name, u32 *array, int count)
+{
+ const u32 *cell;
+ int len, elems;
+ int i;
+
+ debug("%s: %s\n", __func__, prop_name);
+ cell = fdt_getprop(blob, node, prop_name, &len);
+ if (!cell)
+ return -FDT_ERR_NOTFOUND;
+ elems = len / sizeof(u32);
+ if (count > elems)
+ count = elems;
+ for (i = 0; i < count; i++)
+ array[i] = fdt32_to_cpu(cell[i]);
+
+ return count;
+}
+
const u32 *fdtdec_locate_array(const void *blob, int node,
const char *prop_name, int count)
{
long l, n;
long m;
- n = DIV_ROUND(hz, 1000) / 1000L;
+ n = DIV_ROUND_CLOSEST(hz, 1000) / 1000L;
l = sprintf (buf, "%ld", n);
hz -= n * 1000000L;
- m = DIV_ROUND(hz, 1000L);
+ m = DIV_ROUND_CLOSEST(hz, 1000L);
if (m != 0)
sprintf (buf + l, ".%03ld", m);
return (buf);
#include <div64.h>
#define noinline __attribute__((noinline))
-/* some reluctance to put this into a new limits.h, so it is here */
-#define INT_MAX ((int)(~0U>>1))
-
unsigned long simple_strtoul(const char *cp, char **endp,
unsigned int base)
{
static char *pointer(const char *fmt, char *buf, char *end, void *ptr,
int field_width, int precision, int flags)
{
+ u64 num = (uintptr_t)ptr;
+
/*
* Being a boot loader, we explicitly allow pointers to
* (physical) address null.
#ifdef CONFIG_CMD_NET
switch (*fmt) {
+ case 'a':
+ flags |= SPECIAL | ZEROPAD;
+
+ switch (fmt[1]) {
+ case 'p':
+ default:
+ field_width = sizeof(phys_addr_t) * 2 + 2;
+ num = *(phys_addr_t *)ptr;
+ break;
+ }
+ break;
case 'm':
flags |= SPECIAL;
/* Fallthrough */
field_width = 2*sizeof(void *);
flags |= ZEROPAD;
}
- return number(buf, end, (unsigned long)ptr, 16, field_width,
- precision, flags);
+ return number(buf, end, num, 16, field_width, precision, flags);
}
static int vsnprintf_internal(char *buf, size_t size, const char *fmt,
libs-y += $(CPUDIR)/
-ifdef SOC
-libs-y += $(CPUDIR)/$(SOC)/
-endif
libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/)
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
libs-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ drivers/power/pmic/
libs-$(CONFIG_SPL_MTD_SUPPORT) += drivers/mtd/
-libs-$(if $(CONFIG_CMD_NAND),$(CONFIG_SPL_NAND_SUPPORT)) += drivers/mtd/nand/
+libs-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/
libs-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/
libs-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/
libs-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/
--- /dev/null
+#!/bin/bash
+#
+# (C) Copyright 2014 Suriyan Ramasami
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Invoke this test script from U-Boot base directory as ./test/fs/fs-test.sh
+# It currently tests the fs/sb and native commands for ext4 and fat partitions
+# Expected results are as follows:
+# EXT4 tests:
+# fs-test.sb.ext4.out: Summary: PASS: 17 FAIL: 2
+# fs-test.ext4.out: Summary: PASS: 11 FAIL: 8
+# fs-test.fs.ext4.out: Summary: PASS: 11 FAIL: 8
+# FAT tests:
+# fs-test.sb.fat.out: Summary: PASS: 17 FAIL: 2
+# fs-test.fat.out: Summary: PASS: 19 FAIL: 0
+# fs-test.fs.fat.out: Summary: PASS: 19 FAIL: 0
+# Total Summary: TOTAL PASS: 94 TOTAL FAIL: 20
+
+# pre-requisite binaries list.
+PREREQ_BINS="md5sum mkfs mount umount dd fallocate mkdir"
+
+# All generated output files from this test will be in $OUT_DIR
+# Hence everything is sandboxed.
+OUT_DIR="sandbox/test/fs"
+
+# Location of generated sandbox u-boot
+UBOOT="./sandbox/u-boot"
+
+# Our mount directory will be in the sandbox
+MOUNT_DIR="${OUT_DIR}/mnt"
+
+# The file system image we create will have the $IMG prefix.
+IMG="${OUT_DIR}/3GB"
+
+# $SMALL_FILE is the name of the 1MB file in the file system image
+SMALL_FILE="1MB.file"
+
+# $BIG_FILE is the name of the 2.5GB file in the file system image
+BIG_FILE="2.5GB.file"
+
+# $MD5_FILE will have the expected md5s when we do the test
+# They shall have a suffix which represents their file system (ext4/fat)
+MD5_FILE="${OUT_DIR}/md5s.list"
+
+# $OUT shall be the prefix of the test output. Their suffix will be .out
+OUT="${OUT_DIR}/fs-test"
+
+# Full Path of the 1 MB file that shall be created in the fs image.
+MB1="${MOUNT_DIR}/${SMALL_FILE}"
+GB2p5="${MOUNT_DIR}/${BIG_FILE}"
+
+# ************************
+# * Functions start here *
+# ************************
+
+# Check if the prereq binaries exist, or exit
+function check_prereq() {
+ for prereq in $PREREQ_BINS; do
+ if [ ! -x `which $prereq` ]; then
+ echo "Missing $prereq binary. Exiting!"
+ exit
+ fi
+ done
+
+ # We use /dev/urandom to create files. Check if it exists.
+ if [ ! -c /dev/urandom ]; then
+ echo "Missing character special /dev/urandom. Exiting!"
+ exit
+ fi
+}
+
+# If 1st param is "clean", then clean out the generated files and exit
+function check_clean() {
+ if [ "$1" = "clean" ]; then
+ rm -rf "$OUT_DIR"
+ echo "Cleaned up generated files. Exiting"
+ exit
+ fi
+}
+
+# Generate sandbox U-Boot - gleaned from /test/dm/test-dm.sh
+function compile_sandbox() {
+ unset CROSS_COMPILE
+ NUM_CPUS=$(cat /proc/cpuinfo |grep -c processor)
+ make O=sandbox sandbox_config
+ make O=sandbox -s -j${NUM_CPUS}
+
+ # Check if U-Boot exists
+ if [ ! -x "$UBOOT" ]; then
+ echo "$UBOOT does not exist or is not executable"
+ echo "Build error?"
+ echo "Please run this script as ./test/fs/`basename $0`"
+ exit
+ fi
+}
+
+# Clean out all generated files other than the file system images
+# We save time by not deleting and recreating the file system images
+function prepare_env() {
+ rm -f ${MD5_FILE}.* ${OUT}.*
+ mkdir ${OUT_DIR}
+}
+
+# 1st parameter is the name of the image file to be created
+# 2nd parameter is the filesystem - fat ext4 etc
+# -F cant be used with fat as it means something else.
+function create_image() {
+ # Create image if not already present - saves time, while debugging
+ if [ "$2" = "ext4" ]; then
+ MKFS_OPTION="-F"
+ else
+ MKFS_OPTION=""
+ fi
+ if [ ! -f "$1" ]; then
+ fallocate -l 3G "$1" &> /dev/null
+ mkfs -t "$2" $MKFS_OPTION "$1" &> /dev/null
+ if [ $? -ne 0 -a "$2" = "fat" ]; then
+ # If we fail and we did fat, try vfat.
+ mkfs -t vfat $MKFS_OPTION "$1" &> /dev/null
+ fi
+ fi
+}
+
+# 1st parameter is the FS type: fat/ext4
+# 2nd parameter is the name of small file
+# Returns filename which can be used for fat or ext4 for writing
+function fname_for_write() {
+ case $1 in
+ ext4)
+ # ext4 needs absolute path name of file
+ echo /${2}.w
+ ;;
+
+ *)
+ echo ${2}.w
+ ;;
+ esac
+}
+
+# 1st parameter is image file
+# 2nd parameter is file system type - fat/ext4
+# 3rd parameter is name of small file
+# 4th parameter is name of big file
+# 5th parameter is fs/nonfs/sb - to dictate generic fs commands or
+# otherwise or sb hostfs
+# 6th parameter is the directory path for the files. Its "" for generic
+# fs and ext4/fat and full patch for sb hostfs
+# UBOOT is set in env
+function test_image() {
+ addr="0x01000008"
+ length="0x00100000"
+
+ case "$2" in
+ fat)
+ PREFIX="fat"
+ WRITE="write"
+ ;;
+
+ ext4)
+ PREFIX="ext4"
+ WRITE="write"
+ ;;
+
+ *)
+ echo "Unhandled filesystem $2. Exiting!"
+ exit
+ ;;
+ esac
+
+ case "$5" in
+ fs)
+ PREFIX=""
+ WRITE="save"
+ SUFFIX=" 0:0"
+ ;;
+
+ nonfs)
+ SUFFIX=" 0:0"
+ ;;
+
+ sb)
+ PREFIX="sb "
+ WRITE="save"
+ SUFFIX="fs -"
+ ;;
+
+ *)
+ echo "Unhandled mode $5. Exiting!"
+ exit
+ ;;
+
+ esac
+
+ if [ -z "$6" ]; then
+ FILE_WRITE=`fname_for_write $2 $3`
+ FILE_SMALL=$3
+ FILE_BIG=$4
+ else
+ FILE_WRITE=$6/`fname_for_write $2 $3`
+ FILE_SMALL=$6/$3
+ FILE_BIG=$6/$4
+ fi
+
+ # In u-boot commands, <interface> stands for host or hostfs
+ # hostfs maps to the host fs.
+ # host maps to the "sb bind" that we do
+
+ $UBOOT << EOF
+sb=$5
+setenv bind 'if test "\$sb" != sb; then sb bind 0 "$1"; fi'
+run bind
+# Test Case 1 - ls
+${PREFIX}ls host${SUFFIX} $6
+#
+# We want ${PREFIX}size host 0:0 $3 for host commands and
+# sb size hostfs - $3 for hostfs commands.
+# 1MB is 0x0010 0000
+# Test Case 2 - size of small file
+${PREFIX}size host${SUFFIX} $FILE_SMALL
+printenv filesize
+setenv filesize
+
+# 2.5GB (1024*1024*2500) is 0x9C40 0000
+# Test Case 3 - size of big file
+${PREFIX}size host${SUFFIX} $FILE_BIG
+printenv filesize
+setenv filesize
+
+# Notes about load operation
+# If I use 0x01000000 I get DMA misaligned error message
+# Last two parameters are size and offset.
+
+# Test Case 4a - Read full 1MB of small file
+${PREFIX}load host${SUFFIX} $addr $FILE_SMALL
+printenv filesize
+# Test Case 4b - Read full 1MB of small file
+md5sum $addr \$filesize
+setenv filesize
+
+# Test Case 5a - First 1MB of big file
+${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x0
+printenv filesize
+# Test Case 5b - First 1MB of big file
+md5sum $addr \$filesize
+setenv filesize
+
+# fails for ext as no offset support
+# Test Case 6a - Last 1MB of big file
+${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x9C300000
+printenv filesize
+# Test Case 6b - Last 1MB of big file
+md5sum $addr \$filesize
+setenv filesize
+
+# fails for ext as no offset support
+# Test Case 7a - One from the last 1MB chunk of 2GB
+${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x7FF00000
+printenv filesize
+# Test Case 7b - One from the last 1MB chunk of 2GB
+md5sum $addr \$filesize
+setenv filesize
+
+# fails for ext as no offset support
+# Test Case 8a - One from the start 1MB chunk from 2GB
+${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x80000000
+printenv filesize
+# Test Case 8b - One from the start 1MB chunk from 2GB
+md5sum $addr \$filesize
+setenv filesize
+
+# fails for ext as no offset support
+# Test Case 9a - One 1MB chunk crossing the 2GB boundary
+${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x7FF80000
+printenv filesize
+# Test Case 9b - One 1MB chunk crossing the 2GB boundary
+md5sum $addr \$filesize
+setenv filesize
+
+# Generic failure case
+# Test Case 10 - 2MB chunk from the last 1MB of big file
+${PREFIX}load host${SUFFIX} $addr $FILE_BIG 0x00200000 0x9C300000
+printenv filesize
+#
+
+# Read 1MB from small file
+${PREFIX}load host${SUFFIX} $addr $FILE_SMALL
+# Write it back to test the writes
+# Test Case 11a - Check that the write succeeded
+${PREFIX}${WRITE} host${SUFFIX} $addr $FILE_WRITE \$filesize
+mw.b $addr 00 100
+${PREFIX}load host${SUFFIX} $addr $FILE_WRITE
+# Test Case 11b - Check md5 of written to is same as the one read from
+md5sum $addr \$filesize
+setenv filesize
+#
+reset
+
+EOF
+}
+
+# 1st argument is the name of the image file.
+# 2nd argument is the file where we generate the md5s of the files
+# generated with the appropriate start and length that we use to test.
+# It creates the necessary files in the image to test.
+# $GB2p5 is the path of the big file (2.5 GB)
+# $MB1 is the path of the small file (1 MB)
+# $MOUNT_DIR is the path we can use to mount the image file.
+function create_files() {
+ # Mount the image so we can populate it.
+ mkdir -p "$MOUNT_DIR"
+ sudo mount -o loop,rw "$1" "$MOUNT_DIR"
+
+ # Create big file in this image.
+ # Note that we work only on the start 1MB, couple MBs in the 2GB range
+ # and the last 1 MB of the huge 2.5GB file.
+ # So, just put random values only in those areas.
+ if [ ! -f "${GB2p5}" ]; then
+ sudo dd if=/dev/urandom of="${GB2p5}" bs=1M count=1 \
+ &> /dev/null
+ sudo dd if=/dev/urandom of="${GB2p5}" bs=1M count=2 seek=2047 \
+ &> /dev/null
+ sudo dd if=/dev/urandom of="${GB2p5}" bs=1M count=1 seek=2499 \
+ &> /dev/null
+ fi
+
+ # Create a small file in this image.
+ if [ ! -f "${MB1}" ]; then
+ sudo dd if=/dev/urandom of="${MB1}" bs=1M count=1 \
+ &> /dev/null
+ fi
+
+ # Delete the small file which possibly is written as part of a
+ # previous test.
+ sudo rm -f "${MB1}.w"
+
+ # Generate the md5sums of reads that we will test against small file
+ dd if="${MB1}" bs=1M skip=0 count=1 2> /dev/null | md5sum > "$2"
+
+ # Generate the md5sums of reads that we will test against big file
+ # One from beginning of file.
+ dd if="${GB2p5}" bs=1M skip=0 count=1 \
+ 2> /dev/null | md5sum >> "$2"
+
+ # One from end of file.
+ dd if="${GB2p5}" bs=1M skip=2499 count=1 \
+ 2> /dev/null | md5sum >> "$2"
+
+ # One from the last 1MB chunk of 2GB
+ dd if="${GB2p5}" bs=1M skip=2047 count=1 \
+ 2> /dev/null | md5sum >> "$2"
+
+ # One from the start 1MB chunk from 2GB
+ dd if="${GB2p5}" bs=1M skip=2048 count=1 \
+ 2> /dev/null | md5sum >> "$2"
+
+ # One 1MB chunk crossing the 2GB boundary
+ dd if="${GB2p5}" bs=512K skip=4095 count=2 \
+ 2> /dev/null | md5sum >> "$2"
+
+ sync
+ sudo umount "$MOUNT_DIR"
+ rmdir "$MOUNT_DIR"
+}
+
+# 1st parameter is the text to print
+# if $? is 0 its a pass, else a fail
+# As a side effect it shall update env variable PASS and FAIL
+function pass_fail() {
+ if [ $? -eq 0 ]; then
+ echo pass - "$1"
+ PASS=$((PASS + 1))
+ else
+ echo FAIL - "$1"
+ FAIL=$((FAIL + 1))
+ fi
+}
+
+# 1st parameter is the string which leads to an md5 generation
+# 2nd parameter is the file we grep, for that string
+# 3rd parameter is the name of the file which has md5s in it
+# 4th parameter is the line # in the md5 file that we match it against
+# This function checks if the md5 of the file in the sandbox matches
+# that calculated while generating the file
+# 5th parameter is the string to print with the result
+check_md5() {
+ # md5sum in u-boot has output of form:
+ # md5 for 01000008 ... 01100007 ==> <md5>
+ # the 7th field is the actual md5
+ md5_src=`grep -A3 "$1" "$2" | grep "md5 for"`
+ md5_src=($md5_src)
+ md5_src=${md5_src[6]}
+
+ # The md5 list, each line is of the form:
+ # - <md5>
+ # the 2nd field is the actual md5
+ md5_dst=`sed -n $4p $3`
+ md5_dst=($md5_dst)
+ md5_dst=${md5_dst[0]}
+
+ # For a pass they should match.
+ [ "$md5_src" = "$md5_dst" ]
+ pass_fail "$5"
+}
+
+# 1st parameter is the name of the output file to check
+# 2nd parameter is the name of the file containing the md5 expected
+# 3rd parameter is the name of the small file
+# 4th parameter is the name of the big file
+# 5th paramter is the name of the written file
+# This function checks the output file for correct results.
+function check_results() {
+ echo "** Start $1"
+
+ PASS=0
+ FAIL=0
+
+ # Check if the ls is showing correct results for 2.5 gb file
+ grep -A6 "Test Case 1 " "$1" | egrep -iq "2621440000 *$4"
+ pass_fail "TC1: ls of $4"
+
+ # Check if the ls is showing correct results for 1 mb file
+ grep -A6 "Test Case 1 " "$1" | egrep -iq "1048576 *$3"
+ pass_fail "TC1: ls of $3"
+
+ # Check size command on 1MB.file
+ egrep -A3 "Test Case 2 " "$1" | grep -q "filesize=100000"
+ pass_fail "TC2: size of $3"
+
+ # Check size command on 2.5GB.file
+ egrep -A3 "Test Case 3 " "$1" | grep -q "filesize=9c400000"
+ pass_fail "TC3: size of $4"
+
+ # Check read full mb of 1MB.file
+ grep -A6 "Test Case 4a " "$1" | grep -q "filesize=100000"
+ pass_fail "TC4: load of $3 size"
+ check_md5 "Test Case 4b " "$1" "$2" 1 "TC4: load from $3"
+
+ # Check first mb of 2.5GB.file
+ grep -A6 "Test Case 5a " "$1" | grep -q "filesize=100000"
+ pass_fail "TC5: load of 1st MB from $4 size"
+ check_md5 "Test Case 5b " "$1" "$2" 2 "TC5: load of 1st MB from $4"
+
+ # Check last mb of 2.5GB.file
+ grep -A6 "Test Case 6a " "$1" | grep -q "filesize=100000"
+ pass_fail "TC6: load of last MB from $4 size"
+ check_md5 "Test Case 6b " "$1" "$2" 3 "TC6: load of last MB from $4"
+
+ # Check last 1mb chunk of 2gb from 2.5GB file
+ grep -A6 "Test Case 7a " "$1" | grep -q "filesize=100000"
+ pass_fail "TC7: load of last 1mb chunk of 2GB from $4 size"
+ check_md5 "Test Case 7b " "$1" "$2" 4 \
+ "TC7: load of last 1mb chunk of 2GB from $4"
+
+ # Check first 1mb chunk after 2gb from 2.5GB file
+ grep -A6 "Test Case 8a " "$1" | grep -q "filesize=100000"
+ pass_fail "TC8: load 1st MB chunk after 2GB from $4 size"
+ check_md5 "Test Case 8b " "$1" "$2" 5 \
+ "TC8: load 1st MB chunk after 2GB from $4"
+
+ # Check 1mb chunk crossing the 2gb boundary from 2.5GB file
+ grep -A6 "Test Case 9a " "$1" | grep -q "filesize=100000"
+ pass_fail "TC9: load 1MB chunk crossing 2GB boundary from $4 size"
+ check_md5 "Test Case 9b " "$1" "$2" 6 \
+ "TC9: load 1MB chunk crossing 2GB boundary from $4"
+
+ # Check 2mb chunk from the last 1MB of 2.5GB file - generic failure case
+ grep -A6 "Test Case 10 " "$1" | grep -q 'Error: "filesize" not defined'
+ pass_fail "TC10: load 2MB from the last 1MB of $4 - generic fail case"
+
+ # Check 1mb chunk write
+ grep -A3 "Test Case 11a " "$1" | \
+ egrep -q '1048576 bytes written|update journal'
+ pass_fail "TC11: 1MB write to $5 - write succeeded"
+ check_md5 "Test Case 11b " "$1" "$2" 1 \
+ "TC11: 1MB write to $5 - content verified"
+ echo "** End $1"
+}
+
+# Takes in one parameter which is "fs" or "nonfs", which then dictates
+# if a fs test (size/load/save) or a nonfs test (fatread/extread) needs to
+# be performed.
+function test_fs_nonfs() {
+ echo "Creating files in $fs image if not already present."
+ create_files $IMAGE $MD5_FILE_FS
+
+ OUT_FILE="${OUT}.fs.${fs}.out"
+ test_image $IMAGE $fs $SMALL_FILE $BIG_FILE $1 "" \
+ > ${OUT_FILE}
+ check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE \
+ $WRITE_FILE
+ TOTAL_FAIL=$((TOTAL_FAIL + FAIL))
+ TOTAL_PASS=$((TOTAL_PASS + PASS))
+ echo "Summary: PASS: $PASS FAIL: $FAIL"
+ echo "--------------------------------------------"
+}
+
+# ********************
+# * End of functions *
+# ********************
+
+check_clean "$1"
+check_prereq
+compile_sandbox
+prepare_env
+
+# Track TOTAL_FAIL and TOTAL_PASS
+TOTAL_FAIL=0
+TOTAL_PASS=0
+
+# In each loop, for a given file system image, we test both the
+# fs command, like load/size/write, the file system specific command
+# like: ext4load/ext4size/ext4write and the sb load/ls/save commands.
+for fs in ext4 fat; do
+
+ echo "Creating $fs image if not already present."
+ IMAGE=${IMG}.${fs}.img
+ MD5_FILE_FS="${MD5_FILE}.${fs}"
+ create_image $IMAGE $fs
+
+ # sb commands test
+ echo "Creating files in $fs image if not already present."
+ create_files $IMAGE $MD5_FILE_FS
+
+ # Lets mount the image and test sb hostfs commands
+ mkdir -p "$MOUNT_DIR"
+ if [ "$fs" = "fat" ]; then
+ uid="uid=`id -u`"
+ else
+ uid=""
+ fi
+ sudo mount -o loop,rw,$uid "$IMAGE" "$MOUNT_DIR"
+ sudo chmod 777 "$MOUNT_DIR"
+
+ OUT_FILE="${OUT}.sb.${fs}.out"
+ test_image $IMAGE $fs $SMALL_FILE $BIG_FILE sb `pwd`/$MOUNT_DIR \
+ > ${OUT_FILE}
+ sudo umount "$MOUNT_DIR"
+ rmdir "$MOUNT_DIR"
+
+ check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE \
+ $WRITE_FILE
+ TOTAL_FAIL=$((TOTAL_FAIL + FAIL))
+ TOTAL_PASS=$((TOTAL_PASS + PASS))
+ echo "Summary: PASS: $PASS FAIL: $FAIL"
+ echo "--------------------------------------------"
+
+ test_fs_nonfs nonfs
+ test_fs_nonfs fs
+done
+
+echo "Total Summary: TOTAL PASS: $TOTAL_PASS TOTAL FAIL: $TOTAL_FAIL"
+echo "--------------------------------------------"
+if [ $TOTAL_FAIL -eq 0 ]; then
+ echo "PASSED"
+ exit 0
+else
+ echo "FAILED"
+ exit 1
+fi
hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl
HOSTCFLAGS_mkexynosspl.o := -pedantic
+hostprogs-$(CONFIG_X86) += ifdtool
+
hostprogs-$(CONFIG_MX23) += mxsboot
hostprogs-$(CONFIG_MX28) += mxsboot
HOSTCFLAGS_mxsboot.o := -pedantic
--- /dev/null
+/*
+ * ifdtool - Manage Intel Firmware Descriptor information
+ *
+ * Copyright 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * From Coreboot project, but it got a serious code clean-up
+ * and a few new features
+ */
+
+#include <assert.h>
+#include <fcntl.h>
+#include <getopt.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include "ifdtool.h"
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define debug(fmt, args...) printf(fmt, ##args)
+#else
+#define debug(fmt, args...)
+#endif
+
+#define FD_SIGNATURE 0x0FF0A55A
+#define FLREG_BASE(reg) ((reg & 0x00000fff) << 12);
+#define FLREG_LIMIT(reg) (((reg & 0x0fff0000) >> 4) | 0xfff);
+
+/**
+ * find_fd() - Find the flash description in the ROM image
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ * @return pointer to structure, or NULL if not found
+ */
+static struct fdbar_t *find_fd(char *image, int size)
+{
+ uint32_t *ptr, *end;
+
+ /* Scan for FD signature */
+ for (ptr = (uint32_t *)image, end = ptr + size / 4; ptr < end; ptr++) {
+ if (*ptr == FD_SIGNATURE)
+ break;
+ }
+
+ if (ptr == end) {
+ printf("No Flash Descriptor found in this image\n");
+ return NULL;
+ }
+
+ debug("Found Flash Descriptor signature at 0x%08x\n", i);
+
+ return (struct fdbar_t *)ptr;
+}
+
+/**
+ * get_region() - Get information about the selected region
+ *
+ * @frba: Flash region list
+ * @region_type: Type of region (0..MAX_REGIONS-1)
+ * @region: Region information is written here
+ * @return 0 if OK, else -ve
+ */
+static int get_region(struct frba_t *frba, int region_type,
+ struct region_t *region)
+{
+ if (region_type >= MAX_REGIONS) {
+ fprintf(stderr, "Invalid region type.\n");
+ return -1;
+ }
+
+ region->base = FLREG_BASE(frba->flreg[region_type]);
+ region->limit = FLREG_LIMIT(frba->flreg[region_type]);
+ region->size = region->limit - region->base + 1;
+
+ return 0;
+}
+
+static const char *region_name(int region_type)
+{
+ static const char *const regions[] = {
+ "Flash Descriptor",
+ "BIOS",
+ "Intel ME",
+ "GbE",
+ "Platform Data"
+ };
+
+ assert(region_type < MAX_REGIONS);
+
+ return regions[region_type];
+}
+
+static const char *region_filename(int region_type)
+{
+ static const char *const region_filenames[] = {
+ "flashregion_0_flashdescriptor.bin",
+ "flashregion_1_bios.bin",
+ "flashregion_2_intel_me.bin",
+ "flashregion_3_gbe.bin",
+ "flashregion_4_platform_data.bin"
+ };
+
+ assert(region_type < MAX_REGIONS);
+
+ return region_filenames[region_type];
+}
+
+static int dump_region(int num, struct frba_t *frba)
+{
+ struct region_t region;
+ int ret;
+
+ ret = get_region(frba, num, ®ion);
+ if (ret)
+ return ret;
+
+ printf(" Flash Region %d (%s): %08x - %08x %s\n",
+ num, region_name(num), region.base, region.limit,
+ region.size < 1 ? "(unused)" : "");
+
+ return ret;
+}
+
+static void dump_frba(struct frba_t *frba)
+{
+ int i;
+
+ printf("Found Region Section\n");
+ for (i = 0; i < MAX_REGIONS; i++) {
+ printf("FLREG%d: 0x%08x\n", i, frba->flreg[i]);
+ dump_region(i, frba);
+ }
+}
+
+static void decode_spi_frequency(unsigned int freq)
+{
+ switch (freq) {
+ case SPI_FREQUENCY_20MHZ:
+ printf("20MHz");
+ break;
+ case SPI_FREQUENCY_33MHZ:
+ printf("33MHz");
+ break;
+ case SPI_FREQUENCY_50MHZ:
+ printf("50MHz");
+ break;
+ default:
+ printf("unknown<%x>MHz", freq);
+ }
+}
+
+static void decode_component_density(unsigned int density)
+{
+ switch (density) {
+ case COMPONENT_DENSITY_512KB:
+ printf("512KiB");
+ break;
+ case COMPONENT_DENSITY_1MB:
+ printf("1MiB");
+ break;
+ case COMPONENT_DENSITY_2MB:
+ printf("2MiB");
+ break;
+ case COMPONENT_DENSITY_4MB:
+ printf("4MiB");
+ break;
+ case COMPONENT_DENSITY_8MB:
+ printf("8MiB");
+ break;
+ case COMPONENT_DENSITY_16MB:
+ printf("16MiB");
+ break;
+ default:
+ printf("unknown<%x>MiB", density);
+ }
+}
+
+static void dump_fcba(struct fcba_t *fcba)
+{
+ printf("\nFound Component Section\n");
+ printf("FLCOMP 0x%08x\n", fcba->flcomp);
+ printf(" Dual Output Fast Read Support: %ssupported\n",
+ (fcba->flcomp & (1 << 30)) ? "" : "not ");
+ printf(" Read ID/Read Status Clock Frequency: ");
+ decode_spi_frequency((fcba->flcomp >> 27) & 7);
+ printf("\n Write/Erase Clock Frequency: ");
+ decode_spi_frequency((fcba->flcomp >> 24) & 7);
+ printf("\n Fast Read Clock Frequency: ");
+ decode_spi_frequency((fcba->flcomp >> 21) & 7);
+ printf("\n Fast Read Support: %ssupported",
+ (fcba->flcomp & (1 << 20)) ? "" : "not ");
+ printf("\n Read Clock Frequency: ");
+ decode_spi_frequency((fcba->flcomp >> 17) & 7);
+ printf("\n Component 2 Density: ");
+ decode_component_density((fcba->flcomp >> 3) & 7);
+ printf("\n Component 1 Density: ");
+ decode_component_density(fcba->flcomp & 7);
+ printf("\n");
+ printf("FLILL 0x%08x\n", fcba->flill);
+ printf(" Invalid Instruction 3: 0x%02x\n",
+ (fcba->flill >> 24) & 0xff);
+ printf(" Invalid Instruction 2: 0x%02x\n",
+ (fcba->flill >> 16) & 0xff);
+ printf(" Invalid Instruction 1: 0x%02x\n",
+ (fcba->flill >> 8) & 0xff);
+ printf(" Invalid Instruction 0: 0x%02x\n",
+ fcba->flill & 0xff);
+ printf("FLPB 0x%08x\n", fcba->flpb);
+ printf(" Flash Partition Boundary Address: 0x%06x\n\n",
+ (fcba->flpb & 0xfff) << 12);
+}
+
+static void dump_fpsba(struct fpsba_t *fpsba)
+{
+ int i;
+
+ printf("Found PCH Strap Section\n");
+ for (i = 0; i < MAX_STRAPS; i++)
+ printf("PCHSTRP%-2d: 0x%08x\n", i, fpsba->pchstrp[i]);
+}
+
+static const char *get_enabled(int flag)
+{
+ return flag ? "enabled" : "disabled";
+}
+
+static void decode_flmstr(uint32_t flmstr)
+{
+ printf(" Platform Data Region Write Access: %s\n",
+ get_enabled(flmstr & (1 << 28)));
+ printf(" GbE Region Write Access: %s\n",
+ get_enabled(flmstr & (1 << 27)));
+ printf(" Intel ME Region Write Access: %s\n",
+ get_enabled(flmstr & (1 << 26)));
+ printf(" Host CPU/BIOS Region Write Access: %s\n",
+ get_enabled(flmstr & (1 << 25)));
+ printf(" Flash Descriptor Write Access: %s\n",
+ get_enabled(flmstr & (1 << 24)));
+
+ printf(" Platform Data Region Read Access: %s\n",
+ get_enabled(flmstr & (1 << 20)));
+ printf(" GbE Region Read Access: %s\n",
+ get_enabled(flmstr & (1 << 19)));
+ printf(" Intel ME Region Read Access: %s\n",
+ get_enabled(flmstr & (1 << 18)));
+ printf(" Host CPU/BIOS Region Read Access: %s\n",
+ get_enabled(flmstr & (1 << 17)));
+ printf(" Flash Descriptor Read Access: %s\n",
+ get_enabled(flmstr & (1 << 16)));
+
+ printf(" Requester ID: 0x%04x\n\n",
+ flmstr & 0xffff);
+}
+
+static void dump_fmba(struct fmba_t *fmba)
+{
+ printf("Found Master Section\n");
+ printf("FLMSTR1: 0x%08x (Host CPU/BIOS)\n", fmba->flmstr1);
+ decode_flmstr(fmba->flmstr1);
+ printf("FLMSTR2: 0x%08x (Intel ME)\n", fmba->flmstr2);
+ decode_flmstr(fmba->flmstr2);
+ printf("FLMSTR3: 0x%08x (GbE)\n", fmba->flmstr3);
+ decode_flmstr(fmba->flmstr3);
+}
+
+static void dump_fmsba(struct fmsba_t *fmsba)
+{
+ int i;
+
+ printf("Found Processor Strap Section\n");
+ for (i = 0; i < 4; i++)
+ printf("????: 0x%08x\n", fmsba->data[0]);
+}
+
+static void dump_jid(uint32_t jid)
+{
+ printf(" SPI Component Device ID 1: 0x%02x\n",
+ (jid >> 16) & 0xff);
+ printf(" SPI Component Device ID 0: 0x%02x\n",
+ (jid >> 8) & 0xff);
+ printf(" SPI Component Vendor ID: 0x%02x\n",
+ jid & 0xff);
+}
+
+static void dump_vscc(uint32_t vscc)
+{
+ printf(" Lower Erase Opcode: 0x%02x\n",
+ vscc >> 24);
+ printf(" Lower Write Enable on Write Status: 0x%02x\n",
+ vscc & (1 << 20) ? 0x06 : 0x50);
+ printf(" Lower Write Status Required: %s\n",
+ vscc & (1 << 19) ? "Yes" : "No");
+ printf(" Lower Write Granularity: %d bytes\n",
+ vscc & (1 << 18) ? 64 : 1);
+ printf(" Lower Block / Sector Erase Size: ");
+ switch ((vscc >> 16) & 0x3) {
+ case 0:
+ printf("256 Byte\n");
+ break;
+ case 1:
+ printf("4KB\n");
+ break;
+ case 2:
+ printf("8KB\n");
+ break;
+ case 3:
+ printf("64KB\n");
+ break;
+ }
+
+ printf(" Upper Erase Opcode: 0x%02x\n",
+ (vscc >> 8) & 0xff);
+ printf(" Upper Write Enable on Write Status: 0x%02x\n",
+ vscc & (1 << 4) ? 0x06 : 0x50);
+ printf(" Upper Write Status Required: %s\n",
+ vscc & (1 << 3) ? "Yes" : "No");
+ printf(" Upper Write Granularity: %d bytes\n",
+ vscc & (1 << 2) ? 64 : 1);
+ printf(" Upper Block / Sector Erase Size: ");
+ switch (vscc & 0x3) {
+ case 0:
+ printf("256 Byte\n");
+ break;
+ case 1:
+ printf("4KB\n");
+ break;
+ case 2:
+ printf("8KB\n");
+ break;
+ case 3:
+ printf("64KB\n");
+ break;
+ }
+}
+
+static void dump_vtba(struct vtba_t *vtba, int vtl)
+{
+ int i;
+ int num = (vtl >> 1) < 8 ? (vtl >> 1) : 8;
+
+ printf("ME VSCC table:\n");
+ for (i = 0; i < num; i++) {
+ printf(" JID%d: 0x%08x\n", i, vtba->entry[i].jid);
+ dump_jid(vtba->entry[i].jid);
+ printf(" VSCC%d: 0x%08x\n", i, vtba->entry[i].vscc);
+ dump_vscc(vtba->entry[i].vscc);
+ }
+ printf("\n");
+}
+
+static void dump_oem(uint8_t *oem)
+{
+ int i, j;
+ printf("OEM Section:\n");
+ for (i = 0; i < 4; i++) {
+ printf("%02x:", i << 4);
+ for (j = 0; j < 16; j++)
+ printf(" %02x", oem[(i<<4)+j]);
+ printf("\n");
+ }
+ printf("\n");
+}
+
+/**
+ * dump_fd() - Display a dump of the full flash description
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ * @return 0 if OK, -1 on error
+ */
+static int dump_fd(char *image, int size)
+{
+ struct fdbar_t *fdb = find_fd(image, size);
+
+ if (!fdb)
+ return -1;
+
+ printf("FLMAP0: 0x%08x\n", fdb->flmap0);
+ printf(" NR: %d\n", (fdb->flmap0 >> 24) & 7);
+ printf(" FRBA: 0x%x\n", ((fdb->flmap0 >> 16) & 0xff) << 4);
+ printf(" NC: %d\n", ((fdb->flmap0 >> 8) & 3) + 1);
+ printf(" FCBA: 0x%x\n", ((fdb->flmap0) & 0xff) << 4);
+
+ printf("FLMAP1: 0x%08x\n", fdb->flmap1);
+ printf(" ISL: 0x%02x\n", (fdb->flmap1 >> 24) & 0xff);
+ printf(" FPSBA: 0x%x\n", ((fdb->flmap1 >> 16) & 0xff) << 4);
+ printf(" NM: %d\n", (fdb->flmap1 >> 8) & 3);
+ printf(" FMBA: 0x%x\n", ((fdb->flmap1) & 0xff) << 4);
+
+ printf("FLMAP2: 0x%08x\n", fdb->flmap2);
+ printf(" PSL: 0x%04x\n", (fdb->flmap2 >> 8) & 0xffff);
+ printf(" FMSBA: 0x%x\n", ((fdb->flmap2) & 0xff) << 4);
+
+ printf("FLUMAP1: 0x%08x\n", fdb->flumap1);
+ printf(" Intel ME VSCC Table Length (VTL): %d\n",
+ (fdb->flumap1 >> 8) & 0xff);
+ printf(" Intel ME VSCC Table Base Address (VTBA): 0x%06x\n\n",
+ (fdb->flumap1 & 0xff) << 4);
+ dump_vtba((struct vtba_t *)
+ (image + ((fdb->flumap1 & 0xff) << 4)),
+ (fdb->flumap1 >> 8) & 0xff);
+ dump_oem((uint8_t *)image + 0xf00);
+ dump_frba((struct frba_t *)(image + (((fdb->flmap0 >> 16) & 0xff)
+ << 4)));
+ dump_fcba((struct fcba_t *)(image + (((fdb->flmap0) & 0xff) << 4)));
+ dump_fpsba((struct fpsba_t *)
+ (image + (((fdb->flmap1 >> 16) & 0xff) << 4)));
+ dump_fmba((struct fmba_t *)(image + (((fdb->flmap1) & 0xff) << 4)));
+ dump_fmsba((struct fmsba_t *)(image + (((fdb->flmap2) & 0xff) << 4)));
+
+ return 0;
+}
+
+/**
+ * write_regions() - Write each region from an image to its own file
+ *
+ * The filename to use in each case is fixed - see region_filename()
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ * @return 0 if OK, -ve on error
+ */
+static int write_regions(char *image, int size)
+{
+ struct fdbar_t *fdb;
+ struct frba_t *frba;
+ int ret = 0;
+ int i;
+
+ fdb = find_fd(image, size);
+ if (!fdb)
+ return -1;
+
+ frba = (struct frba_t *)(image + (((fdb->flmap0 >> 16) & 0xff) << 4));
+
+ for (i = 0; i < MAX_REGIONS; i++) {
+ struct region_t region;
+ int region_fd;
+
+ ret = get_region(frba, i, ®ion);
+ if (ret)
+ return ret;
+ dump_region(i, frba);
+ if (region.size == 0)
+ continue;
+ region_fd = open(region_filename(i),
+ O_WRONLY | O_CREAT | O_TRUNC, S_IRUSR |
+ S_IWUSR | S_IRGRP | S_IROTH);
+ if (write(region_fd, image + region.base, region.size) !=
+ region.size) {
+ perror("Error while writing");
+ ret = -1;
+ }
+ close(region_fd);
+ }
+
+ return ret;
+}
+
+/**
+ * write_image() - Write the image to a file
+ *
+ * @filename: Filename to use for the image
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ * @return 0 if OK, -ve on error
+ */
+static int write_image(char *filename, char *image, int size)
+{
+ int new_fd;
+
+ debug("Writing new image to %s\n", filename);
+
+ new_fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, S_IRUSR |
+ S_IWUSR | S_IRGRP | S_IROTH);
+ if (write(new_fd, image, size) != size) {
+ perror("Error while writing");
+ return -1;
+ }
+ close(new_fd);
+
+ return 0;
+}
+
+/**
+ * set_spi_frequency() - Set the SPI frequency to use when booting
+ *
+ * Several frequencies are supported, some of which work with fast devices.
+ * For SPI emulators, the slowest (SPI_FREQUENCY_20MHZ) is often used. The
+ * Intel boot system uses this information somehow on boot.
+ *
+ * The image is updated with the supplied value
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ * @freq: SPI frequency to use
+ */
+static void set_spi_frequency(char *image, int size, enum spi_frequency freq)
+{
+ struct fdbar_t *fdb = find_fd(image, size);
+ struct fcba_t *fcba;
+
+ fcba = (struct fcba_t *)(image + (((fdb->flmap0) & 0xff) << 4));
+
+ /* clear bits 21-29 */
+ fcba->flcomp &= ~0x3fe00000;
+ /* Read ID and Read Status Clock Frequency */
+ fcba->flcomp |= freq << 27;
+ /* Write and Erase Clock Frequency */
+ fcba->flcomp |= freq << 24;
+ /* Fast Read Clock Frequency */
+ fcba->flcomp |= freq << 21;
+}
+
+/**
+ * set_em100_mode() - Set a SPI frequency that will work with Dediprog EM100
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ */
+static void set_em100_mode(char *image, int size)
+{
+ struct fdbar_t *fdb = find_fd(image, size);
+ struct fcba_t *fcba;
+
+ fcba = (struct fcba_t *)(image + (((fdb->flmap0) & 0xff) << 4));
+ fcba->flcomp &= ~(1 << 30);
+ set_spi_frequency(image, size, SPI_FREQUENCY_20MHZ);
+}
+
+/**
+ * lock_descriptor() - Lock the NE descriptor so it cannot be updated
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ */
+static void lock_descriptor(char *image, int size)
+{
+ struct fdbar_t *fdb = find_fd(image, size);
+ struct fmba_t *fmba;
+
+ /*
+ * TODO: Dynamically take Platform Data Region and GbE Region into
+ * account.
+ */
+ fmba = (struct fmba_t *)(image + (((fdb->flmap1) & 0xff) << 4));
+ fmba->flmstr1 = 0x0a0b0000;
+ fmba->flmstr2 = 0x0c0d0000;
+ fmba->flmstr3 = 0x08080118;
+}
+
+/**
+ * unlock_descriptor() - Lock the NE descriptor so it can be updated
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ */
+static void unlock_descriptor(char *image, int size)
+{
+ struct fdbar_t *fdb = find_fd(image, size);
+ struct fmba_t *fmba;
+
+ fmba = (struct fmba_t *)(image + (((fdb->flmap1) & 0xff) << 4));
+ fmba->flmstr1 = 0xffff0000;
+ fmba->flmstr2 = 0xffff0000;
+ fmba->flmstr3 = 0x08080118;
+}
+
+/**
+ * open_for_read() - Open a file for reading
+ *
+ * @fname: Filename to open
+ * @sizep: Returns file size in bytes
+ * @return 0 if OK, -1 on error
+ */
+int open_for_read(const char *fname, int *sizep)
+{
+ int fd = open(fname, O_RDONLY);
+ struct stat buf;
+
+ if (fd == -1) {
+ perror("Could not open file");
+ return -1;
+ }
+ if (fstat(fd, &buf) == -1) {
+ perror("Could not stat file");
+ return -1;
+ }
+ *sizep = buf.st_size;
+ debug("File %s is %d bytes\n", fname, *sizep);
+
+ return fd;
+}
+
+/**
+ * inject_region() - Add a file to an image region
+ *
+ * This puts a file into a particular region of the flash. Several pre-defined
+ * regions are used.
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ * @region_type: Region where the file should be added
+ * @region_fname: Filename to add to the image
+ * @return 0 if OK, -ve on error
+ */
+int inject_region(char *image, int size, int region_type, char *region_fname)
+{
+ struct fdbar_t *fdb = find_fd(image, size);
+ struct region_t region;
+ struct frba_t *frba;
+ int region_size;
+ int offset = 0;
+ int region_fd;
+ int ret;
+
+ if (!fdb)
+ exit(EXIT_FAILURE);
+ frba = (struct frba_t *)(image + (((fdb->flmap0 >> 16) & 0xff) << 4));
+
+ ret = get_region(frba, region_type, ®ion);
+ if (ret)
+ return -1;
+ if (region.size <= 0xfff) {
+ fprintf(stderr, "Region %s is disabled in target. Not injecting.\n",
+ region_name(region_type));
+ return -1;
+ }
+
+ region_fd = open_for_read(region_fname, ®ion_size);
+ if (region_fd < 0)
+ return region_fd;
+
+ if ((region_size > region.size) ||
+ ((region_type != 1) && (region_size > region.size))) {
+ fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x) bytes. Not injecting.\n",
+ region_name(region_type), region.size,
+ region.size, region_size, region_size);
+ return -1;
+ }
+
+ if ((region_type == 1) && (region_size < region.size)) {
+ fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x) bytes. Padding before injecting.\n",
+ region_name(region_type), region.size,
+ region.size, region_size, region_size);
+ offset = region.size - region_size;
+ memset(image + region.base, 0xff, offset);
+ }
+
+ if (size < region.base + offset + region_size) {
+ fprintf(stderr, "Output file is too small. (%d < %d)\n",
+ size, region.base + offset + region_size);
+ return -1;
+ }
+
+ if (read(region_fd, image + region.base + offset, region_size)
+ != region_size) {
+ perror("Could not read file");
+ return -1;
+ }
+
+ close(region_fd);
+
+ debug("Adding %s as the %s section\n", region_fname,
+ region_name(region_type));
+
+ return 0;
+}
+
+/**
+ * write_data() - Write some raw data into a region
+ *
+ * This puts a file into a particular place in the flash, ignoring the
+ * regions. Be careful not to overwrite something important.
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ * @addr: x86 ROM address to put file. The ROM ends at
+ * 0xffffffff so use an address relative to that. For an
+ * 8MB ROM the start address is 0xfff80000.
+ * @write_fname: Filename to add to the image
+ * @return 0 if OK, -ve on error
+ */
+static int write_data(char *image, int size, unsigned int addr,
+ const char *write_fname)
+{
+ int write_fd, write_size;
+ int offset;
+
+ write_fd = open_for_read(write_fname, &write_size);
+ if (write_fd < 0)
+ return write_fd;
+
+ offset = addr + size;
+ debug("Writing %s to offset %#x\n", write_fname, offset);
+
+ if (offset < 0 || offset + write_size > size) {
+ fprintf(stderr, "Output file is too small. (%d < %d)\n",
+ size, offset + write_size);
+ return -1;
+ }
+
+ if (read(write_fd, image + offset, write_size) != write_size) {
+ perror("Could not read file");
+ return -1;
+ }
+
+ close(write_fd);
+
+ return 0;
+}
+
+static void print_version(void)
+{
+ printf("ifdtool v%s -- ", IFDTOOL_VERSION);
+ printf("Copyright (C) 2014 Google Inc.\n\n");
+ printf("SPDX-License-Identifier: GPL-2.0+\n");
+}
+
+static void print_usage(const char *name)
+{
+ printf("usage: %s [-vhdix?] <filename> [<outfile>]\n", name);
+ printf("\n"
+ " -d | --dump: dump intel firmware descriptor\n"
+ " -x | --extract: extract intel fd modules\n"
+ " -i | --inject <region>:<module> inject file <module> into region <region>\n"
+ " -w | --write <addr>:<file> write file to appear at memory address <addr>\n"
+ " -s | --spifreq <20|33|50> set the SPI frequency\n"
+ " -e | --em100 set SPI frequency to 20MHz and disable\n"
+ " Dual Output Fast Read Support\n"
+ " -l | --lock Lock firmware descriptor and ME region\n"
+ " -u | --unlock Unlock firmware descriptor and ME region\n"
+ " -r | --romsize Specify ROM size\n"
+ " -D | --write-descriptor <file> Write descriptor at base\n"
+ " -c | --create Create a new empty image\n"
+ " -v | --version: print the version\n"
+ " -h | --help: print this help\n\n"
+ "<region> is one of Descriptor, BIOS, ME, GbE, Platform\n"
+ "\n");
+}
+
+/**
+ * get_two_words() - Convert a string into two words separated by :
+ *
+ * The supplied string is split at ':', two substrings are allocated and
+ * returned.
+ *
+ * @str: String to split
+ * @firstp: Returns first string
+ * @secondp: Returns second string
+ * @return 0 if OK, -ve if @str does not have a :
+ */
+static int get_two_words(const char *str, char **firstp, char **secondp)
+{
+ const char *p;
+
+ p = strchr(str, ':');
+ if (!p)
+ return -1;
+ *firstp = strdup(str);
+ (*firstp)[p - str] = '\0';
+ *secondp = strdup(p + 1);
+
+ return 0;
+}
+
+int main(int argc, char *argv[])
+{
+ int opt, option_index = 0;
+ int mode_dump = 0, mode_extract = 0, mode_inject = 0;
+ int mode_spifreq = 0, mode_em100 = 0, mode_locked = 0;
+ int mode_unlocked = 0, mode_write = 0, mode_write_descriptor = 0;
+ int create = 0;
+ char *region_type_string = NULL, *src_fname = NULL;
+ char *addr_str = NULL;
+ int region_type = -1, inputfreq = 0;
+ enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ;
+ unsigned int addr = 0;
+ int rom_size = -1;
+ bool write_it;
+ char *filename;
+ char *outfile = NULL;
+ struct stat buf;
+ int size = 0;
+ int bios_fd;
+ char *image;
+ int ret;
+ static struct option long_options[] = {
+ {"create", 0, NULL, 'c'},
+ {"dump", 0, NULL, 'd'},
+ {"descriptor", 1, NULL, 'D'},
+ {"em100", 0, NULL, 'e'},
+ {"extract", 0, NULL, 'x'},
+ {"inject", 1, NULL, 'i'},
+ {"lock", 0, NULL, 'l'},
+ {"romsize", 1, NULL, 'r'},
+ {"spifreq", 1, NULL, 's'},
+ {"unlock", 0, NULL, 'u'},
+ {"write", 1, NULL, 'w'},
+ {"version", 0, NULL, 'v'},
+ {"help", 0, NULL, 'h'},
+ {0, 0, 0, 0}
+ };
+
+ while ((opt = getopt_long(argc, argv, "cdD:ehi:lr:s:uvw:x?",
+ long_options, &option_index)) != EOF) {
+ switch (opt) {
+ case 'c':
+ create = 1;
+ break;
+ case 'd':
+ mode_dump = 1;
+ break;
+ case 'D':
+ mode_write_descriptor = 1;
+ src_fname = optarg;
+ break;
+ case 'e':
+ mode_em100 = 1;
+ break;
+ case 'i':
+ if (get_two_words(optarg, ®ion_type_string,
+ &src_fname)) {
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ if (!strcasecmp("Descriptor", region_type_string))
+ region_type = 0;
+ else if (!strcasecmp("BIOS", region_type_string))
+ region_type = 1;
+ else if (!strcasecmp("ME", region_type_string))
+ region_type = 2;
+ else if (!strcasecmp("GbE", region_type_string))
+ region_type = 3;
+ else if (!strcasecmp("Platform", region_type_string))
+ region_type = 4;
+ if (region_type == -1) {
+ fprintf(stderr, "No such region type: '%s'\n\n",
+ region_type_string);
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ mode_inject = 1;
+ break;
+ case 'l':
+ mode_locked = 1;
+ break;
+ case 'r':
+ rom_size = strtol(optarg, NULL, 0);
+ debug("ROM size %d\n", rom_size);
+ break;
+ case 's':
+ /* Parse the requested SPI frequency */
+ inputfreq = strtol(optarg, NULL, 0);
+ switch (inputfreq) {
+ case 20:
+ spifreq = SPI_FREQUENCY_20MHZ;
+ break;
+ case 33:
+ spifreq = SPI_FREQUENCY_33MHZ;
+ break;
+ case 50:
+ spifreq = SPI_FREQUENCY_50MHZ;
+ break;
+ default:
+ fprintf(stderr, "Invalid SPI Frequency: %d\n",
+ inputfreq);
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ mode_spifreq = 1;
+ break;
+ case 'u':
+ mode_unlocked = 1;
+ break;
+ case 'v':
+ print_version();
+ exit(EXIT_SUCCESS);
+ break;
+ case 'w':
+ mode_write = 1;
+ if (get_two_words(optarg, &addr_str, &src_fname)) {
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ addr = strtol(optarg, NULL, 0);
+ break;
+ case 'x':
+ mode_extract = 1;
+ break;
+ case 'h':
+ case '?':
+ default:
+ print_usage(argv[0]);
+ exit(EXIT_SUCCESS);
+ break;
+ }
+ }
+
+ if (mode_locked == 1 && mode_unlocked == 1) {
+ fprintf(stderr, "Locking/Unlocking FD and ME are mutually exclusive\n");
+ exit(EXIT_FAILURE);
+ }
+
+ if (mode_inject == 1 && mode_write == 1) {
+ fprintf(stderr, "Inject/Write are mutually exclusive\n");
+ exit(EXIT_FAILURE);
+ }
+
+ if ((mode_dump + mode_extract + mode_inject +
+ (mode_spifreq | mode_em100 | mode_unlocked |
+ mode_locked)) > 1) {
+ fprintf(stderr, "You may not specify more than one mode.\n\n");
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+
+ if ((mode_dump + mode_extract + mode_inject + mode_spifreq +
+ mode_em100 + mode_locked + mode_unlocked + mode_write +
+ mode_write_descriptor) == 0 && !create) {
+ fprintf(stderr, "You need to specify a mode.\n\n");
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+
+ if (create && rom_size == -1) {
+ fprintf(stderr, "You need to specify a rom size when creating.\n\n");
+ exit(EXIT_FAILURE);
+ }
+
+ if (optind + 1 != argc) {
+ fprintf(stderr, "You need to specify a file.\n\n");
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+
+ filename = argv[optind];
+ if (optind + 2 != argc)
+ outfile = argv[optind + 1];
+
+ if (create)
+ bios_fd = open(filename, O_WRONLY | O_CREAT, 0666);
+ else
+ bios_fd = open(filename, outfile ? O_RDONLY : O_RDWR);
+
+ if (bios_fd == -1) {
+ perror("Could not open file");
+ exit(EXIT_FAILURE);
+ }
+
+ if (!create) {
+ if (fstat(bios_fd, &buf) == -1) {
+ perror("Could not stat file");
+ exit(EXIT_FAILURE);
+ }
+ size = buf.st_size;
+ }
+
+ debug("File %s is %d bytes\n", filename, size);
+
+ if (rom_size == -1)
+ rom_size = size;
+
+ image = malloc(rom_size);
+ if (!image) {
+ printf("Out of memory.\n");
+ exit(EXIT_FAILURE);
+ }
+
+ memset(image, '\xff', rom_size);
+ if (!create && read(bios_fd, image, size) != size) {
+ perror("Could not read file");
+ exit(EXIT_FAILURE);
+ }
+ if (size != rom_size) {
+ debug("ROM size changed to %d bytes\n", rom_size);
+ size = rom_size;
+ }
+
+ write_it = true;
+ ret = 0;
+ if (mode_dump) {
+ ret = dump_fd(image, size);
+ write_it = false;
+ }
+
+ if (mode_extract) {
+ ret = write_regions(image, size);
+ write_it = false;
+ }
+
+ if (mode_write_descriptor)
+ ret = write_data(image, size, -size, src_fname);
+
+ if (mode_inject)
+ ret = inject_region(image, size, region_type, src_fname);
+
+ if (mode_write)
+ ret = write_data(image, size, addr, src_fname);
+
+ if (mode_spifreq)
+ set_spi_frequency(image, size, spifreq);
+
+ if (mode_em100)
+ set_em100_mode(image, size);
+
+ if (mode_locked)
+ lock_descriptor(image, size);
+
+ if (mode_unlocked)
+ unlock_descriptor(image, size);
+
+ if (write_it) {
+ if (outfile) {
+ ret = write_image(outfile, image, size);
+ } else {
+ if (lseek(bios_fd, 0, SEEK_SET)) {
+ perror("Error while seeking");
+ ret = -1;
+ }
+ if (write(bios_fd, image, size) != size) {
+ perror("Error while writing");
+ ret = -1;
+ }
+ }
+ }
+
+ free(image);
+ close(bios_fd);
+
+ return ret ? 1 : 0;
+}
--- /dev/null
+/*
+ * ifdtool - Manage Intel Firmware Descriptor information
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * From Coreboot project
+ */
+
+#include <stdint.h>
+
+#define __packed __attribute__((packed))
+
+#define IFDTOOL_VERSION "1.1-U-Boot"
+
+enum spi_frequency {
+ SPI_FREQUENCY_20MHZ = 0,
+ SPI_FREQUENCY_33MHZ = 1,
+ SPI_FREQUENCY_50MHZ = 4,
+};
+
+enum component_density {
+ COMPONENT_DENSITY_512KB = 0,
+ COMPONENT_DENSITY_1MB = 1,
+ COMPONENT_DENSITY_2MB = 2,
+ COMPONENT_DENSITY_4MB = 3,
+ COMPONENT_DENSITY_8MB = 4,
+ COMPONENT_DENSITY_16MB = 5,
+};
+
+/* flash descriptor */
+struct __packed fdbar_t {
+ uint32_t flvalsig;
+ uint32_t flmap0;
+ uint32_t flmap1;
+ uint32_t flmap2;
+ uint8_t reserved[0xefc - 0x20];
+ uint32_t flumap1;
+};
+
+#define MAX_REGIONS 5
+
+/* regions */
+struct __packed frba_t {
+ uint32_t flreg[MAX_REGIONS];
+};
+
+/* component section */
+struct __packed fcba_t {
+ uint32_t flcomp;
+ uint32_t flill;
+ uint32_t flpb;
+};
+
+#define MAX_STRAPS 18
+
+/* pch strap */
+struct __packed fpsba_t {
+ uint32_t pchstrp[MAX_STRAPS];
+};
+
+/* master */
+struct __packed fmba_t {
+ uint32_t flmstr1;
+ uint32_t flmstr2;
+ uint32_t flmstr3;
+};
+
+/* processor strap */
+struct __packed fmsba_t {
+ uint32_t data[8];
+};
+
+/* ME VSCC */
+struct vscc_t {
+ uint32_t jid;
+ uint32_t vscc;
+};
+
+struct vtba_t {
+ /* Actual number of entries specified in vtl */
+ struct vscc_t entry[8];
+};
+
+struct region_t {
+ int base, limit, size;
+};
projects / karo-tx-uboot.git / commitdiff