UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION)
export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION
-export ARCH CPU BOARD VENDOR SOC
+export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
export MAKE AWK
export DTC CHECK CHECKFLAGS
-export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE
+export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS
export KBUILD_CFLAGS KBUILD_AFLAGS
# When compiling out-of-tree modules, put MODVERDIR in the module
CHECKFLAGS += $(NOSTDINC_FLAGS)
# FIX ME
-cpp_flags := $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(UBOOTINCLUDE) $(NOSTDINC_FLAGS)
+cpp_flags := $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) $(UBOOTINCLUDE) \
+ $(NOSTDINC_FLAGS)
c_flags := $(KBUILD_CFLAGS) $(cpp_flags)
#########################################################################
# Add GCC lib
-ifdef USE_PRIVATE_LIBGCC
-ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
+ifdef CONFIG_USE_PRIVATE_LIBGCC
+ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y)
PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a
else
-PLATFORM_LIBGCC = -L $(USE_PRIVATE_LIBGCC) -lgcc
+PLATFORM_LIBGCC = -L $(CONFIG_USE_PRIVATE_LIBGCC) -lgcc
endif
else
PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`) -lgcc
System.map: u-boot
@$(call SYSTEM_MAP,$<) > $@
-checkthumb:
- @if test $(call cc-version) -lt 0404; then \
- echo -n '*** Your GCC does not produce working '; \
- echo 'binaries in THUMB mode.'; \
- echo '*** Your board is configured for THUMB mode.'; \
- false; \
- fi
-
-# GCC 3.x is reported to have problems generating the type of relocation
-# that U-Boot wants.
-# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html
-checkgcc4:
- @if test $(call cc-version) -lt 0400; then \
- echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \
- false; \
- fi
-
checkdtc:
@if test $(call dtc-version) -lt 0104; then \
echo '*** Your dtc is too old, please upgrade to dtc 1.4 or newer'; \
# Directories & files removed with 'make clean'
CLEAN_DIRS += $(MODVERDIR)
CLEAN_FILES += u-boot.lds include/bmp_logo.h include/bmp_logo_data.h \
- board/*/config.tmp board/*/*/config.tmp \
include/autoconf.mk* include/spl-autoconf.mk \
include/tpl-autoconf.mk
si->clk_bus = gd->bus_clk;
si->clk_cpu = gd->cpu_clk;
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) || \
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || \
defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define bi_bar bi_immr_base
#elif defined(CONFIG_MPC5xxx)
# Only test once
ifneq ($(CONFIG_SPL_BUILD),y)
-ALL-$(CONFIG_SYS_THUMB_BUILD) += checkthumb
+ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
+archprepare: checkthumb
+
+checkthumb:
+ @if test "$(call cc-version)" -lt "0404"; then \
+ echo -n '*** Your GCC does not produce working '; \
+ echo 'binaries in THUMB mode.'; \
+ echo '*** Your board is configured for THUMB mode.'; \
+ false; \
+ fi
+endif
endif
# Try if EABI is supported, else fall back to old API,
+++ /dev/null
-#
-# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-USE_PRIVATE_LIBGCC = yes
+++ /dev/null
-#
-# (C) Copyright 2010-2013
-# NVIDIA Corporation <www.nvidia.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#/
-USE_PRIVATE_LIBGCC = yes
+++ /dev/null
-#
-# (C) Copyright 2010,2011
-# NVIDIA Corporation <www.nvidia.com>
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-USE_PRIVATE_LIBGCC = yes
+++ /dev/null
-#
-# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-USE_PRIVATE_LIBGCC = yes
# SPDX-License-Identifier: GPL-2.0+
#
-# Build private libgcc only when asked for
-ifdef USE_PRIVATE_LIBGCC
-lib-y += _ashldi3.o
-lib-y += _ashrdi3.o
-lib-y += _divsi3.o
-lib-y += _lshrdi3.o
-lib-y += _modsi3.o
-lib-y += _udivsi3.o
-lib-y += _umodsi3.o
-lib-y += div0.o
-endif
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \
+ _lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o
ifdef CONFIG_ARM64
obj-y += crt0_64.o
endif
SYM_PREFIX = _
+export SYM_PREFIX
LDR_FLAGS-y :=
LDR_FLAGS-$(CONFIG_BFIN_BOOTROM_USES_EVT1) += -J
# Note: Toolchains with binutils prior to v2.16
# are no longer supported by U-Boot MIPS tree!
#
-MIPSFLAGS := -march=mips32r2
-
-PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += -DCONFIG_MIPS32 -march=mips32r2
PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
ifdef CONFIG_SYS_BIG_ENDIAN
PLATFORM_LDFLAGS += -m elf32btsmip
PLATFORM_LDFLAGS += -m elf32ltsmip
endif
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T $(srctree)/$(src)/mips.lds
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \
+ -T $(srctree)/examples/standalone/mips.lds
# Note: Toolchains with binutils prior to v2.16
# are no longer supported by U-Boot MIPS tree!
#
-MIPSFLAGS = -march=mips64
-
-PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += -DCONFIG_MIPS64 -march=mips64
PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
ifdef CONFIG_SYS_BIG_ENDIAN
PLATFORM_LDFLAGS += -m elf64btsmip
PLATFORM_LDFLAGS += -m elf64ltsmip
endif
-CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T $(srctree)/$(src)/mips64.lds
+CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 \
+ -T $(srctree)/examples/standalone/mips64.lds
PLATFORM_LDFLAGS += -m elf32ltsmip
endif
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T $(srctree)/$(src)/mips.lds
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \
+ -T $(srctree)/examples/standalone/mips.lds
obj-y += board.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
-# Build private libgcc only when asked for
-ifdef USE_PRIVATE_LIBGCC
-lib-y += ashldi3.o
-lib-y += ashrdi3.o
-lib-y += lshrdi3.o
-endif
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o
CROSS_COMPILE := nds32le-linux-
endif
-CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T $(srctree)/$(src)/nds32.lds
+CONFIG_STANDALONE_LOAD_ADDR = 0x300000 \
+ -T $(srctree)/examples/standalone/nds32.lds
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -mrelax
PLATFORM_RELFLAGS += -gdwarf-2
# Only test once
ifneq ($(CONFIG_SPL_BUILD),y)
-ALL-y += checkgcc4
+archprepare: checkgcc4
+
+# GCC 3.x is reported to have problems generating the type of relocation
+# that U-Boot wants.
+# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html
+checkgcc4:
+ @if test $(call cc-version) -lt 0400; then \
+ echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \
+ false; \
+ fi
endif
# SPDX-License-Identifier: GPL-2.0+
#
-PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 \
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8260 -DCONFIG_CPM2 \
-mstring -mcpu=603e -mmultiple
#include <mpc8260.h>
#include <version.h>
-#define CONFIG_8260 1 /* needed for Linux kernel header files */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <mpc8260.h>
#include <version.h>
-#define CONFIG_8260 1 /* needed for Linux kernel header files */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
"SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
} while (0)
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void update_rdcc(void)
{
u32 val;
}
}
}
-#endif
#if defined(CONFIG_440)
/*
#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
-#if !defined(CONFIG_NAND_SPL)
/*-----------------------------------------------------------------------------+
* sdram_memsize
*-----------------------------------------------------------------------------*/
val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
printf(", CL%d)", val);
}
-#endif /* !CONFIG_NAND_SPL */
#if defined(CONFIG_SPD_EEPROM)
*---------------------------------------------------------------------------*/
phys_size_t initdram(int board_type)
{
- /*
- * Only run this SDRAM init code once. For NAND booting
- * targets like Kilauea, we call initdram() early from the
- * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
- * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
- * which calls initdram() again. This time the controller
- * mustn't be reconfigured again since we're already running
- * from SDRAM.
- */
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
unsigned long val;
#if defined(CONFIG_440)
#endif
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*------------------------------------------------------------------
| DQS calibration.
+-----------------------------------------------------------------*/
DQS_autocalibration();
-#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
/*
set_mcsr(get_mcsr());
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
-#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
-
return (CONFIG_SYS_MBYTES_SDRAM << 20);
}
#endif /* CONFIG_SPD_EEPROM */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#if defined(CONFIG_440)
u32 mfdcr_any(u32 dcr)
{
}
}
#endif /* defined(CONFIG_440) */
-#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
inline void ppc4xx_ibm_ddr2_register_dump(void)
{
#include "ecc.h"
-/*
- * Only compile the DDR auto-calibration code for NOR boot and
- * not for NAND boot (NAND SPL and NAND U-Boot - NUB)
- */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-
#define MAXBXCF 4
#define SDRAM_RXBAS_SHIFT_1M 20
return 0;
}
-#else /* defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
-u32 DQS_autocalibration(void)
-{
- return 0;
-}
-#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
obj-y += 40x_spd_sdram.o
-ifndef CONFIG_NAND_SPL
-ifndef CONFIG_NAND_U_BOOT
obj-y += 44x_spd_ddr.o
-endif
-endif
obj-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o
obj-$(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) += 4xx_ibm_ddr2_autocalib.o
obj-y += 4xx_pci.o
.extern ext_bus_cntlr_init
-#ifdef CONFIG_NAND_U_BOOT
- .extern reconfig_tlb0
-#endif
/*
* Set up GOT: Global Offset Table
*
* Use r12 to access the GOT
*/
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_BUILD)
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
-#endif /* CONFIG_NAND_SPL */
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
- !defined(CONFIG_SPL_BUILD)
- /*
- * NAND U-Boot image is started from offset 0
- */
- .text
-#if defined(CONFIG_440)
- bl reconfig_tlb0
-#endif
- GET_GOT
- bl cpu_init_f /* run low-level CPU init code (from Flash) */
- bl board_init_f
- /* NOTREACHED - board_init_f() does not return */
-#endif
+#endif /* CONFIG_SPL_BUILD */
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
/*
*/
#if defined(CONFIG_440)
-#if !defined(CONFIG_NAND_SPL)
.section .bootpg,"ax"
-#endif
.globl _start_440
/**************************************************************************/
* r3 - 1st arg to board_init(): IMMP pointer
* r4 - 2nd arg to board_init(): boot flag
*/
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_BUILD)
.text
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
stwu r1,-8(r1) /* Save back chain and move SP */
stw r0,+12(r1) /* Save return addr (underflow vect) */
-#ifdef CONFIG_NAND_SPL
- bl nand_boot_common /* will not return */
-#else
#ifndef CONFIG_SPL_BUILD
GET_GOT
#endif
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
/* NOTREACHED - board_init_f() does not return */
-#endif
#endif /* CONFIG_440 */
stw r0, +12(r1) /* Save return addr (underflow vect) */
#endif /* CONFIG_SYS_INIT_DCACHE_CS */
-#ifdef CONFIG_NAND_SPL
- bl nand_boot_common /* will not return */
-#else
GET_GOT /* initialize GOT access */
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f /* run first part of init code (from Flash) */
/* NOTREACHED - board_init_f() does not return */
-#endif /* CONFIG_NAND_SPL */
-
#endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
/*----------------------------------------------------------------------- */
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_BUILD)
/*
* This code finishes saving the registers to the exception frame
* and jumps to the appropriate handler for the exception.
blr
function_epilog(dcbz_area)
#endif /* CONFIG_440 */
-#endif /* CONFIG_NAND_SPL */
+#endif /* CONFIG_SPL_BUILD */
/*------------------------------------------------------------------------------- */
/* Function: in8 */
blr
function_epilog(mftlb1)
#endif /* CONFIG_440 */
-
-#if defined(CONFIG_NAND_SPL)
-/*
- * void nand_boot_relocate(dst, src, bytes)
- *
- * r3 = Destination address to copy code to (in SDRAM)
- * r4 = Source address to copy code from
- * r5 = size to copy in bytes
- */
-nand_boot_relocate:
- mr r6,r3
- mr r7,r4
- mflr r8
-
- /*
- * Copy SPL from icache into SDRAM
- */
- subi r3,r3,4
- subi r4,r4,4
- srwi r5,r5,2
- mtctr r5
-..spl_loop:
- lwzu r0,4(r4)
- stwu r0,4(r3)
- bdnz ..spl_loop
-
- /*
- * Calculate "corrected" link register, so that we "continue"
- * in execution in destination range
- */
- sub r3,r7,r6 /* r3 = src - dst */
- sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
- mtlr r8
- blr
-
-nand_boot_common:
- /*
- * First initialize SDRAM. It has to be available *before* calling
- * nand_boot().
- */
- lis r3,CONFIG_SYS_SDRAM_BASE@h
- ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
- bl initdram
-
- /*
- * Now copy the 4k SPL code into SDRAM and continue execution
- * from there.
- */
- lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
- ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
- lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
- ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
- lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
- ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
- bl nand_boot_relocate
-
- /*
- * We're running from SDRAM now!!!
- *
- * It is necessary for 4xx systems to relocate from running at
- * the original location (0xfffffxxx) to somewhere else (SDRAM
- * preferably). This is because CS0 needs to be reconfigured for
- * NAND access. And we can't reconfigure this CS when currently
- * "running" from it.
- */
-
- /*
- * Finally call nand_boot() to load main NAND U-Boot image from
- * NAND and jump to it.
- */
- bl nand_boot /* will not return */
-#endif /* CONFIG_NAND_SPL */
#elif defined(CONFIG_GEMINI)
#define _machine _MACH_gemini
#define have_of 0
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
#define _machine _MACH_8260
#define have_of 0
#elif defined(CONFIG_SANDPOINT)
#ifndef CONFIG_BOARD_SPECIFIC_LED
# if defined(CONFIG_8xx)
# include <mpc8xx.h>
-# elif defined(CONFIG_8260)
+# elif defined(CONFIG_MPC8260)
# include <mpc8260.h>
# elif defined(CONFIG_5xx)
# include <mpc5xx.h>
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \
|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
## Build a couple of necessary functions into a private libgcc
## if the user asked for it
-ifdef USE_PRIVATE_LIBGCC
-lib-y += _ashldi3.o
-lib-y += _ashrdi3.o
-lib-y += _lshrdi3.o
-endif
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _lshrdi3.o
MINIMAL=
serial_init,
console_init_f,
display_options,
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
prt_8260_rsr,
prt_8260_clks,
-#endif /* CONFIG_8260 */
+#endif /* CONFIG_MPC8260 */
#if defined(CONFIG_MPC83xx)
prt_83xx_rsr,
#endif
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
#endif
-#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \
defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
#endif
#define SPACE_REQUIRED ((32*4)+(32*8)+(6*4))
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
/* store floating double indexed */
#define STFDI(n,p) __asm__ __volatile__ ("stfd " #n ",%0" : "=o"(p[2*n]))
/* store floating double multiple */
*ptr++ = regs->gpr[i];
/* Floating Point Regs */
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
STFDM(ptr);
ptr += 32*2;
#else
/* set the value of the CPU registers */
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
/* load floating double */
#define LFD(n,v) __asm__ __volatile__ ("lfd " #n ",%0" :: "o"(v))
/* load floating double indexed */
regs->gpr[regno] = *ptr;
else switch (regno) {
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
#define caseF(n) \
case (n) + 32: LFD(n, *ptr); break;
regs->gpr[i] = *ptr++;
/* Floating Point Regs */
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
LFDM(ptr);
#endif
ptr += 32*2;
return close(fd);
}
+int os_unlink(const char *pathname)
+{
+ return unlink(pathname);
+}
+
void os_exit(int exit_code)
{
exit(exit_code);
endif
obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o
-
-
-# Build private libgcc only when asked for
-ifdef USE_PRIVATE_LIBGCC
-lib-y += ashiftrt.o
-lib-y += ashiftlt.o
-lib-y += lshiftrt.o
-lib-y += ashldi3.o
-lib-y += ashrsi3.o
-lib-y += lshrdi3.o
-lib-y += movmem.o
-endif
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashiftrt.o ashiftlt.o lshiftrt.o \
+ ashldi3.o ashrsi3.o lshrdi3.o movmem.o
CROSS_COMPILE := sparc-elf-
endif
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) \
- -T $(srctree)/$(src)/sparc.lds
+ -T $(srctree)/examples/standalone/sparc.lds
PLATFORM_CPPFLAGS += -DCONFIG_SPARC -D__sparc__
export NORMAL_LIBGCC = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
PREFIXED_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/$(shell basename $(NORMAL_LIBGCC))
-export USE_PRIVATE_LIBGCC=$(shell dirname $(PREFIXED_LIBGCC))
+CONFIG_USE_PRIVATE_LIBGCC=$(shell dirname $(PREFIXED_LIBGCC))
extern void board_pll_init_f(void);
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void cram_bcr_write(u32 wr_val)
{
wr_val <<= 2;
return;
}
-#endif
phys_size_t initdram(int board_type)
{
-#if defined(CONFIG_NAND_SPL)
- u32 reg;
-
- /* don't reinit PLL when booting via I2C bootstrap option */
- mfsdr(SDR0_PINSTP, reg);
- if (reg != 0xf0000000)
- board_pll_init_f();
-#endif
-
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
int i;
u32 val;
/* Wait a short while, since for NAND booting this is too fast */
for (i=0; i<200000; i++)
;
-#endif
return (CONFIG_SYS_MBYTES_RAM << 20);
}
mtcpr(CPR0_CLKUP, 0x40000000);
}
#endif /* CPU_<speed>_405EZ */
-
-#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
-/*
- * Get timebase clock frequency
- */
-unsigned long get_tbclk(void)
-{
- unsigned long cpr_plld;
- unsigned long cpr_primad;
- unsigned long primad_cpudv;
- unsigned long pllFbkDiv;
- unsigned long freqProcessor;
-
- /*
- * Read PLL Mode registers
- */
- mfcpr(CPR0_PLLD, cpr_plld);
-
- /*
- * Read CPR_PRIMAD register
- */
- mfcpr(CPR0_PRIMAD, cpr_primad);
-
- /*
- * Determine CPU clock frequency
- */
- primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
- if (primad_cpudv == 0)
- primad_cpudv = 16;
-
- /*
- * Determine FBK_DIV.
- */
- pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
- if (pllFbkDiv == 0)
- pllFbkDiv = 256;
-
- freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
-
- return (freqProcessor);
-}
-#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */
void configure_ppc440ep_pins(void);
int is_nand_selected(void);
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
/*************************************************************************
*
* Bamboo has one bank onboard sdram (plus DIMM)
0,
0
};
-#endif
#if 0
{ /* GPIO Alternate1 Alternate2 Alternate3 */
phys_size_t initdram (int board_type)
{
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
long dram_size;
dram_size = spd_sdram();
return dram_size;
-#else
- return CONFIG_SYS_MBYTES_SDRAM << 20;
-#endif
}
/*----------------------------------------------------------------------------+
if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
{
update_ndfc_ios(gpio_tab);
-
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
SDR0_CUST0_CHIPSELGAT_EN1 |
SDR0_CUST0_CHIPSELGAT_EN2);
-#else
- mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
- SDR0_CUST0_NDFC_ENABLE |
- SDR0_CUST0_NDFC_BW_8_BIT |
- SDR0_CUST0_NDFC_ARE_MASK |
- SDR0_CUST0_CHIPSELGAT_EN0 |
- SDR0_CUST0_CHIPSELGAT_EN2);
-#endif
-
ndfc_selection_in_fpga();
}
else
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
-#ifndef CONFIG_NAND_SPL
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
-#else
- tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G)
- tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
-#endif
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
- /*
- * For NAND booting the first TLB has to be reconfigured to full size
- * and with caching disabled after running from RAM!
- */
-#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0)
-#define TLB02 TLB2(AC_RWX | SA_IG)
-
- .globl reconfig_tlb0
-reconfig_tlb0:
- sync
- isync
- addi r4,r0,0x0000 /* TLB entry #0 */
- lis r5,TLB00@h
- ori r5,r5,TLB00@l
- tlbwe r5,r4,0x0000 /* Save it out */
- lis r5,TLB01@h
- ori r5,r5,TLB01@l
- tlbwe r5,r4,0x0001 /* Save it out */
- lis r5,TLB02@h
- ori r5,r5,TLB02@l
- tlbwe r5,r4,0x0002 /* Save it out */
- sync
- isync
- blr
-#endif
*/
/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
- mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
-#else
mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
-#endif
/* Remove TLB entry of boot EBC mapping */
remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
* use the speed up boot process. It is patched after relocation to
* enable SA_I
*/
-#ifndef CONFIG_NAND_SPL
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */
-#else
- tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_RWX | SA_G)
- tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
- tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_RWX | SA_IG)
-#endif
/*
* TLB entries for SDRAM are not needed on this platform.
#endif
tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
- /*
- * For NAND booting the first TLB has to be reconfigured to full size
- * and with caching disabled after running from RAM!
- */
-#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02 TLB2(AC_RWX | SA_IG)
-
- .globl reconfig_tlb0
-reconfig_tlb0:
- sync
- isync
- addi r4,r0,0x0000 /* TLB entry #0 */
- lis r5,TLB00@h
- ori r5,r5,TLB00@l
- tlbwe r5,r4,0x0000 /* Save it out */
- lis r5,TLB01@h
- ori r5,r5,TLB01@l
- tlbwe r5,r4,0x0001 /* Save it out */
- lis r5,TLB02@h
- ori r5,r5,TLB02@l
- tlbwe r5,r4,0x0002 /* Save it out */
- sync
- isync
- blr
-#endif
/* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
-#ifndef CONFIG_NAND_SPL
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
-#else
- tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
-#endif
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
- /*
- * For NAND booting the first TLB has to be reconfigured to full size
- * and with caching disabled after running from RAM!
- */
-#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02 TLB2(AC_RWX | SA_IG)
-
- .globl reconfig_tlb0
-reconfig_tlb0:
- sync
- isync
- addi r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */
- lis r5,TLB00@h
- ori r5,r5,TLB00@l
- tlbwe r5,r4,0x0000 /* Save it out */
- lis r5,TLB01@h
- ori r5,r5,TLB01@l
- tlbwe r5,r4,0x0001 /* Save it out */
- lis r5,TLB02@h
- ori r5,r5,TLB02@l
- tlbwe r5,r4,0x0002 /* Save it out */
- sync
- isync
- blr
-#endif
extern int denali_wait_for_dlllock(void);
extern void denali_core_search_data_eye(void);
-#if defined(CONFIG_NAND_SPL)
-/* Using arch/powerpc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big
- * for the 4k NAND boot image so define bus_frequency to 133MHz here
- * which is save for the refresh counter setup.
- */
-#define get_bus_freq(val) 133333333
-#endif
-
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
************************************************************************/
phys_size_t initdram (int board_type)
{
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \
- defined(CONFIG_NAND_SPL)
+#if !defined(CONFIG_SYS_RAMBOOT)
ulong speed = get_bus_freq(0);
mtsdram(DDR0_02, 0x00000000);
mtsdram(DDR0_02, 0x00000001);
denali_wait_for_dlllock();
-#endif /* #ifndef CONFIG_NAND_U_BOOT */
+#endif /* #ifndef CONFIG_SYS_RAMBOOT */
#ifdef CONFIG_DDR_DATA_EYE
/* -----------------------------------------------------------+
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
- defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
- defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
}
#endif
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
/*
* On NAND-booting sequoia, we need to patch the chips select numbers
* in the dtb (CS0 - NAND, CS3 - NOR)
return;
}
}
-#endif /* CONFIG_NAND_U_BOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
+++ /dev/null
-config.tmp
+++ /dev/null
-/config.tmp
+++ /dev/null
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
+++ /dev/null
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
+++ /dev/null
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
+++ /dev/null
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
+++ /dev/null
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --dma 6
LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
+++ /dev/null
-#
-# Copyright (c) Switchfin Org. <dpn@switchfin.org>
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
+++ /dev/null
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --dma 6
LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
#include <ioports.h>
}
};
-#endif /* CONFIG_8260 */
+#endif /* CONFIG_MPC8260 */
/* ------------------------------------------------------------------------- */
#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
#if (defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \
- (defined(CONFIG_8260) && defined(CONFIG_CONS_NONE))
+ (defined(CONFIG_MPC8260) && defined(CONFIG_CONS_NONE))
#if CONFIG_CONS_INDEX == 1
#define CMA_MB_SERIAL_BASE CMA_MB_SERIALA_BASE
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
-#ifndef CONFIG_NAND_SPL
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
-#else
- tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
-#endif
/* TLB entries for DDR2 SDRAM are generated dynamically */
/* TODO: what about high IO space */
tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
- /*
- * For NAND booting the first TLB has to be reconfigured to full size
- * and with caching disabled after running from RAM!
- */
-#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02 TLB2(AC_RWX | SA_IG)
-
- .globl reconfig_tlb0
-reconfig_tlb0:
- sync
- isync
- addi r4,r0,0x0000 /* TLB entry #0 */
- lis r5,TLB00@h
- ori r5,r5,TLB00@l
- tlbwe r5,r4,0x0000 /* Save it out */
- lis r5,TLB01@h
- ori r5,r5,TLB01@l
- tlbwe r5,r4,0x0001 /* Save it out */
- lis r5,TLB02@h
- ori r5,r5,TLB02@l
- tlbwe r5,r4,0x0002 /* Save it out */
- sync
- isync
- blr
-#endif
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
- mtdcr(EBC0_CFGADDR, PB2CR);
-#else
mtdcr(EBC0_CFGADDR, PB0CR);
-#endif
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
- mtdcr(EBC0_CFGADDR, PB2CR);
-#else
mtdcr(EBC0_CFGADDR, PB0CR);
-#endif
mtdcr(EBC0_CFGDATA, pbcr);
/*
#ifndef _HYMOD_H_
#define _HYMOD_H_
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
#include <asm/iopin_8260.h>
#endif
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
+++ /dev/null
-#
-# Copyright (c) Switchfin Org. <dpn@switchfin.org>
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
+++ /dev/null
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+++ /dev/null
-/config.tmp
+++ /dev/null
-config.tmp
+++ /dev/null
-/config.tmp
Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek <monstr@monstr.eu>
Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu <vlad.lungu@windriver.com>
Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN -
-Active mips mips32 - imgtec malta malta malta:
MIPS32,SYS_BIG_ENDIAN Paul Burton <paul.burton@imgtec.com>
-Active mips mips32 - imgtec malta maltael malta:
MIPS32,SYS_LITTLE_ENDIAN Paul Burton <paul.burton@imgtec.com>
+Active mips mips32 - imgtec malta malta malta:
SYS_BIG_ENDIAN Paul Burton <paul.burton@imgtec.com>
+Active mips mips32 - imgtec malta maltael malta:
SYS_LITTLE_ENDIAN Paul Burton <paul.burton@imgtec.com>
Active mips mips32 - micronas vct vct_platinum vct:VCT_PLATINUM -
Active mips mips32 - micronas vct vct_platinum_onenand vct:VCT_PLATINUM,VCT_ONENAND -
Active mips mips32 - micronas vct vct_platinum_onenand_small vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE -
Active powerpc ppc4xx - amcc - taihu - John Otken <jotken@softadvances.com>
Active powerpc ppc4xx - amcc - taishan - Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc - yucca - -
-Active powerpc ppc4xx - amcc acadia acadia_nand acadia:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc bamboo bamboo_nand bamboo:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands arches canyonlands:ARCHES Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands canyonlands canyonlands:CANYONLANDS Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc canyonlands canyonlands_nand canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands glacier canyonlands:GLACIER Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc canyonlands glacier_nand canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc kilauea haleakala kilauea:HALEAKALA Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc kilauea haleakala_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc kilauea kilauea kilauea:KILAUEA Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc kilauea kilauea_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia rainier sequoia:RAINIER Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc sequoia rainier_nand sequoia:RAINIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia rainier_ramboot sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia sequoia sequoia:SEQUOIA Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc sequoia sequoia_nand sequoia:SEQUOIA,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia sequoia_ramboot sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc walnut sycamore walnut Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc walnut walnut - Stefan Roese <sr@denx.de>
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
#endif
-#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \
defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
#endif
#endif
display_options, /* say that we are here */
display_text_info, /* show debugging info if required */
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
prt_8260_rsr,
prt_8260_clks,
-#endif /* CONFIG_8260 */
+#endif /* CONFIG_MPC8260 */
#if defined(CONFIG_MPC83xx)
prt_83xx_rsr,
#endif
print_num("sramstart", bd->bi_sramstart);
print_num("sramsize", bd->bi_sramsize);
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || \
- defined(CONFIG_8260) || defined(CONFIG_E500)
+ defined(CONFIG_MPC8260) || defined(CONFIG_E500)
print_num("immr_base", bd->bi_immr_base);
#endif
print_num("bootflags", bd->bi_bootflags);
#include <common.h>
#include <command.h>
-#if defined(CONFIG_8xx) || defined(CONFIG_8260)
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260)
#if defined(CONFIG_8xx)
#include <asm/8xx_immap.h>
#include <commproc.h>
#include <asm/iopin_8xx.h>
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
#include <asm/immap_8260.h>
#include <asm/cpm_8260.h>
#include <asm/iopin_8260.h>
#if defined(CONFIG_8xx)
volatile sysconf8xx_t *sc = &immap->im_siu_conf;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
volatile sysconf8260_t *sc = &immap->im_siu_conf;
#endif
printf ("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask);
printf ("SIEL = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec);
printf ("TESR = %08x SDCR = %08x\n", sc->sc_tesr, sc->sc_sdcr);
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
printf ("BCR = %08x\n", sc->sc_bcr);
printf ("P_ACR = %02x P_ALRH= %08x P_ALRL= %08x\n",
sc->sc_ppc_acr, sc->sc_ppc_alrh, sc->sc_ppc_alrl);
#if defined(CONFIG_8xx)
volatile memctl8xx_t *memctl = &immap->im_memctl;
int nbanks = 8;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
volatile memctl8260_t *memctl = &immap->im_memctl;
int nbanks = 12;
#endif
printf ("MAR = %08x", memctl->memc_mar);
#if defined(CONFIG_8xx)
printf (" MCR = %08x\n", memctl->memc_mcr);
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
putc ('\n');
#endif
printf ("MAMR = %08x MBMR = %08x",
memctl->memc_mamr, memctl->memc_mbmr);
#if defined(CONFIG_8xx)
printf ("\nMSTAT = %04x\n", memctl->memc_mstat);
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
printf (" MCMR = %08x\n", memctl->memc_mcmr);
#endif
printf ("MPTPR = %04x MDR = %08x\n",
memctl->memc_mptpr, memctl->memc_mdr);
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
printf ("PSDMR = %08x LSDMR = %08x\n",
memctl->memc_psdmr, memctl->memc_lsdmr);
printf ("PURT = %02x PSRT = %02x\n",
return 0;
}
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
int
do_icinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#if defined(CONFIG_8xx)
volatile car8xx_t *car = &immap->im_clkrst;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
volatile car8260_t *car = &immap->im_clkrst;
#endif
printf ("SCCR = %08x\n", car->car_sccr);
printf ("PLPRCR= %08x\n", car->car_plprcr);
printf ("RSR = %08x\n", car->car_rsr);
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
printf ("SCCR = %08x\n", car->car_sccr);
printf ("SCMR = %08x\n", car->car_scmr);
printf ("RSR = %08x\n", car->car_rsr);
#define PB_NB_ODR 16
#define PC_NBITS 12
#define PD_NBITS 13
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
#define PA_NBITS 32
#define PA_NB_ODR 32
#define PB_NBITS 28
#if defined(CONFIG_8xx)
volatile iop8xx_t *iop = &immap->im_ioport;
volatile ushort *l, *r;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
volatile iop8260_t *iop = &immap->im_ioport;
volatile uint *l, *r;
#endif
#if defined(CONFIG_8xx)
l = &iop->iop_padir;
R = &immap->im_cpm.cp_pbdir;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
l = &iop->iop_pdira;
R = &iop->iop_pdirb;
#endif
binary ("PB_DIR", *R++, PB_NBITS);
binary ("PA_PAR", *l++, PA_NBITS);
binary ("PB_PAR", *R++, PB_NBITS);
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
binary ("PA_SOR", *l++, PA_NBITS);
binary ("PB_SOR", *R++, PB_NBITS);
#endif
#if defined(CONFIG_8xx)
l = &iop->iop_pcdir;
r = &iop->iop_pddir;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
l = &iop->iop_pdirc;
r = &iop->iop_pdird;
#endif
binary ("PC_SO ", *l++, PC_NBITS);
binary (" ", 0, 0);
r++;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
binary ("PC_SOR", *l++, PC_NBITS);
binary ("PD_SOR", *r++, PD_NBITS);
binary ("PC_ODR", *l++, PC_NBITS);
#if defined(CONFIG_8xx)
ulong clock = gd->cpu_clk;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
ulong clock = gd->arch.brg_clk;
#endif
#if defined(CONFIG_8xx)
volatile cpm8xx_t *cp = &immap->im_cpm;
volatile uint *p = &cp->cp_brgc1;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
volatile uint *p = &immap->im_brgc1;
#endif
int i = 1;
while (i <= 4)
prbrg (i++, *p++);
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
p = &immap->im_brgc5;
while (i <= 8)
prbrg (i++, *p++);
volatile i2c8xx_t *i2c = &immap->im_i2c;
volatile cpm8xx_t *cp = &immap->im_cpm;
volatile iic_t *iip = (iic_t *) & cp->cp_dparam[PROFF_IIC];
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
volatile i2c8260_t *i2c = &immap->im_i2c;
volatile iic_t *iip;
uint dpaddr;
""
);
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
U_BOOT_CMD(
icinfo, 1, 1, do_icinfo,
"print Interrupt Controller registers",
if (argc == 2) {
size = simple_strtoul(argv[1], NULL, 16);
+ } else if (argc == 1 && chk) {
+ puts("## Error: external checksum format must pass size\n");
+ return CMD_RET_FAILURE;
} else {
char *s = addr;
pid_t pid; /* 0 if exited */
#endif
char **argv; /* program name and arguments */
+ /* was quoted when parsed; copy of struct o_string.nonnull field */
+ int *argv_nonnull;
#ifdef __U_BOOT__
int argc; /* number of program arguments */
#endif
static int parse_group(o_string *dest, struct p_context *ctx, struct in_str *input, int ch);
#endif
static char *lookup_param(char *src);
-static char *make_string(char **inp);
+static char *make_string(char **inp, int *nonnull);
static int handle_dollar(o_string *dest, struct p_context *ctx, struct in_str *input);
#ifndef __U_BOOT__
static int parse_string(o_string *dest, struct p_context *ctx, const char *src);
if (child->sp) {
char * str = NULL;
- str = make_string((child->argv + i));
+ str = make_string(child->argv + i,
+ child->argv_nonnull + i);
parse_string_outer(str, FLAG_EXIT_FROM_LOOP | FLAG_REPARSING);
free(str);
return last_return_code;
for (a = 0; a < child->argc; a++) {
free(child->argv[a]);
}
- free(child->argv);
+ free(child->argv);
+ free(child->argv_nonnull);
child->argc = 0;
#endif
child->argv=NULL;
argc = ++child->argc;
child->argv = realloc(child->argv, (argc+1)*sizeof(*child->argv));
if (child->argv == NULL) return 1;
+ child->argv_nonnull = realloc(child->argv_nonnull,
+ (argc+1)*sizeof(*child->argv_nonnull));
+ if (child->argv_nonnull == NULL)
+ return 1;
child->argv[argc-1]=str;
+ child->argv_nonnull[argc-1] = dest->nonnull;
child->argv[argc]=NULL;
+ child->argv_nonnull[argc] = 0;
for (s = dest->data; s && *s; s++,str++) {
if (*s == '\\') s++;
*str = *s;
prog->redirects = NULL;
#endif
prog->argv = NULL;
+ prog->argv_nonnull = NULL;
#ifndef __U_BOOT__
prog->is_stopped = 0;
#endif
return list;
}
-/* Make new string for parser */
-static char * make_string(char ** inp)
+/*
+ * Make new string for parser
+ * inp - array of argument strings to flatten
+ * nonnull - indicates argument was quoted when originally parsed
+ */
+static char *make_string(char **inp, int *nonnull)
{
char *p;
char *str = NULL;
noeval = 1;
for (n = 0; inp[n]; n++) {
p = insert_var_value_sub(inp[n], noeval);
- str = xrealloc(str, (len + strlen(p)));
+ str = xrealloc(str, (len + strlen(p) + (2 * nonnull[n])));
if (n) {
strcat(str, " ");
} else {
*str = '\0';
}
+ if (nonnull[n])
+ strcat(str, "'");
strcat(str, p);
+ if (nonnull[n])
+ strcat(str, "'");
len = strlen(str) + 3;
if (p != inp[n]) free(p);
}
#
#########################################################################
-# clean the slate ...
-PLATFORM_RELFLAGS =
-PLATFORM_CPPFLAGS =
-PLATFORM_LDFLAGS =
-
+# This file is included from ./Makefile and spl/Makefile.
+# Clean the state to avoid the same flags added twice.
+#
+# (Tegra needs different flags for SPL.
+# That's the reason why this file must be included from spl/Makefile too.
+# If we did not have Tegra SoCs, build system would be much simpler...)
+PLATFORM_RELFLAGS :=
+PLATFORM_CPPFLAGS :=
+PLATFORM_LDFLAGS :=
+LDFLAGS :=
+LDFLAGS_FINAL :=
+OBJCOPYFLAGS :=
#########################################################################
# Some architecture config.mk files need to know what CPUDIR is set to,
#########################################################################
-RELFLAGS= $(PLATFORM_RELFLAGS)
+RELFLAGS := $(PLATFORM_RELFLAGS)
OBJCOPYFLAGS += --gap-fill=0xff
-CPPFLAGS = $(RELFLAGS)
-CPPFLAGS += -pipe $(PLATFORM_CPPFLAGS)
+PLATFORM_CPPFLAGS += $(RELFLAGS)
+PLATFORM_CPPFLAGS += -pipe
LDFLAGS += $(PLATFORM_LDFLAGS)
LDFLAGS_FINAL += -Bstatic
+
+export PLATFORM_CPPFLAGS
+export RELFLAGS
+export LDFLAGS_FINAL
+export CONFIG_STANDALONE_LOAD_ADDR
*p++ = in_be32((u32 *)(base + NDFC_DATA));
}
-#ifndef CONFIG_NAND_SPL
/*
* Don't use these speedup functions in NAND boot image, since the image
* has to fit into 4kByte.
}
-#endif /* #ifndef CONFIG_NAND_SPL */
-
void board_nand_select_device(struct nand_chip *nand, int chip)
{
/*
nand->options |= NAND_BUSWIDTH_16;
#endif
-#ifndef CONFIG_NAND_SPL
nand->write_buf = ndfc_write_buf;
nand->verify_buf = ndfc_verify_buf;
nand->read_byte = ndfc_read_byte;
chip++;
-#else
- /*
- * Setup EBC (CS0 only right now)
- */
- mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG);
-
- mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
- mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
-#endif
return 0;
}
static struct phy_driver AR8021_driver = {
.name = "AR8021",
.uid = 0x4dd040,
- .mask = 0x4fffff,
+ .mask = 0x4ffff0,
.features = PHY_GBIT_FEATURES,
.config = ar8021_config,
.startup = genphy_startup,
memcpy(msg, &packet_len, sizeof(packet_len));
memcpy(msg + sizeof(packet_len), (void *)packet, length);
- if (length & 1)
- length++;
err = usb_bulk_msg(dev->pusb_dev,
usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2
extra-$(CONFIG_MPC5xxx) += interrupt
extra-$(CONFIG_8xx) += test_burst timer
-extra-$(CONFIG_8260) += mem_to_mem_idma2intr
+extra-$(CONFIG_MPC8260) += mem_to_mem_idma2intr
extra-$(CONFIG_PPC) += sched
#
# relocatable executable. The relocation data is not needed, and
# also causes the entry point of the standalone application to be
# inconsistent.
-ifeq ($(ARCH),powerpc)
-# FIX ME
-CPPFLAGS := $(filter-out $(RELFLAGS), $(CPPFLAGS))
+ifeq ($(CONFIG_PPC),y)
+PLATFORM_CPPFLAGS := $(filter-out $(RELFLAGS),$(PLATFORM_CPPFLAGS))
endif
# We don't want gcc reordering functions if possible. This ensures that an
unsigned long bi_dsp_freq; /* dsp core frequency */
unsigned long bi_ddr_freq; /* ddr frequency */
#endif
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \
|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
#include <mpc5xxx.h>
#elif defined(CONFIG_MPC512X)
#include <asm/immap_512x.h>
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
#if defined(CONFIG_MPC8247) \
|| defined(CONFIG_MPC8248) \
|| defined(CONFIG_MPC8271) \
|| defined(CONFIG_MPC8272)
#define CONFIG_MPC8272_FAMILY 1
#endif
-#if defined(CONFIG_MPC8272_FAMILY)
-#define CONFIG_MPC8260 1
-#endif
#include <asm/immap_8260.h>
#endif
#ifdef CONFIG_MPC86xx
int get_clocks_866 (void);
int sdram_adjust_866 (void);
int adjust_sdram_tbs_8xx (void);
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
int prt_8260_clks (void);
#elif defined(CONFIG_MPC5xxx)
int prt_mpc5xxx_clks (void);
#endif
/* $(CPU)/cpu_init.c */
-#if defined(CONFIG_8xx) || defined(CONFIG_8260)
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260)
void cpu_init_f (volatile immap_t *immr);
#endif
#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx)
#endif
int cpu_init_r (void);
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
int prt_8260_rsr (void);
#elif defined(CONFIG_MPC83xx)
int prt_83xx_rsr (void);
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_CPU86 1 /* ...on a CPU86 board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_CPU87 1 /* ...on a CPU87 board */
#define CONFIG_PCI
#define CONFIG_CPM2 1 /* Has a CPM2 */
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
#define CONFIG_MPC8272_FAMILY 1
#define CONFIG_IDS8247 1
#define CPU_ID_STR "MPC8247"
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */
#define CONFIG_SYS_TEXT_BASE 0xffb00000
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MPC8260 /* This is an MPC8260 CPU */
#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */
#define CONFIG_CPM2 1 /* Has a CPM2 */
* details. :-(
*/
#define CONFIG_MPC8272 1
-#else
-#define CONFIG_MPC8260 1
#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_MPC8266ADS 1 /* ...on motorola ADS board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
#define CONFIG_PM826 1 /* ...on a PM8260 module */
#define CONFIG_CPM2 1 /* Has a CPM2 */
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
#define CONFIG_PM828 1 /* ...on a PM828 module */
#define CONFIG_CPM2 1 /* Has a CPM2 */
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
-#else
-#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
-#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
-#endif
/*-----------------------------------------------------------------------
* RTC
#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
#endif
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller. sr - 2006-08-25
- */
-#if defined (CONFIG_NAND_U_BOOT)
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
-#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
-#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
-
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 16
-#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
-#endif
#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
/* 440EPx errata CHIP 11 */
/*
* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_NAND_CS 2 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
/* Memory Bank 2 (NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x018003c0
#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
-#else
-#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
-/* Memory Bank 2 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x03017200
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH_BASE | 0xda000)
-
-/* Memory Bank 0 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x018003c0
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
-#endif
/* Memory Bank 1 (RESET) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x7f817200 /* 0x03017200 */
*
*****************************************************************************/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
#ifdef CONFIG_MPC8248
#define CPU_ID_STR "MPC8248"
#else
-#define CONFIG_MPC8260
#define CPU_ID_STR "MPC8250"
#endif /* CONFIG_MPC8248 */
#define CONFIG_SYS_TEXT_BASE 0x40000000
-#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
#if 0
#define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
#define CONFIG_MPC8272_FAMILY 1
#define CONFIG_TQM8272 1
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */
#define CONFIG_SYS_TEXT_BASE 0xFE000000
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#else
-#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
-#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
-#endif
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#else
-/*
- * No NOR-flash on Acadia when NAND-booting. We need to undef the
- * NOR device-tree fixup code as well, since flash_info is not defined
- * in this case.
- */
-#define CONFIG_SYS_NO_FLASH 1
-#undef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-#endif
-
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller. sr - 2006-08-25
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
-#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
-#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
-
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 16
-#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
/*-----------------------------------------------------------------------
* RAM (CRAM)
*----------------------------------------------------------------------*/
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_PPC_OLD \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
- CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=fff10000\0" \
"ramdisk_addr=fff20000\0" \
"kozio=bootm ffc60000\0" \
#define CONFIG_CMD_NAND
#define CONFIG_CMD_USB
-/*
- * No NOR on Acadia when NAND-booting
- */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#endif
-
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_NAND_CS 3
/* Memory Bank 0 (Flash) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x03337200
/* Memory Bank 2 (CRAM) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x030400c0
#define CONFIG_SYS_EBC_PB2CR 0x020bc000
-#else
-#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
-/* Memory Bank 0 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x018003c0
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
-
-/*
- * When NAND-booting the CRAM EBC setup must be done in sync mode, since the
- * NAND-SPL already initialized the CRAM and EBC to sync mode.
- */
-/* Memory Bank 1 (CRAM) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x9C0201C0
-#define CONFIG_SYS_EBC_PB1CR 0x000bc000
-
-/* Memory Bank 2 (CRAM) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x9C0201C0
-#define CONFIG_SYS_EBC_PB2CR 0x020bc000
-#endif
/* Memory Bank 4 (CPLD) initialization */
#define CONFIG_SYS_EBC_PB4AP 0x04006000
"cp.b ${fileaddr} " __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
-#define CONFIG_AMCC_DEF_ENV_NAND_UPD \
- "u-boot-nand=" __stringify(CONFIG_HOSTNAME) "/u-boot-nand.bin\0"\
- "nload=tftp 200000 ${u-boot-nand}\0" \
- "nupdate=nand erase 0 100000;nand write 200000 0 100000\0" \
- "nupd=run nload nupdate\0"
-
#endif /* __AMCC_COMMON_H */
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_ATC 1 /* ...on a ATC board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#else
-#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
-#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
-#endif
/*-----------------------------------------------------------------------
* FLASH related
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller. sr - 2006-08-25
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
-#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
-#define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
-
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 16
-#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_NAND_CS 1
-#else
-#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
-/* Memory Bank 0 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x018003c0
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
-#endif
/*-----------------------------------------------------------------------
* DDR SDRAM
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_PPC_OLD \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
- CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=fff00000\0" \
"ramdisk_addr=fff10000\0" \
""
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SYS_HUSH_PARSER
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 1
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/* define to enable run status via led */
/* #define CONFIG_STATUS_LED */
*/
#define CONFIG_MISC_INIT_R
#define CONFIG_UART_CONSOLE 0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 1
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
*/
#define CONFIG_MISC_INIT_R
#define CONFIG_UART_CONSOLE 0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
*/
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/* FLASH/ETHERNET uses the same async bank */
#define SHARED_RESOURCES 1
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/* Define if want to do post memory test */
#undef CONFIG_POST
*/
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 1
#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
#define CONFIG_ADI_GPIO2
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BAUDRATE 57600
#define CONFIG_SYS_PROMPT "Acvilon> "
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
* Misc Settings
*/
#define CONFIG_UART_CONSOLE 0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Run core 1 from L1 SRAM start address when init uboot on core 0
#define CONFIG_BOOTCOMMAND "run nandboot"
#define CONFIG_BOOTDELAY 2
#define CONFIG_LOADADDR 0x2000000
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
/*
* Define here the location of the environment variables (FLASH).
*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
-#else
-#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
-#define CONFIG_SYS_NOR_CS 3 /* NOR chip connected to CSx */
-#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
-#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
-#endif
-
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller. sr - 2006-08-25
- *
- * This is the first official implementation of booting from 2k page sized
- * NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8)
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */
- /* this addr */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) /* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (1 << 20) /* Size of RAM U-Boot image */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) /* NAND chip page size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
- /* NAND chip page count */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 /* Location of bad block marker*/
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE /* Fifth addr used (<=128MB) */
-
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
- 48, 49, 50, 51, 52, 53, 54, 55, \
- 56, 57, 58, 59, 60, 61, 62, 63}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
/*-----------------------------------------------------------------------
* FLASH related
/*------------------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT)
#if !defined(CONFIG_ARCHES)
/*
* NAND booting U-Boot version uses a fixed initialization, since the whole
#define CONFIG_SYS_SDRAM0_MMODE 0x00000432
#define CONFIG_SYS_SDRAM0_MEMODE 0x00000004
#endif /* !defined(CONFIG_ARCHES) */
-#endif /* !defined(CONFIG_NAND_U_BOOT) */
#define CONFIG_SYS_MBYTES_SDRAM 512 /* 512MB */
CONFIG_AMCC_DEF_ENV \
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
- CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=fc000000\0" \
"fdt_addr=fc1e0000\0" \
"ramdisk_addr=fc200000\0" \
* 0xfe00.0000 -> 4.ce00.0000
*/
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-/* Memory Bank 3 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x10055e00
-#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
-
-/* Memory Bank 0 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x018003c0
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
-#else
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x10055e00
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
#define CONFIG_SYS_EBC_PB3AP 0x018003c0
#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
#endif
-#endif /*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
#if !defined(CONFIG_ARCHES)
/* Memory Bank 2 (CPLD) initialization */
#define FLASHBOOT_ENV_SETTINGS \
"flashboot=flread 20040000 1000000 300000;" \
"bootm 0x1000000\0"
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
"flashboot=flread 20040000 1000000 3c0000;" \
"bootm 0x1000000\0"
#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
"flashboot=flread 20040000 1000000 300000;" \
"bootm 0x1000000\0"
#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_UART_CONSOLE 1
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
#define CONFIG_ADI_GPIO2
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_DBAU1X00 1
#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
*
*****************************************************************************/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MPC8260
#define CPU_ID_STR "MPC8270"
#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */
*
*****************************************************************************/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_GW8260 1 /* on an GW8260 Board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_HYMOD 1 /* ...on a Hymod board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
#define CONFIG_INCA_IP 1 /* on a INCA-IP Board */
#define CONFIG_XWAY_SWAP_BYTES
#define CONFIG_BAUDRATE 115200
#define CONFIG_MISC_INIT_R /* needed for MAC address */
#define CONFIG_UART_CONSOLE 0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
#undef CONFIG_SHOW_BOOT_PROGRESS
/* Enable this if bootretry required; currently it's disabled */
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#else
-#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
-#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
-#endif
/*-----------------------------------------------------------------------
* FLASH related
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 405EX the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from location 0xfffff000...0xffffffff the
- * NAND controller cannot be accessed since it is attached to CS0 too.
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
-#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
-#define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
-
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 16
-#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
*
* DDR Autocalibration Method_B is the default.
*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
#undef CONFIG_PPC4xx_DDR_METHOD_A
-#endif
#define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_PPC_OLD \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
- CONFIG_AMCC_DEF_ENV_NAND_UPD \
"logversion=2\0" \
"kernel_addr=fc000000\0" \
"fdt_addr=fc1e0000\0" \
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SNTP
-/*
- * Don't run the memory POST on the NAND-booting version. It will
- * overwrite part of the U-Boot image which is already loaded from NAND
- * to SDRAM.
- */
-#if defined(CONFIG_NAND_U_BOOT)
-#define CONFIG_SYS_POST_MEMORY_ON 0
-#else
#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
-#endif
/* POST support */
#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-/* booting from NAND, so NAND chips select has to be on CS 0 */
-#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
-
-/* Memory Bank 1 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x05806500
-#define CONFIG_SYS_EBC_PB1CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 0 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x018003c0
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1e000)
-#else
#define CONFIG_SYS_NAND_CS 1 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
/* Memory Bank 1 (NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x018003c0
#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_ADDR | 0x1e000)
-#endif
/* Memory Bank 2 (FPGA) initialization */
#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_ENABLED | \
* (easy to change)
*/
-#define CONFIG_8260 1
-#define CONFIG_MPC8260 1
#define CONFIG_MUAS3001 1
#define CONFIG_SYS_TEXT_BASE 0xFF000000
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_PB1X00 1
#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
*
*****************************************************************************/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
#define CONFIG_BOOTCOMMAND "run nandboot"
#define CONFIG_BOOTDELAY 2
#define CONFIG_LOADADDR 0x2000000
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 /* MIPS32 CPU core */
#define CONFIG_QEMU_MIPS
#define CONFIG_MISC_INIT_R
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS64 /* MIPS64 CPU core */
#define CONFIG_QEMU_MIPS
#define CONFIG_MISC_INIT_R
CONFIG_AMCC_DEF_ENV \
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
- CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=fc000000\0" \
"fdt_addr=fc1e0000\0" \
"ramdisk_addr=fc200000\0" \
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
*
*****************************************************************************/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_SACSng 1 /* munged for the SACSng */
#define CONFIG_CPM2 1 /* Has a CPM2 */
/*
* Environment
*/
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-#define CONFIG_ENV_IS_IN_NAND /* use NAND for environ vars */
-#define CONFIG_ENV_IS_EMBEDDED /* use embedded environment */
-#elif defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */
#define CONFIG_ENV_SIZE (8 << 10)
/*
#endif
#endif /* CONFIG_CMD_FLASH */
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller. sr - 2006-08-25
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */
- /* this addr */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
-#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
-#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
-
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 16
-#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
/*
* DDR SDRAM
*/
#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
- !defined(CONFIG_SYS_RAMBOOT)
+#if !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#endif
#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_PPC_OLD \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
- CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=FC000000\0" \
"ramdisk_addr=FC180000\0" \
""
* overwrite part of the U-Boot image which is already loaded from NAND
* to SDRAM.
*/
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_SYS_POST_MEMORY_ON 0
#else
#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
/*
* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
- !defined(CONFIG_SYS_RAMBOOT)
+#if !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x03017200
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
"flashboot=flread 20040000 1000000 300000;" \
"bootm 0x1000000\0"
#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
+#ifdef CONFIG_SPL_BUILD
+# define CONFIG_USE_PRIVATE_LIBGCC
+#endif
+
#define CONFIG_SYS_GENERIC_BOARD
/* Misc utility code */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 /* MIPS 4Kc CPU core */
#define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
*/
int os_close(int fd);
+/**
+ * Access to the OS unlink() system call
+ *
+ * \param pathname Path of file to delete
+ * \return 0 for success, other for error
+ */
+int os_unlink(const char *pathname);
+
/**
* Access to the OS exit() system call
*
#define PLPRCR 0x00000284
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
#define HID2 1011
* @sector_size: Sector size of this device
* @nr_sectors: No.of sectors on this device
* @e_rd_cmd: Enum list for read commands
- * @flags: Importent param, for flash specific behaviour
+ * @flags: Important param, for flash specific behaviour
*/
struct spi_flash_params {
const char *name;
* @memory_map: Address of read-only SPI flash access
* @read: Flash read ops: Read len bytes at offset into buf
* Supported cmds: Fast Array Read
- * @write: Flash write ops: Write len bytes from buf into offeset
+ * @write: Flash write ops: Write len bytes from buf into offset
* Supported cmds: Page Program
* @erase: Flash erase ops: Erase len bytes from offset
* Supported cmds: Sector erase 4K, 32K, 64K
- * return 0 - Sucess, 1 - Failure
+ * return 0 - Success, 1 - Failure
*/
struct spi_flash {
struct spi_slave *spi;
obj-$(CONFIG_RANDOM_MACADDR) += rand.o
obj-$(CONFIG_BOOTP_RANDOM_DELAY) += rand.o
obj-$(CONFIG_CMD_LINK_LOCAL) += rand.o
+
+subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o cache.o
-COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
- $(nandobj)System.map
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)System.map: $(nandobj)u-boot-spl
- @$(NM) $< | \
- grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
- sort > $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)/cache.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@
-
-$(obj)/gpio.c:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/gpio.c $@
-
-$(obj)/ndfc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
-
-# from board directory
-$(obj)/memory.c:
- @rm -f $@
- ln -s $(SRCTREE)/board/amcc/acadia/memory.c $@
-
-$(obj)/pll.c:
- @rm -f $@
- ln -s $(SRCTREE)/board/amcc/acadia/pll.c $@
-
-# from nand_spl directory
-$(obj)/nand_boot.c:
- @rm -f $@
- ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
-
-# from drivers/mtd/nand directory
-$(obj)/nand_ecc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-# AMCC 405EZ Reference Platform (Acadia) board
-#
-
-#
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
-# in the last 4kBytes of memory space in cache.
-# We will copy this SPL into internal SRAM in start.S. So we set
-# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
-#
-CONFIG_SYS_TEXT_BASE = 0xf8004000
-
-# PAD_TO used to generate a 16kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
-PAD_TO = 0xf8008000
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc:common)
-SECTIONS
-{
- .resetvec 0xf8004ffc :
- {
- KEEP(*(.resetvec))
- } = 0xffff
-
- .text :
- {
- start.o (.text)
- nand_boot.o (.text)
- ndfc.o (.text)
-
- *(.text)
- *(.fixup)
- }
- _etext = .;
-
- .data :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- *(.data*)
- *(.sdata*)
- __got2_start = .;
- *(.got2)
- __got2_end = .;
- }
-
- _edata = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss)
- *(.bss)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
-}
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o init.o resetvec.o
-COBJS = nand_boot.o nand_ecc.o ndfc.o sdram.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)/ndfc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
-
-# from board directory
-$(obj)/init.S:
- @rm -f $@
- ln -s $(SRCTREE)/board/amcc/bamboo/init.S $@
-
-# from nand_spl directory
-$(obj)/nand_boot.c:
- @rm -f $@
- ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
-
-# from drivers/mtd/nand directory
-$(obj)/nand_ecc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-# AMCC 440EP Reference Platform (Bamboo) board
-#
-
-#
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
-# in the last 4kBytes of memory space in cache.
-# We will copy this SPL into instruction-cache in start.S. So we set
-# CONFIG_SYS_TEXT_BASE to starting address in i-cache here.
-#
-CONFIG_SYS_TEXT_BASE = 0x00800000
-
-# PAD_TO used to generate a 16kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
-PAD_TO = 0x00804000
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-static void wait_init_complete(void)
-{
- u32 val;
-
- do {
- mfsdram(SDRAM0_MCSTS, val);
- } while (!(val & 0x80000000));
-}
-
-/*
- * phys_size_t initdram(int board_type)
- *
- * As the name already indicates, this function is called very early
- * from start.S and configures the SDRAM with fixed values. This is needed,
- * since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has
- * not enough free space to implement the complete I2C SPD DDR autodetection
- * routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM
- * when booting from NAND flash.
- *
- * Note:
- * As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
- * DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
- * modules are still plugged in. So it is recommended to remove the DIMM
- * modules while using the NAND booting code with the fixed SDRAM setup!
- */
-phys_size_t initdram(int board_type)
-{
- /*
- * Soft-reset SDRAM controller.
- */
- mtsdr(SDR0_SRST, SDR0_SRST_DMC);
- mtsdr(SDR0_SRST, 0x00000000);
-
- /*
- * Disable memory controller.
- */
- mtsdram(SDRAM0_CFG0, 0x00000000);
-
- /*
- * Setup some default
- */
- mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
- mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
- mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
-
- /*
- * Following for CAS Latency = 2.5 @ 133 MHz PLB
- */
- mtsdram(SDRAM0_B0CR, 0x00082001);
- mtsdram(SDRAM0_TR0, 0x41094012);
- mtsdram(SDRAM0_TR1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
- mtsdram(SDRAM0_RTR, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
- mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/
-
- /*
- * Enable the controller, then wait for DCEN to complete
- */
- mtsdram(SDRAM0_CFG0, 0x80000000); /* DCEN=1, PMUD=0*/
- wait_init_complete();
-
- return CONFIG_SYS_MBYTES_SDRAM << 20;
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc:common)
-SECTIONS
-{
- .resetvec 0x00800FFC :
- {
- KEEP(*(.resetvec))
- } = 0xffff
-
- .text :
- {
- start.o (.text)
- init.o (.text)
- nand_boot.o (.text)
- sdram.o (.text)
- ndfc.o (.text)
-
- *(.text)
- *(.fixup)
- }
- _etext = .;
-
- .data :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- *(.data*)
- *(.sdata*)
- __got2_start = .;
- *(.got2)
- __got2_end = .;
- }
-
- _edata = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss)
- *(.bss)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
-}
+++ /dev/null
-#
-# (C) Copyright 2008
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS := start.o
-SOBJS += init.o
-SOBJS += resetvec.o
-COBJS := ddr2_fixed.o
-COBJS += nand_boot.o
-COBJS += nand_ecc.o
-COBJS += ndfc.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)/ndfc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
-
-# from board directory
-$(obj)/init.S:
- @rm -f $@
- ln -s $(SRCTREE)/board/amcc/canyonlands/init.S $@
-
-# from nand_spl directory
-$(obj)/nand_boot.c:
- @rm -f $@
- ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
-
-# from drivers/mtd/nand directory
-$(obj)/nand_ecc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
+++ /dev/null
-#
-# (C) Copyright 2008
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-# AMCC 460EX Reference Platform (Canyonlands) board
-#
-
-#
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On 460EX platforms the SPL is located at 0xfffff000...0xffffffff,
-# in the last 4kBytes of memory space in cache.
-# We will copy this SPL into internal SRAM in start.S. So we set
-# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
-#
-CONFIG_SYS_TEXT_BASE = 0xE3003000
-
-# PAD_TO used to generate a 128kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x20000
-PAD_TO = 0xE3023000
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2008-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-/*
- * This code can configure those two Crucial SODIMM's:
- *
- * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
- * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
- *
- */
-
-#define TEST_ADDR 0x10000000
-#define TEST_MAGIC 0x11223344
-
-static void wait_init_complete(void)
-{
- u32 val;
-
- do {
- mfsdram(SDRAM_MCSTAT, val);
- } while (!(val & 0x80000000));
-}
-
-static void ddr_start(void)
-{
- mtsdram(SDRAM_MCOPT2, 0x28000000);
- wait_init_complete();
-}
-
-static void ddr_init_common(void)
-{
- /*
- * Reset the DDR-SDRAM controller.
- */
- mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
- mtsdr(SDR0_SRST, 0x00000000);
-
- /*
- * These values are cloned from a running NOR booting
- * Canyonlands with SPD-DDR2 detection and calibration
- * enabled. This will only work for the same memory
- * configuration as used here:
- *
- */
- mtsdram(SDRAM_MCOPT2, 0x00000000);
- mtsdram(SDRAM_MODT0, 0x01000000);
- mtsdram(SDRAM_WRDTR, 0x82000823);
- mtsdram(SDRAM_CLKTR, 0x40000000);
- mtsdram(SDRAM_MB0CF, 0x00000201);
- mtsdram(SDRAM_RTR, 0x06180000);
- mtsdram(SDRAM_SDTR1, 0x80201000);
- mtsdram(SDRAM_SDTR2, 0x42103243);
- mtsdram(SDRAM_SDTR3, 0x0A0D0D16);
- mtsdram(SDRAM_MMODE, 0x00000632);
- mtsdram(SDRAM_MEMODE, 0x00000040);
- mtsdram(SDRAM_INITPLR0, 0xB5380000);
- mtsdram(SDRAM_INITPLR1, 0x82100400);
- mtsdram(SDRAM_INITPLR2, 0x80820000);
- mtsdram(SDRAM_INITPLR3, 0x80830000);
- mtsdram(SDRAM_INITPLR4, 0x80810040);
- mtsdram(SDRAM_INITPLR5, 0x80800532);
- mtsdram(SDRAM_INITPLR6, 0x82100400);
- mtsdram(SDRAM_INITPLR7, 0x8A080000);
- mtsdram(SDRAM_INITPLR8, 0x8A080000);
- mtsdram(SDRAM_INITPLR9, 0x8A080000);
- mtsdram(SDRAM_INITPLR10, 0x8A080000);
- mtsdram(SDRAM_INITPLR11, 0x80000432);
- mtsdram(SDRAM_INITPLR12, 0x808103C0);
- mtsdram(SDRAM_INITPLR13, 0x80810040);
- mtsdram(SDRAM_RDCC, 0x40000000);
- mtsdram(SDRAM_RQDC, 0x80000038);
- mtsdram(SDRAM_RFDC, 0x00000257);
-
- mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */
-}
-
-phys_size_t initdram(int board_type)
-{
- /*
- * First try init for this module:
- *
- * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
- */
-
- ddr_init_common();
-
- /*
- * Crucial CT6464AC667.8FB - 512MB SO-DIMM
- */
- mtdcr(SDRAM_R0BAS, 0x0000F800);
- mtdcr(SDRAM_R1BAS, 0x0400F800);
- mtsdram(SDRAM_MCOPT1, 0x05122000);
- mtsdram(SDRAM_CODT, 0x02800021);
- mtsdram(SDRAM_MB1CF, 0x00000201);
-
- ddr_start();
-
- /*
- * Now test if the dual-ranked module is really installed
- * by checking an address in the upper 256MByte region
- */
- out_be32((void *)TEST_ADDR, TEST_MAGIC);
- if (in_be32((void *)TEST_ADDR) != TEST_MAGIC) {
- /*
- * The test failed, so we assume that the single
- * ranked module is installed:
- *
- * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
- */
-
- ddr_init_common();
-
- mtdcr(SDRAM_R0BAS, 0x0000F000);
- mtsdram(SDRAM_MCOPT1, 0x05322000);
- mtsdram(SDRAM_CODT, 0x00800021);
-
- ddr_start();
- }
-
- return CONFIG_SYS_MBYTES_SDRAM << 20;
-}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc:common)
-SECTIONS
-{
- .resetvec 0xE3003FFC :
- {
- KEEP(*(.resetvec))
- } = 0xffff
-
- .text :
- {
- start.o (.text)
- init.o (.text)
- nand_boot.o (.text)
- ddr2_fixed.o (.text)
- ndfc.o (.text)
-
- *(.text)
- *(.fixup)
- }
- _etext = .;
-
- .data :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- *(.data*)
- *(.sdata*)
- __got2_start = .;
- *(.got2)
- __got2_end = .;
- }
-
- _edata = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss)
- *(.bss)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
-}
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o cache.o
-COBJS = 44x_spd_ddr2.o nand_boot.o nand_ecc.o ndfc.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)/44x_spd_ddr2.c: $(obj)/ecc.h
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c $@
-
-$(obj)/cache.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@
-
-$(obj)/ecc.h:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/ecc.h $@
-
-$(obj)/ndfc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
-
-# from nand_spl directory
-$(obj)/nand_boot.c:
- @rm -f $@
- ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
-
-# from drivers/nand directory
-$(obj)/nand_ecc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-# AMCC 405EX Reference Platform (Kilauea) board
-#
-
-#
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
-# in the last 4kBytes of memory space in cache.
-# We will copy this SPL into SDRAM since we can't access the NAND
-# controller at CS0 while running from this location. So we set
-# CONFIG_SYS_TEXT_BASE to starting address in SDRAM here.
-#
-CONFIG_SYS_TEXT_BASE = 0x00800000
-
-# PAD_TO used to generate a 16kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
-PAD_TO = 0x00804000
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc:common)
-SECTIONS
-{
- .resetvec 0x00800FFC :
- {
- KEEP(*(.resetvec))
- } = 0xffff
-
- .text :
- {
- start.o (.text)
- nand_boot.o (.text)
- ndfc.o (.text)
-
- *(.text)
- *(.fixup)
- }
- _etext = .;
-
- .data :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- *(.data*)
- *(.sdata*)
- __got2_start = .;
- *(.got2)
- __got2_end = .;
- }
-
- _edata = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss)
- *(.bss)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
-}
+++ /dev/null
-#
-# (C) Copyright 2006-2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o init.o resetvec.o
-COBJS = denali_data_eye.o nand_boot.o nand_ecc.o ndfc.o sdram.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)/denali_data_eye.c:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/denali_data_eye.c $@
-
-$(obj)/ndfc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
-
-# from board directory
-$(obj)/init.S:
- @rm -f $@
- ln -s $(SRCTREE)/board/amcc/sequoia/init.S $@
-
-$(obj)/sdram.c:
- @rm -f $@
- @rm -f $(obj)/sdram.h
- ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $@
- ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)/sdram.h
-
-# from nand_spl directory
-$(obj)/nand_boot.c:
- @rm -f $@
- ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
-
-# from drivers/mtd/nand directory
-$(obj)/nand_ecc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
+++ /dev/null
-#
-# (C) Copyright 2006
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-# AMCC 440EPx Reference Platform (Sequoia) board
-#
-
-#
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
-# in the last 4kBytes of memory space in cache.
-# We will copy this SPL into internal SRAM in start.S. So we set
-# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
-#
-CONFIG_SYS_TEXT_BASE = 0xE0013000
-
-# PAD_TO used to generate a 16kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
-PAD_TO = 0xE0017000
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2006-2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc:common)
-SECTIONS
-{
- .resetvec 0xE0013FFC :
- {
- KEEP(*(.resetvec))
- } = 0xffff
-
- .text :
- {
- start.o (.text)
- init.o (.text)
- nand_boot.o (.text)
- sdram.o (.text)
- ndfc.o (.text)
-
- *(.text)
- *(.fixup)
- }
- _etext = .;
-
- .data :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- *(.data*)
- *(.sdata*)
- __got2_start = .;
- *(.got2)
- __got2_end = .;
- }
-
- _edata = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss)
- *(.bss)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
-}
include scripts/Kbuild.include
-# Added for U-Boot
-# We must include config.mk after Kbuild.include
-# so that some config.mk can use cc-option.
-include config.mk
-
# For backward compatibility check that these variables do not change
save-cflags := $(CFLAGS)
kbuild-file := $(if $(wildcard $(kbuild-dir)/Kbuild),$(kbuild-dir)/Kbuild,$(kbuild-dir)/Makefile)
include $(kbuild-file)
+# Added for U-Boot
+asflags-y += $(PLATFORM_CPPFLAGS)
+ccflags-y += $(PLATFORM_CPPFLAGS)
+cppflags-y += $(PLATFORM_CPPFLAGS)
+
# If the save-* variables changed error out
ifeq ($(KBUILD_NOPEDANTIC),)
ifneq ("$(save-cflags)","$(CFLAGS)")
modname_flags = $(if $(filter 1,$(words $(modname))),\
-D"KBUILD_MODNAME=KBUILD_STR($(call name-fix,$(modname)))")
-# U-Boot also uses $(CPPFLAGS)
-orig_c_flags = $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(KBUILD_CFLAGS) $(KBUILD_SUBDIR_CCFLAGS) \
+orig_c_flags = $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(KBUILD_SUBDIR_CCFLAGS) \
$(ccflags-y) $(CFLAGS_$(basetarget).o)
_c_flags = $(filter-out $(CFLAGS_REMOVE_$(basetarget).o), $(orig_c_flags))
-_a_flags = $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(KBUILD_AFLAGS) $(KBUILD_SUBDIR_ASFLAGS) \
+_a_flags = $(KBUILD_CPPFLAGS) $(KBUILD_AFLAGS) $(KBUILD_SUBDIR_ASFLAGS) \
$(asflags-y) $(AFLAGS_$(basetarget).o)
-_cpp_flags = $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(cppflags-y) $(CPPFLAGS_$(@F))
+_cpp_flags = $(KBUILD_CPPFLAGS) $(cppflags-y) $(CPPFLAGS_$(@F))
#
# Enable gcov profiling flags for a file, directory or for all files depending
KBUILD_CPPFLAGS += -DCONFIG_TPL_BUILD
endif
-# Enable garbage collection of un-used sections for SPL
-KBUILD_CFLAGS += -ffunction-sections -fdata-sections
-LDFLAGS_FINAL += --gc-sections
-
ifeq ($(CONFIG_TPL_BUILD),y)
export CONFIG_TPL_BUILD
SPL_BIN := u-boot-tpl
include $(TOPDIR)/config.mk
+# Enable garbage collection of un-used sections for SPL
+KBUILD_CFLAGS += -ffunction-sections -fdata-sections
+LDFLAGS_FINAL += --gc-sections
+
# FIX ME
-c_flags := $(KBUILD_CFLAGS) $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(UBOOTINCLUDE) $(NOSTDINC_FLAGS)
+cpp_flags := $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) $(UBOOTINCLUDE) \
+ $(NOSTDINC_FLAGS)
+c_flags := $(KBUILD_CFLAGS) $(cpp_flags)
# Auto-generate the spl-autoconf.mk file (which is included by all makefiles for SPL)
quiet_cmd_autoconf = GEN $@
libs-y := $(patsubst %/, %/built-in.o, $(libs-y))
# Add GCC lib
-ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
+ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y)
PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a
PLATFORM_LIBS := $(filter-out %/lib.a, $(filter-out -lgcc, $(PLATFORM_LIBS))) $(PLATFORM_LIBGCC)
endif
$(u-boot-spl-dirs):
$(Q)$(MAKE) $(build)=$@
-# FIX ME
-cpp_flags := $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(UBOOTINCLUDE) $(NOSTDINC_FLAGS)
-
quiet_cmd_cpp_lds = LDS $@
cmd_cpp_lds = $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ \
-x assembler-with-cpp -P -o $@ $<
#define DEBUG
#include <common.h>
+#ifdef CONFIG_SANDBOX
+#include <os.h>
+#endif
static const char test_cmd[] = "setenv list 1\n setenv list ${list}2; "
"setenv list ${list}3\0"
run_command("if test " expr " ; then " \
"setenv " #name "_" #expected_result " y; else " \
"setenv " #name "_" #expected_result " n; fi", 0); \
- assert(!strcmp(#expected_result, getenv(#name "_" #expected_result)));
+ assert(!strcmp(#expected_result, getenv(#name "_" #expected_result))); \
+ setenv(#name "_" #expected_result, NULL);
/* Basic operators */
HUSH_TEST(streq, "aaa = aaa", y);
HUSH_TEST(or_1_0_inv_inv, "! ! aaa = aaa -o ! ! bbb != bbb", y);
HUSH_TEST(or_1_1_inv_inv, "! ! aaa = aaa -o ! ! bbb = bbb", y);
+ setenv("ut_var_nonexistent", NULL);
+ setenv("ut_var_exists", "1");
+ HUSH_TEST(z_varexp_quoted, "-z \"$ut_var_nonexistent\"", y);
+ HUSH_TEST(z_varexp_quoted, "-z \"$ut_var_exists\"", n);
+ setenv("ut_var_exists", NULL);
+
+ run_command("setenv ut_var_space \" \"", 0);
+ assert(!strcmp(getenv("ut_var_space"), " "));
+ run_command("setenv ut_var_test $ut_var_space", 0);
+ assert(!getenv("ut_var_test"));
+ run_command("setenv ut_var_test \"$ut_var_space\"", 0);
+ assert(!strcmp(getenv("ut_var_test"), " "));
+ run_command("setenv ut_var_test \" 1${ut_var_space}${ut_var_space} 2 \"", 0);
+ assert(!strcmp(getenv("ut_var_test"), " 1 2 "));
+ setenv("ut_var_space", NULL);
+ setenv("ut_var_test", NULL);
+
#ifdef CONFIG_SANDBOX
- /*
- * File existence
- * This assume U-Boot sandbox is run from the U-Boot build directory
- */
- HUSH_TEST(e, "-e host - u-boot", y);
+ /* File existence */
+ HUSH_TEST(e, "-e host - creating_this_file_breaks_uboot_unit_test", n);
+ run_command("sb save host - creating_this_file_breaks_uboot_unit_test 0 1", 0);
+ HUSH_TEST(e, "-e host - creating_this_file_breaks_uboot_unit_test", y);
+ /* Perhaps this could be replaced by an "rm" shell command one day */
+ assert(!os_unlink("creating_this_file_breaks_uboot_unit_test"));
HUSH_TEST(e, "-e host - creating_this_file_breaks_uboot_unit_test", n);
#endif
#endif
projects / karo-tx-uboot.git / commitdiff