-#if PHYS_SDRAM_1_WIDTH == 16
-#define MXC_DCD_ITEM_16(addr, val) mxc_dcd_item (addr), (val)
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 16
+#define MXC_DCD_ITEM_16(addr, val) mxc_dcd_item (addr), (val)
#define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
#else
#define MXC_DCD_ITEM_16(addr, val)
#define MXC_DCD_CMD_CHK_16(type, flags, addr, mask)
#endif
#define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
#else
#define MXC_DCD_ITEM_16(addr, val)
#define MXC_DCD_CMD_CHK_16(type, flags, addr, mask)
#endif
-#if PHYS_SDRAM_1_WIDTH > 16
-#define MXC_DCD_ITEM_32(addr, val) mxc_dcd_item (addr), (val)
+#if CONFIG_SYS_SDRAM_BUS_WIDTH > 16
+#define MXC_DCD_ITEM_32(addr, val) mxc_dcd_item (addr), (val)
#define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
#else
#define MXC_DCD_ITEM_32(addr, val)
#define MXC_DCD_CMD_CHK_32(type, flags, addr, mask)
#endif
#define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
#else
#define MXC_DCD_ITEM_32(addr, val)
#define MXC_DCD_CMD_CHK_32(type, flags, addr, mask)
#endif
-#if PHYS_SDRAM_1_WIDTH == 64
-#define MXC_DCD_ITEM_64(addr, val) mxc_dcd_item (addr), (val)
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 64
+#define MXC_DCD_ITEM_64(addr, val) mxc_dcd_item (addr), (val)
#define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
#else
#define MXC_DCD_ITEM_64(addr, val)
#define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
#else
#define MXC_DCD_ITEM_64(addr, val)
#define DSE1_VAL 6 /* Drive Strength for DATA lines */
#define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */
#else
#define DSE1_VAL 6 /* Drive Strength for DATA lines */
#define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */
#else
#define MMDC2_MPWLGCR 0x021b4808
#define MMDC2_MPWLDECTRL0 0x021b480c
#define MMDC2_MPWLDECTRL1 0x021b4810
#define MMDC2_MPWLGCR 0x021b4808
#define MMDC2_MPWLDECTRL0 0x021b480c
#define MMDC2_MPWLDECTRL1 0x021b4810
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
#endif
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
#endif
MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000013)
MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)
MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000013)
MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */