writeb(CLKCTRL_FRAC_CLKGATE,
&clkctrl_regs->hw_clkctrl_frac1_clr[CLKCTRL_FRAC1_PIX]);
- writel(CLKCTRL_DIS_LCDIF_CLKGATE,
- &clkctrl_regs->hw_clkctrl_lcdif_set);
- clrsetbits_le32(&clkctrl_regs->hw_clkctrl_lcdif,
- CLKCTRL_DIS_LCDIF_DIV_MASK | CLKCTRL_DIS_LCDIF_CLKGATE,
- k_best << CLKCTRL_DIS_LCDIF_DIV_OFFSET);
+ /* The i.MX28 Ref. Manual states:
+ * CLK_DIS_LCDIF Gate. If set to 1, CLK_DIS_LCDIF is gated off.
+ * 0: CLK_DIS_LCDIF is not gated.
+ * When this bit is modified, or when it is high,
+ * the DIV field should not change its value.
+ * The DIV field can change ONLY when this clock gate bit field is low.
+ * Note: This register does not have set/clear/toggle functionality!
+ */
+ /* clear CLKCTRL_DIS_LCDIF_CLKGATE */
+ writel(0, &clkctrl_regs->hw_clkctrl_lcdif);
+ writel(k_best << CLKCTRL_DIS_LCDIF_DIV_OFFSET,
+ &clkctrl_regs->hw_clkctrl_lcdif);
while (readl(&clkctrl_regs->hw_clkctrl_lcdif) & CLKCTRL_DIS_LCDIF_BUSY)
;
mxs_reg_32(hw_clkctrl_pll2ctrl0); /* 0x40 */
mxs_reg_32(hw_clkctrl_cpu); /* 0x50 */
mxs_reg_32(hw_clkctrl_hbus); /* 0x60 */
- mxs_reg_32(hw_clkctrl_xbus); /* 0x70 */
+ reg_32(hw_clkctrl_xbus); /* 0x70 */
mxs_reg_32(hw_clkctrl_xtal); /* 0x80 */
- mxs_reg_32(hw_clkctrl_ssp0); /* 0x90 */
- mxs_reg_32(hw_clkctrl_ssp1); /* 0xa0 */
- mxs_reg_32(hw_clkctrl_ssp2); /* 0xb0 */
- mxs_reg_32(hw_clkctrl_ssp3); /* 0xc0 */
- mxs_reg_32(hw_clkctrl_gpmi); /* 0xd0 */
- mxs_reg_32(hw_clkctrl_spdif); /* 0xe0 */
- mxs_reg_32(hw_clkctrl_emi); /* 0xf0 */
- mxs_reg_32(hw_clkctrl_saif0); /* 0x100 */
- mxs_reg_32(hw_clkctrl_saif1); /* 0x110 */
- mxs_reg_32(hw_clkctrl_lcdif); /* 0x120 */
- mxs_reg_32(hw_clkctrl_etm); /* 0x130 */
- mxs_reg_32(hw_clkctrl_enet); /* 0x140 */
- mxs_reg_32(hw_clkctrl_hsadc); /* 0x150 */
- mxs_reg_32(hw_clkctrl_flexcan); /* 0x160 */
+ reg_32(hw_clkctrl_ssp0); /* 0x90 */
+ reg_32(hw_clkctrl_ssp1); /* 0xa0 */
+ reg_32(hw_clkctrl_ssp2); /* 0xb0 */
+ reg_32(hw_clkctrl_ssp3); /* 0xc0 */
+ reg_32(hw_clkctrl_gpmi); /* 0xd0 */
+ reg_32(hw_clkctrl_spdif); /* 0xe0 */
+ reg_32(hw_clkctrl_emi); /* 0xf0 */
+ reg_32(hw_clkctrl_saif0); /* 0x100 */
+ reg_32(hw_clkctrl_saif1); /* 0x110 */
+ reg_32(hw_clkctrl_lcdif); /* 0x120 */
+ reg_32(hw_clkctrl_etm); /* 0x130 */
+ reg_32(hw_clkctrl_enet); /* 0x140 */
+ reg_32(hw_clkctrl_hsadc); /* 0x150 */
+ reg_32(hw_clkctrl_flexcan); /* 0x160 */
reg_32(reserved[4]); /* 0x170-0x1a0 */
mxs_reg_8(hw_clkctrl_frac0); /* 0x1b0 */
mxs_reg_8(hw_clkctrl_frac1); /* 0x1c0 */
mxs_reg_32(hw_clkctrl_clkseq); /* 0x1d0 */
- mxs_reg_32(hw_clkctrl_reset); /* 0x1e0 */
- mxs_reg_32(hw_clkctrl_status); /* 0x1f0 */
- mxs_reg_32(hw_clkctrl_version); /* 0x200 */
+ reg_32(hw_clkctrl_reset); /* 0x1e0 */
+ reg_32(hw_clkctrl_status); /* 0x1f0 */
+ reg_32(hw_clkctrl_version); /* 0x200 */
};
#endif
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
#include <jffs2/jffs2.h>
#include <mtd_node.h>
-struct node_info nodes[] = {
+static struct node_info nodes[] = {
{ "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
+ { "ti,am3352-gpmc", MTD_DEV_TYPE_NAND, },
};
#else
int checkboard(void)
{
tx51_print_cpuinfo();
-
- printf("Board: Ka-Ro TX51-%sxx%s\n",
- TX51_MOD_PREFIX, TX51_MOD_SUFFIX);
-
+#if CONFIG_NR_DRAM_BANKS > 1
+ printf("Board: Ka-Ro TX51-8xx1 | TX51-8xx2\n");
+#else
+ printf("Board: Ka-Ro TX51-8xx0\n");
+#endif
return 0;
}
ima3-mx53 arm armv7 ima3-mx53 esg mx5 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg
vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
cgtqmx6qeval arm armv7 cgtqmx6eval congatec mx6 cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
-tx51-6xx0 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=600,NR_DRAM_BANKS=1,SYS_SDRAM_CLK=166
-tx51-6xx1 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=600,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=200
-tx51-6xx2 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=600,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=166
-tx51-8xx0 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=1,SYS_SDRAM_CLK=166
-tx51-8xx1 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=200
-tx51-8xx2 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=166
+tx51-8xx0 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=1
+tx51-8xx1_2 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=2
tx53-xx30 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=1
tx53-xx31 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=2
tx6u-8x10 arm armv7 tx6 karo mx6 tx6:MX6DL
Building U-Boot
---------------
-Note: There are currently six variants of the TX51 module, that
+Note: There are currently three variants of the TX51 module, that
require slightly different U-Boot configurations. They are
- distinguished through the first and last digit of the module
- name suffix. Replace the '?' in the following description with
- the corresponding numbers from your TX51 module.
- E.g. TX51-8021 => 'make tx51-8xx1_config'
+ distinguished through the last digit of the module name
+ suffix. The following table lists the module names and the
+ corresponding U-Boot configuration name:
+
+ Module Name U-Boot config
+ ---------------------------------------
+ TX51-8xx0 tx51-8xx0_config
+ TX51-8xx1 tx51-8xx1_2_config
+ TX51-8xx2 tx51-8xx1_2_config
Unpacking the source
--------------------
----------------
export ARCH=arm
export CROSS_COMPILE=arm-cortexa8-linux-gnueabi-
-make tx51-?xx?_config (see above Note!)
+make tx51-8xx?_config (see above Note!)
make
#include <common.h>
#include <malloc.h>
#include <video_fb.h>
+#include <mxcfb.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#define PS2KHZ(ps) (1000000000UL / (ps))
+DECLARE_GLOBAL_DATA_PTR;
+
static GraphicDevice panel;
/*
* Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
* setenv videomode
* video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
- * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
+ * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
*/
static void mxs_lcd_init(GraphicDevice *panel,
struct ctfb_res_modes *mode, int bpp)
{
struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
- uint32_t word_len = 0, bus_width = 0;
- uint8_t valid_data = 0;
+ uint32_t word_len, bus_width;
+ uint8_t valid_data;
+ uint32_t vctrl0 = 0;
/* Kick in the LCDIF clock */
mxs_set_lcdclk(PS2KHZ(mode->pixclock));
bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
valid_data = 0xf;
break;
+ default:
+ printf("Invalid color depth: %d\n", bpp);
+ hang();
}
writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
®s->hw_lcdif_transfer_count);
- writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
+ if (!(mode->sync & FB_SYNC_OE_LOW_ACT))
+ vctrl0 |= LCDIF_VDCTRL0_ENABLE_POL;
+
+ if (mode->sync & FB_SYNC_CLK_LAT_FALL)
+ vctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL;
+
+ if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
+ vctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
+
+ if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
+ vctrl0 |= LCDIF_VDCTRL0_VSYNC_POL;
+
+ writel(vctrl0 | LCDIF_VDCTRL0_ENABLE_PRESENT |
LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
mode->vsync_len, ®s->hw_lcdif_vdctrl0);
{
int bpp = -1;
char *penv;
- void *fb;
struct ctfb_res_modes mode;
puts("Video: ");
panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
- /* Allocate framebuffer */
- fb = malloc(panel.memSize);
- if (!fb) {
- printf("MXSFB: Error allocating framebuffer!\n");
- return NULL;
- }
-
- /* Wipe framebuffer */
- memset(fb, 0, panel.memSize);
-
- panel.frameAdrs = (u32)fb;
+ panel.frameAdrs = gd->fb_base;
printf("%s\n", panel.modeIdent);
/* Start framebuffer */
mxs_lcd_init(&panel, &mode, bpp);
- return (void *)&panel;
+ return &panel;
}
/*
* Memory configurations
*/
+#ifndef CONFIG_SYS_SDRAM_CLK
+#define CONFIG_SYS_SDRAM_CLK 166
+#endif
#define PHYS_SDRAM_1 0x90000000 /* Base address of bank 1 */
#define PHYS_SDRAM_1_SIZE SZ_128M
#if CONFIG_NR_DRAM_BANKS > 1
projects / karo-tx-uboot.git / commitdiff