COBJS-$(CONFIG_SPLASH_SCREEN) += splashimage.o
endif
COBJS-$(CONFIG_CMD_NAND) += nand.o
-COBJS-$(CONFIG_CMD_MMC) += mmc.o
+COBJS-$(CONFIG_ENV_IS_IN_MMC) += mmc.o
COBJS := $(COBJS-y)
SOBJS :=
}
#endif
-#ifdef CONFIG_CMD_MMC
+#ifdef CONFIG_ENV_IS_IN_MMC
int karo_load_mmc_part(const char *part, void *addr, size_t len);
#else
static inline int karo_load_mmc_part(const char *part, void *addr, size_t len)
#include <fdt_support.h>
#include <mmc.h>
#include <mxcfb.h>
+#include <fs.h>
+#include <fat.h>
+#include <malloc.h>
#include <linux/list.h>
#include <linux/fb.h>
#include <jffs2/load_kernel.h>
-#include <malloc.h>
#include "karo.h"
-#define CONFIG_MMC_BOOT_DEV 0
-
DECLARE_GLOBAL_DATA_PTR;
#define MAX_SEARCH_PARTITIONS 16
-static int find_efi_partition(const char *ifname, int devno, const char *part_str,
- block_dev_desc_t **dev_desc,
- disk_partition_t *info)
+static int find_partitions(const char *ifname, int devno, int fstype,
+ block_dev_desc_t **dev_desc, disk_partition_t *info)
{
int ret = -1;
char *dup_str = NULL;
* or user requested partition 0 (entire device).
*/
if (dd->part_type == PART_TYPE_UNKNOWN) {
- printf("** No partition table - %s %d **\n", ifname,
- devno);
+ printf("** No partition table on device %s %d **\n",
+ ifname, devno);
goto cleanup;
}
if (ret)
continue;
- if (strcmp((char *)info->name, part_str) == 0) {
+ if (fat_register_device(dd, p) == 0) {
part = p;
dd->log2blksz = LOG2(dd->blksz);
break;
}
}
if (!part) {
- printf("** No valid partitions found **\n");
+ printf("** No valid partition on device %s %d **\n",
+ ifname, devno);
ret = -1;
goto cleanup;
}
return ret;
}
+static int karo_mmc_find_part(struct mmc *mmc, const char *part, int devno,
+ disk_partition_t *part_info)
+{
+ int ret;
+ block_dev_desc_t *mmc_dev;
+
+ if (strcmp(part, "dtb") == 0) {
+ const int partnum = CONFIG_SYS_MMC_ENV_PART;
+
+ part_info->blksz = mmc->read_bl_len;
+ part_info->start = CONFIG_SYS_DTB_OFFSET / part_info->blksz;
+ part_info->size = CONFIG_SYS_DTB_PART_SIZE / part_info->blksz;
+ printf("Using virtual partition %s(%d) ["LBAF".."LBAF"]\n",
+ part, partnum, part_info->start,
+ part_info->start + part_info->size - 1);
+ return partnum;
+ }
+
+ ret = find_partitions("mmc", devno, FS_TYPE_FAT, &mmc_dev, part_info);
+ if (ret < 0) {
+ printf("No eMMC partition found: %d\n", ret);
+ return ret;
+ }
+ return 0;
+}
+
int karo_load_mmc_part(const char *part, void *addr, size_t len)
{
int ret;
struct mmc *mmc;
disk_partition_t part_info;
int devno = CONFIG_MMC_BOOT_DEV;
- uint blk_start, blk_cnt;
- block_dev_desc_t *mmc_dev;
+ lbaint_t blk_cnt;
+ int partnum;
mmc = find_mmc_device(devno);
if (!mmc) {
return -ENODEV;
}
- mmc_init(mmc);
-
- ret = find_efi_partition("mmc", devno, part, &mmc_dev, &part_info);
- if (ret < 0) {
- printf("eMMC partition '%s' not found: %d\n", part, ret);
- goto out;
+ if (mmc_init(mmc)) {
+ printf("Failed to init MMC device %d\n", devno);
+ return -EIO;
}
- mmc_switch_part(devno, ret);
-
- blk_start = 0;
- blk_cnt = DIV_ROUND_UP(len, part_info.blksz);
-
- debug("Found partition '%s': offset=%08x size=%08lx\n",
- part, blk_start, part_info.size);
- if (part_info.size < blk_cnt)
- blk_cnt = part_info.size;
-
- debug("Reading %u blks from MMC partition '%s' offset %u to %p\n",
- blk_cnt, part, blk_start, addr);
- ret = mmc->block_dev.block_read(devno, blk_start, blk_cnt, addr);
- if (ret == 0) {
- printf("Failed to read MMC partition %s\n", part);
- ret = -EIO;
+
+ blk_cnt = DIV_ROUND_UP(len, mmc->read_bl_len);
+
+ partnum = karo_mmc_find_part(mmc, part, devno, &part_info);
+ if (partnum > 0) {
+ if (part_info.start + blk_cnt < part_info.start) {
+ printf("%s: given length 0x%08x exceeds size of partition\n",
+ __func__, len);
+ return -EINVAL;
+ }
+ if (part_info.start + blk_cnt > mmc->block_dev.lba)
+ blk_cnt = mmc->block_dev.lba - part_info.start;
+
+ mmc_switch_part(devno, partnum);
+
+ memset(addr, 0xee, len);
+
+ debug("Reading 0x"LBAF" blks from MMC partition %d offset 0x"LBAF" to %p\n",
+ blk_cnt, partnum, part_info.start, addr);
+ ret = mmc->block_dev.block_read(devno, part_info.start, blk_cnt, addr);
+ if (ret == 0) {
+ printf("Failed to read MMC partition %s\n", part);
+ ret = -EIO;
+ goto out;
+ }
+ debug("Read %u (%u) byte from partition '%s' @ offset 0x"LBAF"\n",
+ ret * mmc->read_bl_len, len, part, part_info.start);
+ } else if (partnum == 0) {
+ int len_read;
+
+ printf("Reading file %s from mmc partition %d\n", part, 0);
+ len_read = fs_read(part, (ulong)addr, 0, len);
+ if (len_read < len) {
+ printf("Read only %u of %u bytes\n", len_read, len);
+ }
+ } else {
+ ret = partnum;
goto out;
}
- debug("Read %u byte from partition '%s' @ offset %08x\n",
- ret * mmc->read_bl_len, part, blk_start);
+ ret = 0;
out:
- mmc_switch_part(devno, 0);
+ if (partnum > 0)
+ mmc_switch_part(devno, 0);
return ret < 0 ? ret : 0;
}
#PLATFORM_CPPFLAGS += -Wno-unused-but-set-variable
PLATFORM_CPPFLAGS += -Werror
+ifeq ($(CONFIG_TX6_V2),)
# calculate U_BOOT_IMG_SIZE to be at least 3 eraseblocks larger than the maximum expected image size
CONFIG_SYS_NAND_BLOCK_SIZE := 131072
CONFIG_SYS_NAND_BLOCKS := 1024
ifneq ($(CONFIG_SYS_NAND_BLOCK_SIZE),)
CONFIG_U_BOOT_IMG_SIZE = $(shell echo 'e=$(CONFIG_SYS_NAND_BLOCK_SIZE);s=640*1024;s + (e - s % e) % e + 3*e' | bc)
-CONFIG_SYS_USERFS_SIZE = $(shell expr \( $(CONFIG_SYS_NAND_BLOCKS) - 9 \) \* $(CONFIG_SYS_NAND_BLOCK_SIZE) - $(CONFIG_U_BOOT_IMG_SIZE) - 36 \* 1048576)
-CONFIG_SYS_USERFS_SIZE2 = $(shell expr \( $(CONFIG_SYS_NAND_BLOCKS) - 12 \) \* $(CONFIG_SYS_NAND_BLOCK_SIZE) - $(CONFIG_U_BOOT_IMG_SIZE) - 36 \* 1048576)
+CONFIG_SYS_USERFS_SIZE = $(shell expr \( $(CONFIG_SYS_NAND_BLOCKS) - 12 \) \* $(CONFIG_SYS_NAND_BLOCK_SIZE) - $(CONFIG_U_BOOT_IMG_SIZE) - 36 \* 1048576)
+CONFIG_SYS_USERFS_SIZE2 = $(shell expr \( $(CONFIG_SYS_NAND_BLOCKS) - 15 \) \* $(CONFIG_SYS_NAND_BLOCK_SIZE) - $(CONFIG_U_BOOT_IMG_SIZE) - 36 \* 1048576)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_BLOCK_SIZE=$(CONFIG_SYS_NAND_BLOCK_SIZE)
PLATFORM_CPPFLAGS += -DCONFIG_U_BOOT_IMG_SIZE=$(CONFIG_U_BOOT_IMG_SIZE)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_ENV_PART_SIZE=$(shell printf "%uk" `expr 3 \* $(CONFIG_SYS_NAND_BLOCK_SIZE) / 1024`)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_USERFS_PART_SIZE=$(shell printf "%uk" `expr $(CONFIG_SYS_USERFS_SIZE) / 1024`)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_USERFS_PART_SIZE2=$(shell printf "%uk" `expr $(CONFIG_SYS_USERFS_SIZE) / 1024`)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_DTB_PART_SIZE=$(shell printf "%uk" `expr $(CONFIG_SYS_NAND_BLOCK_SIZE) / 1024`)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_DTB_PART_SIZE=$(shell printf "%uk" `expr $(CONFIG_SYS_NAND_BLOCK_SIZE) \* 4 / 1024`)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_BBT_SIZE=$(shell printf "%uk" `expr 4 \* $(CONFIG_SYS_NAND_BLOCK_SIZE) / 1024`)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_BBT_OFFSET=$(shell printf "0x%x" `expr \( $(CONFIG_SYS_NAND_BLOCKS) - 4 \) \* $(CONFIG_SYS_NAND_BLOCK_SIZE)`)
-endif
+endif # CONFIG_SYS_NAND_BLOCK_SIZE
+else
+CONFIG_SYS_MMC_BOOT_PART_SIZE = $(shell expr 4096 \* 1024)
+CONFIG_U_BOOT_IMG_SIZE = $(shell expr 1 \* 1048576)
+CONFIG_MAX_DTB_SIZE = $(shell expr 64 \* 1024)
+CONFIG_ENV_SIZE = $(shell expr 128 \* 1024)
+CONFIG_ENV_OFFSET = $(shell expr $(CONFIG_SYS_MMC_BOOT_PART_SIZE) - $(CONFIG_ENV_SIZE))
+CONFIG_SYS_DTB_OFFSET=$(shell expr $(CONFIG_ENV_OFFSET) - $(CONFIG_MAX_DTB_SIZE))
+
+PLATFORM_CPPFLAGS += -DCONFIG_ENV_SIZE=$(CONFIG_ENV_SIZE)
+PLATFORM_CPPFLAGS += -DCONFIG_U_BOOT_IMG_SIZE=$(CONFIG_U_BOOT_IMG_SIZE)
+PLATFORM_CPPFLAGS += -DCONFIG_MAX_DTB_SIZE=$(CONFIG_MAX_DTB_SIZE)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_DTB_PART_SIZE=$(CONFIG_MAX_DTB_SIZE)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_MMC_BOOT_PART_SIZE=$(CONFIG_SYS_MMC_BOOT_PART_SIZE)
+PLATFORM_CPPFLAGS += -DCONFIG_ENV_OFFSET=$(shell printf "0x%x" $(CONFIG_ENV_OFFSET))
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_DTB_OFFSET=$(shell printf "0x%x" $(CONFIG_SYS_DTB_OFFSET))
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_DTB_BLKNO=$(shell printf "0x%x" `expr $(CONFIG_SYS_DTB_OFFSET) / 512`)
+#PLATFORM_CPPFLAGS += -D
+endif # CONFIG_TX6_V2
.endif
.endm
-#define MXC_DCD_ITEM(addr, val) mxc_dcd_item addr, val
+#define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val)
#if PHYS_SDRAM_1_WIDTH == 64
-#define MXC_DCD_ITEM_64(addr, val) mxc_dcd_item addr, val
+#define MXC_DCD_ITEM_64(addr, val) mxc_dcd_item (addr), (val)
#define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
#else
#define MXC_DCD_ITEM_64(addr, val)
#define MXC_DCD_CMD_FLAG_WRITE 0x0
#define MXC_DCD_CMD_FLAG_CLR 0x1
#define MXC_DCD_CMD_FLAG_SET 0x3
-#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
-#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
-#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
+#define MXC_DCD_CMD_FLAG_CHK_CLR ((0 << 0) | (0 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_SET ((0 << 0) | (1 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_ANY_CLR ((1 << 0) | (0 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_ANY_SET ((1 << 0) | (1 << 1))
-#define MXC_DCD_CMD_WRT(type, flags, next) \
- .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
+#define MXC_DCD_START \
+ .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \
+dcd_start:
-#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
- .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
+ .macro MXC_DCD_END
+1:
+ .ifgt . - dcd_start - 1768
+ .error "DCD too large!"
+ .endif
+dcd_end:
+ .endm
+
+#define MXC_DCD_CMD_WRT(type, flags) \
+1: .word CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type))
+
+#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
+1: .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \
CPU_2_BE_32(addr), CPU_2_BE_32(mask)
-#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
- .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
+#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
+1: .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \
CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
-#define MXC_DCD_CMD_NOP() \
- .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+#define MXC_DCD_CMD_NOP() \
+1: .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+
#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
#endif
dcd_hdr:
- .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
-dcd_start:
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset)
+ MXC_DCD_START
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
/* RESET_OUT GPIO_7_12 */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1, 0x00000001) /* UART1 RTS */
MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT, 0x00000003) /* UART1 RTS INPUT_SEL */
+#ifdef CONFIG_NAND_MXS
/* NAND */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE, 0x00000000) /* NANDF_CLE: NANDF_CLE */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE, 0x00000000) /* NANDF_ALE: NANDF_ALE */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000) /* NANDF_D5: NANDF_D5 */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000) /* NANDF_D6: NANDF_D6 */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000) /* NANDF_D7: NANDF_D7 */
-
+#endif
/* ext. mem CS */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000) /* NANDF_CS2: NANDF_CS2 */
/* DRAM_DQM[0..7] */
MXC_DCD_ITEM_64(MMDC2_MPRDDQBY3DL, 0x33333333)
/* MDMISC */
MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
-ddr_reset:
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
/* MSDSCR Conf Req */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000)
-con_ack:
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+
/* MDCTL */
MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)
-ddr_calib:
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL)
MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL)
- MXC_DCD_ITEM(MMDC1_MDRWD, 0x000026d2) /* MDRWD */
+ MXC_DCD_ITEM(MMDC1_MDRWD, 0x000026d2)
MXC_DCD_ITEM(MMDC1_MDOR, MDOR_VAL)
MXC_DCD_ITEM(MMDC1_MDOTC, MDOTC_VAL)
MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_0)
MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_0)
- MXC_DCD_ITEM(MMDC1_MDASP, (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1) /* MDASP */
+ MXC_DCD_ITEM(MMDC1_MDASP, (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1)
/* CS0 MRS: */
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
#if BANK_ADDR_BITS > 1
- /* CS1 MRS: MR2 */
+ /* CS1 MRS: */
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
- MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0))
#endif
MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
- MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222) /* MPODTCTRL */
+ MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222)
MXC_DCD_ITEM_64(MMDC2_MPODTCTRL, 0x00022222)
/* DDR3 calibration */
/* ZQ calibration */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
- MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa139002b)
+ MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1390001)
-zq_calib:
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
-#ifndef DO_WL_CALIB
#define WL_DLY_DQS_VAL 30
#define WL_DLY_DQS0 (WL_DLY_DQS_VAL + 0)
#define WL_DLY_DQS1 (WL_DLY_DQS_VAL + 0)
#define WL_DLY_DQS5 (WL_DLY_DQS_VAL + 0)
#define WL_DLY_DQS6 (WL_DLY_DQS_VAL + 0)
#define WL_DLY_DQS7 (WL_DLY_DQS_VAL + 0)
-#endif
/* Write leveling */
- MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
-#ifdef DO_WL_CALIB
- MXC_DCD_ITEM(MMDC1_MDSCR, 0x00808231) /* MRS: start write leveling */
- MXC_DCD_ITEM(MMDC1_MPWLGCR, 0x00000001) /* initiate Write leveling */
-wl_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000001)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000f00)
-#if PHYS_SDRAM_1_WIDTH == 64
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000001)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000f00)
-#endif /* PHYS_SDRAM_1_WIDTH == 64 */
-#else
MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
MXC_DCD_ITEM(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
-wl_calib:
-#endif /* DO_WL_CALIB */
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset)
-
- MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
-
- MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
/* DQS gating calibration */
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
+#if BANK_ADDR_BITS > 1
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
+#endif
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
-
MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
MXC_DCD_ITEM(MMDC1_MPMUR0, 0x00000800)
MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */
-dqs_fifo_reset:
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue 2nd fifo reset */
-dqs_fifo_reset2:
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
-dqs_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10000000)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x00001000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10001000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
/* DRAM_SDQS[0..7] pad config */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
- MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
/* Read delay calibration */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
-rd_dl_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000010)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000000f)
- MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x00000010)
- MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000000f)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f)
+ MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
-wr_dl_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000010)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000000f)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)
#if PHYS_SDRAM_1_WIDTH == 64
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib2)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
MXC_DCD_ITEM(MMDC2_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
-wr_dl_calib2:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x00000010)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000000f)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000001f)
#endif
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
+#if BANK_ADDR_BITS > 1
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) /* MRS: select normal data path */
+#endif
+ MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
MXC_DCD_ITEM(MMDC1_MAPSR, 0x00001006)
MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
/* MDSCR: Normal operation */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)
-
-con_ack_clr:
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDSCR, 0x00004000)
-dcd_end:
- .ifgt dcd_end - dcd_start - 1768
- .error "DCD too large!"
- .endif
+ MXC_DCD_END
#define VDD_CORE_VAL_LP mV_to_regval(900 * 10)
#define VDD_SOC_VAL mV_to_regval(1425 * 10)
#define VDD_SOC_VAL_LP mV_to_regval(900 * 10)
-#define VDD_DDR_VAL mV_to_regval(1350 * 10)
-#define VDD_DDR_VAL_LP mV_to_regval(1350 * 10)
+#define VDD_DDR_VAL mV_to_regval(1500 * 10)
+#define VDD_DDR_VAL_LP mV_to_regval(1500 * 10)
/* calculate voltages in 10mV */
+/* DCDC1-3 */
#define mV_to_regval(mV) DIV_ROUND(((((mV) < 6000) ? 6000 : (mV)) - 6000), 125)
#define regval_to_mV(v) (((v) * 125 + 6000))
+/* LDO1-2 */
#define mV_to_regval2(mV) DIV_ROUND(((((mV) < 9000) ? 9000 : (mV)) - 9000), 250)
#define regval2_to_mV(v) (((v) * 250 + 9000))
+/* LDO3 */
#define mV_to_regval3(mV) DIV_ROUND(((((mV) < 6000) ? 6000 : (mV)) - 6000), 250)
#define regval3_to_mV(v) (((v) * 250 + 6000))
+/* LDORTC */
#define mV_to_regval_rtc(mV) DIV_ROUND(((((mV) < 17000) ? 17000 : (mV)) - 17000), 250)
#define regval_rtc_to_mV(v) (((v) * 250 + 17000))
{ RN5T618_DC1DAC_SLP, VDD_CORE_VAL_LP, },
{ RN5T618_DC2DAC_SLP, VDD_SOC_VAL_LP, },
{ RN5T618_DC3DAC_SLP, VDD_DDR_VAL_LP, },
- { RN5T618_LDOEN1, 0x04, ~0x1f, },
+ { RN5T618_LDOEN1, 0x01f, ~0x1f, },
{ RN5T618_LDOEN2, 0x10, ~0x30, },
{ RN5T618_LDODIS, 0x00, },
{ RN5T618_LDO3DAC, VDD_HIGH_VAL, },
MX6_PAD_SD3_CLK__GPIO_7_3,
};
-static const iomux_v3_cfg_t mmc4_pads[] = {
+static const iomux_v3_cfg_t mmc3_pads[] = {
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* eMMC RESET */
MX6_PAD_NANDF_ALE__USDHC4_RST,
};
struct fsl_esdhc_cfg cfg;
int cd_gpio;
} tx6qdl_esdhc_cfg[] = {
+ {
+ .pads = mmc3_pads,
+ .num_pads = ARRAY_SIZE(mmc3_pads),
+ .clkid = MXC_ESDHC4_CLK,
+ .cfg = {
+ .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
+ .max_bus_width = 4,
+ },
+ .cd_gpio = -EINVAL,
+ },
{
.pads = mmc0_pads,
.num_pads = ARRAY_SIZE(mmc0_pads),
},
.cd_gpio = IMX_GPIO_NR(7, 3),
},
- {
- .pads = mmc4_pads,
- .num_pads = ARRAY_SIZE(mmc4_pads),
- .clkid = MXC_ESDHC4_CLK,
- .cfg = {
- .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
- .max_bus_width = 4,
- },
- .cd_gpio = -EINVAL,
- },
};
static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
*/
lcd_is_enabled = 0;
- karo_load_splashimage(1);
-
if (lcd_enabled) {
+ karo_load_splashimage(1);
+
debug("Switching LCD on\n");
gpio_set_value(TX6_LCD_PWR_GPIO, 1);
udelay(100);
#define VDD_SOC_VAL mV_to_regval(vout_to_vref(1425 * 10, 6))
#define VDD_SOC_VAL_LP mV_to_regval(vout_to_vref(900 * 10, 6))
#define VDD_DDR_VAL mV_to_regval(vout_to_vref(1500 * 10, 7))
+#define VDD_DDR_VAL_LP mV_to_regval(vout_to_vref(1500 * 10, 7))
#define VDD_CORE_VAL mV_to_regval(vout_to_vref(1425 * 10, 8))
#define VDD_CORE_VAL_LP mV_to_regval(vout_to_vref(900 * 10, 8))
#define R2_5 110
#define R1_5_2 470
#define R2_5_2 150
-/* Buck2 */
+/* Buck2 (SOC) */
#define R1_6 150
#define R2_6 180
-/* Buck3 */
+/* Buck3 (DDR) */
#define R1_7 150
#define R2_7 140
-/* Buck4 */
+/* Buck4 (CORE) */
#define R1_8 150
#define R2_8 180
u8 mask;
} ltc3676_regs[] = {
{ LTC3676_MSKPG, ~LTC3676_MSKPG_BUCK1, },
- { LTC3676_DVB2B, VDD_SOC_VAL | LTC3676_PGOOD_MASK, ~0x3f, },
- { LTC3676_DVB3B, VDD_DDR_VAL, ~0x3f, },
- { LTC3676_DVB4B, VDD_CORE_VAL | LTC3676_PGOOD_MASK, ~0x3f, },
+ { LTC3676_DVB2B, VDD_SOC_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, },
+ { LTC3676_DVB3B, VDD_DDR_VAL_LP, ~0x3f, },
+ { LTC3676_DVB4B, VDD_CORE_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, },
{ LTC3676_DVB2A, VDD_SOC_VAL, ~0x3f, },
{ LTC3676_DVB3A, VDD_DDR_VAL, ~0x3f, },
{ LTC3676_DVB4A, VDD_CORE_VAL, ~0x3f, },
/* LCD Logo and Splash screen support */
#define CONFIG_LCD
#ifdef CONFIG_LCD
-#ifndef CONFIG_TX6_V2
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
-#endif
#define CONFIG_VIDEO_IPUV3
#define CONFIG_IPUV3_CLK 266000000
#define CONFIG_LCD_LOGO
";nboot linux\0" \
"bootcmd_mmc=set autostart no;run bootargs_mmc" \
";fatload mmc 0 ${loadaddr} uImage\0" \
- "bootcmd_nand=set autostart no;run bootargs_ubifs" \
- ";nboot linux\0" \
+ CONFIG_SYS_BOOT_CMD_NAND \
"bootcmd_net=set autoload y;set autostart n;run bootargs_nfs" \
";dhcp\0" \
"bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
- "boot_mode=nand\0" \
+ "boot_mode=" CONFIG_SYS_DEFAULT_BOOT_MODE "\0" \
"cpu_clk=800\0" \
"default_bootargs=set bootargs " CONFIG_BOOTARGS \
" ${append_bootargs}\0" \
"fdtaddr=11000000\0" \
- "fdtsave=nand erase.part dtb" \
- ";nand write ${fdtaddr} dtb ${fdtsize}\0" \
+ CONFIG_SYS_FDTSAVE_CMD \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"nfsroot=/tftpboot/rootfs\0" \
#endif /* CONFIG_MFG */
#ifndef CONFIG_TX6_V2
+#define CONFIG_SYS_DEFAULT_BOOT_MODE "nand"
+#define CONFIG_SYS_BOOT_CMD_NAND \
+ "bootcmd_nand=set autostart no;run bootargs_ubifs;nboot linux\0"
+#define CONFIG_SYS_FDTSAVE_CMD \
+ "fdtsave=nand erase.part dtb" \
+ ";nand write ${fdtaddr} dtb ${fdtsize}\0"
#define MTD_NAME "gpmi-nand"
#define MTDIDS_DEFAULT "nand0=" MTD_NAME
#define CONFIG_SYS_NAND_ONFI_DETECTION
#else
+#define CONFIG_SYS_DEFAULT_BOOT_MODE "mmc"
+#define CONFIG_SYS_BOOT_CMD_NAND ""
+#define CONFIG_SYS_FDTSAVE_CMD \
+ "fdtsave=mmc open 0 1;mmc write ${fdtaddr} " xstr(CONFIG_SYS_DTB_BLKNO) " 80;mmc close 0 1\0"
#define MTD_NAME ""
#define MTDIDS_DEFAULT ""
#define CONFIG_SUPPORT_EMMC_BOOT
+#define CONFIG_MMC_BOOT_DEV 0
#endif
/*
#ifndef CONFIG_TX6_V2
#define CONFIG_CMD_NAND
#define CONFIG_CMD_MTDPARTS
-#else
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_GPT
#endif
#define CONFIG_CMD_BOOTCE
#define CONFIG_CMD_TIME
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BASE 0x00000000
#define CONFIG_CMD_ROMUPDATE
-#else
-#undef CONFIG_ENV_IS_IN_NAND
-#endif /* CONFIG_CMD_NAND */
#define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
#define CONFIG_ENV_SIZE SZ_128K
#define CONFIG_ENV_RANGE (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#undef CONFIG_ENV_IS_IN_NAND
+#endif /* CONFIG_CMD_NAND */
+
#ifdef CONFIG_ENV_OFFSET_REDUND
#define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_SYS_ENV_PART_SIZE) \
"(env)," \
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
#define CONFIG_CMD_EXT2
/*
*/
#ifdef CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
-#undef CONFIG_ENV_OFFSET
-#undef CONFIG_ENV_SIZE
-#define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
-#define CONFIG_ENV_SIZE SZ_128K
+#define CONFIG_SYS_MMC_ENV_PART 1
#define CONFIG_DYNAMIC_MMC_DEVNO
#endif /* CONFIG_ENV_IS_IN_MMC */
#else
projects / karo-tx-uboot.git / commitdiff