]> git.kernelconcepts.de Git - karo-tx-uboot.git/commitdiff
driver/i2c/mxc: Enable I2C bus 3 and 4
authorYork Sun <yorksun@freescale.com>
Fri, 20 Mar 2015 17:20:40 +0000 (10:20 -0700)
committerLothar Waßmann <LW@KARO-electronics.de>
Tue, 8 Sep 2015 20:31:08 +0000 (22:31 +0200)
Some SoCs have more than two I2C busses. Instead of adding ifdef
to the driver, macros are put into board header file where
CONFIG_SYS_I2C_MXC is defined.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Heiko Schocher <hs@denx.de>
30 files changed:
README
drivers/i2c/mxc_i2c.c
include/configs/aristainetos.h
include/configs/cm_fx6.h
include/configs/embestmx6boards.h
include/configs/flea3.h
include/configs/gw_ventana.h
include/configs/imx31_phycore.h
include/configs/ls1021aqds.h
include/configs/ls1021atwr.h
include/configs/ls2085a_common.h
include/configs/m53evk.h
include/configs/mx35pdk.h
include/configs/mx53ard.h
include/configs/mx53evk.h
include/configs/mx53loco.h
include/configs/mx53smd.h
include/configs/mx6qsabreauto.h
include/configs/mx6sabresd.h
include/configs/mx6slevk.h
include/configs/mx6sxsabresd.h
include/configs/nitrogen6x.h
include/configs/novena.h
include/configs/ot1200.h
include/configs/platinum.h
include/configs/tbs2910.h
include/configs/titanium.h
include/configs/tqma6.h
include/configs/wandboard.h
include/configs/woodburn_common.h

diff --git a/README b/README
index 09a1cba50d2958f629869468c7a0d1b47385e75f..651260e9e074ddb86887abd034cb5604166963d1 100644 (file)
--- a/README
+++ b/README
@@ -2516,6 +2516,8 @@ CBFS (Coreboot Filesystem) support
                  - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
                If those defines are not set, default value is 100000
                for speed, and 0 for slave.
+                 - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3
+                 - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4
 
                - drivers/i2c/rcar_i2c.c:
                  - activate this driver with CONFIG_SYS_I2C_RCAR
index ee86ea06efd4b90a0333119c680ae247a2975b0c..36edf03b28868c22bc44b2cd879f9d8d7531c8b2 100644 (file)
@@ -114,6 +114,9 @@ static u16 i2c_clk_div[50][2] = {
 #ifndef CONFIG_SYS_MXC_I2C3_SPEED
 #define CONFIG_SYS_MXC_I2C3_SPEED 100000
 #endif
+#ifndef CONFIG_SYS_MXC_I2C4_SPEED
+#define CONFIG_SYS_MXC_I2C4_SPEED 100000
+#endif
 
 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
 #define CONFIG_SYS_MXC_I2C1_SLAVE 0
@@ -124,6 +127,9 @@ static u16 i2c_clk_div[50][2] = {
 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
 #define CONFIG_SYS_MXC_I2C3_SLAVE 0
 #endif
+#ifndef CONFIG_SYS_MXC_I2C4_SLAVE
+#define CONFIG_SYS_MXC_I2C4_SLAVE 0
+#endif
 
 
 /*
@@ -411,23 +417,30 @@ int bus_i2c_write(void *base, uchar chip, uint addr, int alen,
        return ret;
 }
 
-#if !defined(I2C2_BASE_ADDR)
-#define I2C2_BASE_ADDR NULL
-#endif
-
-#if !defined(I2C3_BASE_ADDR)
-#define I2C3_BASE_ADDR NULL
-#endif
-
-#if !defined(I2C4_BASE_ADDR)
-#define I2C4_BASE_ADDR NULL
-#endif
-
 static void * const i2c_bases[] = {
+#if defined(CONFIG_SOC_MX25)
+       (void *)IMX_I2C_BASE,
+       (void *)IMX_I2C2_BASE,
+       (void *)IMX_I2C3_BASE
+#elif defined(CONFIG_SOC_MX27)
+       (void *)IMX_I2C1_BASE,
+       (void *)IMX_I2C2_BASE
+#elif defined(CONFIG_SOC_MX31) || defined(CONFIG_SOC_MX35) || \
+       defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) || \
+       defined(CONFIG_SOC_MX6) || defined(CONFIG_LS102XA)
+       (void *)I2C1_BASE_ADDR,
+       (void *)I2C2_BASE_ADDR,
+       (void *)I2C3_BASE_ADDR
+#elif defined(CONFIG_SOC_VF610)
+       (void *)I2C0_BASE_ADDR
+#elif defined(CONFIG_FSL_LSCH3)
        (void *)I2C1_BASE_ADDR,
        (void *)I2C2_BASE_ADDR,
        (void *)I2C3_BASE_ADDR,
        (void *)I2C4_BASE_ADDR
+#else
+#error "architecture not supported"
+#endif
 };
 
 struct i2c_parms {
@@ -545,12 +558,17 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
                         mxc_i2c_set_bus_speed,
                         CONFIG_SYS_MXC_I2C2_SPEED,
                         CONFIG_SYS_MXC_I2C2_SLAVE, 1)
-#if defined(CONFIG_SOC_MX31) || defined(CONFIG_SOC_MX35) ||\
-       defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) ||\
-       defined(CONFIG_SOC_MX6) || defined(CONFIG_SOC_LS102XA)
+#ifdef CONFIG_SYS_I2C_MXC_I2C3
 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
                         mxc_i2c_read, mxc_i2c_write,
                         mxc_i2c_set_bus_speed,
                         CONFIG_SYS_MXC_I2C3_SPEED,
                         CONFIG_SYS_MXC_I2C3_SLAVE, 2)
 #endif
+#ifdef CONFIG_SYS_I2C_MXC_I2C4
+U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
+                        mxc_i2c_read, mxc_i2c_write,
+                        mxc_i2c_set_bus_speed,
+                        CONFIG_SYS_MXC_I2C4_SPEED,
+                        CONFIG_SYS_MXC_I2C4_SLAVE, 3)
+#endif
index d5fd8dd6a7ee9c28b411350b119a815ae5232806..4eab912a719d9e489ce9f50408046339bddc866a 100644 (file)
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 #define CONFIG_SYS_I2C_SLAVE           0x7f
 #define CONFIG_SYS_I2C_NOPROBES                { {0, 0x00} }
index 80703116382c75eb97495b69001188ad7122888c..0098ad5f2282f77fc23c69761e37fc40c623aca5 100644 (file)
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 #define CONFIG_SYS_MXC_I2C3_SPEED      400000
 
index e54bb85f0a6c9dd343a7075ec05495f731a3d5c7..c380afa451454d82e805265ec9fc5639d3d5a965 100644 (file)
@@ -55,6 +55,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 
 /* USB Configs */
index 881568853e9055ec6256b1d49de2ec72b23574b1..9ee06d7c2c9e484ad7edd71901e9ae676cfdd1f4 100644 (file)
@@ -51,6 +51,7 @@
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_SPD_BUS_NUM         2 /* I2C3 */
 #define CONFIG_SYS_MXC_I2C3_SLAVE      0xfe
 #define CONFIG_MXC_SPI
index 33e895e679b487f8e17288e360824336485a9bc2..717c9dbd008cd8974124227a0f7a1d8746f9074f 100644 (file)
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 #define CONFIG_I2C_GSC                 0
 #define CONFIG_I2C_PMIC                        1
index 6ff141e88c3ccb4217cdb0543746393f3bfb06e3..c70c04cbc9b93bc030b80cbb7549fcfa8d9094a5 100644 (file)
@@ -37,6 +37,7 @@
 
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_CLK_OFFSET      I2C2_CLK_OFFSET
 
 #define CONFIG_MXC_UART
index 7b0ec28c85d5ea666d8f61fa832c4be13d7b5881..ec71f423b743fde883722516d13161f92fb28449 100644 (file)
@@ -388,6 +388,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 
 /*
  * I2C bus multiplexer
index f61e15f43530ee002d5935fa08633293f753976f..045a4094eb602aa7dd0c490b5c7c7776356ba7aa 100644 (file)
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 
 /* EEPROM */
 #ifndef CONFIG_SD_BOOT
index aca7301ae171ae4e37de4f048b2bcfaf90a7be09..26ef32a17768f811c2a6e2574620610f160e5f12 100644 (file)
@@ -84,6 +84,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_MXC_I2C4                /* enable I2C bus 4 */
 #define CONFIG_SYS_MXC_I2C1_SPEED      40000000
 #define CONFIG_SYS_MXC_I2C2_SPEED      40000000
 
index 0f894e3fb22714119abfdff171095914cc4a9f49..e7e0b4f98d5cba6ca403cb2673da9c386336455b 100644 (file)
 #ifdef CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_RTC_BUS_NUM         1 /* I2C2 */
 #endif
 
index 560cbf18e14effa4c0596a12e8166b1e28a94e0c..8a3169832b6e41806fcfbc5ec57d02bd5a3de5ed 100644 (file)
@@ -41,6 +41,7 @@
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_MXC_SPI
 #define CONFIG_MXC_GPIO
 
index dad49fc0471a1df0bb0a4650d9a7dc1c08a9bac0..7d23c3db5f5a996fd19f44b410bf618db2affdf2 100644 (file)
@@ -47,6 +47,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
index 007b952c7edef27d226434400df2624e12174783..36998f7f8f9dfd848e55fff9f285f296872b8a15 100644 (file)
@@ -40,6 +40,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 
 /* PMIC Configs */
 #define CONFIG_POWER
index c66db9dccdedf6f7472e6a86e682bab64df84543..14f54d5422832f2cc84402eb64bd1c700b776648 100644 (file)
@@ -75,6 +75,7 @@
 /* I2C Configs */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 
 /* PMIC Controller */
 #define CONFIG_POWER
index 1a97c069b748f3df47aa200b9a43a2712eb441bb..1aafcbabae4618203049ab857c6da378ea807573 100644 (file)
@@ -37,6 +37,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
index 23d1537199c504fcbc7a54ad3b61c2c92c0a6191..1d417afdb022bd37838e468748d955716aff3fe1 100644 (file)
@@ -54,6 +54,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 
 /* NAND flash command */
index a00cdb5a58d7d657fbe7f1c01c2d5b518d858ead..8100e9ee770f0a405a9a38e331a75a3096901436 100644 (file)
@@ -55,6 +55,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED             100000
 
 /* PMIC */
index 6ed21295acb7528957dca46aa3e66827e1a4cc25..013ebbef3786d36d9b39dbc6c024008ad3a9a164 100644 (file)
@@ -51,6 +51,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED             100000
 
 /* PMIC */
index 59ca66220f42aa6d87653cb2303fb40a7d740d0c..b71cd3d76aaa4c5f3db014faa9ab88a3d9c23ec3 100644 (file)
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED             100000
 
 /* PMIC */
index b7599cbef0572440f419a47159f7eecc933e9f99..cf7fc411cc7d8012c87056f25687b19b49a8b670 100644 (file)
@@ -62,6 +62,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 #define CONFIG_I2C_EDID
 
index 7db09b511d83584a3eef6eddc39f98a2622ed22d..f9cf86d2aa3464115b3a56041539d541c2488310 100644 (file)
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_MXC
 #define CONFIG_SYS_I2C_SPEED           100000
index 7714eb815f05183354da98298e61e04e170289ac..36ad1b3d1282b26599c52065950e975d4647e296 100644 (file)
@@ -61,6 +61,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED            100000
 
 /* OCOTP Configs */
index 134bb45887aba2f28df53c6cb8838e3abc017fc4..91ffc7c068b5d3f237c965a13396df4a39cee40c 100644 (file)
@@ -62,6 +62,7 @@
 /* I2C config */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED                   100000
 
 /* MMC config */
index 7a150bdc82bc463363b5918cc975709c379ffb3e..b587b9a11fa266c02516c077c134e8430c7fefbd 100644 (file)
 #ifdef CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 #define CONFIG_I2C_EDID
 #endif
index 764fd5d121a4a97aa54afa9eb19f37b9c3633e83..b39440242fe041ec9d754de4991a490119b0d6f7 100644 (file)
@@ -42,6 +42,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 
 /* MMC Configs */
index b7f19ce199a8cf14c68aee0a6eeea3e99655d3cd..2f76d5a3e457d3826a76c1f55f43491039c978bf 100644 (file)
@@ -67,6 +67,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_SYS_I2C_SPEED           100000
 
index f335e62226cf6fe9c3b0d14cbe667980f3ae70e6..f6faedbcdb72bc6f5eeb755ee4c65f8a911fcbe5 100644 (file)
@@ -61,6 +61,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 
 /* MMC Configuration */
index 437b8e909eec2a97f39a139311ad40c36f95b825..459824a41570c2447eab6e0282cb79ecf3dd835d 100644 (file)
@@ -46,6 +46,7 @@
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_SPD_BUS_NUM         0
 #define CONFIG_MXC_SPI
 #define CONFIG_MXC_GPIO