]> git.kernelconcepts.de Git - karo-tx-uboot.git/commitdiff
am33xx evm: Update secure_emif_sdram_config during ddr init
authorSatyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
Thu, 9 Aug 2012 18:29:57 +0000 (18:29 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 1 Sep 2012 12:58:19 +0000 (14:58 +0200)
This patch updates secure_emif_sdram_config with the
same value written to sdram_config during ddr3 initialization.

During suspend/resume, this value is copied into sdram_config.
With this, a write to sdram_config at the end of resume sequence
which triggers an init sequence can be avoided.

Without this register write in place, the DDR_RESET line goes
low for a few cycles during resume which is a violation of the
JEDEC spec.

Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
arch/arm/cpu/armv7/am33xx/ddr.c
arch/arm/include/asm/arch-am33xx/cpu.h
arch/arm/include/asm/arch-am33xx/sys_proto.h

index cffd4abcf7f51fb495e653d3288b6820b5735431..fd9fc4a7206d36b1d2809f648b84e504848110be 100644 (file)
@@ -17,6 +17,7 @@ http://www.ti.com/
 
 #include <asm/arch/cpu.h>
 #include <asm/arch/ddr_defs.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <asm/emif.h>
 
@@ -46,8 +47,10 @@ void config_sdram(const struct emif_regs *regs)
 {
        writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
        writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
-       if (regs->zq_config)
+       if (regs->zq_config){
                writel(regs->zq_config, &emif_reg->emif_zq_config);
+               writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+       }
        writel(regs->sdram_config, &emif_reg->emif_sdram_config);
 }
 
index de9ee91496eb5dfe7052591fd79bc1f63e9b4967..6cfbef76a79236130add2df5de3aa5f8a662e4e2 100644 (file)
@@ -234,6 +234,8 @@ struct vtp_reg {
 struct ctrl_stat {
        unsigned int resv1[16];
        unsigned int statusreg;         /* ofset 0x40 */
+       unsigned int resv2[51];
+       unsigned int secure_emif_sdram_config;  /* offset 0x0110 */
 };
 
 /* AM33XX GPIO registers */
index 8a4b24839fa32454ef30ade47a27942315164050..819ea650f00245069f5b93617de43e2d52c8834c 100644 (file)
@@ -46,6 +46,7 @@ u32 get_sysboot_value(void);
 int print_cpuinfo(void);
 #endif
 
+extern struct ctrl_stat *cstat;
 u32 get_device_type(void);
 void setup_clocks_for_console(void);
 void ddr_pll_config(unsigned int ddrpll_M);