Macpaul Lin <macpaul@andestech.com>
ADP-AG101 N1213 (AG101 SoC)
+ ADP-AG101P N1213 (AG101P XC5 FPGA)
#########################################################################
# End of MAINTAINERS list #
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
- .data : { *(.data) }
+ .data : { *(.data*) }
. = ALIGN(4);
# define machine_is_adpag101() (0)
#endif
+#define MACH_TYPE_ADPAG101P 1
+
+#ifdef CONFIG_ARCH_ADPAG101P
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ADPAG101P
+# endif
+# define machine_is_adpag101p() (machine_arch_type == MACH_TYPE_ADPAG101P)
+#else
+# define machine_is_adpag101p() (1)
+#endif
+
#endif /* __ASM_NDS32_MACH_TYPE_H */
--- /dev/null
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := adp-ag101p.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsdc010.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+ /*
+ * refer to BOOT_PARAMETER_PA_BASE within
+ * "linux/arch/nds32/include/asm/misc_spec.h"
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P;
+ gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+ ftsmc020_init(); /* initialize Flash */
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned long sdram_base = PHYS_SDRAM_0;
+ unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+ unsigned long actual_size;
+
+ actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+ gd->ram_size = actual_size;
+
+ if (expected_size != actual_size) {
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+ }
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ ftsdc010_mmc_init(0);
+ return 0;
+}
qi_lb60 mips xburst qi_lb60 qi
nios2-generic nios2 nios2 nios2-generic altera
adp-ag101 nds32 n1213 adp-ag101 AndesTech ag101
+adp-ag101p nds32 n1213 adp-ag101p AndesTech ag101
PCI5441 nios2 nios2 pci5441 psyent
PK1C20 nios2 nios2 pk1c20 psyent
EVB64260 powerpc 74xx_7xx evb64260 - - EVB64260
--- /dev/null
+/*
+ * (C) Copyright 2011 Andes Technology Corp
+ * Macpaul Lin <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Andes Power Control Unit
+ */
+#ifndef __ANDES_PCU_H
+#define __ANDES_PCU_H
+
+#ifndef __ASSEMBLY__
+
+struct pcs {
+ unsigned int cr; /* PCSx Configuration (clock scaling) */
+ unsigned int parm; /* PCSx Parameter*/
+ unsigned int stat1; /* PCSx Status 1 */
+ unsigned int stat2; /* PCSx Stusts 2 */
+ unsigned int pdd; /* PCSx PDD */
+};
+
+struct andes_pcu {
+ unsigned int rev; /* 0x00 - PCU Revision */
+ unsigned int spinfo; /* 0x04 - Scratch Pad Info */
+ unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */
+ unsigned int soc_id; /* 0x10 - SoC ID */
+ unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */
+ unsigned int soc_apb; /* 0x18 - SoC APB configuration */
+ unsigned int rsvd2; /* 0x1C */
+ unsigned int dcsrcr0; /* 0x20 - Driving Capability
+ and Slew Rate Control 0 */
+ unsigned int dcsrcr1; /* 0x24 - Driving Capability
+ and Slew Rate Control 1 */
+ unsigned int dcsrcr2; /* 0x28 - Driving Capability
+ and Slew Rate Control 2 */
+ unsigned int rsvd3; /* 0x2C */
+ unsigned int mfpsr0; /* 0x30 - Multi-Func Port Setting 0 */
+ unsigned int mfpsr1; /* 0x34 - Multi-Func Port Setting 1 */
+ unsigned int dmaes; /* 0x38 - DMA Engine Selection */
+ unsigned int rsvd4; /* 0x3C */
+ unsigned int oscc; /* 0x40 - OSC Control */
+ unsigned int pwmcd; /* 0x44 - PWM Clock divider */
+ unsigned int socmisc; /* 0x48 - SoC Misc. */
+ unsigned int rsvd5[13]; /* 0x4C-0x7C: Reserved */
+ unsigned int bsmcr; /* 0x80 - BSM Controrl */
+ unsigned int bsmst; /* 0x84 - BSM Status */
+ unsigned int wes; /* 0x88 - Wakeup Event Sensitivity*/
+ unsigned int west; /* 0x8C - Wakeup Event Status */
+ unsigned int rsttiming; /* 0x90 - Reset Timing */
+ unsigned int intr_st; /* 0x94 - PCU Interrupt Status */
+ unsigned int rsvd6[2]; /* 0x98-0x9C: Reserved */
+ struct pcs pcs1; /* 0xA0-0xB0: PCS1 (clock scaling) */
+ unsigned int pcsrsvd1[3]; /* 0xB4-0xBC: Reserved */
+ struct pcs pcs2; /* 0xC0-0xD0: PCS2 (AHB clock gating) */
+ unsigned int pcsrsvd2[3]; /* 0xD4-0xDC: Reserved */
+ struct pcs pcs3; /* 0xE0-0xF0: PCS3 (APB clock gating) */
+ unsigned int pcsrsvd3[3]; /* 0xF4-0xFC: Reserved */
+ struct pcs pcs4; /* 0x100-0x110: PCS4 main PLL scaling */
+ unsigned int pcsrsvd4[3]; /* 0x114-0x11C: Reserved */
+ struct pcs pcs5; /* 0x120-0x130: PCS5 PCI PLL scaling */
+ unsigned int pcsrsvd5[3]; /* 0x134-0x13C: Reserved */
+ struct pcs pcs6; /* 0x140-0x150: PCS6 AC97 PLL scaling */
+ unsigned int pcsrsvd6[3]; /* 0x154-0x15C: Reserved */
+ struct pcs pcs7; /* 0x160-0x170: PCS7 GMAC PLL scaling */
+ unsigned int pcsrsvd7[3]; /* 0x174-0x17C: Reserved */
+ struct pcs pcs8; /* 0x180-0x190: PCS8 voltage scaling */
+ unsigned int pcsrsvd8[3]; /* 0x194-0x19C: Reserved */
+ struct pcs pcs9; /* 0x1A0-0x1B0: PCS9 power control */
+ unsigned int pcsrsvd9[93]; /* 0x1B4-0x3FC: Reserved */
+ unsigned int pmspdm[40]; /* 0x400-0x4fC: Power Manager
+ Scratch Pad Memory 0 */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * PCU Revision Register (ro)
+ */
+#define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff)
+#define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff)
+
+/*
+ * Scratch Pad Info Register (ro)
+ */
+#define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff)
+#define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf)
+
+/*
+ * SoC ID Register (ro)
+ */
+#define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf)
+#define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff)
+#define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff)
+
+/*
+ * SoC AHB Configuration Register (ro)
+ */
+#define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0)
+#define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1)
+#define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2)
+#define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3)
+#define ANDES_PCU_SOC_AHB_SPIROM(x) ((x) << 4)
+#define ANDES_PCU_SOC_AHB_DDR2C(x) ((x) << 5)
+#define ANDES_PCU_SOC_AHB_DDR2MEM(x) ((x) << 6)
+#define ANDES_PCU_SOC_AHB_DMAC(x) ((x) << 7)
+#define ANDES_PCU_SOC_AHB_DLM2(x) ((x) << 8)
+#define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9)
+#define ANDES_PCU_SOC_AHB_GMAC(x) ((x) << 12)
+#define ANDES_PCU_SOC_AHB_IDE(x) ((x) << 13)
+#define ANDES_PCU_SOC_AHB_USBOTG(x) ((x) << 14)
+#define ANDES_PCU_SOC_AHB_INTC(x) ((x) << 15)
+#define ANDES_PCU_SOC_AHB_LPCIO(x) ((x) << 16)
+#define ANDES_PCU_SOC_AHB_LPCREG(x) ((x) << 17)
+#define ANDES_PCU_SOC_AHB_PCIIO(x) ((x) << 18)
+#define ANDES_PCU_SOC_AHB_PCIMEM(x) ((x) << 19)
+#define ANDES_PCU_SOC_AHB_L2CC(x) ((x) << 20)
+#define ANDES_PCU_SOC_AHB_AHB2AHBREG(x) ((x) << 27)
+#define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x) ((x) << 28)
+#define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x) ((x) << 29)
+#define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x) ((x) << 30)
+#define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x) ((x) << 31)
+
+/*
+ * SoC APB Configuration Register (ro)
+ */
+#define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1)
+#define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2)
+#define ANDES_PCU_SOC_APB_UART1(x) ((x) << 3)
+#define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5)
+#define ANDES_PCU_SOC_APB_AC97I2S(x) ((x) << 6)
+#define ANDES_PCU_SOC_APB_UART2(x) ((x) << 8)
+#define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16)
+#define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17)
+#define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18)
+#define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19)
+#define ANDES_PCU_SOC_APB_GPIO(x) ((x) << 20)
+#define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22)
+#define ANDES_PCU_SOC_APB_PWM(x) ((x) << 23)
+
+/*
+ * Driving Capability and Slew Rate Control Register 0 (rw)
+ */
+#define ANDES_PCU_DCSRCR0_TRIAHB(x) (((x) & 0x1f) << 0)
+#define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8)
+#define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12)
+#define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16)
+#define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20)
+
+/*
+ * Driving Capability and Slew Rate Control Register 1 (rw)
+ */
+#define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0)
+
+/*
+ * Driving Capability and Slew Rate Control Register 2 (rw)
+ */
+#define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0)
+#define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4)
+#define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8)
+#define ANDES_PCU_DCSRCR2_SPI(x) (((x) & 0xf) << 12)
+#define ANDES_PCU_DCSRCR2_SD(x) (((x) & 0xf) << 16)
+#define ANDES_PCU_DCSRCR2_CFC(x) (((x) & 0xf) << 20)
+#define ANDES_PCU_DCSRCR2_GPIO(x) (((x) & 0xf) << 24)
+#define ANDES_PCU_DCSRCR2_PCU(x) (((x) & 0xf) << 28)
+
+/*
+ * Multi-function Port Setting Register 0 (rw)
+ */
+#define ANDES_PCU_MFPSR0_PCIMODE(x) ((x) << 0)
+#define ANDES_PCU_MFPSR0_IDEMODE(x) ((x) << 1)
+#define ANDES_PCU_MFPSR0_MINI_TC01(x) ((x) << 2)
+#define ANDES_PCU_MFPSR0_AHB_DEBUG(x) ((x) << 3)
+#define ANDES_PCU_MFPSR0_AHB_TARGET(x) ((x) << 4)
+#define ANDES_PCU_MFPSR0_DEFAULT_IVB(x) (((x) & 0x7) << 28)
+#define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x) ((x) << 31)
+
+/*
+ * Multi-function Port Setting Register 1 (rw)
+ */
+#define ANDES_PCU_MFPSR1_SUSPEND(x) ((x) << 0)
+#define ANDES_PCU_MFPSR1_PWM0(x) ((x) << 1)
+#define ANDES_PCU_MFPSR1_PWM1(x) ((x) << 2)
+#define ANDES_PCU_MFPSR1_AC97CLKOUT(x) ((x) << 3)
+#define ANDES_PCU_MFPSR1_PWREN(x) ((x) << 4)
+#define ANDES_PCU_MFPSR1_PME(x) ((x) << 5)
+#define ANDES_PCU_MFPSR1_I2C(x) ((x) << 6)
+#define ANDES_PCU_MFPSR1_UART1(x) ((x) << 7)
+#define ANDES_PCU_MFPSR1_UART2(x) ((x) << 8)
+#define ANDES_PCU_MFPSR1_SPI(x) ((x) << 9)
+#define ANDES_PCU_MFPSR1_SD(x) ((x) << 10)
+#define ANDES_PCU_MFPSR1_GPUPLLSRC(x) ((x) << 27)
+#define ANDES_PCU_MFPSR1_DVOMODE(x) ((x) << 28)
+#define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x) ((x) << 29)
+#define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x) ((x) << 30)
+#define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x) ((x) << 31)
+
+/*
+ * DMA Engine Selection Register (rw)
+ */
+#define ANDES_PCU_DMAES_AC97RX(x) ((x) << 2)
+#define ANDES_PCU_DMAES_AC97TX(x) ((x) << 3)
+#define ANDES_PCU_DMAES_UART1RX(x) ((x) << 4)
+#define ANDES_PCU_DMAES_UART1TX(x) ((x) << 5)
+#define ANDES_PCU_DMAES_UART2RX(x) ((x) << 6)
+#define ANDES_PCU_DMAES_UART2TX(x) ((x) << 7)
+#define ANDES_PCU_DMAES_SDDMA(x) ((x) << 8)
+#define ANDES_PCU_DMAES_CFCDMA(x) ((x) << 9)
+
+/*
+ * OSC Control Register (rw)
+ */
+#define ANDES_PCU_OSCC_OSCH_OFF(x) ((x) << 0)
+#define ANDES_PCU_OSCC_OSCH_STABLE(x) ((x) << 1)
+#define ANDES_PCU_OSCC_OSCH_TRI(x) ((x) << 2)
+#define ANDES_PCU_OSCC_OSCH_RANGE(x) (((x) & 0x3) << 4)
+#define ANDES_PCU_OSCC_OSCH2_RANGE(x) (((x) & 0x3) << 6)
+#define ANDES_PCU_OSCC_OSCH3_RANGE(x) (((x) & 0x3) << 8)
+
+/*
+ * PWM Clock Divider Register (rw)
+ */
+#define ANDES_PCU_PWMCD_PWMDIV(x) (((x) & 0xf) << 0)
+
+/*
+ * SoC Misc. Register (rw)
+ */
+#define ANDES_PCU_SOCMISC_RSCPUA(x) ((x) << 0)
+#define ANDES_PCU_SOCMISC_RSCPUB(x) ((x) << 1)
+#define ANDES_PCU_SOCMISC_RSPCI(x) ((x) << 2)
+#define ANDES_PCU_SOCMISC_USBWAKE(x) ((x) << 3)
+#define ANDES_PCU_SOCMISC_EXLM_WAITA(x) (((x) & 0x3) << 4)
+#define ANDES_PCU_SOCMISC_EXLM_WAITB(x) (((x) & 0x3) << 6)
+#define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x) (((x) << 8)
+#define ANDES_PCU_SOCMISC_300MHZSEL(x) (((x) << 9)
+#define ANDES_PCU_SOCMISC_DDRDLL_SRST(x) (((x) << 10)
+#define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x) (((x) << 11)
+#define ANDES_PCU_SOCMISC_DDRDLL_TEST(x) (((x) << 12)
+#define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x) (((x) << 13)
+#define ANDES_PCU_SOCMISC_ENCPUA(x) (((x) << 14)
+#define ANDES_PCU_SOCMISC_ENCPUB(x) (((x) << 15)
+#define ANDES_PCU_SOCMISC_PWON_PWBTN(x) (((x) << 16)
+#define ANDES_PCU_SOCMISC_PWON_GPIO1(x) (((x) << 17)
+#define ANDES_PCU_SOCMISC_PWON_GPIO2(x) (((x) << 18)
+#define ANDES_PCU_SOCMISC_PWON_GPIO3(x) (((x) << 19)
+#define ANDES_PCU_SOCMISC_PWON_GPIO4(x) (((x) << 20)
+#define ANDES_PCU_SOCMISC_PWON_GPIO5(x) (((x) << 21)
+#define ANDES_PCU_SOCMISC_PWON_WOL(x) (((x) << 22)
+#define ANDES_PCU_SOCMISC_PWON_RTC(x) (((x) << 23)
+#define ANDES_PCU_SOCMISC_PWON_RTCALM(x) (((x) << 24)
+#define ANDES_PCU_SOCMISC_PWON_XDBGIN(x) (((x) << 25)
+#define ANDES_PCU_SOCMISC_PWON_PME(x) (((x) << 26)
+#define ANDES_PCU_SOCMISC_PWON_PWFAIL(x) (((x) << 27)
+#define ANDES_PCU_SOCMISC_CPUA_SRSTED(x) (((x) << 28)
+#define ANDES_PCU_SOCMISC_CPUB_SRSTED(x) (((x) << 29)
+#define ANDES_PCU_SOCMISC_WD_RESET(x) (((x) << 30)
+#define ANDES_PCU_SOCMISC_HW_RESET(x) (((x) << 31)
+
+/*
+ * BSM Control Register (rw)
+ */
+#define ANDES_PCU_BSMCR_LINK0(x) (((x) & 0xf) << 0)
+#define ANDES_PCU_BSMCR_LINK1(x) (((x) & 0xf) << 4)
+#define ANDES_PCU_BSMCR_SYNCSRC(x) (((x) & 0xf) << 24)
+#define ANDES_PCU_BSMCR_CMD(x) (((x) & 0x7) << 28)
+#define ANDES_PCU_BSMCR_IE(x) ((x) << 31)
+
+/*
+ * BSM Status Register
+ */
+#define ANDES_PCU_BSMSR_CI0(x) (((x) & 0xf) << 0)
+#define ANDES_PCU_BSMSR_CI1(x) (((x) & 0xf) << 4)
+#define ANDES_PCU_BSMSR_SYNCSRC(x) (((x) & 0xf) << 24)
+#define ANDES_PCU_BSMSR_BSMST(x) (((x) & 0xf) << 28)
+
+/*
+ * Wakeup Event Sensitivity Register (rw)
+ */
+#define ANDES_PCU_WESR_POLOR(x) (((x) & 0xff) << 0)
+
+/*
+ * Wakeup Event Status Register (ro)
+ */
+#define ANDES_PCU_WEST_SIG(x) (((x) & 0xff) << 0)
+
+/*
+ * Reset Timing Register
+ */
+#define ANDES_PCU_RSTTIMING_RG0(x) (((x) & 0xff) << 0)
+#define ANDES_PCU_RSTTIMING_RG1(x) (((x) & 0xff) << 8)
+#define ANDES_PCU_RSTTIMING_RG2(x) (((x) & 0xff) << 16)
+#define ANDES_PCU_RSTTIMING_RG3(x) (((x) & 0xff) << 24)
+
+/*
+ * PCU Interrupt Status Register
+ */
+#define ANDES_PCU_INTR_ST_BSM(x) ((x) << 0)
+#define ANDES_PCU_INTR_ST_PCS1(x) ((x) << 1)
+#define ANDES_PCU_INTR_ST_PCS2(x) ((x) << 2)
+#define ANDES_PCU_INTR_ST_PCS3(x) ((x) << 3)
+#define ANDES_PCU_INTR_ST_PCS4(x) ((x) << 4)
+#define ANDES_PCU_INTR_ST_PCS5(x) ((x) << 5)
+#define ANDES_PCU_INTR_ST_PCS6(x) ((x) << 6)
+#define ANDES_PCU_INTR_ST_PCS7(x) ((x) << 7)
+#define ANDES_PCU_INTR_ST_PCS8(x) ((x) << 8)
+#define ANDES_PCU_INTR_ST_PCS9(x) ((x) << 9)
+
+/*
+ * PCSx Configuration Register
+ */
+#define ANDES_PCU_PCSX_CR_WAKEUP_EN(x) (((x) & 0xff) << 0)
+#define ANDES_PCU_PCSX_CR_LW(x) (((x) & 0xf) << 16)
+#define ANDES_PCU_PCSX_CR_LS(x) (((x) & 0xf) << 20)
+#define ANDES_PCU_PCSX_CR_TYPE(x) (((x) >> 28) & 0x7) /* (ro) */
+
+/*
+ * PCSx Parameter Register (rw)
+ */
+#define ANDES_PCU_PCSX_PARM_NEXT(x) (((x) & 0xffffff) << 0)
+#define ANDES_PCU_PCSX_PARM_SYNCSRC(x) (((x) & 0xf) << 24)
+#define ANDES_PCU_PCSX_PARM_PCSCMD(x) (((x) & 0x7) << 28)
+#define ANDES_PCU_PCSX_PARM_IE(x) (((x) << 31)
+
+/*
+ * PCSx Status Register 1
+ */
+#define ANDES_PCU_PCSX_STAT1_ERRNO(x) (((x) & 0xf) << 0)
+#define ANDES_PCU_PCSX_STAT1_ST(x) (((x) & 0x7) << 28)
+
+/*
+ * PCSx Status Register 2
+ */
+#define ANDES_PCU_PCSX_STAT2_CRNTPARM(x) (((x) & 0xffffff) << 0)
+#define ANDES_PCU_PCSX_STAT2_SYNCSRC(x) (((x) & 0xf) << 24)
+
+/*
+ * PCSx PDD Register
+ * This is reserved for PCS(1-7)
+ */
+#define ANDES_PCU_PCS8_PDD_1BYTE(x) (((x) & 0xff) << 0)
+#define ANDES_PCU_PCS8_PDD_2BYTE(x) (((x) & 0xff) << 8)
+#define ANDES_PCU_PCS8_PDD_3BYTE(x) (((x) & 0xff) << 16)
+#define ANDES_PCU_PCS8_PDD_4BYTE(x) (((x) & 0xff) << 24)
+
+#define ANDES_PCU_PCS9_PDD_TIME1(x) (((x) & 0x3f) << 0)
+#define ANDES_PCU_PCS9_PDD_TIME2(x) (((x) & 0x3f) << 6)
+#define ANDES_PCU_PCS9_PDD_TIME3(x) (((x) & 0x3f) << 12)
+#define ANDES_PCU_PCS9_PDD_TIME4(x) (((x) & 0x3f) << 18)
+#define ANDES_PCU_PCS9_PDD_TICKTYPE(x) ((x) << 24)
+#define ANDES_PCU_PCS9_PDD_GPU_SRST(x) ((x) << 27)
+#define ANDES_PCU_PCS9_PDD_PWOFFTIME(x) (((x) & 0x3) << 28)
+#define ANDES_PCU_PCS9_PDD_SUS2DRAM(x) ((x) << 30)
+#define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x) ((x) << 31)
+
+#endif /* __ANDES_PCU_H */
--- /dev/null
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag101.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG101P
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_MEM_REMAP
+#endif
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0x03200000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+#endif
+
+/*
+ * Timer
+ */
+
+/*
+ * According to the discussion in u-boot mailing list before,
+ * CONFIG_SYS_HZ at 1000 is mandatory.
+ */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_CLK_FREQ 39062500
+#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ (5*1000000)
+#define OSC_CLK (4*OSC_5MHZ)
+#define RTC_DIV_COUNT (0.5) /* Why?? */
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FTSDC010
+#define CONFIG_FTSDC010_NUMBER 1
+#define CONFIG_CMD_FAT
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN (512 << 10)
+
+/*
+ * size in bytes reserved for initial data
+ */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
+
+/*
+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
+ * in C language.
+ */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
+ (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+ FTAHBC020S_SLAVE_BSR_SIZE(0xb))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PMU Power controller configuration
+ */
+#define CONFIG_PMU
+#define CONFIG_FTPMU010_POWER
+
+#ifdef CONFIG_FTPMU010_POWER
+#include <faraday/ftpmu010.h>
+#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
+#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
+ FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
+ FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
+ FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
+ FTPMU010_SDRAMHTC_CKE_DCSR | \
+ FTPMU010_SDRAMHTC_DQM_DCSR | \
+ FTPMU010_SDRAMHTC_SDCLK_DCSR)
+#endif
+
+/*
+ * SDRAM controller configuration
+ */
+#define CONFIG_FTSDMC021
+
+#ifdef CONFIG_FTSDMC021
+#include <faraday/ftsdmc021.h>
+
+#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
+ FTSDMC021_TP1_TRP(1) | \
+ FTSDMC021_TP1_TRCD(1) | \
+ FTSDMC021_TP1_TRF(3) | \
+ FTSDMC021_TP1_TWR(1) | \
+ FTSDMC021_TP1_TCL(2))
+
+#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
+ FTSDMC021_TP2_INI_REFT(8) | \
+ FTSDMC021_TP2_REF_INTV(0x180))
+
+/*
+ * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
+ * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
+ * C language.
+ */
+#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
+ FTSDMC021_CR1_DSZ(3) | \
+ FTSDMC021_CR1_MBW(2) | \
+ FTSDMC021_CR1_BNKSIZE(6))
+
+#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
+ FTSDMC021_CR2_IREF | \
+ FTSDMC021_CR2_ISMR)
+
+#define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
+#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
+ CONFIG_SYS_FTSDMC021_BANK0_BASE)
+
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
+#if defined(CONFIG_MEM_REMAP)
+#define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/
+#endif
+#else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
+#define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */
+#endif
+
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
+
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+ GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+ GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_MEM_REMAP */
+
+/*
+ * Load address and memory test area should agree with
+ * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x300000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#define CONFIG_SYS_FTSMC020_CONFIGS { \
+ { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
+ { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
+#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_SIZE_32M | \
+ FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
+ FTSMC020_TPR_AST(1) | \
+ FTSMC020_TPR_CTW(1) | \
+ FTSMC020_TPR_ATI(1) | \
+ FTSMC020_TPR_AT2(1) | \
+ FTSMC020_TPR_WTC(1) | \
+ FTSMC020_TPR_AHT(1) | \
+ FTSMC020_TPR_TRNA(1))
+#endif
+
+/*
+ * FLASH on ADP_AG101P is connected to BANK0
+ * Just disalbe the other BANK to avoid detection error.
+ */
+#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
+ FTSMC020_BANK_SIZE_32M | \
+ FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
+ FTSMC020_TPR_CTW(3) | \
+ FTSMC020_TPR_ATI(0xf) | \
+ FTSMC020_TPR_AT2(3) | \
+ FTSMC020_TPR_WTC(3) | \
+ FTSMC020_TPR_AHT(3) | \
+ FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG (0x00)
+#define FTSMC020_BANK1_TIMING (0x00)
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* support JEDEC */
+
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define PHYS_FLASH_1 0x80400000 /* BANK 1 */
+#else /* !CONFIG_SKIP_LOWLEVEL_INIT */
+#ifdef CONFIG_MEM_REMAP
+#define PHYS_FLASH_1 0x80000000 /* BANK 0 */
+#else
+#define PHYS_FLASH_1 0x00000000 /* BANK 0 */
+#endif /* CONFIG_MEM_REMAP */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2)
+#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
+#define CONFIG_ENV_SIZE 8192
+#define CONFIG_ENV_OVERWRITE
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2011 Andes Technology Corp
+ * Macpaul Lin <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller
+ */
+#ifndef __DWCDDR21MCTL_H
+#define __DWCDDR21MCTL_H
+
+#ifndef __ASSEMBLY__
+struct dwcddr21mctl {
+ unsigned int ccr; /* Controller Configuration */
+ unsigned int dcr; /* DRAM Configuration */
+ unsigned int iocr; /* I/O Configuration */
+ unsigned int csr; /* Controller Status */
+ unsigned int drr; /* DRAM refresh */
+ unsigned int tpr0; /* SDRAM Timing Parameters 0 */
+ unsigned int tpr1; /* SDRAM Timing Parameters 1 */
+ unsigned int tpr2; /* SDRAM Timing Parameters 2 */
+ unsigned int gdllcr; /* Global DLL Control */
+ unsigned int dllcr[10]; /* DLL Control */
+ unsigned int rslr[4]; /* Rank System Lantency */
+ unsigned int rdgr[4]; /* Rank DQS Gating */
+ unsigned int dqtr[9]; /* DQ Timing */
+ unsigned int dqstr; /* DQS Timing */
+ unsigned int dqsbtr; /* DQS_b Timing */
+ unsigned int odtcr; /* ODT Configuration */
+ unsigned int dtr[2]; /* Data Training */
+ unsigned int dtar; /* Data Training Address */
+ unsigned int rsved[82]; /* Reserved */
+ unsigned int mr; /* Mode Register */
+ unsigned int emr; /* Extended Mode Register */
+ unsigned int emr2; /* Extended Mode Register 2 */
+ unsigned int emr3; /* Extended Mode Register 3 */
+ unsigned int hpcr[32]; /* Host Port Configurarion */
+ unsigned int pqcr[8]; /* Priority Queue Configuration */
+ unsigned int mmgcr; /* Memory Manager General Config */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Control Configuration Register
+ */
+#define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0)
+#define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1)
+#define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2)
+#define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3)
+#define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4)
+#define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13)
+#define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14)
+#define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15)
+#define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17)
+#define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27)
+#define DWCDDR21MCTL_CCR_ITMRST(x) ((x) << 28)
+#define DWCDDR21MCTL_CCR_IB(x) ((x) << 29)
+#define DWCDDR21MCTL_CCR_DTT(x) ((x) << 30)
+#define DWCDDR21MCTL_CCR_IT(x) ((x) << 31)
+
+/*
+ * DRAM Configuration Register
+ */
+#define DWCDDR21MCTL_DCR_DDRMD(x) ((x) << 0)
+#define DWCDDR21MCTL_DCR_DIO(x) (((x) & 0x3) << 1)
+#define DWCDDR21MCTL_DCR_DSIZE(x) (((x) & 0x7) << 3)
+#define DWCDDR21MCTL_DCR_SIO(x) (((x) & 0x7) << 6)
+#define DWCDDR21MCTL_DCR_PIO(x) ((x) << 9)
+#define DWCDDR21MCTL_DCR_RANKS(x) (((x) & 0x3) << 10)
+#define DWCDDR21MCTL_DCR_RNKALL(x) ((x) << 12)
+#define DWCDDR21MCTL_DCR_AMAP(x) (((x) & 0x3) << 13)
+#define DWCDDR21MCTL_DCR_RANK(x) (((x) & 0x3) << 25)
+#define DWCDDR21MCTL_DCR_CMD(x) (((x) & 0xf) << 27)
+#define DWCDDR21MCTL_DCR_EXE(x) ((x) << 31)
+
+/*
+ * I/O Configuration Register
+ */
+#define DWCDDR21MCTL_IOCR_RTT(x) (((x) & 0xf) << 0)
+#define DWCDDR21MCTL_IOCR_DS(x) (((x) & 0xf) << 4)
+#define DWCDDR21MCTL_IOCR_TESTEN(x) ((x) << 0x8)
+#define DWCDDR21MCTL_IOCR_RTTOH(x) (((x) & 0x7) << 26)
+#define DWCDDR21MCTL_IOCR_RTTOE(x) ((x) << 29)
+#define DWCDDR21MCTL_IOCR_DQRTT(x) ((x) << 30)
+#define DWCDDR21MCTL_IOCR_DQSRTT(x) ((x) << 31)
+
+/*
+ * Controller Status Register
+ */
+#define DWCDDR21MCTL_CSR_DRIFT(x) (((x) & 0x3ff) << 0)
+#define DWCDDR21MCTL_CSR_DFTERR(x) ((x) << 18)
+#define DWCDDR21MCTL_CSR_ECCERR(x) ((x) << 19)
+#define DWCDDR21MCTL_CSR_DTERR(x) ((x) << 20)
+#define DWCDDR21MCTL_CSR_DTIERR(x) ((x) << 21)
+#define DWCDDR21MCTL_CSR_ECCSEC(x) ((x) << 22)
+
+/*
+ * DRAM Refresh Register
+ */
+#define DWCDDR21MCTL_DRR_TRFC(x) (((x) & 0xff) << 0)
+#define DWCDDR21MCTL_DRR_TRFPRD(x) (((x) & 0xffff) << 8)
+#define DWCDDR21MCTL_DRR_RFBURST(x) (((x) & 0xf) << 24)
+#define DWCDDR21MCTL_DRR_RD(x) ((x) << 31)
+
+/*
+ * SDRAM Timing Parameters Register 0
+ */
+#define DWCDDR21MCTL_TPR0_TMRD(x) (((x) & 0x3) << 0)
+#define DWCDDR21MCTL_TPR0_TRTP(x) (((x) & 0x7) << 2)
+#define DWCDDR21MCTL_TPR0_TWTR(x) (((x) & 0x7) << 5)
+#define DWCDDR21MCTL_TPR0_TRP(x) (((x) & 0xf) << 8)
+#define DWCDDR21MCTL_TPR0_TRCD(x) (((x) & 0xf) << 12)
+#define DWCDDR21MCTL_TPR0_TRAS(x) (((x) & 0x1f) << 16)
+#define DWCDDR21MCTL_TPR0_TRRD(x) (((x) & 0xf) << 21)
+#define DWCDDR21MCTL_TPR0_TRC(x) (((x) & 0x3f) << 25)
+#define DWCDDR21MCTL_TPR0_TCCD(x) ((x) << 31)
+
+/*
+ * SDRAM Timing Parameters Register 1
+ */
+#define DWCDDR21MCTL_TPR1_TAOND(x) (((x) & 0x3) << 0)
+#define DWCDDR21MCTL_TPR1_TRTW(x) ((x) << 2)
+#define DWCDDR21MCTL_TPR1_TFAW(x) (((x) & 0x3f) << 3)
+#define DWCDDR21MCTL_TPR1_TRNKRTR(x) (((x) & 0x3) << 12)
+#define DWCDDR21MCTL_TPR1_TRNKWTW(x) (((x) & 0x3) << 14)
+#define DWCDDR21MCTL_TPR1_XCL(x) (((x) & 0xf) << 23)
+#define DWCDDR21MCTL_TPR1_XWR(x) (((x) & 0xf) << 27)
+#define DWCDDR21MCTL_TPR1_XTP(x) ((x) << 31)
+
+/*
+ * SDRAM Timing Parameters Register 2
+ */
+#define DWCDDR21MCTL_TPR2_TXS(x) (((x) & 0x3ff) << 0)
+#define DWCDDR21MCTL_TPR2_TXP(x) (((x) & 0x1f) << 10)
+#define DWCDDR21MCTL_TPR2_TCKE(x) (((x) & 0xf) << 15)
+
+/*
+ * Global DLL Control Register
+ */
+#define DWCDDR21MCTL_GDLLCR_DRES(x) (((x) & 0x3) << 0)
+#define DWCDDR21MCTL_GDLLCR_IPUMP(x) (((x) & 0x7) << 2)
+#define DWCDDR21MCTL_GDLLCR_TESTEN(x) ((x) << 5)
+#define DWCDDR21MCTL_GDLLCR_DTC(x) (((x) & 0x7) << 6)
+#define DWCDDR21MCTL_GDLLCR_ATC(x) (((x) & 0x3) << 9)
+#define DWCDDR21MCTL_GDLLCR_TESTSW(x) ((x) << 11)
+#define DWCDDR21MCTL_GDLLCR_MBIAS(x) (((x) & 0xff) << 12)
+#define DWCDDR21MCTL_GDLLCR_SBIAS(x) (((x) & 0xff) << 20)
+#define DWCDDR21MCTL_GDLLCR_LOCKDET(x) ((x) << 29)
+
+/*
+ * DLL Control Register 0-9
+ */
+#define DWCDDR21MCTL_DLLCR_SFBDLY(x) (((x) & 0x7) << 0)
+#define DWCDDR21MCTL_DLLCR_SFWDLY(x) (((x) & 0x7) << 3)
+#define DWCDDR21MCTL_DLLCR_MFBDLY(x) (((x) & 0x7) << 6)
+#define DWCDDR21MCTL_DLLCR_MFWDLY(x) (((x) & 0x7) << 9)
+#define DWCDDR21MCTL_DLLCR_SSTART(x) (((x) & 0x3) << 12)
+#define DWCDDR21MCTL_DLLCR_PHASE(x) (((x) & 0xf) << 14)
+#define DWCDDR21MCTL_DLLCR_ATESTEN(x) ((x) << 18)
+#define DWCDDR21MCTL_DLLCR_DRSVD(x) ((x) << 19)
+#define DWCDDR21MCTL_DLLCR_DD(x) ((x) << 31)
+
+/*
+ * Rank System Lantency Register
+ */
+#define DWCDDR21MCTL_RSLR_SL0(x) (((x) & 0x7) << 0)
+#define DWCDDR21MCTL_RSLR_SL1(x) (((x) & 0x7) << 3)
+#define DWCDDR21MCTL_RSLR_SL2(x) (((x) & 0x7) << 6)
+#define DWCDDR21MCTL_RSLR_SL3(x) (((x) & 0x7) << 9)
+#define DWCDDR21MCTL_RSLR_SL4(x) (((x) & 0x7) << 12)
+#define DWCDDR21MCTL_RSLR_SL5(x) (((x) & 0x7) << 15)
+#define DWCDDR21MCTL_RSLR_SL6(x) (((x) & 0x7) << 18)
+#define DWCDDR21MCTL_RSLR_SL7(x) (((x) & 0x7) << 21)
+#define DWCDDR21MCTL_RSLR_SL8(x) (((x) & 0x7) << 24)
+
+/*
+ * Rank DQS Gating Register
+ */
+#define DWCDDR21MCTL_RDGR_DQSSEL0(x) (((x) & 0x3) << 0)
+#define DWCDDR21MCTL_RDGR_DQSSEL1(x) (((x) & 0x3) << 2)
+#define DWCDDR21MCTL_RDGR_DQSSEL2(x) (((x) & 0x3) << 4)
+#define DWCDDR21MCTL_RDGR_DQSSEL3(x) (((x) & 0x3) << 6)
+#define DWCDDR21MCTL_RDGR_DQSSEL4(x) (((x) & 0x3) << 8)
+#define DWCDDR21MCTL_RDGR_DQSSEL5(x) (((x) & 0x3) << 10)
+#define DWCDDR21MCTL_RDGR_DQSSEL6(x) (((x) & 0x3) << 12)
+#define DWCDDR21MCTL_RDGR_DQSSEL7(x) (((x) & 0x3) << 14)
+#define DWCDDR21MCTL_RDGR_DQSSEL8(x) (((x) & 0x3) << 16)
+
+/*
+ * DQ Timing Register
+ */
+#define DWCDDR21MCTL_DQTR_DQDLY0(x) (((x) & 0xf) << 0)
+#define DWCDDR21MCTL_DQTR_DQDLY1(x) (((x) & 0xf) << 4)
+#define DWCDDR21MCTL_DQTR_DQDLY2(x) (((x) & 0xf) << 8)
+#define DWCDDR21MCTL_DQTR_DQDLY3(x) (((x) & 0xf) << 12)
+#define DWCDDR21MCTL_DQTR_DQDLY4(x) (((x) & 0xf) << 16)
+#define DWCDDR21MCTL_DQTR_DQDLY5(x) (((x) & 0xf) << 20)
+#define DWCDDR21MCTL_DQTR_DQDLY6(x) (((x) & 0xf) << 24)
+#define DWCDDR21MCTL_DQTR_DQDLY7(x) (((x) & 0xf) << 28)
+
+/*
+ * DQS Timing Register
+ */
+#define DWCDDR21MCTL_DQSTR_DQSDLY0(x) (((x) & 0x7) << 0)
+#define DWCDDR21MCTL_DQSTR_DQSDLY1(x) (((x) & 0x7) << 3)
+#define DWCDDR21MCTL_DQSTR_DQSDLY2(x) (((x) & 0x7) << 6)
+#define DWCDDR21MCTL_DQSTR_DQSDLY3(x) (((x) & 0x7) << 9)
+#define DWCDDR21MCTL_DQSTR_DQSDLY4(x) (((x) & 0x7) << 12)
+#define DWCDDR21MCTL_DQSTR_DQSDLY5(x) (((x) & 0x7) << 15)
+#define DWCDDR21MCTL_DQSTR_DQSDLY6(x) (((x) & 0x7) << 18)
+#define DWCDDR21MCTL_DQSTR_DQSDLY7(x) (((x) & 0x7) << 21)
+#define DWCDDR21MCTL_DQSTR_DQSDLY8(x) (((x) & 0x7) << 24)
+
+/*
+ * DQS_b (DQSBTR) Timing Register
+ */
+#define DWCDDR21MCTL_DQSBTR_DQSDLY0(x) (((x) & 0x7) << 0)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY1(x) (((x) & 0x7) << 3)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY2(x) (((x) & 0x7) << 6)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY3(x) (((x) & 0x7) << 9)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY4(x) (((x) & 0x7) << 12)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY5(x) (((x) & 0x7) << 15)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY6(x) (((x) & 0x7) << 18)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY7(x) (((x) & 0x7) << 21)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY8(x) (((x) & 0x7) << 24)
+
+/*
+ * ODT Configuration Register
+ */
+#define DWCDDR21MCTL_ODTCR_RDODT0(x) (((x) & 0xf) << 0)
+#define DWCDDR21MCTL_ODTCR_RDODT1(x) (((x) & 0xf) << 4)
+#define DWCDDR21MCTL_ODTCR_RDODT2(x) (((x) & 0xf) << 8)
+#define DWCDDR21MCTL_ODTCR_RDODT3(x) (((x) & 0xf) << 12)
+#define DWCDDR21MCTL_ODTCR_WDODT0(x) (((x) & 0xf) << 16)
+#define DWCDDR21MCTL_ODTCR_WDODT1(x) (((x) & 0xf) << 20)
+#define DWCDDR21MCTL_ODTCR_WDODT2(x) (((x) & 0xf) << 24)
+#define DWCDDR21MCTL_ODTCR_WDODT3(x) (((x) & 0xf) << 28)
+
+/*
+ * Data Training Register
+ */
+#define DWCDDR21MCTL_DTR0_DTBYTE0(x) (((x) & 0xff) << 0) /* def: 0x11 */
+#define DWCDDR21MCTL_DTR0_DTBYTE1(x) (((x) & 0xff) << 8) /* def: 0xee */
+#define DWCDDR21MCTL_DTR0_DTBYTE2(x) (((x) & 0xff) << 16) /* def: 0x22 */
+#define DWCDDR21MCTL_DTR0_DTBYTE3(x) (((x) & 0xff) << 24) /* def: 0xdd */
+
+#define DWCDDR21MCTL_DTR1_DTBYTE4(x) (((x) & 0xff) << 0) /* def: 0x44 */
+#define DWCDDR21MCTL_DTR1_DTBYTE5(x) (((x) & 0xff) << 8) /* def: 0xbb */
+#define DWCDDR21MCTL_DTR1_DTBYTE6(x) (((x) & 0xff) << 16) /* def: 0x88 */
+#define DWCDDR21MCTL_DTR1_DTBYTE7(x) (((x) & 0xff) << 24) /* def: 0x77 */
+
+/*
+ * Data Training Address Register
+ */
+#define DWCDDR21MCTL_DTAR_DTCOL(x) (((x) & 0xfff) << 0)
+#define DWCDDR21MCTL_DTAR_DTROW(x) (((x) & 0xffff) << 12)
+#define DWCDDR21MCTL_DTAR_DTBANK(x) (((x) & 0x7) << 28)
+
+/*
+ * Mode Register
+ */
+#define DWCDDR21MCTL_MR_BL(x) (((x) & 0x7) << 0)
+#define DWCDDR21MCTL_MR_BT(x) ((x) << 3)
+#define DWCDDR21MCTL_MR_CL(x) (((x) & 0x7) << 4)
+#define DWCDDR21MCTL_MR_TM(x) ((x) << 7)
+#define DWCDDR21MCTL_MR_DR(x) ((x) << 8)
+#define DWCDDR21MCTL_MR_WR(x) (((x) & 0x7) << 9)
+#define DWCDDR21MCTL_MR_PD(x) ((x) << 12)
+
+/*
+ * Extended Mode register
+ */
+#define DWCDDR21MCTL_EMR_DE(x) ((x) << 0)
+#define DWCDDR21MCTL_EMR_ODS(x) ((x) << 1)
+#define DWCDDR21MCTL_EMR_RTT2(x) ((x) << 2)
+#define DWCDDR21MCTL_EMR_AL(x) (((x) & 0x7) << 3)
+#define DWCDDR21MCTL_EMR_RTT6(x) ((x) << 6)
+#define DWCDDR21MCTL_EMR_OCD(x) (((x) & 0x7) << 7)
+#define DWCDDR21MCTL_EMR_DQS(x) ((x) << 10)
+#define DWCDDR21MCTL_EMR_RDQS(x) ((x) << 11)
+#define DWCDDR21MCTL_EMR_OE(x) ((x) << 12)
+
+#define EMR_RTT2(x) DWCDDR21MCTL_EMR_RTT2(x)
+#define EMR_RTT6(x) DWCDDR21MCTL_EMR_RTT6(x)
+
+#define DWCDDR21MCTL_EMR_RTT_DISABLED (EMR_RTT6(0) | EMR_RTT2(0))
+#define DWCDDR21MCTL_EMR_RTT_75 (EMR_RTT6(0) | EMR_RTT2(1))
+#define DWCDDR21MCTL_EMR_RTT_150 (EMR_RTT6(1) | EMR_RTT2(0))
+#define DWCDDR21MCTL_EMR_RTT_50 (EMR_RTT6(1) | EMR_RTT2(1))
+
+/*
+ * Extended Mode register 2
+ */
+#define DWCDDR21MCTL_EMR2_PASR(x) (((x) & 0x7) << 0)
+#define DWCDDR21MCTL_EMR2_DCC(x) ((x) << 3)
+#define DWCDDR21MCTL_EMR2_SRF(x) ((x) << 7)
+
+/*
+ * Extended Mode register 3: [15:0] reserved for JEDEC.
+ */
+
+/*
+ * Host port Configuration register 0-31
+ */
+#define DWCDDR21MCTL_HPCR_HPBL(x) (((x) & 0xf) << 0)
+
+/*
+ * Priority Queue Configuration register 0-7
+ */
+#define DWCDDR21MCTL_HPCR_TOUT(x) (((x) & 0xf) << 0)
+#define DWCDDR21MCTL_HPCR_TOUTX(x) (((x) & 0x3) << 8)
+#define DWCDDR21MCTL_HPCR_LPQS(x) (((x) & 0x3) << 10)
+#define DWCDDR21MCTL_HPCR_PQBL(x) (((x) & 0xff) << 12)
+#define DWCDDR21MCTL_HPCR_SWAIT(x) (((x) & 0x1f) << 20)
+#define DWCDDR21MCTL_HPCR_INTRPT(x) (((x) & 0x7) << 25)
+#define DWCDDR21MCTL_HPCR_APQS(x) ((x) << 28)
+
+/*
+ * Memory Manager General Configuration register
+ */
+#define DWCDDR21MCTL_MMGCR_UHPP(x) (((x) & 0x3) << 0)
+
+#endif /* __DWCDDR21MCTL_H */
projects / karo-tx-uboot.git / commitdiff