+commit 5b464c289ba715d0979b6e1f94947bb8f1068d16
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Mar 9 14:52:11 2008 +0100
+
+ SCM: fix 'packed' attribute ignored for field of type 'can_msg_t' warnings
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit db695b78515ddb88a2d4f3357c120345efbf59ec
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Mar 9 10:44:01 2008 +0100
+
+ scb9328: Fix flash warning: type qualifiers ignored on function return type
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 2b3e7e61d6a72f16aee93f870bc6af67f30758c4
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Mar 9 10:50:41 2008 +0100
+
+ esd/common/fpga.c: fix indentation.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit cc3843e36453e2b8db65d7e56de938ba045016a0
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Mar 9 10:33:31 2008 +0100
+
+ common/kgdb.c: fix 'dereferencing type-punned pointer' warning
+
+ and get rid of a couple of unneeded casts.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 8d4f4a838d7dc7cf4de17e3e9a67e2f222b6a1c8
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Mar 9 10:09:53 2008 +0100
+
+ esd/common/fpga.c: fix 'assignment of read-only location' error
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit c6fe4dabac066e8758345d249032768496983a3e
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Mar 9 02:13:19 2008 +0100
+
+ Makefile: make build silently again.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 76babc86576f092573599334c85ec543fdbc6015
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Mar 9 02:07:49 2008 +0100
+
+ m501sk: Fix out of tree building
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 210ed2004e062fdd03f25ab4925998aa1bd08a07
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Mar 9 00:06:09 2008 +0100
+
+ ADS5121: fix out of tree build
+
+ and simplify Makefile a bit.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 46cb5074a3f74de64ebd97dd0c4ec7eb3d768b93
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Mar 8 22:35:31 2008 +0100
+
+ Release v1.3.2
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 78a90f827df74520e939c794fc7413dace21c4db
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Mar 8 22:35:04 2008 +0100
+
+ Update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 58f3c57c6008b42e01f551d3be6efd88c14ac87f
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Mar 8 21:30:04 2008 +0100
+
+ esd: Fix warning: passing argument 1 of 'fpga_boot' discards qualifiers from pointer target type
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit d75469d48c05795144f4b8ba76addbb4920a7bba
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Sat Mar 8 09:25:49 2008 +0900
+
+ net: rtl8169: Add processing when OWNbit did't enable in rtl_recv()
+
+ When rtl_recv() of rtl8169 is called, OWNbit of status register
+ is not enable occasionally.
+ rtl_recv() doesn't work normally when the driver doesn't do
+ appropriate processing.
+ This patch fix this problem.
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 82afabfeb8ae6a27c7b396011ea99f4712aa73fa
+Author: Heiko Schocher <hs@denx.de>
+Date: Fri Mar 7 08:15:28 2008 +0100
+
+ mgsuvd: update board configuration
+
+ initialize the UPIOx controller.
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit e492c90c26215e459aec0fdf0f8ef1fd204988f5
+Author: Heiko Schocher <hs@denx.de>
+Date: Fri Mar 7 08:13:41 2008 +0100
+
+ mgcoge: update board configuration
+
+ add support for the config Flash.
+ initialize the UPIOx controller.
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 270fe261b7f9292800b2b3d1bf19ae7cbc880258
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Fri Mar 7 12:27:31 2008 -0600
+
+ mpc83xx: make dtb basename file references equal those of linux
+
+ the dts file basenames were updated in linux - this helps avoid
+ inadvertently loading any old dtbs laying around.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit f30b6154f16f5ffa4a9f5bfca5e114d72b6ef675
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Wed Feb 27 16:08:22 2008 -0600
+
+ net: uec_phy: actually increment the timeout counter
+
+ allow u-boot to recover (and, e.g., switch to another interface) in the
+ case where a PHY does not report autonegotiation is complete within its
+ two second timeout value.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 772003e43957ee0c895abed7cd82cbe72820cbb8
+Author: Markus Brunner <super.firetwister@googlemail.com>
+Date: Wed Mar 5 21:38:12 2008 +0100
+
+ fix taihu soft spi_read
+
+ The taihu board used gpio_read_out_bit which reads the output register and not
+ the pin state.
+
+ Signed-off-by: Markus Brunner <super.firetwister@gmail.com>
+
+commit fc84a8495ac750f6b4adae81f8c4f100f65b6340
+Author: Stefan Roese <sr@denx.de>
+Date: Fri Mar 7 08:01:43 2008 +0100
+
+ ppc4xx: Sequoia: Add device tree (fdt) Linux booting default env variables
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit bd4458cb47abecabd406b1210457be96c69fc49d
+Author: Dave Liu <r63238@freescale.com>
+Date: Tue Mar 4 16:59:22 2008 +0800
+
+ 837xEMDS: Improve the system performance
+
+ 1. Make the CSB bus pipeline depth as 4, and enable
+ the repeat mode;
+ 2. Raise the eTSEC emergency priority;
+ 3. Use the highest IP blocks clock.
+
+ Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit d8ab58b212481b1c57947ea21aa96c4ce800d0b4
+Author: Detlev Zundel <dzu@denx.de>
+Date: Thu Mar 6 16:45:53 2008 +0100
+
+ Replace "run load; run update" with conditionalized "run load update".
+
+ The latter version stops when "run load" fails for whatever reasons
+ rendering the combination *a lot* more secure.
+
+ Signed-off-by: Detlev Zundel <dzu@denx.de>
+
+commit 6bc113886d7d316df1a4e459bec8baf027518551
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Mar 4 17:40:41 2008 +0100
+
+ net: Print error message upon net usage when no ethernet-interface is found
+
+ This patch fixes a problem seen on PPC4xx boards, when no MAC address is
+ defined. Then no ethernet interface is available but a simple "tftp"
+ command will return without any error message which is quite confusing.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit a30a549a3553032d809e0356306b62de0b125901
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Mar 4 10:03:03 2008 -0600
+
+ Remove erroneous or extra spd.h #includers.
+
+ Many of the spd.h #includers don't need it,
+ and wanted to have spd_sdram() declared instead.
+ Since they didn't get that, some also had open
+ coded extern declarations of it instead or as well.
+ Fix it all up by using spd_sdram.h where needed.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit a4475386cef14af3fd88f0518b688e755669486d
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Mar 4 17:41:28 2008 +0100
+
+ PCS440EP: fix build problems (redundant #define)
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit e85e2fa85ec09a6fac2846d1d881d8737e2bbda9
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Mar 4 17:39:25 2008 +0100
+
+ net: Print error message upon net usage when no ethernet-interface is found
+
+ This patch fixes a problem seen on PPC4xx boards, when no MAC address is
+ defined. Then no ethernet interface is available but a simple "tftp"
+ command will return without any error message which is quite confusing.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 384faaafb999cae3ce447c93e28a0b7e2e5fef53
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Mar 4 17:38:50 2008 +0100
+
+ W7OLMC/W7OLMG: fix build problems (redundant #define)
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit f9301e1cda296245ba052d7b08321199c3d0af9d
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Mar 4 14:58:31 2008 +0100
+
+ Makefile: fix problem with out-of-tree builds introduced by 5013c09f
+
+ Commit 5013c09f (Makefile: cleanup "clean" target) introduced a
+ problem for out-of-tree builds which caused "make clean" to fail.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit dfece9500556bed5d8244b1c15d973cec7c25bfe
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Mar 4 11:58:26 2008 +0100
+
+ examples/Makefile: build "hello_world" on 8xx, too.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 74eb0222594fd23aafdf168e60e872814eea8b62
+Author: Mike Nuss <mike@terascala.com>
+Date: Mon Mar 3 15:27:05 2008 -0500
+
+ PPC4xx (Sequoia): Fix Ethernet "remote fault" problems
+
+ Every now and then a Sequoia board (or equivalent hardware) had
+ problems connecting to a Gigabit capable network interface.
+
+ There were differences in the PHY setup between Linux and U-Boot.
+
+ This patch fixes the problem. Apparently "remote fault" is being set,
+ which signals to some devices (on the other end of the cable) that a
+ fault has occurred, while other devices ignore it. I believe the RF bit
+ was causing the issue, but I removed T4 also, to match up with Linux.
+
+ Signed-off-by: Mike Nuss <mike@terascala.com>
+
+commit 491fb6dea9f52fdb9cb5996e8e978b9e9685179f
+Author: Timur Tabi <timur@freescale.com>
+Date: Mon Mar 3 09:58:52 2008 -0600
+
+ fix QE firmware uploading limit
+
+ Fix a typo in qe_upload_firmware() that prevented uploading firmware on
+ systems with more than one RISC core.
+
+ Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit 42ba58e0c302b339a3c2faa6006a013c6f186b7a
+Author: Bernhard Nemec <bnemec@ganssloser.com>
+Date: Mon Mar 3 11:57:23 2008 +0000
+
+ Fix endianess problem in cramfs code (cramfs is always host-endian in Linux)
+
+ Originally pointed out by Laurent Pinchart <laurent.pinchart@tbox.biz>,
+ see http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/22846
+
+ Signed-off-by: Bernhard Nemec <bnemec <at> ganssloser.com>
+
+commit 84d0c2f1e39caff58bf765a7ab7c72da23c25ec8
+Author: Kim B. Heino <Kim.Heino@bluegiga.com>
+Date: Mon Mar 3 10:39:13 2008 +0200
+
+ fix copy from ram to dataflash
+
+ If I try to "cp.b <ram> <dataflash>", u-boot selects normal flash
+ routines instead of dataflash. This is because it checks "if source
+ address is not dataflash" instead of target address.
+
+ Signed-off-by: Kim B. Heino <Kim.Heino@bluegiga.com>
+
+commit 32bf3d143a888f8deacfdcc97e898f6c06d0aea4
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Mar 3 12:16:44 2008 +0100
+
+ Fix quoting problem (preboot setting) in many board config files.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 5b0b2b6fc9fe22e3864c2a57316d91a2507ec215
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Mar 3 12:36:49 2008 +0100
+
+ ADS5121: Fix default environment.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 91c82076ae492bb1f9d9c47a481314631d32dc8e
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Mar 2 16:12:31 2008 +0100
+
+ Makefile: Fix missing unconfig and mkconfig use
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 8ce4e5c2c02cb7e8adddf7b651d3050d81ce4c1d
+Author: michael <trimarchi@gandalf.sssup.it>
+Date: Sun Mar 2 23:33:46 2008 +0100
+
+ Fix checking fat32 cluster size.
+
+ This fixes the cluster size tests in the FAT32 file system.
+ The current implementation of VFAT support doesn't work if the
+ referred cluster has an offset > 16bit representation, causing
+ "fatload" and "fatls" commands etc. to fail.
+
+ Signed-off-by: michael trimarchi <trimarchi@gandalf.sssup.it>
+
+commit 661bad63a076a96c39c64f136915f146725af92b
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Mar 2 22:57:23 2008 +0100
+
+ Prepare v1.3.2-rc2 release candidate
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 76957cb3d621bf664311908e5962e151c633c285
+Author: Stefan Roese <sr@denx.de>
+Date: Sat Mar 1 12:11:40 2008 +0100
+
+ ppc4xx: EMAC: Fix 405EZ fifo size setup in EMAC_MR1
+
+ The 405EZ only supports 512 bytes of rx-/tx-fifo EMAC sizes. But
+ currently 4k/2k is configured. This patch fixes this issue.
+
+ Thanks to Thomas Kindler <tkindler@lenord.de> for pointing this out.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 118978c8eb43803e2794233922df4249fa278b83
+Author: Woodruff, Richard <r-woodruff2@ti.com>
+Date: Fri Feb 29 17:34:35 2008 -0600
+
+ Fix alignment error on ARM for modules
+
+ Fix alignment fault on ARM when running modules. With out an explicit
+ linker file gcc4.2.1 will half word align __bss_start's value. The word
+ dereference will crash hello_world.
+
+ signed-off-by Richard Woodruff <r-woodruff2@ti.com>
+
+commit ce1120dd703e6f12c59e4eba9962356a0300b832
+Author: Dave Liu <r63238@freescale.com>
+Date: Fri Feb 29 17:45:31 2008 +0800
+
+ fs: Fix ext2 read issue
+
+ The ext2 aligned process will corrupt the key
+ data struct, the patch fix this.
+
+ Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit 5013c09f7a5675952a3ca88b6bc6c924e63af33e
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Mar 2 22:45:33 2008 +0100
+
+ Makefile: cleanup "clean" target
+
+ Make sure CDPATH settings cannot interfere.
+ Update CHANGELOG.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit ffda586fc1373243c9794babde69500f6293a8d8
+Author: Li Yang <leoli@freescale.com>
+Date: Fri Feb 29 11:46:05 2008 +0800
+
+ add cscope build target
+
+ Add cscope build target to generate cscope database for code browsing.
+
+ Signed-off-by: Li Yang <leoli@freescale.com>
+
+commit f655adef65e4cf6b929054b049ee19ae9b5ccbe2
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Wed Feb 27 15:06:39 2008 -0600
+
+ net: uec_phy: handle 88e1111 rev.B2 erratum 5.6
+
+ erratum 5.6 states the autoneg completion bit is functional only if the
+ autoneg bit is asserted.
+
+ This fixes any secondarily-issued networking commands on non-gigabit
+ links on the mpc8360 mds board.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 5f91db7f582ca17b1f19f10189c025696f333d2e
+Author: John Rigby <jrigby@freescale.com>
+Date: Tue Feb 26 09:38:14 2008 -0700
+
+ MPC5121e ADS PCI support take 3
+
+ Adds PCI support for MPC5121
+
+ Tested with drivers/net/rtl8139.c
+
+ Support is conditional since PCI on old silicon does not work.
+
+ ads5121_PCI_config turns on PCI
+
+ In this version, condition compilation of PCI code has been moved
+ from ifdef in board/ads5121/pci.c to board/ads5121/Makefile as
+ suggested by Jean-Christophe PLAGNIOL-VILLARD
+
+ Signed-off-by: John Rigby <jrigby@freescale.com>
+
+commit 44b4dbed4133f657705b7c5193209da9978243a7
+Author: Anatolij Gustschin <agust@denx.de>
+Date: Mon Feb 25 23:53:07 2008 +0100
+
+ Fix warnings while compilation of post/drivers/memory.c
+
+ Fix warnings while compilation with new gcc in eldk-4.2
+
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 4fae35a53b3e958254d6574a1cc7e10811fc6726
+Author: Anatolij Gustschin <agust@denx.de>
+Date: Mon Feb 25 20:54:04 2008 +0100
+
+ ppc4xx: Fix problem in 4xx_enet.c driver
+
+ U-Boot crashes in the net loop if CONFIG_4xx_DCACHE is
+ enabled. To reproduce the problem ensure that 'ethrotate'
+ environment variable isn't set to "no" and then run
+ "tftp 200000 not_existent_file".
+ This patch tries to fix the issue.
+
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 60ec654c5eb80d0fe0c38a3bd42140215bc06484
+Author: Anatolij Gustschin <agust@denx.de>
+Date: Mon Feb 25 20:04:20 2008 +0100
+
+ POST: Disable cache while SPR POST
+
+ Currently (since commit b2e2142c) u-boot crashes on
+ sequoia board while SPR test if CONFIG_4xx_DCACHE is
+ enabled. This patch disables the cache while SPR test.
+
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit c313b2c6c555e7d89ec59bd51c59ab164ad0105d
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Mon Feb 25 17:52:40 2008 +0100
+
+ TQM5200: use automatic fdt memory fixup (part 2)
+
+ Call fdt_fixup_memory() on the boards TQM5200, TQM5200_B, TQM5200S,
+ TB5200 and TB5200_B to fixup the /memory node with the memory values
+ detected by U-Boot.
+
+ Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit 44ceec253ea941b301abf4b079d52324def69d92
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Mon Feb 25 15:17:05 2008 +0100
+
+ TQM5200: use automatic fdt memory fixup
+
+ Call fdt_fixup_memory() on the boards TQM5200, TQM5200_B, TQM5200S,
+ TB5200 and TB5200_B to fixup the /memory node with the memory values
+ detected by U-Boot.
+
+ Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit f3a329acb26017d8e10e9c93e1e726c2a5ac634a
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Mon Feb 25 13:27:52 2008 +0100
+
+ TQM5200: fix bug in SDRAM initialization code
+
+ This patch fixes a bug in the SDRAM initialization code for the
+ TQM5200. The hi_addr bit is now set correctly. Without this patch
+ the hi_addr bit is always set to 1, if the second SDRAM bank is
+ not populated.
+
+ For other MPC5200 boards a correspondig patch has already been applied
+ some time ago, see commit a63109281ad41b0fb489fdcb901171f76bcdbc2c.
+
+ Signed-off-by: Martin Krause <martin.krause@tqs.de>
+ --
+ Forget the first patch please. I confused flash with SDRAM in
+ the comment ...
+
+commit 217bf6b6a313d9ccb619a4dbc09f73f77cd48df1
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Mon Feb 25 00:03:12 2008 +0100
+
+ mx1fs2/flash: Fix multiple compiler warnings
+
+ "pointer targets in assignment differ in signedness"
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 5599c28cef55be42a8ca6fa8086b1a44e56a85d2
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Mon Feb 25 00:03:11 2008 +0100
+
+ arm-imx: Fix register definitions
+
+ Sync register definitions with linux
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit c9bcf75fecc58886af77d2a571cff2eab39eab6f
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Mon Feb 25 00:03:10 2008 +0100
+
+ actua1/actua2/actua3: Fix multiple unused variable warnings
+
+ - actua1:
+ actux1.c: In function 'checkboard':
+ actux1.c:92: warning: unused variable 'revision'
+
+ - actua2:
+ actux2.c: In function 'checkboard':
+ actux2.c:100: warning: unused variable 's'
+ actux2.c:99: warning: unused variable 'revision'
+ actux2.c: In function 'reset_phy':
+ actux2.c:130: warning: unused variable 'i'
+
+ - actua3:
+ actux3.c: In function 'checkboard':
+ actux3.c:114: warning: unused variable 'revision'
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit f8fa6368a6a0c02164da8e2f52f18d457c6977bd
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sun Feb 24 11:44:29 2008 +0900
+
+ Remove the __STRICT_ANSI__ check from the __u64/__s64 declaration on 32bit targets.
+
+ The previous patch was lacking of i386, microblaze, nios and nios2. This
+ patch tries to fix them.
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 2b22fa4baee51e6b467c44ea1be0d1ecd86e8775
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Wed Feb 27 16:30:47 2008 -0600
+
+ 85xx: Don't icbi when unlocking the cache
+
+ There is no reason to icbi when invalidating the temporary stack in
+ the d-cache. Its impossible on e500 to have the i-cache contain
+ any addresses in the temp stack and it can be problematic in generating
+ transactions on the bus to non-valid addresses.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 534ea6b6f86f8b75ef2ac061ef110a98f103d7d6
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Feb 27 15:50:50 2008 -0600
+
+ Fix source for ECM error IVPR
+
+ The source vector for the ECM was being set to 2,
+ but that's what the source vector for DDR was being
+ set to. Change it to 1.
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 21fae8b2b4e4e6e648796e07e20ab13e9cb18923
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Feb 27 14:29:58 2008 -0600
+
+ Invalidate INIT_RAM TLB mappings
+
+ Commit 0db37dc... (and some others) changed the INIT_RAM TLB
+ mappings to be unguarded. This collided with an existing "bug"
+ where the mappings for the INIT_RAM were being kept around.
+ This meant that speculative loads to those addresses were
+ succeeding in the TLB, and going out to the bus, where they
+ were causing an exception (there's nothing at that address). The
+ Flash code was coincidentally causing such a speculative load.
+ Rather than go back to mapping the INIT RAM as guarded, we fix
+ it so that the entries for the INIT_RAM are invalidated. Thus
+ the speculative loads will fail in the TLB, and have no effect.
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 347b7938d3e561eb215aa386c37fb5acb5a383c6
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Feb 17 22:56:17 2008 +0100
+
+ sbc8548: Fix Revision reading and unused variable 'path'
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 495d162374c472f46454453553382ad0735dc725
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Feb 17 22:56:16 2008 +0100
+
+ sbc8548: Fix cfi flash bank declaration
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 33fa5c0bfaf465de8ceb23fcd6b397f68b35a817
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Mon Feb 25 13:13:37 2008 -0600
+
+ 86xx: Fix renamed GUR symbols in sbc8641d board.
+
+ Back in commit a551cee99ad1d1da20fd23ad265de47448852f56
+ (86xx: Fix GUR PCI config registers properly), we should have
+ changed the MPC86xx_PORBMSR_HA and MPC86xx_PORDEVSR_IO_SEL
+ symbols in the sbc8641d board as well. Fix this oversight.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 64cd594e623c39f73964d18787763e4533f791f7
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Feb 25 16:50:48 2008 +0100
+
+ ppc4xx: Fix acadia_nand build problem
+
+ Don't include testdram() on NAND-booting target acadia_nand. This saves
+ a few bytes and makes the target build clean again.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 14e099e698d41e8179d05c2b2dbcf704a236f748
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Feb 24 23:03:12 2008 +0000
+
+ mx1fs2/flash: Fix multiple pointertargets in assignment differ in signedness
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 724902c8464e610642b3a170278b99710325888e
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Feb 24 23:03:11 2008 +0000
+
+ arm-imx: Fix registers definition
+
+ Sync registers definition with linux
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 4cd288b589ea1178947c6e364453c32b3dede6b7
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Feb 24 23:03:10 2008 +0000
+
+ actua1/actua2/actua3: Fix multipleunused variable
+
+ - actua1:
+ actux1.c: In function 'checkboard':
+ actux1.c:92: warning: unused variable 'revision'
+
+ - actua2:
+ actux2.c: In function 'checkboard':
+ actux2.c:100: warning: unused variable 's'
+ actux2.c:99: warning: unused variable 'revision'
+ actux2.c: In function 'reset_phy':
+ actux2.c:130: warning: unused variable 'i'
+
+ - actua3:
+ actux3.c: In function 'checkboard':
+ actux3.c:114: warning: unused variable 'revision'
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit b29661fc1151077776454288051bc9a488351ce8
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Feb 24 15:21:36 2008 +0100
+
+ Coding style cleanup. Prepare v1.3.2-rc2 release candidate
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
commit 00b48a48424894daa589d166d73277830b1c6ac4
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sat Feb 23 12:15:56 2008 +0100
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
VERSION = 1
PATCHLEVEL = 3
SUBLEVEL = 2
-EXTRAVERSION = -rc2
+EXTRAVERSION =
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
VERSION_FILE = $(obj)include/version_autogenerated.h
endif
export obj src
+# Make sure CDPATH settings don't interfere
+unexport CDPATH
+
#########################################################################
ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk))
etags:
etags -a -o $(obj)etags `find $(SUBDIRS) $(TAG_SUBDIRS) \
-name '*.[ch]' -print`
+cscope:
+ find $(SUBDIRS) $(TAG_SUBDIRS) -name '*.[ch]' -print \
+ > cscope.files
+ cscope -b -q -k
$(obj)System.map: $(obj)u-boot
@$(NM) $< | \
all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
$(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
$(SUBDIRS) $(VERSION_FILE) gdbtools updater env depend \
-dep tags ctags etags $(obj)System.map:
+dep tags ctags etags cscope $(obj)System.map:
@echo "System not configured - see README" >&2
@ exit 1
endif # config.mk
icecube_5100_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/icecube
- @ >$(obj)include/config.h
@[ -z "$(findstring LOWBOOT_,$@)" ] || \
{ if [ "$(findstring DDR,$@)" ] ; \
then echo "TEXT_BASE = 0xFF800000" >$(obj)board/icecube/config.tmp ; \
lite5200b_LOWBOOT_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/icecube
- @ >$(obj)include/config.h
@ echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h
@ $(XECHO) "... DDR memory revision"
@ echo "#define CONFIG_MPC5200" >>$(obj)include/config.h
prs200_highboot_DDR_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/mcc200
- @ >$(obj)include/config.h
@[ -n "$(findstring highboot,$@)" ] || \
{ $(XECHO) "... with lowboot configuration" ; \
}
$(XECHO) "... with console on COM12" ; \
}
@[ -z "$(findstring prs200,$@)" ] || \
- { echo "#define CONFIG_PRS200" >>$(obj)include/config.h ;\
+ { echo "#define CONFIG_PRS200" >>$(obj)include/config.h ;\
}
@$(MKCONFIG) -n $@ -a mcc200 ppc mpc5xxx mcc200
munices_config: unconfig
@$(MKCONFIG) munices ppc mpc5xxx munices
-o2dnt_config:
+o2dnt_config: unconfig
@$(MKCONFIG) o2dnt ppc mpc5xxx o2dnt
-pf5200_config: unconfig
+pf5200_config: unconfig
@$(MKCONFIG) pf5200 ppc mpc5xxx pf5200 esd
PM520_config \
PM520_ROMBOOT_config \
PM520_ROMBOOT_DDR_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
@[ -z "$(findstring DDR,$@)" ] || \
{ echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h ; \
$(XECHO) "... DDR memory revision" ; \
@$(MKCONFIG) -a smmaco4 ppc mpc5xxx tqm5200
cm5200_config: unconfig
- @./mkconfig -a cm5200 ppc mpc5xxx cm5200
+ @$(MKCONFIG) -a cm5200 ppc mpc5xxx cm5200
spieval_config: unconfig
@$(MKCONFIG) -a spieval ppc mpc5xxx tqm5200
Total5200_Rev2_lowboot_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/total5200
- @ >$(obj)include/config.h
@[ -z "$(findstring 5100,$@)" ] || \
{ echo "#define CONFIG_MGT5100" >>$(obj)include/config.h ; \
$(XECHO) "... with MGT5100 processor" ; \
TQM5200_STK100_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/tqm5200
- @ >$(obj)include/config.h
@[ -z "$(findstring cam5200,$@)" ] || \
{ echo "#define CONFIG_CAM5200" >>$(obj)include/config.h ; \
echo "#define CONFIG_TQM5200S" >>$(obj)include/config.h ; \
#########################################################################
## MPC512x Systems
#########################################################################
-ads5121_config: unconfig
- @$(MKCONFIG) ads5121 ppc mpc512x ads5121
+ads5121_config \
+ads5121_PCI_config \
+ : unconfig
+ @mkdir -p $(obj)include
+ @if [ "$(findstring _PCI_,$@)" ] ; then \
+ echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
+ $(XECHO) "... with PCI enabled" ; \
+ fi
+ @$(MKCONFIG) -a ads5121 ppc mpc512x ads5121
#########################################################################
## MPC8xx Systems
#########################################################################
-Adder_config \
+Adder_config \
Adder87x_config \
-AdderII_config \
+AdderII_config \
: unconfig
@mkdir -p $(obj)include
$(if $(findstring AdderII,$@), \
@$(MKCONFIG) -a Adder ppc mpc8xx adder
AdderUSB_config: unconfig
- @./mkconfig -a AdderUSB ppc mpc8xx adder
+ @$(MKCONFIG) -a AdderUSB ppc mpc8xx adder
-ADS860_config \
-FADS823_config \
+ADS860_config \
+FADS823_config \
FADS850SAR_config \
MPC86xADS_config \
MPC885ADS_config \
GEN860T_SC_config \
GEN860T_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
@[ -z "$(findstring _SC,$@)" ] || \
{ echo "#define CONFIG_SC" >>$(obj)include/config.h ; \
$(XECHO) "With reduced H/W feature set (SC)..." ; \
ICU862_100MHz_config \
ICU862_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
@[ -z "$(findstring _100MHz,$@)" ] || \
{ echo "#define CONFIG_100MHz" >>$(obj)include/config.h ; \
$(XECHO) "... with 100MHz system clock" ; \
IVML24_128_config \
IVML24_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
@[ -z "$(findstring IVML24_config,$@)" ] || \
{ echo "#define CONFIG_IVML24_16M" >>$(obj)include/config.h ; \
}
IVMS8_128_config \
IVMS8_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
@[ -z "$(findstring IVMS8_config,$@)" ] || \
{ echo "#define CONFIG_IVMS8_16M" >>$(obj)include/config.h ; \
}
KUP4K_config : unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx kup4k kup
-KUP4X_config : unconfig
+KUP4X_config : unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx kup4x kup
LANTEC_config : unconfig
NETVIA_V2_config \
NETVIA_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
@[ -z "$(findstring NETVIA_config,$@)" ] || \
{ echo "#define CONFIG_NETVIA_VERSION 1" >>$(obj)include/config.h ; \
$(XECHO) "... Version 1" ; \
NETPHONE_V2_config \
NETPHONE_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
@[ -z "$(findstring NETPHONE_config,$@)" ] || \
{ echo "#define CONFIG_NETPHONE_VERSION 1" >>$(obj)include/config.h ; \
}
NETTA_6412_config \
NETTA_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
@[ -z "$(findstring ISDN_,$@)" ] || \
{ echo "#define CONFIG_NETTA_ISDN 1" >>$(obj)include/config.h ; \
}
NETTA2_V2_config \
NETTA2_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
@[ -z "$(findstring NETTA2_config,$@)" ] || \
{ echo "#define CONFIG_NETTA2_VERSION 1" >>$(obj)include/config.h ; \
}
NC650_Rev2_config \
CP850_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
@[ -z "$(findstring CP850,$@)" ] || \
{ echo "#define CONFIG_CP850 1" >>$(obj)include/config.h ; \
echo "#define CONFIG_IDS852_REV2 1" >>$(obj)include/config.h ; \
RPXlite_DW_LCD_config \
RPXlite_DW_64_LCD_config \
RPXlite_DW_NVRAM_config \
-RPXlite_DW_NVRAM_64_config \
+RPXlite_DW_NVRAM_64_config \
RPXlite_DW_NVRAM_LCD_config \
-RPXlite_DW_NVRAM_64_LCD_config \
+RPXlite_DW_NVRAM_64_LCD_config \
RPXlite_DW_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
@[ -z "$(findstring _64,$@)" ] || \
{ echo "#define RPXlite_64MHz" >>$(obj)include/config.h ; \
$(XECHO) "... with 64MHz system clock ..."; \
SM850_config : unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx
-spc1920_config:
+spc1920_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx spc1920
SPD823TS_config: unconfig
TK885D_config \
virtlab2_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
@[ -z "$(findstring _LCD,$@)" ] || \
{ echo "#define CONFIG_LCD" >>$(obj)include/config.h ; \
echo "#define CONFIG_NEC_NL6448BC20" >>$(obj)include/config.h ; \
PPChameleonEVB_ME_33_config \
PPChameleonEVB_HI_33_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
@[ -z "$(findstring EVB_BA,$@)" ] || \
{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>$(obj)include/config.h ; \
$(XECHO) "... BASIC model" ; \
@if [ "$(findstring _PCI_,$@)" ] ; then \
echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
$(XECHO) "... with PCI enabled" ; \
- else \
- >$(obj)include/config.h ; \
fi
@if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
$(XECHO) "... booting from 8-bit flash" ; \
TQM8260_AI_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \
TQM8265_AA_config) CTYPE=MPC8265; CFREQ=300; CACHE=no; BMODE=60x;; \
esac; \
- >$(obj)include/config.h ; \
if [ "$${CTYPE}" != "MPC8260" ] ; then \
echo "#define CONFIG_$${CTYPE}" >>$(obj)include/config.h ; \
fi; \
@$(MKCONFIG) -a TQM8260 ppc mpc8260 tqm8260
TQM8272_config: unconfig
- @$(MKCONFIG) -a TQM8272 ppc mpc8260 tqm8272
+ @$(MKCONFIG) TQM8272 ppc mpc8260 tqm8272
VoVPN-GW_66MHz_config \
VoVPN-GW_100MHz_config: unconfig
M5235EVB_Flash16_config) FLASH=16;; \
M5235EVB_Flash32_config) FLASH=32;; \
esac; \
- >$(obj)include/config.h ; \
if [ "$${FLASH}" != "16" ] ; then \
echo "#define NORFLASH_PS32BIT 1" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0xFFC00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
EB+MCF-EV123_config : unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/BuS/EB+MCF-EV123
- @ >$(obj)include/config.h
@echo "TEXT_BASE = 0xFFE00000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk
@$(MKCONFIG) EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
EB+MCF-EV123_internal_config : unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/BuS/EB+MCF-EV123
- @ >$(obj)include/config.h
@echo "TEXT_BASE = 0xF0000000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk
@$(MKCONFIG) EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
M5329AFEE_config) NAND=0;; \
M5329BFEE_config) NAND=16;; \
esac; \
- >$(obj)include/config.h ; \
if [ "$${NAND}" != "0" ] ; then \
echo "#define NANDFLASH_SIZE $${NAND}" > $(obj)include/config.h ; \
fi
@case "$@" in \
M5373EVB_config) NAND=16;; \
esac; \
- >include/config.h ; \
if [ "$${NAND}" != "0" ] ; then \
echo "#define NANDFLASH_SIZE $${NAND}" > $(obj)include/config.h ; \
fi
M54455EVB_i33_config) FLASH=INTEL; FREQ=33333333;; \
M54455EVB_i66_config) FLASH=INTEL; FREQ=66666666;; \
esac; \
- >$(obj)include/config.h ; \
if [ "$${FLASH}" = "INTEL" ] ; then \
echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
M5475FFE_config) BOOT=2;CODE=32;VID=1;USB=1;RAM=64;RAM1=64;; \
M5475GFE_config) BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
esac; \
- >include/config.h ; \
echo "#define CFG_BUSCLK 133333333" > $(obj)include/config.h ; \
echo "#define CFG_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \
echo "#define CFG_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \
M5485GFE_config) BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
M5485HFE_config) BOOT=2;CODE=16;VID=1;USB=0;RAM=64;RAM1=0;; \
esac; \
- >include/config.h ; \
echo "#define CFG_BUSCLK 100000000" > $(obj)include/config.h ; \
echo "#define CFG_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \
echo "#define CFG_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \
MPC8313ERDB_33_config \
MPC8313ERDB_66_config: unconfig
@mkdir -p $(obj)include
- @echo "" >$(obj)include/config.h ; \
- if [ "$(findstring _33_,$@)" ] ; then \
+ @if [ "$(findstring _33_,$@)" ] ; then \
$(XECHO) -n "...33M ..." ; \
echo "#define CFG_33MHZ" >>$(obj)include/config.h ; \
fi ; \
MPC832XEMDS_SLAVE_config \
MPC832XEMDS_ATM_config: unconfig
@mkdir -p $(obj)include
- @echo "" >$(obj)include/config.h ; \
- if [ "$(findstring _HOST_,$@)" ] ; then \
+ @if [ "$(findstring _HOST_,$@)" ] ; then \
$(XECHO) -n "... PCI HOST " ; \
echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _ATM_,$@)" ] ; then \
$(XECHO) -n "...ATM..." ; \
echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
- echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds freescale
MPC8360EMDS_SLAVE_config \
MPC8360EMDS_ATM_config: unconfig
@mkdir -p $(obj)include
- @echo "" >$(obj)include/config.h ; \
- if [ "$(findstring _HOST_,$@)" ] ; then \
+ @if [ "$(findstring _HOST_,$@)" ] ; then \
$(XECHO) -n "... PCI HOST " ; \
echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _ATM_,$@)" ] ; then \
$(XECHO) -n "...ATM..." ; \
echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
- echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale
MPC8360ERDK_33_config \
MPC8360ERDK_66_config \
-MPC8360ERDK_config:
+MPC8360ERDK_config: unconfig
@mkdir -p $(obj)include
- @echo "" >$(obj)include/config.h ; \
- if [ "$(findstring _33_,$@)" ] ; then \
+ @if [ "$(findstring _33_,$@)" ] ; then \
$(XECHO) -n "... CLKIN 33MHz " ; \
echo "#define CONFIG_CLKIN_33MHZ" >>$(obj)include/config.h ;\
fi ;
MPC837XEMDS_config \
MPC837XEMDS_HOST_config: unconfig
@mkdir -p $(obj)include
- @echo "" >$(obj)include/config.h ; \
- if [ "$(findstring _HOST_,$@)" ] ; then \
+ @if [ "$(findstring _HOST_,$@)" ] ; then \
$(XECHO) -n "... PCI HOST " ; \
echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
fi ;
MPC8540EVAL_33_config \
MPC8540EVAL_66_config \
MPC8540EVAL_33_slave_config \
-MPC8540EVAL_66_slave_config: unconfig
+MPC8540EVAL_66_slave_config: unconfig
@mkdir -p $(obj)include
- @echo "" >$(obj)include/config.h ; \
- if [ "$(findstring _33_,$@)" ] ; then \
+ @if [ "$(findstring _33_,$@)" ] ; then \
$(XECHO) "... 33 MHz PCI" ; \
else \
echo "#define CONFIG_SYSCLK_66M" >>$(obj)include/config.h ; \
MPC8541CDS_legacy_config \
MPC8541CDS_config: unconfig
@mkdir -p $(obj)include
- @echo "" >$(obj)include/config.h ; \
- if [ "$(findstring _legacy_,$@)" ] ; then \
+ @if [ "$(findstring _legacy_,$@)" ] ; then \
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
$(XECHO) "... legacy" ; \
fi
MPC8548CDS_legacy_config \
MPC8548CDS_config: unconfig
@mkdir -p $(obj)include
- @echo "" >$(obj)include/config.h ; \
- if [ "$(findstring _legacy_,$@)" ] ; then \
+ @if [ "$(findstring _legacy_,$@)" ] ; then \
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
$(XECHO) "... legacy" ; \
fi
MPC8555CDS_legacy_config \
MPC8555CDS_config: unconfig
@mkdir -p $(obj)include
- @echo "" >$(obj)include/config.h ; \
- if [ "$(findstring _legacy_,$@)" ] ; then \
+ @if [ "$(findstring _legacy_,$@)" ] ; then \
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
$(XECHO) "... legacy" ; \
fi
echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \
$(XECHO) "... 66 MHz PCI" ; \
else \
- >$(obj)include/config.h ; \
$(XECHO) "... 33 MHz PCI" ; \
fi
@$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560
sbc8560_config \
sbc8560_33_config \
-sbc8560_66_config: unconfig
+sbc8560_66_config: unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _66_,$@)" ] ; then \
echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \
$(XECHO) "... 66 MHz PCI" ; \
else \
- >$(obj)include/config.h ; \
$(XECHO) "... 33 MHz PCI" ; \
fi
@$(MKCONFIG) -a sbc8560 ppc mpc85xx sbc8560
@if [ "$(findstring _4M_,$@)" ] ; then \
echo "#define CONFIG_STXSSA_4M" >>$(obj)include/config.h ; \
$(XECHO) "... with 4 MiB flash memory" ; \
- else \
- >$(obj)include/config.h ; \
fi
@$(MKCONFIG) -a stxssa ppc mpc85xx stxssa
TQM8560_config: unconfig
@mkdir -p $(obj)include
@CTYPE=$(subst TQM,,$(@:_config=)); \
- >$(obj)include/config.h ; \
$(XECHO) "... TQM"$${CTYPE}; \
echo "#define CONFIG_MPC$${CTYPE}">>$(obj)include/config.h; \
echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \
@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
sbc8641d_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc86xx sbc8641d
+ @$(MKCONFIG) $(@:_config=) ppc mpc86xx sbc8641d
#########################################################################
## 74xx/7xx Systems
trab_old_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/trab
- @ >$(obj)include/config.h
@[ -z "$(findstring _bigram,$@)" ] || \
{ echo "#define CONFIG_FLASH_8MB" >>$(obj)include/config.h ; \
echo "#define CONFIG_RAM_32MB" >>$(obj)include/config.h ; \
gth2_config : unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
- @echo "#define CONFIG_GTH2 1" >>$(obj)include/config.h
+ @echo "#define CONFIG_GTH2 1" >$(obj)include/config.h
@$(MKCONFIG) -a gth2 mips mips gth2
#########################################################################
csb226_config : unconfig
@$(MKCONFIG) $(@:_config=) arm pxa csb226
-delta_config :
+delta_config : unconfig
@$(MKCONFIG) $(@:_config=) arm pxa delta
innokom_config : unconfig
@$(MKCONFIG) $(@:_config=) arm pxa logodl
pdnb3_config \
-scpu_config: unconfig
+scpu_config: unconfig
@mkdir -p $(obj)include
@if [ "$(findstring scpu_,$@)" ] ; then \
- echo "#define CONFIG_SCPU" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_SCPU" >>$(obj)include/config.h ; \
$(XECHO) "... on SCPU board variant" ; \
- else \
- >$(obj)include/config.h ; \
fi
@$(MKCONFIG) -a pdnb3 arm ixp pdnb3 prodrive
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4
apollon_config : unconfig
+ @mkdir -p $(obj)include
@echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h
@$(MKCONFIG) $(@:_config=) arm arm1136 apollon
@echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
incaip_150MHz_config \
incaip_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
@[ -z "$(findstring _100MHz,$@)" ] || \
{ echo "#define CPU_CLOCK_RATE 100000000" >>$(obj)include/config.h ; \
$(XECHO) "... with 100MHz system clock" ; \
#########################################################################
dbau1000_config : unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
- @echo "#define CONFIG_DBAU1000 1" >>$(obj)include/config.h
+ @echo "#define CONFIG_DBAU1000 1" >$(obj)include/config.h
@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
dbau1100_config : unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
- @echo "#define CONFIG_DBAU1100 1" >>$(obj)include/config.h
+ @echo "#define CONFIG_DBAU1100 1" >$(obj)include/config.h
@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
dbau1500_config : unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
- @echo "#define CONFIG_DBAU1500 1" >>$(obj)include/config.h
+ @echo "#define CONFIG_DBAU1500 1" >$(obj)include/config.h
@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
dbau1550_config : unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
- @echo "#define CONFIG_DBAU1550 1" >>$(obj)include/config.h
+ @echo "#define CONFIG_DBAU1550 1" >$(obj)include/config.h
@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
dbau1550_el_config : unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
- @echo "#define CONFIG_DBAU1550 1" >>$(obj)include/config.h
+ @echo "#define CONFIG_DBAU1550 1" >$(obj)include/config.h
@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
pb1000_config : unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
- @echo "#define CONFIG_PB1000 1" >>$(obj)include/config.h
+ @echo "#define CONFIG_PB1000 1" >$(obj)include/config.h
@$(MKCONFIG) -a pb1x00 mips mips pb1x00
qemu_mips_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
- @echo "#define CONFIG_QEMU_MIPS 1" >>$(obj)include/config.h
+ @echo "#define CONFIG_QEMU_MIPS 1" >$(obj)include/config.h
@$(MKCONFIG) -a qemu-mips mips mips qemu-mips
#########################################################################
DK1C20_standard_32_config \
DK1C20_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
@[ -z "$(findstring _safe_32,$@)" ] || \
{ echo "#define CONFIG_NIOS_SAFE_32 1" >>$(obj)include/config.h ; \
$(XECHO) "... NIOS 'safe_32' configuration" ; \
DK1S10_mtx_ldk_20_config \
DK1S10_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
@[ -z "$(findstring _safe_32,$@)" ] || \
{ echo "#define CONFIG_NIOS_SAFE_32 1" >>$(obj)include/config.h ; \
$(XECHO) "... NIOS 'safe_32' configuration" ; \
ADNPESC1_base_32_config \
ADNPESC1_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
@[ -z "$(findstring _DNPEVA2,$@)" ] || \
{ echo "#define CONFIG_DNPEVA2 1" >>$(obj)include/config.h ; \
$(XECHO) "... DNP/EVA2 configuration" ; \
#########################################################################
suzaku_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
- @echo "#define CONFIG_SUZAKU 1" >> $(obj)include/config.h
+ @echo "#define CONFIG_SUZAKU 1" > $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
ml401_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
- @echo "#define CONFIG_ML401 1" >> $(obj)include/config.h
+ @echo "#define CONFIG_ML401 1" > $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) microblaze microblaze ml401 xilinx
xupv2p_config: unconfig
@mkdir -p $(obj)include
- @ >$(obj)include/config.h
- @echo "#define CONFIG_XUPV2P 1" >> $(obj)include/config.h
+ @echo "#define CONFIG_XUPV2P 1" > $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) microblaze microblaze xupv2p xilinx
#========================================================================
## sh3 (Renesas SuperH)
#########################################################################
ms7720se_config: unconfig
- @ >include/config.h
- @echo "#define CONFIG_MS7720SE 1" >> include/config.h
- @./mkconfig -a $(@:_config=) sh sh3 ms7720se
+ @echo "#define CONFIG_MS7720SE 1" > include/config.h
+ @$(MKCONFIG) -a $(@:_config=) sh sh3 ms7720se
#########################################################################
## sh4 (Renesas SuperH)
#########################################################################
ms7750se_config: unconfig
- @ >$(obj)include/config.h
- @echo "#define CONFIG_MS7750SE 1" >> $(obj)include/config.h
- @./mkconfig -a $(@:_config=) sh sh4 ms7750se
+ @echo "#define CONFIG_MS7750SE 1" > $(obj)include/config.h
+ @$(MKCONFIG) -a $(@:_config=) sh sh4 ms7750se
-ms7722se_config : unconfig
- @ >$(obj)include/config.h
- @echo "#define CONFIG_MS7722SE 1" >> $(obj)include/config.h
- @./mkconfig -a $(@:_config=) sh sh4 ms7722se
+ms7722se_config : unconfig
+ @echo "#define CONFIG_MS7722SE 1" > $(obj)include/config.h
+ @$(MKCONFIG) -a $(@:_config=) sh sh4 ms7722se
#########################################################################
#########################################################################
#########################################################################
clean:
+ @rm -f $(obj)examples/82559_eeprom $(obj)examples/eepro100_eeprom \
+ $(obj)examples/hello_world $(obj)examples/interrupt \
+ $(obj)examples/mem_to_mem_idma2intr \
+ $(obj)examples/sched $(obj)examples/smc91111_eeprom \
+ $(obj)examples/test_burst $(obj)examples/timer
+ @rm -f $(obj)tools/bmp_logo $(obj)tools/easylogo/easylogo \
+ $(obj)tools/env/{fw_printenv,fw_setenv} \
+ $(obj)tools/envcrc \
+ $(obj)tools/gdb/{astest,gdbcont,gdbsend} \
+ $(obj)tools/gen_eth_addr $(obj)tools/img2srec \
+ $(obj)tools/mkimage $(obj)tools/mpc86x_clk \
+ $(obj)tools/ncb $(obj)tools/ubsha1
+ @rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \
+ $(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
+ $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
+ $(obj)board/{integratorap,integratorcp}/u-boot.lds \
+ $(obj)board/{bf533-ezkit,bf533-stamp,bf537-stamp,bf561-ezkit}/u-boot.lds
+ @rm -f $(obj)include/bmp_logo.h $(obj)nand_spl/{u-boot-spl,u-boot-spl.map}
+ @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl.map}
+ @rm -f $(obj)api_examples/demo $(VERSION_FILE)
@find $(OBJTREE) -type f \
\( -name 'core' -o -name '*.bak' -o -name '*~' \
- -o -name '*.o' -o -name '*.a' \) -print \
+ -o -name '*.o' -o -name '*.a' \) -print \
| xargs rm -f
- @rm -f $(obj)examples/hello_world $(obj)examples/timer \
- $(obj)examples/eepro100_eeprom $(obj)examples/sched \
- $(obj)examples/mem_to_mem_idma2intr $(obj)examples/82559_eeprom \
- $(obj)examples/smc91111_eeprom $(obj)examples/interrupt \
- $(obj)examples/test_burst
- @rm -f $(obj)tools/img2srec $(obj)tools/mkimage $(obj)tools/envcrc \
- $(obj)tools/gen_eth_addr $(obj)tools/ubsha1
- @rm -f $(obj)tools/mpc86x_clk $(obj)tools/ncb
- @rm -f $(obj)tools/easylogo/easylogo $(obj)tools/bmp_logo
- @rm -f $(obj)tools/gdb/astest $(obj)tools/gdb/gdbcont $(obj)tools/gdb/gdbsend
- @rm -f $(obj)tools/env/fw_printenv $(obj)tools/env/fw_setenv
- @rm -f $(obj)board/cray/L1/bootscript.c $(obj)board/cray/L1/bootscript.image
- @rm -f $(obj)board/netstar/eeprom $(obj)board/netstar/crcek $(obj)board/netstar/crcit
- @rm -f $(obj)board/netstar/*.srec $(obj)board/netstar/*.bin
- @rm -f $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom
- @rm -f $(obj)board/integratorap/u-boot.lds $(obj)board/integratorcp/u-boot.lds
- @rm -f $(obj)board/bf533-ezkit/u-boot.lds $(obj)board/bf533-stamp/u-boot.lds
- @rm -f $(obj)board/bf537-stamp/u-boot.lds $(obj)board/bf561-ezkit/u-boot.lds
- @rm -f $(obj)include/bmp_logo.h
- @rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map
- @rm -f $(obj)onenand_ipl/onenand-ipl $(obj)onenand_ipl/onenand-ipl.bin \
- $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)onenand_ipl/onenand-ipl.map
- @rm -f $(obj)api_examples/demo $(VERSION_FILE)
clobber: clean
@find $(OBJTREE) -type f \( -name .depend \
-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
-print0 \
| xargs -0 rm -f
- @rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS
- @rm -fr $(obj)*.*~
+ @rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \
+ $(obj)cscope.* $(obj)*.*~
@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
- @rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c
- @rm -f $(obj)tools/sha1.c $(obj)tools/image.c
- @rm -f $(obj)tools/fdt.c $(obj)tools/fdt_ro.c $(obj)tools/fdt_rw.c
- @rm -f $(obj)tools/fdt_strerror.c $(obj)tools/fdt_wip.c
- @rm -f $(obj)tools/libfdt_internal.h
- @rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c
+ @rm -f $(obj)tools/{crc32.c,environment.c,env/crc32.c,sha1.c,inca-swap-bytes}
+ @rm -f $(obj)tools/{image.c,fdt.c,fdt_ro.c,fdt_rw.c,fdt_strerror.c}
+ @rm -f $(obj)tools/{fdt_wip.c,libfdt_internal.h}
+ @rm -f $(obj)cpu/mpc824x/bedbug_603e.c
@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -lname "*" -print | xargs rm -f
*/
int checkboard (void)
{
- char revision;
char *s = getenv ("serial#");
puts ("Board: AcTux-1 rev.");
*/
int checkboard (void)
{
- char revision;
char *s = getenv ("serial#");
puts ("Board: AcTux-2 rev.");
putc (ACTUX2_BOARDREL + 'A' - 1);
+
+ if (s != NULL) {
+ puts (", serial# ");
+ puts (s);
+ }
putc ('\n');
return (0);
void reset_phy (void)
{
- int i;
-
/* init IcPlus IP175C ethernet switch to native IP175C mode */
miiphy_write ("NPE0", 29, 31, 0x175C);
}
*/
int checkboard (void)
{
- char revision;
char *s = getenv ("serial#");
puts ("Board: AcTux-3 rev.");
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
CLOCK_SCCR1_PSCFIFO_EN | \
CLOCK_SCCR1_DDR_EN | \
CLOCK_SCCR1_FEC_EN | \
+ CLOCK_SCCR1_PCI_EN | \
CLOCK_SCCR1_TPR_EN)
#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
--- /dev/null
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/mmu.h>
+#include <asm/global_data.h>
+#include <pci.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <fdt_support.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
+
+static struct pci_controller pci_hose;
+
+
+/**************************************************************************
+ * pci_init_board()
+ *
+ */
+void
+pci_init_board(void)
+{
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile law512x_t *pci_law;
+ volatile pot512x_t *pci_pot;
+ volatile pcictrl512x_t *pci_ctrl;
+ volatile pciconf512x_t *pci_conf;
+ u16 reg16;
+ u32 reg32;
+ u32 dev;
+ struct pci_controller *hose;
+
+ /* Set PCI divider for 33MHz */
+ reg32 = immr->clk.scfr[0];
+ reg32 &= ~(SCFR1_PCI_DIV_MASK);
+ reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT;
+ immr->clk.scfr[0] = reg32;
+
+ pci_law = immr->sysconf.pcilaw;
+ pci_pot = immr->ios.pot;
+ pci_ctrl = &immr->pci_ctrl;
+ pci_conf = &immr->pci_conf;
+
+ hose = &pci_hose;
+
+ /*
+ * Release PCI RST Output signal
+ */
+ pci_ctrl->gcr = 0;
+ udelay(2000);
+ pci_ctrl->gcr = 1;
+
+ /* We need to wait at least a 1sec based on PCI specs */
+ {
+ int i;
+
+ for (i = 0; i < 1000; i++)
+ udelay(1000);
+ }
+
+ /*
+ * Configure PCI Local Access Windows
+ */
+ pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+ pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
+
+ /*
+ * Configure PCI Outbound Translation Windows
+ */
+
+ /* PCI mem space - prefetch */
+ pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[0].pocmr = POCMR_EN | POCMR_PRE | POCMR_CM_256M;
+
+ /* PCI IO space */
+ pci_pot[1].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[1].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
+
+ /* PCI mmio - non-prefetch mem space */
+ pci_pot[2].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[2].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
+
+ /*
+ * Configure PCI Inbound Translation Windows
+ */
+
+ /* we need RAM mapped to PCI space for the devices to
+ * access main memory */
+ pci_ctrl[0].pitar1 = 0x0;
+ pci_ctrl[0].pibar1 = 0x0;
+ pci_ctrl[0].piebar1 = 0x0;
+ pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+ PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ /* PCI memory prefetch space */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEM_BASE,
+ CFG_PCI_MEM_PHYS,
+ CFG_PCI_MEM_SIZE,
+ PCI_REGION_MEM|PCI_REGION_PREFETCH);
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI_MMIO_BASE,
+ CFG_PCI_MMIO_PHYS,
+ CFG_PCI_MMIO_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI IO space */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI_IO_BASE,
+ CFG_PCI_IO_PHYS,
+ CFG_PCI_IO_SIZE,
+ PCI_REGION_IO);
+
+ /* System memory space */
+ pci_set_region(hose->regions + 3,
+ CONFIG_PCI_SYS_MEM_BUS,
+ CONFIG_PCI_SYS_MEM_PHYS,
+ gd->ram_size,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ hose->region_count = 4;
+
+ pci_setup_indirect(hose,
+ (CFG_IMMR + 0x8300),
+ (CFG_IMMR + 0x8304));
+
+ pci_register_hose(hose);
+
+ /*
+ * Write to Command register
+ */
+ reg16 = 0xff;
+ dev = PCI_BDF(hose->first_busno, 0, 0);
+ pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+ printf("PCI: Bus Dev VenId DevId Class Int\n");
+#endif
+ /*
+ * Hose scan.
+ */
+ hose->last_busno = pci_hose_scan(hose);
+}
+
+#if defined(CONFIG_OF_LIBFDT)
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+ int nodeoffset;
+ int tmp[2];
+ const char *path;
+
+ nodeoffset = fdt_path_offset(blob, "/aliases");
+ if (nodeoffset >= 0) {
+ path = fdt_getprop(blob, nodeoffset, "pci", NULL);
+ if (path) {
+ tmp[0] = cpu_to_be32(pci_hose.first_busno);
+ tmp[1] = cpu_to_be32(pci_hose.last_busno);
+ do_fixup_by_path(blob, path, "bus-range",
+ &tmp, sizeof(tmp), 1);
+
+ tmp[0] = cpu_to_be32(gd->pci_clk);
+ do_fixup_by_path(blob, path, "clock-frequency",
+ &tmp, sizeof(tmp[0]), 1);
+ }
+ }
+}
+#endif /* CONFIG_OF_LIBFDT */
return (CFG_MBYTES_RAM << 20);
}
+#ifndef CONFIG_NAND_SPL
int testdram(void)
{
return (0);
}
+#endif
unsigned char spi_read(void)
{
- return (unsigned char)gpio_read_out_bit(SPI_DIN_GPIO15);
+ return (unsigned char)gpio_read_in_bit(SPI_DIN_GPIO15);
}
void taihu_spi_chipsel(int cs)
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
#include <asm/io.h>
-#include <spd.h>
+#include <spd_sdram.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
-extern long int spd_sdram(void);
long int fixed_sdram(void);
int board_early_init_f (void)
#define MAX_ONES 226
#ifdef CFG_FPGA_PRG
-# define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (ppc output)*/
-# define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (ppc output) */
-# define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (ppc output) */
-# define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (ppc input) */
-# define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (ppc input) */
+# define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (ppc output) */
+# define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (ppc output) */
+# define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (ppc output) */
+# define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (ppc input) */
+# define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (ppc input) */
#else
-# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
-# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
+# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
+# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
+# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
+# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
+# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
#endif
-#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
-#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
-#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
+#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
+#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
+#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
#ifndef SET_FPGA
# define SET_FPGA(data) out32(GPIO0_OR, data)
SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \
SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set data to 1 */ \
SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set clock to 1 */ \
- SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
+ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
#define FPGA_WRITE_0 { \
SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \
SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_LOW); /* set data to 0 */ \
SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_LOW); /* set clock to 1 */ \
- SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
+ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
#ifndef FPGA_DONE_STATE
# define FPGA_DONE_STATE (in32(GPIO0_IR) & FPGA_DONE)
#endif
-static int fpga_boot(unsigned char *fpgadata, int size)
+static int fpga_boot (const unsigned char *fpgadata, int size)
{
- int i,index,len;
- int count;
+ int i, index, len;
+ int count;
+ unsigned char b;
+
#ifdef CFG_FPGA_SPARTAN2
- int j;
+ int j;
#else
- unsigned char b;
- int bit;
+ int bit;
#endif
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++)
- {
- len = fpgadata[index];
- DBG("FPGA: %s\n", &(fpgadata[index+1]));
- index += len+3;
- }
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i = 0; i < 4; i++) {
+ len = fpgadata[index];
+ DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
+ index += len + 3;
+ }
#ifdef CFG_FPGA_SPARTAN2
- /* search for preamble 0xFFFFFFFF */
- while (1)
- {
- if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) &&
- (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff))
- break; /* preamble found */
- else
- index++;
- }
+ /* search for preamble 0xFFFFFFFF */
+ while (1) {
+ if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
+ && (fpgadata[index + 2] == 0xff)
+ && (fpgadata[index + 3] == 0xff))
+ break; /* preamble found */
+ else
+ index++;
+ }
#else
- /* search for preamble 0xFF2X */
- for (index = 0; index < size-1 ; index++)
- {
- if ((fpgadata[index] == 0xff) && ((fpgadata[index+1] & 0xf0) == 0x30))
- break;
- }
- index += 2;
+ /* search for preamble 0xFF2X */
+ for (index = 0; index < size - 1; index++) {
+ if ((fpgadata[index] == 0xff)
+ && ((fpgadata[index + 1] & 0xf0) == 0x30))
+ break;
+ }
+ index += 2;
#endif
- DBG("FPGA: configdata starts at position 0x%x\n",index);
- DBG("FPGA: length of fpga-data %d\n", size-index);
+ DBG ("FPGA: configdata starts at position 0x%x\n", index);
+ DBG ("FPGA: length of fpga-data %d\n", size - index);
- /*
- * Setup port pins for fpga programming
- */
+ /*
+ * Setup port pins for fpga programming
+ */
#ifndef CONFIG_M5249
- out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */
+ out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */
#endif
- SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */
-
- DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
- DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
-
- /*
- * Init fpga by asserting and deasserting PROGRAM*
- */
- SET_FPGA(FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog active */
-
- /* Wait for FPGA init line low */
- count = 0;
- while (FPGA_INIT_STATE)
- {
- udelay(1000); /* wait 1ms */
- /* Check for timeout - 100us max, so use 3ms */
- if (count++ > 3)
- {
- DBG("FPGA: Booting failed!\n");
- return ERROR_FPGA_PRG_INIT_LOW;
+ SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */
+
+ DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+ DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
+
+ /*
+ * Init fpga by asserting and deasserting PROGRAM*
+ */
+ SET_FPGA (FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog active */
+
+ /* Wait for FPGA init line low */
+ count = 0;
+ while (FPGA_INIT_STATE) {
+ udelay (1000); /* wait 1ms */
+ /* Check for timeout - 100us max, so use 3ms */
+ if (count++ > 3) {
+ DBG ("FPGA: Booting failed!\n");
+ return ERROR_FPGA_PRG_INIT_LOW;
+ }
}
- }
-
- DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
- DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
-
- /* deassert PROGRAM* */
- SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog inactive */
-
- /* Wait for FPGA end of init period . */
- count = 0;
- while (!(FPGA_INIT_STATE))
- {
- udelay(1000); /* wait 1ms */
- /* Check for timeout */
- if (count++ > 3)
- {
- DBG("FPGA: Booting failed!\n");
- return ERROR_FPGA_PRG_INIT_HIGH;
+
+ DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+ DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
+
+ /* deassert PROGRAM* */
+ SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog inactive */
+
+ /* Wait for FPGA end of init period . */
+ count = 0;
+ while (!(FPGA_INIT_STATE)) {
+ udelay (1000); /* wait 1ms */
+ /* Check for timeout */
+ if (count++ > 3) {
+ DBG ("FPGA: Booting failed!\n");
+ return ERROR_FPGA_PRG_INIT_HIGH;
+ }
}
- }
- DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
- DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
+ DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+ DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
- DBG("write configuration data into fpga\n");
- /* write configuration-data into fpga... */
+ DBG ("write configuration data into fpga\n");
+ /* write configuration-data into fpga... */
#ifdef CFG_FPGA_SPARTAN2
- /*
- * Load uncompressed image into fpga
- */
- for (i=index; i<size; i++)
- {
- for (j=0; j<8; j++)
- {
- if ((fpgadata[i] & 0x80) == 0x80)
- {
- FPGA_WRITE_1;
- }
- else
- {
- FPGA_WRITE_0;
- }
- fpgadata[i] <<= 1;
+ /*
+ * Load uncompressed image into fpga
+ */
+ for (i = index; i < size; i++) {
+ b = fpgadata[i];
+ for (j = 0; j < 8; j++) {
+ if ((b & 0x80) == 0x80) {
+ FPGA_WRITE_1;
+ } else {
+ FPGA_WRITE_0;
+ }
+ b <<= 1;
+ }
}
- }
#else
- /* send 0xff 0x20 */
- FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
- FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
- FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_1; FPGA_WRITE_0;
- FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_0;
-
- /*
- ** Bit_DeCompression
- ** Code 1 .. maxOnes : n '1's followed by '0'
- ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
- ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
- ** 255 : '1'
- */
-
- for (i=index; i<size; i++)
- {
- b = fpgadata[i];
- if ((b >= 1) && (b <= MAX_ONES))
- {
- for(bit=0; bit<b; bit++)
- {
- FPGA_WRITE_1;
- }
- FPGA_WRITE_0;
- }
- else if (b == (MAX_ONES+1))
- {
- for(bit=1; bit<b; bit++)
- {
- FPGA_WRITE_1;
- }
- }
- else if ((b >= (MAX_ONES+2)) && (b <= 254))
- {
- for(bit=0; bit<(b-(MAX_ONES+2)); bit++)
- {
- FPGA_WRITE_0;
- }
- FPGA_WRITE_1;
- }
- else if (b == 255)
- {
- FPGA_WRITE_1;
+ /* send 0xff 0x20 */
+ FPGA_WRITE_1;
+ FPGA_WRITE_1;
+ FPGA_WRITE_1;
+ FPGA_WRITE_1;
+ FPGA_WRITE_1;
+ FPGA_WRITE_1;
+ FPGA_WRITE_1;
+ FPGA_WRITE_1;
+ FPGA_WRITE_0;
+ FPGA_WRITE_0;
+ FPGA_WRITE_1;
+ FPGA_WRITE_0;
+ FPGA_WRITE_0;
+ FPGA_WRITE_0;
+ FPGA_WRITE_0;
+ FPGA_WRITE_0;
+
+ /*
+ ** Bit_DeCompression
+ ** Code 1 .. maxOnes : n '1's followed by '0'
+ ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
+ ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
+ ** 255 : '1'
+ */
+
+ for (i = index; i < size; i++) {
+ b = fpgadata[i];
+ if ((b >= 1) && (b <= MAX_ONES)) {
+ for (bit = 0; bit < b; bit++) {
+ FPGA_WRITE_1;
+ }
+ FPGA_WRITE_0;
+ } else if (b == (MAX_ONES + 1)) {
+ for (bit = 1; bit < b; bit++) {
+ FPGA_WRITE_1;
+ }
+ } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
+ for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
+ FPGA_WRITE_0;
+ }
+ FPGA_WRITE_1;
+ } else if (b == 255) {
+ FPGA_WRITE_1;
+ }
}
- }
#endif
- DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
- DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
-
- /*
- * Check if fpga's DONE signal - correctly booted ?
- */
-
- /* Wait for FPGA end of programming period . */
- count = 0;
- while (!(FPGA_DONE_STATE))
- {
- udelay(1000); /* wait 1ms */
- /* Check for timeout */
- if (count++ > 3)
- {
- DBG("FPGA: Booting failed!\n");
- return ERROR_FPGA_PRG_DONE;
+ DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+ DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
+
+ /*
+ * Check if fpga's DONE signal - correctly booted ?
+ */
+
+ /* Wait for FPGA end of programming period . */
+ count = 0;
+ while (!(FPGA_DONE_STATE)) {
+ udelay (1000); /* wait 1ms */
+ /* Check for timeout */
+ if (count++ > 3) {
+ DBG ("FPGA: Booting failed!\n");
+ return ERROR_FPGA_PRG_DONE;
+ }
}
- }
- DBG("FPGA: Booting successful!\n");
- return 0;
+ DBG ("FPGA: Booting successful!\n");
+ return 0;
}
#include <ioports.h>
#include <mpc83xx.h>
#include <i2c.h>
-#include <spd.h>
#include <miiphy.h>
#include <command.h>
#include <libfdt.h>
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
-#if defined(CONFIG_SPD_EEPROM)
-#include <spd_sdram.h>
-#else
#include <asm/mmu.h>
-#endif
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* UCC3 */
#include <ioports.h>
#include <mpc83xx.h>
#include <i2c.h>
-#include <spd.h>
#include <miiphy.h>
#include <command.h>
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
-#if defined(CONFIG_SPD_EEPROM)
-#include <spd_sdram.h>
-#else
#include <asm/mmu.h>
-#endif
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <spi.h>
-#include <spd.h>
#include <miiphy.h>
-#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
-#endif
+
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include <ioports.h>
#include <mpc83xx.h>
#include <i2c.h>
-#include <spd.h>
#include <miiphy.h>
-
#ifdef CONFIG_PCI
#include <asm/mpc8349_pci.h>
#include <pci.h>
#endif
-
-#ifdef CONFIG_SPD_EEPROM
#include <spd_sdram.h>
-#else
#include <asm/mmu.h>
-#endif
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include <ioports.h>
#include <mpc83xx.h>
#include <i2c.h>
-#include <spd.h>
#include <miiphy.h>
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
-#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
-#else
#include <asm/mmu.h>
-#endif
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include <ioports.h>
#include <mpc83xx.h>
#include <i2c.h>
-#include <spd.h>
#include <miiphy.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <common.h>
#include <i2c.h>
-#include <spd.h>
-#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
-#endif
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include <common.h>
#include <i2c.h>
-#include <spd.h>
#include <asm/io.h>
-#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
-#endif
#if defined(CFG_DRAM_TEST)
int
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
-#include <spd.h>
+#include <spd_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
-extern long int spd_sdram(void);
-
void local_bus_init(void);
void sdram_init(void);
long int fixed_sdram(void);
initdram(int board_type)
{
long dram_size = 0;
- extern long spd_sdram (void);
puts("Initializing\n");
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
-#include <spd.h>
+#include <spd_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
-extern long int spd_sdram(void);
-
void local_bus_init(void);
void sdram_init(void);
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
#include <asm/io.h>
-#include <spd.h>
+#include <spd_sdram.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
-extern long int spd_sdram(void);
-
void sdram_init(void);
int board_early_init_f (void)
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
-#include <spd.h>
+#include <spd_sdram.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
-extern long int spd_sdram(void);
-
void local_bus_init(void);
void sdram_init(void);
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
-#include <spd.h>
+#include <spd_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
-extern long int spd_sdram(void);
-
void local_bus_init(void);
void sdram_init(void);
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
-#include <spd.h>
+#include <spd_sdram.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
-extern long int spd_sdram(void);
void local_bus_init(void);
void sdram_init(void);
initdram(int board_type)
{
long dram_size = 0;
- extern long spd_sdram (void);
puts("Initializing\n");
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
-#include <spd.h>
+#include <spd_sdram.h>
#include <i2c.h>
#include <ioports.h>
#include <libfdt.h>
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
-extern long int spd_sdram(void);
-
void local_bus_init(void);
void sdram_init(void);
#include <asm/immap_86xx.h>
#include <asm/immap_fsl_pci.h>
#include <i2c.h>
-#include <spd.h>
#include <asm/io.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <spd_sdram.h>
#include "../common/pixis.h"
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
-#if defined(CONFIG_SPD_EEPROM)
-#include "spd_sdram.h"
-#endif
-
void sdram_init(void);
long int fixed_sdram(void);
void mpc8610hpcd_diu_init(void);
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/immap_fsl_pci.h>
-#include <spd.h>
+#include <spd_sdram.h>
#include <asm/io.h>
#include <libfdt.h>
#include <fdt_support.h>
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
-#if defined(CONFIG_SPD_EEPROM)
-#include "spd_sdram.h"
-#endif
-
void sdram_init(void);
long int fixed_sdram(void);
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := m501sk.o eeprom.o
+COBJS := m501sk.o eeprom.o
SOBJS := memsetup.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
return 0;
}
+/*
+ * Early board initalization.
+ */
+int board_early_init_r(void)
+{
+ /* setup the UPIOx */
+ *(char *)(CFG_PIGGY_BASE + 0x02) = 0xc0;
+ *(char *)(CFG_PIGGY_BASE + 0x03) = 0x15;
+ return 0;
+}
+
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
/*
* update "memory" property in the blob
{
int ret, nodeoffset = 0;
ulong memory_data[2] = {0};
- ulong flash_data[4] = {0};
+ ulong flash_data[8] = {0};
memory_data[0] = cpu_to_be32(bd->bi_memstart);
memory_data[1] = cpu_to_be32(bd->bi_memsize);
printf("ft_blob_update(): cannot find /memory node "
"err:%s\n", fdt_strerror(nodeoffset));
}
- /* update Flash size */
- flash_data[2] = cpu_to_be32(bd->bi_flashstart);
- flash_data[3] = cpu_to_be32(bd->bi_flashsize);
+ /* update Flash addr, size */
+ flash_data[2] = cpu_to_be32(CFG_FLASH_BASE);
+ flash_data[3] = cpu_to_be32(CFG_FLASH_SIZE);
+ flash_data[4] = cpu_to_be32(1);
+ flash_data[5] = cpu_to_be32(0);
+ flash_data[6] = cpu_to_be32(CFG_FLASH_BASE_1);
+ flash_data[7] = cpu_to_be32(CFG_FLASH_SIZE_1);
nodeoffset = fdt_path_offset (blob, "/localbus");
if (nodeoffset >= 0) {
ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data,
}
else {
/* memory node is required in dts */
- printf("ft_blob_update(): cannot find /localbus node "
+ printf("ft_blob_update(): cannot find /soc/cpm/ethernet node "
"err:%s\n", fdt_strerror(nodeoffset));
}
return (size);
}
+/*
+ * Early board initalization.
+ */
+int board_early_init_r(void)
+{
+ /* setup the UPIOx */
+ *(char *)(CFG_PIGGY_BASE + 0x02) = 0xc0;
+ *(char *)(CFG_PIGGY_BASE + 0x03) = 0x35;
+ return 0;
+}
+
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
/*
* update "memory" property in the blob
}
/* BRG */
brg_data[0] = cpu_to_be32(bd->bi_busfreq);
- nodeoffset = fdt_path_offset (blob, "/soc866/cpm");
+ nodeoffset = fdt_path_offset (blob, "/soc/cpm");
if (nodeoffset >= 0) {
ret = fdt_setprop(blob, nodeoffset, "brg-frequency", brg_data,
sizeof(brg_data));
if (ret < 0)
- printf("ft_blob_update): cannot set /soc866/cpm/brg-frequency "
+ printf("ft_blob_update): cannot set /soc/cpm/brg-frequency "
"property err:%s\n", fdt_strerror(ret));
}
else {
/* memory node is required in dts */
- printf("ft_blob_update(): cannot find /localbus node "
+ printf("ft_blob_update(): cannot find /soc/cpm node "
"err:%s\n", fdt_strerror(nodeoffset));
}
/* MAC Adresse */
- nodeoffset = fdt_path_offset (blob, "/soc866/cpm/ethernet");
+ nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet");
if (nodeoffset >= 0) {
ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr,
sizeof(uchar) * 6);
if (ret < 0)
- printf("ft_blob_update): cannot set /soc866/cpm/scc/mac-address "
+ printf("ft_blob_update): cannot set /soc/cpm/scc/mac-address "
"property err:%s\n", fdt_strerror(ret));
}
else {
/* memory node is required in dts */
- printf("ft_blob_update(): cannot find /localbus node "
+ printf("ft_blob_update(): cannot find /soc/cpm/ethernet node "
"err:%s\n", fdt_strerror(nodeoffset));
}
}
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
-#include <spd.h>
-
-extern long int spd_sdram (void);
+#include <spd_sdram.h>
long int fixed_sdram (void);
long int initdram (int board_type)
{
long dram_size = 0;
- extern long spd_sdram (void);
+
#if !defined(CONFIG_RAM_AS_FLASH)
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
sys_info_t sysinfo;
int i;
uchar *boottype;
uchar *bootletter;
- uchar *fmt;
+ char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";
imx_gpio_mode(PD14_PF_FLM_VSYNC);
imx_gpio_mode(PD13_PF_LP_HSYNC);
imx_gpio_mode(PD6_PF_LSCLK);
- imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_GPIO);
+ imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_DR);
imx_gpio_mode(PD11_PF_CONTRAST);
imx_gpio_mode(PD10_PF_SPL_SPR);
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
-#include <spd.h>
+#include <spd_sdram.h>
#if defined(CONFIG_DDR_ECC)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
-extern long int spd_sdram(void);
-
void local_bus_init(void);
void sdram_init(void);
long int fixed_sdram(void);
initdram(int board_type)
{
long dram_size = 0;
- extern long spd_sdram (void);
puts("Initializing\n");
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
-#include <spd.h>
+#include <spd_sdram.h>
#include <miiphy.h>
#if defined(CONFIG_DDR_ECC)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
-extern long int spd_sdram(void);
-
void local_bus_init(void);
long int fixed_sdram(void);
initdram(int board_type)
{
long dram_size = 0;
- extern long spd_sdram (void);
+
puts("Initializing\n");
#include <mpc83xx.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
-#include <spd.h>
-#include <miiphy.h>
-#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
-#endif
+#include <miiphy.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
-#include <spd.h>
+#include <spd_sdram.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
-extern long int spd_sdram(void);
-
void local_bus_init(void);
void sdram_init(void);
long int fixed_sdram (void);
{
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+ volatile u_char *rev= (void *)CFG_BD_REV;
printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
- (volatile)(*(u_char *)CFG_BD_REV) >> 4);
+ (*rev) >> 4);
/*
* Initialize local bus.
ft_pci_setup(void *blob, bd_t *bd)
{
int node, tmp[2];
- const char *path;
node = fdt_path_offset(blob, "/aliases");
tmp[0] = 0;
if (node >= 0) {
#ifdef CONFIG_PCI1
+ const char *path;
path = fdt_getprop(blob, node, "pci0", NULL);
if (path) {
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
}
#endif
#ifdef CONFIG_PCIE1
+ const char *path;
path = fdt_getprop(blob, node, "pci1", NULL);
if (path) {
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
*/
-extern long int spd_sdram (void);
-
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
-#include <spd.h>
+#include <spd_sdram.h>
#include <miiphy.h>
long int fixed_sdram (void);
long int initdram (int board_type)
{
long dram_size = 0;
- extern long spd_sdram (void);
+
#if 0
#if !defined(CONFIG_RAM_AS_FLASH)
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/immap_fsl_pci.h>
-#include <spd.h>
+#include <spd_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>
extern void ddr_enable_ecc (unsigned int dram_size);
#endif
-#if defined(CONFIG_SPD_EEPROM)
-#include "spd_sdram.h"
-#endif
-
void sdram_init (void);
long int fixed_sdram (void);
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint devdisr = gur->devdisr;
- uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
+ uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
+ >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
#ifdef CONFIG_PCI1
{
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
#ifdef DEBUG
- uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
+ uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
+ >> MPC8641_PORBMSR_HA_SHIFT;
uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
#endif
if ((io_sel == 2 || io_sel == 3 || io_sel == 5
#if ( SCB9328_FLASH_BUS_WIDTH == 1 )
# define FLASH_BUS vu_char
+# define FLASH_BUS_RET u_char
# if ( SCB9328_FLASH_INTERLEAVE == 1 )
# define FLASH_CMD( x ) x
# else
#elif ( SCB9328_FLASH_BUS_WIDTH == 2 )
# define FLASH_BUS vu_short
+# define FLASH_BUS_RET u_short
# if ( SCB9328_FLASH_INTERLEAVE == 1 )
# define FLASH_CMD( x ) x
# elif ( SCB9328_FLASH_INTERLEAVE == 2 )
#elif ( SCB9328_FLASH_BUS_WIDTH == 4 )
# define FLASH_BUS vu_long
+# define FLASH_BUS_RET u_long
# if ( SCB9328_FLASH_INTERLEAVE == 1 )
# define FLASH_CMD( x ) x
# elif ( SCB9328_FLASH_INTERLEAVE == 2 )
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
-static FLASH_BUS flash_status_reg (void)
+static FLASH_BUS_RET flash_status_reg (void)
{
FLASH_BUS *addr = (FLASH_BUS *) 0;
/*----------------*/
/* Message */
-typedef struct can_msg {
+struct can_msg {
uchar ctrl_0;
uchar ctrl_1;
uchar arbit_0;
uchar arbit_3;
uchar config;
uchar data[8];
-} can_msg_t;
+} __attribute__ ((packed));
+
+typedef struct can_msg can_msg_t;
/* CAN Register */
typedef struct can_reg {
ushort gbl_mask_std;
uint gbl_mask_extd;
uint msg15_mask;
- can_msg_t msg1 __attribute__ ((packed));
+ can_msg_t msg1;
uchar clkout;
- can_msg_t msg2 __attribute__ ((packed));
+ can_msg_t msg2;
uchar bus_config;
- can_msg_t msg3 __attribute__ ((packed));
+ can_msg_t msg3;
uchar bit_timing_0;
- can_msg_t msg4 __attribute__ ((packed));
+ can_msg_t msg4;
uchar bit_timing_1;
- can_msg_t msg5 __attribute__ ((packed));
+ can_msg_t msg5;
uchar interrupt;
- can_msg_t msg6 __attribute__ ((packed));
+ can_msg_t msg6;
uchar resv1;
- can_msg_t msg7 __attribute__ ((packed));
+ can_msg_t msg7;
uchar resv2;
- can_msg_t msg8 __attribute__ ((packed));
+ can_msg_t msg8;
uchar resv3;
- can_msg_t msg9 __attribute__ ((packed));
+ can_msg_t msg9;
uchar p1conf;
- can_msg_t msg10 __attribute__ ((packed));
+ can_msg_t msg10;
uchar p2conf;
- can_msg_t msg11 __attribute__ ((packed));
+ can_msg_t msg11;
uchar p1in;
- can_msg_t msg12 __attribute__ ((packed));
+ can_msg_t msg12;
uchar p2in;
- can_msg_t msg13 __attribute__ ((packed));
+ can_msg_t msg13;
uchar p1out;
- can_msg_t msg14 __attribute__ ((packed));
+ can_msg_t msg14;
uchar p2out;
- can_msg_t msg15 __attribute__ ((packed));
+ can_msg_t msg15;
uchar ser_res_addr;
uchar resv_cs[0x8000-0x100]; /* 0x8000 is the min size for CS */
} can_reg_t;
*/
-extern long int spd_sdram (void);
-
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <asm/io.h>
-#include <spd.h>
+#include <spd_sdram.h>
#include <miiphy.h>
long int fixed_sdram (void);
initdram (int board_type)
{
long dram_size = 0;
- extern long spd_sdram (void);
#if defined(CONFIG_DDR_DLL)
{
*/
-extern long int spd_sdram (void);
-
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <asm/io.h>
-#include <spd.h>
+#include <spd_sdram.h>
#include <miiphy.h>
long int fixed_sdram (void);
initdram (int board_type)
{
long dram_size = 0;
- extern long spd_sdram (void);
#if defined(CONFIG_DDR_DLL)
{
#include "mt48lc16m16a2-75.h"
#endif
+#ifdef CONFIG_OF_LIBFDT
+#include <fdt_support.h>
+#endif /* CONFIG_OF_LIBFDT */
+
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_PS2MULT
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
/* find RAM size using SDRAM CS1 only */
- sdram_start(0);
- test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
- sdram_start(1);
- test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+ if (!dramsize)
+ sdram_start(0);
+ test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+ if (!dramsize) {
+ sdram_start(1);
+ test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+ }
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+ fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
#include <mpc83xx.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
-#include <spd.h>
#include <miiphy.h>
#include <asm-ppc/mmu.h>
#include <pci.h>
/* External definitions */
ulong flash_get_size (ulong base, int banknum);
extern flash_info_t flash_info[];
-extern long spd_sdram (void);
/* Local functions */
static int detect_num_flash_banks(void);
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/mmu.h>
-#include <spd.h>
struct sdram_conf_s {
unsigned long size;
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
-#include <spd.h>
#include <flash.h>
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[]; /* FLASH chips info */
void local_bus_init (void);
-long int fixed_sdram (void);
ulong flash_get_size (ulong base, int banknum);
#ifdef CONFIG_PS2MULT
#define PPC405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */
#define PPC405GP_GPIO0_IR 0xef60071cL /* GPIO Input */
-/* AMCC 405GP DCRs */
-#define CPC0_CR0 0xb1 /* Chip control register 0 */
-
/* LMG FPGA <=> CPU GPIO signals */
#define LMG_XCV_INIT 0x10000000L
#define LMG_XCV_PROG 0x04000000L
/* check if we are copying to Flash */
if ( (addr2info(dest) != NULL)
#ifdef CONFIG_HAS_DATAFLASH
- && (!addr_dataflash(addr))
+ && (!addr_dataflash(dest))
#endif
) {
int rc;
static int initialized = 0;
static int kgdb_active = 0, first_entry = 1;
static struct pt_regs entry_regs;
-static u_int error_jmp_buf[BUFMAX/2];
+static long error_jmp_buf[BUFMAX/2];
static int longjmp_on_fault = 0;
#ifdef KGDB_DEBUG
static int kdebug = 1;
/* probably should check which exception occured as well */
if (longjmp_on_fault) {
longjmp_on_fault = 0;
- kgdb_longjmp((long*)error_jmp_buf, KGDBERR_MEMFAULT);
+ kgdb_longjmp(error_jmp_buf, KGDBERR_MEMFAULT);
panic("kgdb longjump failed!\n");
}
printf("kgdb: handle_exception; trap [0x%x]\n", kgdb_trap(regs));
- if (kgdb_setjmp((long*)error_jmp_buf) != 0)
+ if (kgdb_setjmp(error_jmp_buf) != 0)
panic("kgdb: error or fault in entry init!\n");
kgdb_enter(regs, &kd);
printf("kgdb: remcomInBuffer: %s\n", remcomInBuffer);
#endif
- errnum = kgdb_setjmp((long*)error_jmp_buf);
+ errnum = kgdb_setjmp(error_jmp_buf);
if (errnum == 0) switch (remcomInBuffer[0]) {
kgdb_error(int errnum)
{
longjmp_on_fault = 0;
- kgdb_longjmp((long*)error_jmp_buf, errnum);
+ kgdb_longjmp(error_jmp_buf, errnum);
panic("kgdb_error: longjmp failed!\n");
}
u8 cpmf;
u8 sys_div;
u8 ips_div;
+ u8 pci_div;
u32 ref_clk = CFG_MPC512X_CLKIN;
u32 spll;
u32 sys_clk;
u32 core_clk;
u32 csb_clk;
u32 ips_clk;
+ u32 pci_clk;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
/* in case we cannot get a sane IPS divisor, fail gracefully */
ips_clk = 0;
}
+ pci_div = (im->clk.scfr[0] & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
+ if (pci_div != 0) {
+ pci_clk = csb_clk / pci_div;
+ } else {
+ /* in case we cannot get a sane IPS divisor, fail gracefully */
+ pci_clk = 333333;
+ }
gd->ips_clk = ips_clk;
+ gd->pci_clk = pci_clk;
gd->csb_clk = csb_clk;
gd->cpu_clk = core_clk;
gd->bus_clk = csb_clk;
int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
- printf ("Clock configuration:\n");
- printf (" CPU: %4d MHz\n", gd->cpu_clk / 1000000);
- printf (" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
- printf (" IPS Bus: %4d MHz\n", gd->ips_clk / 1000000);
- printf (" DDR: %4d MHz\n", 2 * gd->csb_clk / 1000000);
+ printf("Clock configuration:\n");
+ printf(" CPU: %4d MHz\n", gd->cpu_clk / 1000000);
+ printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
+ printf(" IPS Bus: %4d MHz\n", gd->ips_clk / 1000000);
+ printf(" PCI: %4d MHz\n", gd->pci_clk / 1000000);
+ printf(" DDR: %4d MHz\n", 2 * gd->csb_clk / 1000000);
return 0;
}
set_msr (get_msr () | MSR_EE);
#ifdef CONFIG_INTERRUPTS
- pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */
+ pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */
debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1);
pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
blr
-#ifdef CFG_INIT_RAM_LOCK
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
andi. r4,r4,0x1ff
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
-1: icbi r0,r3
- dcbi r0,r3
+1: dcbi r0,r3
addi r3,r3,CFG_CACHELINE_SIZE
bdnz 1b
- sync /* Wait for all icbi to complete on bus */
+ sync
+
+ /* Invalidate the TLB entries for the cache */
+ lis r3,CFG_INIT_RAM_ADDR@h
+ ori r3,r3,CFG_INIT_RAM_ADDR@l
+ tlbivax 0,r3
+ addi r3,r3,0x1000
+ tlbivax 0,r3
+ addi r3,r3,0x1000
+ tlbivax 0,r3
+ addi r3,r3,0x1000
+ tlbivax 0,r3
isync
blr
-#endif
#endif
u32 bd_cached;
u32 bd_uncached = 0;
+#ifdef CONFIG_4xx_DCACHE
+ static u32 last_used_ea = 0;
+#endif
EMAC_4XX_HW_PST hw_p = dev->priv;
#ifdef CONFIG_4xx_DCACHE
flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
- bd_uncached = bis->bi_memsize;
+ if (!last_used_ea)
+ bd_uncached = bis->bi_memsize;
+ else
+ bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
+
+ last_used_ea = bd_uncached;
program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
TLB_WORD2_I_ENABLE);
#else
/* set transmit enable & receive enable */
out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
- /* set receive fifo to 4k and tx fifo to 2k */
mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
- mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
+
+ /* set rx-/tx-fifo size */
+ mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
/* set speed */
if (speed == _1000BASET) {
u16 adv;
miiphy_read (devname, addr, PHY_ANAR, &adv);
- adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
- PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
- PHY_ANLPAR_10);
+ adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_TXFD | PHY_ANLPAR_TX |
+ PHY_ANLPAR_10FD | PHY_ANLPAR_10);
miiphy_write (devname, addr, PHY_ANAR, adv);
miiphy_read (devname, addr, PHY_1000BTCR, &adv);
} rtl_chip_info[] = {
{"RTL-8169", 0x00, 0xff7e1880,},
{"RTL-8169", 0x04, 0xff7e1880,},
+ {"RTL-8169", 0x00, 0xff7e1880,},
+ {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
+ {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
+ {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
+ {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
+ {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
+ {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
+ {"RTL-8101e", 0x34, 0xff7e1880,},
+ {"RTL-8100e", 0x32, 0xff7e1880,},
};
enum _DescStatusBit {
(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
static struct pci_device_id supported[] = {
+ {PCI_VENDOR_ID_REALTEK, 0x8167},
{PCI_VENDOR_ID_REALTEK, 0x8169},
{}
};
tpc->cur_rx = cur_rx;
return 1;
+ } else {
+ ushort sts = RTL_R8(IntrStatus);
+ RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
+ udelay(100); /* wait */
}
tpc->cur_rx = cur_rx;
return (0); /* initially as this is called to flush the input */
}
/* Validate some of the fields */
- if ((firmware->count < 1) || (firmware->count >= MAX_QE_RISC)) {
+ if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
printf("Invalid data\n");
return -EINVAL;
}
return 0;
}
+ i++;
udelay(1000); /* 1 ms */
status = phy_read(mii_info, PHY_BMSR);
}
{
uec_private_t *uec = (uec_private_t *) dev->priv;
struct uec_mii_info *mii_info;
+ u16 status;
if (!uec->mii_info) {
- printf ("%s: the PHY not intialized\n", __FUNCTION__);
+ printf ("%s: the PHY not initialized\n", __FUNCTION__);
return;
}
mii_info = uec->mii_info;
phy_write (mii_info, 0x00, 0x8100);
udelay (1000000);
}
+
+ /* handle 88e1111 rev.B2 erratum 5.6 */
+ if (mii_info->autoneg) {
+ status = phy_read (mii_info, PHY_BMCR);
+ phy_write (mii_info, PHY_BMCR, status | PHY_BMCR_AUTON);
+ }
+ /* now the B2 will correctly report autoneg completion status */
}
void change_phy_interface_mode (struct eth_device *dev, enet_interface_e mode)
endif
ifeq ($(ARCH),arm)
+ifeq ($(BOARD),omap2420h4)
+LOAD_ADDR = 0x80300000
+else
LOAD_ADDR = 0xc100000
endif
+endif
ifeq ($(ARCH),mips)
LOAD_ADDR = 0x80200000 -T mips.lds
BIN = hello_world.bin
ifeq ($(CPU),mpc8xx)
-ELF = test_burst
-SREC = test_burst.srec
-BIN = test_burst.bin
+ELF += test_burst
+SREC += test_burst.srec
+BIN += test_burst.bin
endif
ifeq ($(ARCH),i386)
void app_startup(char **argv)
{
- unsigned long * cp = &__bss_start;
+ unsigned char * cp = (unsigned char *) &__bss_start;
/* Zero out BSS */
- while (cp < &_end) {
+ while (cp < (unsigned char *)&_end) {
*cp++ = 0;
}
sector++;
}
+ if (byte_len == 0)
+ return 1;
+
/* read sector aligned part */
block_len = byte_len & ~(SECTOR_SIZE - 1);
+
+ if (block_len == 0) {
+ u8 p[SECTOR_SIZE];
+
+ block_len = SECTOR_SIZE;
+ ext2fs_block_dev_desc->block_read(ext2fs_block_dev_desc->dev,
+ part_info.start + sector,
+ 1, (unsigned long *)p);
+ memcpy(buf, p, byte_len);
+ return 1;
+ }
+
if (ext2fs_block_dev_desc->block_read (ext2fs_block_dev_desc->dev,
part_info.start + sector,
block_len / SECTOR_SIZE,
printf (" ** ext2fs_devread() read error - block\n");
return (0);
}
+ block_len = byte_len & ~(SECTOR_SIZE - 1);
buf += block_len;
byte_len -= block_len;
sector += block_len / SECTOR_SIZE;
newclust = get_fatent(mydata, endclust);
if((newclust -1)!=endclust)
goto getit;
- if (newclust <= 0x0001 || newclust >= 0xfff0) {
+ if (CHECK_CLUST(newclust, mydata->fatsize)) {
FAT_DPRINT("curclust: 0x%x\n", newclust);
FAT_DPRINT("Invalid FAT entry\n");
return gotsize;
filesize -= actsize;
buffer += actsize;
curclust = get_fatent(mydata, endclust);
- if (curclust <= 0x0001 || curclust >= 0xfff0) {
+ if (CHECK_CLUST(curclust, mydata->fatsize)) {
FAT_DPRINT("curclust: 0x%x\n", curclust);
FAT_ERROR("Invalid FAT entry\n");
return gotsize;
slotptr--;
curclust = get_fatent(mydata, curclust);
- if (curclust <= 0x0001 || curclust >= 0xfff0) {
+ if (CHECK_CLUST(curclust, mydata->fatsize)) {
FAT_DPRINT("curclust: 0x%x\n", curclust);
FAT_ERROR("Invalid FAT entry\n");
return -1;
return retdent;
}
curclust = get_fatent (mydata, curclust);
- if (curclust <= 0x0001 || curclust >= 0xfff0) {
+ if (CHECK_CLUST(curclust, mydata->fatsize)) {
FAT_DPRINT ("curclust: 0x%x\n", curclust);
FAT_ERROR ("Invalid FAT entry\n");
return NULL;
*
*/
+#define IO_ADDRESS(x) ((x) | IMX_IO_BASE)
+
# ifndef __ASSEMBLY__
-# define __REG(x) (*((volatile u32 *)(x)))
-# define __REG2(x,y) \
- ( __builtin_constant_p(y) ? (__REG((x) + (y))) \
- : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
+# define __REG(x) (*((volatile u32 *)IO_ADDRESS(x)))
+# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
# else
# define __REG(x) (x)
# define __REG2(x,y) ((x)+(y))
/* PLL registers */
#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
+#define CSCR_SPLL_RESTART (1<<22)
+#define CSCR_MPLL_RESTART (1<<21)
+#define CSCR_SYSTEM_SEL (1<<16)
+#define CSCR_BCLK_DIV (0xf<<10)
+#define CSCR_MPU_PRESC (1<<15)
+#define CSCR_SPEN (1<<1)
+#define CSCR_MPEN (1<<0)
+
#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
-#define CSCR_MPLL_RESTART (1<<21)
-
/*
* GPIO Module and I/O Multiplexer
* x = 0..3 for reg_A, reg_B, reg_C, reg_D
#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
+#define GPIO_PORT_MAX 3
+
#define GPIO_PIN_MASK 0x1f
#define GPIO_PORT_MASK (0x3 << 5)
+#define GPIO_PORT_SHIFT 5
#define GPIO_PORTA (0<<5)
#define GPIO_PORTB (1<<5)
#define GPIO_PORTC (2<<5)
#define GPIO_PF (0<<9)
#define GPIO_AF (1<<9)
+#define GPIO_OCR_SHIFT 10
#define GPIO_OCR_MASK (3<<10)
#define GPIO_AIN (0<<10)
#define GPIO_BIN (1<<10)
#define GPIO_CIN (2<<10)
-#define GPIO_GPIO (3<<10)
+#define GPIO_DR (3<<10)
+
+#define GPIO_AOUT_SHIFT 12
+#define GPIO_AOUT_MASK (3<<12)
+#define GPIO_AOUT (0<<12)
+#define GPIO_AOUT_ISR (1<<12)
+#define GPIO_AOUT_0 (2<<12)
+#define GPIO_AOUT_1 (3<<12)
-#define GPIO_AOUT (1<<12)
-#define GPIO_BOUT (1<<13)
+#define GPIO_BOUT_SHIFT 14
+#define GPIO_BOUT_MASK (3<<14)
+#define GPIO_BOUT (0<<14)
+#define GPIO_BOUT_ISR (1<<14)
+#define GPIO_BOUT_0 (2<<14)
+#define GPIO_BOUT_1 (3<<14)
+
+#define GPIO_GIUS (1<<16)
/* assignements for GPIO alternate/primary functions */
/* FIXME: This list is not completed. The correct directions are
* missing on some (many) pins
*/
-#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 )
-#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
+#define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 )
#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )
-#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
+#define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 )
#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )
#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )
#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
-#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 )
+#define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 )
#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 )
#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 )
#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 )
-#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 )
+#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 )
#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 )
-#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 )
+#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 )
#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 )
-#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 )
+#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 )
#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 )
#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 )
#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 )
#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 )
#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 )
#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 )
+#define PC24_BIN_UART3_RI ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 )
+#define PC25_BIN_UART3_DSR ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 )
+#define PC26_AOUT_UART3_DTR ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 )
+#define PC27_BIN_UART3_DCD ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 )
+#define PC28_BIN_UART3_CTS ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 )
+#define PC29_AOUT_UART3_RTS ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 )
+#define PC30_BIN_UART3_TX ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 )
+#define PC31_AOUT_UART3_RX ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 )
-#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
-#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 )
+#define PD7_AF_UART2_DTR ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
+#define PD7_AIN_SPI2_SCLK ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 )
#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 )
#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
-#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 )
+#define PD8_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 )
#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 )
#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
-#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
+#define PD9_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 )
#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
-#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
+#define PD10_AIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 )
#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
-#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 )
+#define PD31_BIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 )
+
+/*
+ * PWM controller
+ */
+#define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */
+#define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */
+#define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */
+#define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */
+
+#define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */
+#define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */
+#define PWMC_SWR (0x01<<16) /* Software Reset */
+#define PWMC_CLKSRC (0x01<<15) /* Clock Source */
+#define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */
+#define PWMC_IRQ (0x01<< 7) /* Interrupt Request */
+#define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */
+#define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */
+#define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */
+#define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */
+#define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */
+
+#define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */
+#define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */
+#define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */
/*
* DMA Controller
#define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */
#define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */
#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */
-#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /*Â Control Registers */
+#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */
#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */
#define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */
#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */
#define POS_POS(x) ((x) & 1f)
#define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28)
-#define LSCR1_GRAY1(x) (((x) & 0xf) << 4)
-#define LSCR1_GRAY2(x) ((x) & 0xf)
+#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26)
+#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16)
+#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8)
+#define LSCR1_GRAY2(x) (((x) & 0xf) << 4)
+#define LSCR1_GRAY1(x) (((x) & 0xf))
#define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C)
#define PWMR_CLS(x) (((x) & 0x1ff) << 16)
#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
#define UCR1_DOZE (1<<1) /* Doze */
#define UCR1_UARTEN (1<<0) /* UART enabled */
-#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
-#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
-#define UCR2_CTSC (1<<13) /* CTS pin control */
+#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
+#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
+#define UCR2_CTSC (1<<13) /* CTS pin control */
#define UCR2_CTS (1<<12) /* Clear to send */
#define UCR2_ESCEN (1<<11) /* Escape enable */
#define UCR2_PREN (1<<8) /* Parity enable */
#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
#define UCR2_TXEN (1<<2) /* Transmitter enabled */
#define UCR2_RXEN (1<<1) /* Receiver enabled */
-#define UCR2_SRST (1<<0) /* SW reset */
-#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
+#define UCR2_SRST (1<<0) /* SW reset */
+#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
#define UCR3_PARERREN (1<<12) /* Parity enable */
#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
#define UCR3_DSR (1<<10) /* Data set ready */
#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
-#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
-#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
-#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
-#define UCR3_BPEN (1<<0) /* Preset registers enable */
+#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
+#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
+#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
+#define UCR3_BPEN (1<<0) /* Preset registers enable */
#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
-#define UCR4_INVR (1<<9) /* Inverted infrared reception */
-#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
-#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
-#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
-#define UCR4_IRSC (1<<5) /* IR special case */
-#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
-#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
-#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
-#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
+#define UCR4_INVR (1<<9) /* Inverted infrared reception */
+#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
+#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
+#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
+#define UCR4_IRSC (1<<5) /* IR special case */
+#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
+#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
+#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
+#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
-#define USR1_RTSS (1<<14) /* RTS pin status */
-#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
-#define USR1_RTSD (1<<12) /* RTS delta */
-#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
+#define USR1_RTSS (1<<14) /* RTS pin status */
+#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
+#define USR1_RTSD (1<<12) /* RTS delta */
+#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
-#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
+#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
-#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
-#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
-#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
-#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
-#define USR2_IDLE (1<<12) /* Idle condition */
-#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
-#define USR2_WAKE (1<<7) /* Wake */
-#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
-#define USR2_TXDC (1<<3) /* Transmitter complete */
-#define USR2_BRCD (1<<2) /* Break condition */
+#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
+#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
+#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
+#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
+#define USR2_IDLE (1<<12) /* Idle condition */
+#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
+#define USR2_WAKE (1<<7) /* Wake */
+#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
+#define USR2_TXDC (1<<3) /* Transmitter complete */
+#define USR2_BRCD (1<<2) /* Break condition */
#define USR2_ORE (1<<1) /* Overrun error */
#define USR2_RDR (1<<0) /* Recv data ready */
#define UTS_FRCPERR (1<<13) /* Force parity error */
#define UTS_LOOP (1<<12) /* Loop tx and rx */
#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
-#define UTS_TXFULL (1<<4) /* TxFIFO full */
-#define UTS_RXFULL (1<<3) /* RxFIFO full */
+#define UTS_TXFULL (1<<4) /* TxFIFO full */
+#define UTS_RXFULL (1<<3) /* RxFIFO full */
#define UTS_SOFTRST (1<<0) /* Software reset */
/* General purpose timers registers */
typedef __signed__ int __s32;
typedef unsigned int __u32;
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-typedef __signed__ long long __s64;
-typedef unsigned long long __u64;
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
#endif
/*
typedef __signed__ int __s32;
typedef unsigned int __u32;
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-typedef __signed__ long long __s64;
-typedef unsigned long long __u64;
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
#endif
/*
typedef __signed__ int __s32;
typedef unsigned int __u32;
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-typedef __signed__ long long __s64;
-typedef unsigned long long __u64;
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
#endif
/*
typedef __signed__ int __s32;
typedef unsigned int __u32;
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-typedef __signed__ long long __s64;
-typedef unsigned long long __u64;
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
#endif
/*
#if defined(CONFIG_MPC512X)
u32 ips_clk;
u32 csb_clk;
+ u32 pci_clk;
#endif /* CONFIG_MPC512X */
#if defined(CONFIG_MPC8220)
unsigned long bExtUart;
typedef struct law512x {
u32 bar; /* Base Addr Register */
u32 ar; /* Attributes Register */
-} law521x_t;
+} law512x_t;
/*
* System configuration registers
u32 lpcs6aw; /* LP CS6 Access Window */
u32 lpcs7aw; /* LP CS7 Access Window */
u8 res1[0x1c];
- law521x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */
+ law512x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */
u8 res2[0x28];
- law521x_t ddrlaw; /* DDR Local Access Window */
+ law512x_t ddrlaw; /* DDR Local Access Window */
u8 res3[0x18];
u32 mbxbar; /* MBX Base Address */
u32 srambar; /* SRAM Base Address */
* PCI Software Configuration Registers
*/
typedef struct pciconf512x {
- u8 fixme[0x80];
+ u32 config_address;
+ u32 config_data;
+ u32 int_ack;
+ u8 res[116];
} pciconf512x_t;
+/*
+ * PCI Outbound Translation Register
+ */
+typedef struct pci_outbound_window {
+ u32 potar;
+ u8 res0[4];
+ u32 pobar;
+ u8 res1[4];
+ u32 pocmr;
+ u8 res2[4];
+} pot512x_t;
+
/*
* Sequencer
*/
typedef struct ios512x {
- u8 fixme[0x100];
+ pot512x_t pot[6];
+ u8 res0[0x60];
+ u32 pmcr;
+ u8 res1[4];
+ u32 dtcr;
+ u8 res2[4];
} ios512x_t;
/*
* PCI Controller
*/
typedef struct pcictrl512x {
- u8 fixme[0x100];
+ u32 esr;
+ u32 ecdr;
+ u32 eer;
+ u32 eatcr;
+ u32 eacr;
+ u32 eeacr;
+ u32 edlcr;
+ u32 edhcr;
+ u32 gcr;
+ u32 ecr;
+ u32 gsr;
+ u8 res0[12];
+ u32 pitar2;
+ u8 res1[4];
+ u32 pibar2;
+ u32 piebar2;
+ u32 piwar2;
+ u8 res2[4];
+ u32 pitar1;
+ u8 res3[4];
+ u32 pibar1;
+ u32 piebar1;
+ u32 piwar1;
+ u8 res4[4];
+ u32 pitar0;
+ u8 res5[4];
+ u32 pibar0;
+ u8 res6[4];
+ u32 piwar0;
+ u8 res7[132];
} pcictrl512x_t;
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo;"
#undef CONFIG_BOOTARGS
#define CONFIG_BAUDRATE 9600
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#define CONFIG_BOOTDELAY 5
#define CONFIG_PREBOOT \
"echo; " \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; " \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_PREBOOT \
"echo; " \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; " \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BAUDRATE 9600
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */
#define CONFIG_BOOTDELAY 5
#undef CONFIG_BOOTARGS
-/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */
+/*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
/* ronen - autoboot using tftp */
#if (CONFIG_BOOTDELAY >= 0)
#undef CONFIG_BOOTARGS
-/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */
+/*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
/* ronen - autoboot using tftp */
#if (CONFIG_BOOTDELAY >= 0)
#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
# define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
/* using this define saves us updating another source file */
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
#define CONFIG_BOOTCOUNT_LIMIT
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BAUDRATE 9600
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" \
"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"ramdiskaddr=1000000\0" \
"ramdiskfile=ramfs.83xx\0" \
"fdtaddr=400000\0" \
- "fdtfile=mpc832xemds.dtb\0" \
+ "fdtfile=mpc832x_mds.dtb\0" \
""
#define CONFIG_NFSBOOTCOMMAND \
#define CONFIG_BAUDRATE 115200
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#define CONFIG_EXTRA_ENV_SETTINGS \
"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
"update=protect off fe000000 fe03ffff; " \
"era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
"fdtaddr=400000\0" \
"fdtfile=mpc8349emds.dtb\0" \
""
"ramdiskaddr=1000000\0" \
"ramdiskfile=ramfs.83xx\0" \
"fdtaddr=400000\0" \
- "fdtfile=mpc8360emds.dtb\0" \
+ "fdtfile=mpc836x_mds.dtb\0" \
""
#define CONFIG_NFSBOOTCOMMAND \
HRCWH_LDP_CLEAR)
#endif
+/* Arbiter Configuration Register */
+#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
+#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
+
+/* System Priority Control Register */
+#define CFG_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
+
/*
- * eTSEC Clock Config
+ * IP blocks clock configuration
*/
#define CFG_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
#define CFG_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
+#define CFG_SCCR_SATACM SCCR_SATACM_1 /* CSB:SATA[0:3] = 1:1 */
/*
* System IO Config
"ramdiskaddr=1000000\0" \
"ramdiskfile=ramfs.83xx\0" \
"fdtaddr=400000\0" \
- "fdtfile=mpc837xemds.dtb\0" \
+ "fdtfile=mpc8379_mds.dtb\0" \
""
#define CONFIG_NFSBOOTCOMMAND \
#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
#define CONFIG_BOOTFILE uImage
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-#define CONFIG_FDTFILE mpc837x_rdb.dtb
+#define CONFIG_FDTFILE mpc8379_rdb.dtb
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
#define CONFIG_BOOT_RETRY_TIME 900
#define CONFIG_BOOT_RETRY_MIN 30
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
"cp.b 100000 fff00000 ${filesize};" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
#define CONFIG_PREBOOT "echo;" \
- "echo 'Type \"run flash_nfs\" to mount root filesystem over NFS';" \
+ "echo 'Type \\\"run flash_nfs\\\" to mount root filesystem over NFS';" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#define CONFIG_8xx_GCLK_FREQ 48000000L
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BAUDRATE 9600
#endif
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BAUDRATE 115200
#endif
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
"cp.b 300000 40000000 40000;" \
"setenv filesize;saveenv\0" \
"cphwib=cp.b 4003fc00 33fc00 400\0" \
- "upd=run load;run cphwib;run update\0" \
+ "upd=run load cphwib update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_BAUDRATE 115200
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"load=tftp 100000 /tftpboot/tqm834x/u-boot.bin\0" \
"update=protect off 80000000 8003ffff; " \
"era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_PREBOOT \
"setenv stdout serial;setenv stderr serial;" \
"echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
* 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
* 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
* 0x8200_0000 - 0x8200_001F CPLD (32 B)
+ * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB)
+ * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB)
+ * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
* 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
*/
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC512X 1 /* MPC512X family */
-#undef CONFIG_PCI
+/* CONFIG_PCI is defined at config time */
#define CFG_MPC512X_CLKIN 66000000 /* in Hz */
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
+/*
+ * PCI
+ */
+#ifdef CONFIG_PCI
+
+/*
+ * General PCI
+ */
+#define CFG_PCI_MEM_BASE 0xA0000000
+#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
+#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI_MMIO_BASE (CFG_PCI_MEM_BASE + CFG_PCI_MEM_SIZE)
+#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
+#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
+#define CFG_PCI_IO_BASE 0x00000000
+#define CFG_PCI_IO_PHYS 0x84000000
+#define CFG_PCI_IO_SIZE 0x01000000 /* 16M */
+
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#endif
+
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
#define CONFIG_HOSTNAME ads5121
#define CONFIG_BOOTFILE ads5121/uImage
+#define CONFIG_ROOTPATH /opt/eldk/pcc_6xx
#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
#define CONFIG_BAUDRATE 115200
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#define CONFIG_EXTRA_ENV_SETTINGS \
"u-boot_addr_r=200000\0" \
- "kernel_addr_r=200000\0" \
+ "kernel_addr_r=300000\0" \
"fdt_addr_r=400000\0" \
"ramdisk_addr_r=500000\0" \
"u-boot_addr=FFF00000\0" \
- "kernel_addr=FC000000\0" \
+ "kernel_addr=FC040000\0" \
"fdt_addr=FC2C0000\0" \
"ramdisk_addr=FC300000\0" \
"ramdiskfile=ads5121/uRamdisk\0" \
"addtty=setenv bootargs ${bootargs} " \
"console=${consdev},${baudrate}\0" \
"flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr_r} - ${fdt_addr}\0" \
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"net_self=tftp ${kernel_addr_r} ${bootfile};" \
"tftp ${ramdisk_addr_r} ${ramdiskfile};" \
- "tftp ${fdt_addr} ${fdtfile};" \
+ "tftp ${fdt_addr_r} ${fdtfile};" \
"run ramargs addip addtty;" \
- "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr}\0"\
- "load=tftp ${u-boot_addr} ${u-boot}\0" \
+ "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
+ "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
"update=protect off ${u-boot_addr} +${filesize};" \
"era ${u-boot_addr} +${filesize};" \
"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
"ethprime=ppc_4xx_eth3\0" \
"ethact=ppc_4xx_eth3\0" \
"autoload=no\0" \
#define CONFIG_PREBOOT \
"echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;"\
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\
"echo"
#undef CONFIG_BOOTARGS
#endif /* CFG_ENV_IS_IN_EEPROM */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
"cp.b 100000 fffa0000 60000;" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#endif
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"load=tftp 100000 hcu4/u-boot.bin\0" \
"update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \
"cp.b 100000 FFFB0000 50000\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
"vx_rom=hcu4/hcu4_vx_rom\0" \
"vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \
"vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \
"load=tftp 100000 hcu5/u-boot.bin\0" \
"update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \
"cp.b 100000 FFFB0000 50000\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
"vx_rom=hcu5/hcu5_vx_rom\0" \
"vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \
"vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_HOSTNAME idmr
#define CONFIG_BOOTFILE /tftpboot/idmr/uImage
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root " \
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root " \
"filesystem over NFS; echo"
#define CONFIG_MCFTMR
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
* Default configuration (environment varibles...)
*----------------------------------------------------------------------*/
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"update=protect off 50000000 5003ffff;era 50000000 5003ffff;" \
"cp.b 100000 50000000 40000;" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b ${fileaddr} fffc0000 ${filesize};" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
"kozio=bootm ffc60000\0" \
"pciconfighost=1\0" \
"pcie_mode=RP:RP:RP\0" \
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CFG_DTT_MIN_TEMP -30
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
"cp.b 200000 FFFA0000 60000\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
"update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
"cp.b 200000 FFF80000 80000\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
"lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
"autoscr 200000\0" \
""
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_CPM2 1 /* Has a CPM2 */
+/* Do boardspecific init */
+#define CONFIG_BOARD_EARLY_INIT_R 1
+
/*
* Select serial console configuration
*
#define CFG_FLASH_SIZE 32
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER
-#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
-#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
+#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
+#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
+
+#define CFG_FLASH_BASE_1 0x50000000
+#define CFG_FLASH_SIZE_1 64
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE_1 }
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
* ---- --- ------- ------ ------
* 0 60x GPCM 8 bit FLASH
* 1 60x SDRAM 32 bit SDRAM
+ * 3 60x GPCM 8 bit GPIO/PIGGY
+ * 5 60x GPCM 16 bit CFG-Flash
*
*/
/* Bank 0 - FLASH
PSDMR_WRC_1C |\
PSDMR_CL_2)
+/* GPIO/PIGGY on CS3 initialization values
+*/
+#define CFG_PIGGY_BASE 0x30000000
+#define CFG_PIGGY_SIZE 128
+
+#define CFG_BR3_PRELIM ((CFG_PIGGY_BASE & BRx_BA_MSK) |\
+ BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
+
+#define CFG_OR3_PRELIM (MEG_TO_AM(CFG_PIGGY_SIZE) |\
+ ORxG_CSNT | ORxG_ACS_DIV2 |\
+ ORxG_SCY_3_CLK | ORxG_TRLX )
+
+/* CFG-Flash on CS5 initialization values
+*/
+#define CFG_BR5_PRELIM ((CFG_FLASH_BASE_1 & BRx_BA_MSK) |\
+ BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
+
+#define CFG_OR5_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE_1) |\
+ ORxG_CSNT | ORxG_ACS_DIV2 |\
+ ORxG_SCY_5_CLK | ORxG_TRLX )
+
#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
/* pass open firmware flat tree */
#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
#define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */
+/* Do boardspecific init */
+#define CONFIG_BOARD_EARLY_INIT_R 1
+
#define CONFIG_8xx_GCLK_FREQ 66000000
#define CFG_SMC_UCODE_PATCH 1 /* Relocate SMC1 */
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
* 64 Refresh cycle in ms per number of rows
*/
#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
-/* HS HS noch zu setzen */
+
+/* GPIO/PIGGY on CS3 initialization values
+*/
+#define CFG_PIGGY_BASE (0x30000000)
+#define CFG_OR3_PRELIM (0xfe000d24)
+#define CFG_BR3_PRELIM (0x30000401)
/*
* Internal Definitions
#define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,866@0"
-#define OF_SOC "soc@f0000000"
+#define OF_SOC "soc@fff00000"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc/cpm/serial@a80"
#define CONFIG_ZERO_BOOTDELAY_CHECK
#undef CONFIG_BOOTARGS
-/* #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\"
- * to mount root filesystem over NFS;echo" */
+/* #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
#if (CONFIG_BOOTDELAY >= 0)
#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
"cp.b 100000 fff00000 40000;" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
"serverip=11.0.0.152\0"
#if defined (CONFIG_P3M750)
* Default configuration (environment varibles...)
*----------------------------------------------------------------------*/
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
"unlock=yes\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0" \
"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
"cp.b 100000 FFFA0000 60000\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
- "echo"
-
/* check U-Boot image with SHA1 sum */
#define CONFIG_SHA1_CHECK_UB_IMG 1
#define CONFIG_SHA1_START CFG_MONITOR_BASE
* Default configuration (environment varibles...)
*----------------------------------------------------------------------*/
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \
"cp.b 100000 50000000 ${filesize};" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
"ipaddr=10.0.0.233\0" \
"serverip=10.0.0.152\0" \
"netmask=255.255.0.0\0" \
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
"update=protect off fff00000 fff3ffff; " \
"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
"fdtaddr=400000\0" \
"fdtfile=sbc8349.dtb\0" \
""
#define CFG_OR0_PRELIM 0xff806e65
#define CFG_OR6_PRELIM 0xfc006e65
-#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
/*
- * (C) Copyright 2006-2007
+ * (C) Copyright 2006-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
#define CFG_DTT_HYSTERESIS 3
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
/* Setup some board specific values for the default environment variables */
#ifndef CONFIG_RAINIER
#define CONFIG_HOSTNAME sequoia
-#define CFG_BOOTFILE "bootfile=/tftpboot/sequoia/uImage\0"
+#define CFG_BOOTFILE "bootfile=sequoia/uImage\0"
+#define CFG_DTBFILE "fdt_file=sequoia/sequoia.dtb\0"
#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
#else
#define CONFIG_HOSTNAME rainier
-#define CFG_BOOTFILE "bootfile=/tftpboot/rainier/uImage\0"
+#define CFG_BOOTFILE "bootfile=rainier/uImage\0"
+#define CFG_DTBFILE "fdt_file=rainier/rainier.dtb\0"
#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
#endif
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
+ "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \
+ "flash_nfs=run nfsargs addip addtty addmisc;" \
"bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
+ "flash_self=run ramargs addip addtty addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
+ "net_nfs=tftp 200000 ${bootfile};" \
+ "run nfsargs addip addtty addmisc;" \
+ "bootm\0" \
+ "fdt_file=sequoia/sequoia.dtb\0" \
+ "fdt_addr=400000\0" \
+ "net_nfs_fdt=tftp 200000 ${bootfile};" \
+ "tftp ${fdt_addr} ${fdt_file};" \
+ "run nfsargs addip addtty addmisc;" \
+ "bootm 200000 - ${fdt_addr}\0" \
"kernel_addr=FC000000\0" \
"ramdisk_addr=FC180000\0" \
"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
"cp.b 200000 FFFA0000 60000\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_HOSTNAME sorcery
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"load=tftp 200000 /tftpboot/taihu/u-boot.bin\0" \
"update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \
"cp.b 200000 FFFC0000 40000\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
*----------------------------------------------------------------------*/
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
"fixedip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
"$(gatewayip):$(netmask):$(hostname):$(netdev):off panic=1\0" \
"dhcp=setenv bootargs $(bootargs) ip=dhcp\0" \
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"boot\" for the network boot using DHCP, TFTP and NFS;" \
- "echo Type \"run netboot_initrd\" for the network boot with initrd;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
- "echo Type \"run flash_local\" to mount local root filesystem;" \
+ "echo Type \\\"boot\\\" for the network boot using DHCP, TFTP and NFS;" \
+ "echo Type \\\"run netboot_initrd\\\" for the network boot with initrd;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_local\\\" to mount local root filesystem;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#endif
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
#define CFG_DTT_HYSTERESIS 3
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
"cp.b 200000 fff80000 80000;" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=yucca/uImage\0" \
"kernel_addr=E7F10000\0" \
"ramdisk_addr=E7F20000\0" \
"update=protect off 2:4-7;era 2:4-7;" \
"cp.b ${fileaddr} FFFB0000 ${filesize};" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
"pciconfighost=1\0" \
"pcie_mode=RP:EP:EP\0" \
""
| CRAMFS_FLAG_WRONG_SIGNATURE \
| CRAMFS_FLAG_SHIFTED_ROOT_OFFSET )
-#if __BYTE_ORDER == __LITTLE_ENDIAN
#define CRAMFS_16(x) (x)
#define CRAMFS_24(x) (x)
#define CRAMFS_32(x) (x)
#define CRAMFS_GET_OFFSET(x) ((x)->offset)
#define CRAMFS_SET_OFFSET(x,y) ((x)->offset = (y))
#define CRAMFS_SET_NAMELEN(x,y) ((x)->namelen = (y))
-#elif __BYTE_ORDER == __BIG_ENDIAN
-#ifdef __KERNEL__
-#define CRAMFS_16(x) swab16(x)
-#define CRAMFS_24(x) ((swab32(x)) >> 8)
-#define CRAMFS_32(x) swab32(x)
-#else /* not __KERNEL__ */
-#define CRAMFS_16(x) bswap_16(x)
-#define CRAMFS_24(x) ((bswap_32(x)) >> 8)
-#define CRAMFS_32(x) bswap_32(x)
-#endif /* not __KERNEL__ */
-#define CRAMFS_GET_NAMELEN(x) (((u8*)(x))[8] & 0x3f)
-#define CRAMFS_GET_OFFSET(x) ((CRAMFS_24(((u32*)(x))[2] & 0xffffff) << 2) |\
- ((((u32*)(x))[2] & 0xc0000000) >> 30))
-#define CRAMFS_SET_NAMELEN(x,y) (((u8*)(x))[8] = (((0x3f & (y))) | \
- (0xc0 & ((u8*)(x))[8])))
-#define CRAMFS_SET_OFFSET(x,y) (((u32*)(x))[2] = (((y) & 3) << 30) | \
- CRAMFS_24((((y) & 0x03ffffff) >> 2)) | \
- (((u32)(((u8*)(x))[8] & 0x3f)) << 24))
-#else
-#error "__BYTE_ORDER must be __LITTLE_ENDIAN or __BIG_ENDIAN"
-#endif
/* Uncompression interfaces to the underlying zlib */
int cramfs_uncompress_block(void *dst, void *src, int srclen);
#define START(dent) (FAT2CPU16((dent)->start) \
+ (mydata->fatsize != 32 ? 0 : \
(FAT2CPU16((dent)->starthi) << 16)))
-
+#define CHECK_CLUST(x, fatsize) ((x) <= 1 || \
+ (x) >= ((fatsize) != 32 ? 0xfff0 : 0xffffff0))
typedef struct boot_sector {
__u8 ignored[3]; /* Bootstrap code */
#define LPCS6AW 0x003C
#define LPCA7AW 0x0040
#define SRAMBAR 0x00C4
+#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */
#define LPC_OFFSET 0x10000
#define SCFR1_IPS_DIV_MASK 0x03800000
#define SCFR1_IPS_DIV_SHIFT 23
+#define SCFR1_PCI_DIV 0x6
+#define SCFR1_PCI_DIV_MASK 0x00700000
+#define SCFR1_PCI_DIV_SHIFT 20
+
/* SCFR2 System Clock Frequency Register 2
*/
#define SCFR2_SYS_DIV 0xFC000000
#define I2C_IF 0x02
#define I2C_RXAK 0x01
+/* POTAR - PCI Outbound Translation Address Register
+ */
+#define POTAR_TA_MASK 0x000fffff
+
+/* POBAR - PCI Outbound Base Address Register
+ */
+#define POBAR_BA_MASK 0x000fffff
+
+/* POCMR - PCI Outbound Comparision Mask Register
+ */
+#define POCMR_EN 0x80000000
+#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */
+#define POCMR_PRE 0x20000000 /* prefetch enable */
+#define POCMR_SBS 0x00100000 /* special byte swap enable */
+#define POCMR_CM_MASK 0x000fffff
+#define POCMR_CM_4G 0x00000000
+#define POCMR_CM_2G 0x00080000
+#define POCMR_CM_1G 0x000C0000
+#define POCMR_CM_512M 0x000E0000
+#define POCMR_CM_256M 0x000F0000
+#define POCMR_CM_128M 0x000F8000
+#define POCMR_CM_64M 0x000FC000
+#define POCMR_CM_32M 0x000FE000
+#define POCMR_CM_16M 0x000FF000
+#define POCMR_CM_8M 0x000FF800
+#define POCMR_CM_4M 0x000FFC00
+#define POCMR_CM_2M 0x000FFE00
+#define POCMR_CM_1M 0x000FFF00
+#define POCMR_CM_512K 0x000FFF80
+#define POCMR_CM_256K 0x000FFFC0
+#define POCMR_CM_128K 0x000FFFE0
+#define POCMR_CM_64K 0x000FFFF0
+#define POCMR_CM_32K 0x000FFFF8
+#define POCMR_CM_16K 0x000FFFFC
+#define POCMR_CM_8K 0x000FFFFE
+#define POCMR_CM_4K 0x000FFFFF
+
+/* PITAR - PCI Inbound Translation Address Register
+ */
+#define PITAR_TA_MASK 0x000fffff
+
+/* PIBAR - PCI Inbound Base/Extended Address Register
+ */
+#define PIBAR_MASK 0xffffffff
+#define PIEBAR_EBA_MASK 0x000fffff
+
+/* PIWAR - PCI Inbound Windows Attributes Register
+ */
+#define PIWAR_EN 0x80000000
+#define PIWAR_SBS 0x40000000
+#define PIWAR_PF 0x20000000
+#define PIWAR_RTT_MASK 0x000f0000
+#define PIWAR_RTT_NO_SNOOP 0x00040000
+#define PIWAR_RTT_SNOOP 0x00050000
+#define PIWAR_WTT_MASK 0x0000f000
+#define PIWAR_WTT_NO_SNOOP 0x00004000
+#define PIWAR_WTT_SNOOP 0x00005000
+#define PIWAR_IWS_MASK 0x0000003F
+#define PIWAR_IWS_4K 0x0000000B
+#define PIWAR_IWS_8K 0x0000000C
+#define PIWAR_IWS_16K 0x0000000D
+#define PIWAR_IWS_32K 0x0000000E
+#define PIWAR_IWS_64K 0x0000000F
+#define PIWAR_IWS_128K 0x00000010
+#define PIWAR_IWS_256K 0x00000011
+#define PIWAR_IWS_512K 0x00000012
+#define PIWAR_IWS_1M 0x00000013
+#define PIWAR_IWS_2M 0x00000014
+#define PIWAR_IWS_4M 0x00000015
+#define PIWAR_IWS_8M 0x00000016
+#define PIWAR_IWS_16M 0x00000017
+#define PIWAR_IWS_32M 0x00000018
+#define PIWAR_IWS_64M 0x00000019
+#define PIWAR_IWS_128M 0x0000001A
+#define PIWAR_IWS_256M 0x0000001B
+#define PIWAR_IWS_512M 0x0000001C
+#define PIWAR_IWS_1G 0x0000001D
+#define PIWAR_IWS_2G 0x0000001E
+
#endif /* __MPC512X_H__ */
#define EMAC_M1_IST (0x01000000)
#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
#define EMAC_M1_MF_100MBPS (0x00400000)
-#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */
-#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */
-#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */
+#define EMAC_M1_RFS_MASK (0x00380000)
+#define EMAC_M1_RFS_16K (0x00280000)
+#define EMAC_M1_RFS_8K (0x00200000)
+#define EMAC_M1_RFS_4K (0x00180000)
#define EMAC_M1_RFS_2K (0x00100000)
#define EMAC_M1_RFS_1K (0x00080000)
-#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */
+#define EMAC_M1_TX_FIFO_MASK (0x00070000)
+#define EMAC_M1_TX_FIFO_16K (0x00050000)
#define EMAC_M1_TX_FIFO_8K (0x00040000)
#define EMAC_M1_TX_FIFO_4K (0x00030000)
#define EMAC_M1_TX_FIFO_2K (0x00020000)
#define EMAC_M1_IST 0x01000000
#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
#define EMAC_M1_MF_100MBPS 0x00400000
-#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
+#define EMAC_M1_RFS_MASK 0x00300000
+#define EMAC_M1_RFS_4K 0x00300000
#define EMAC_M1_RFS_2K 0x00200000
#define EMAC_M1_RFS_1K 0x00100000
-#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
+#define EMAC_M1_RFS_512 0x00000000
+#define EMAC_M1_TX_FIFO_MASK 0x000c0000
+#define EMAC_M1_TX_FIFO_2K 0x00080000
#define EMAC_M1_TX_FIFO_1K 0x00040000
+#define EMAC_M1_TX_FIFO_512 0x00000000
#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
#define EMAC_M1_TR0_MULTI 0x00008000
#define EMAC_M1_TR1_DEPEND 0x00004000
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
#endif /* defined(CONFIG_440GX) */
+#define EMAC_MR1_FIFO_MASK (EMAC_M1_RFS_MASK | EMAC_M1_TX_FIFO_MASK)
+#if defined(CONFIG_405EZ)
+/* 405EZ only supports 512 bytes fifos */
+#define EMAC_MR1_FIFO_SIZE (EMAC_M1_RFS_512 | EMAC_M1_TX_FIFO_512)
+#else
+/* Set receive fifo to 4k and tx fifo to 2k */
+#define EMAC_MR1_FIFO_SIZE (EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K)
+#endif
+
/* Transmit Mode Register 0 */
#define EMAC_TXM0_GNP0 (0x80000000)
#define EMAC_TXM0_GNP1 (0x40000000)
{
struct eth_device* old_current;
- if (!eth_current)
+ if (!eth_current) {
+ puts ("No ethernet found.\n");
return -1;
+ }
old_current = eth_current;
do {
#include <asm/processor.h>
+#ifdef CONFIG_4xx_DCACHE
+#include <asm/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
static struct {
int number;
char * name;
};
unsigned long (*get_spr) (void) = (void *) code;
+#ifdef CONFIG_4xx_DCACHE
+ /* disable cache */
+ change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
+#endif
for (i = 0; i < spr_test_list_size; i++) {
int num = spr_test_list[i].number;
ret = -1;
}
}
+#ifdef CONFIG_4xx_DCACHE
+ /* enable cache */
+ change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
+#endif
return ret;
}
*
* For other processors, let the compiler generate the best code it can.
*/
-static void move64(unsigned long long *src, unsigned long long *dest)
+static void move64(const unsigned long long *src, unsigned long long *dest)
{
#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X)
asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
int ret = 0;
for ( i = 0; i < num_patterns; i++) {
- move64((unsigned long long *)&(pattern[i]), pmem++);
+ move64(&(pattern[i]), pmem++);
/*
* Put a different pattern on the data lines: otherwise they
* may float long enough to read back what we wrote.
*/
- move64((unsigned long long *)&otherpattern, pmem--);
+ move64(&otherpattern, pmem--);
move64(pmem, &temp64);
#ifdef INJECT_DATA_ERRORS
projects / karo-tx-uboot.git / commitdiff