powerpc/85xx: improve definition of BR_PHYS_ADDR macro

The BR_PHYS_ADDR(x) macro was missing parentheses around "x" in the macro
definition, so callers had to supply their own parenthesis.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 2a23d84cba5ffd4f2300da684296ac2c791d60bc..d1def75c66a3d9959754f3a1bb386a2288154785 100644 (file)
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -82,10 +82,10 @@ void lbc_sdram_init(void);
 
 /* Convert an address into the right format for the BR registers */
 #if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
-#define BR_PHYS_ADDR(x)        ((unsigned long)((x & 0x0ffff8000ULL) | \
-                                        ((x & 0x300000000ULL) >> 19)))
+#define BR_PHYS_ADDR(x)        \
+       ((u32)(((x) & 0x0ffff8000ULL) | (((x) & 0x300000000ULL) >> 19)))
 #else
-#define BR_PHYS_ADDR(x) (x & 0xffff8000)
+#define BR_PHYS_ADDR(x) ((u32)(x) & 0xffff8000)
 #endif
 
 /* OR - Option Registers

diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 33ded71160c4c968b8ad8a0b9b4093f44794cc9e..ceed5eaff01a134d6795fbd0250e8b253b42fcba 100644 (file)
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -217,8 +217,7 @@
 #endif
 
 #define CONFIG_FLASH_BR_PRELIM \
-               (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
-                | BR_PS_16 | BR_V)
+       (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
 
 #define CONFIG_SYS_BR1_PRELIM \
@@ -380,14 +379,14 @@
 #endif
 
 #define CONFIG_SYS_BR4_PRELIM \
-               (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
+               (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                | BR_PS_8               /* Port Size = 8 bit */ \
                | BR_MS_FCM             /* MSEL = FCM */ \
                | BR_V)                 /* valid */
 #define CONFIG_SYS_OR4_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #define CONFIG_SYS_BR5_PRELIM \
-               (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \
+               (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                | BR_PS_8               /* Port Size = 8 bit */ \
                | BR_MS_FCM             /* MSEL = FCM */ \
@@ -395,7 +394,7 @@
 #define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 
 #define CONFIG_SYS_BR6_PRELIM \
-               (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \
+               (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                | BR_PS_8               /* Port Size = 8 bit */ \
                | BR_MS_FCM             /* MSEL = FCM */ \

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index e26399465150afdf2853cfe4f966459eca549cbc..95ce0034c389b9338a50852803161876b47efc77 100644 (file)
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -189,8 +189,7 @@ extern unsigned long get_clock_freq(void);
 #endif
 
 #define CONFIG_SYS_BR0_PRELIM \
-       (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800000)) \
-       | BR_PS_16 | BR_V)
+       (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
 #define CONFIG_SYS_BR1_PRELIM \
        (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 

diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 956449e8843142a69ebeb1fb1de3fdd7d30912f5..d1b5b70ad5bd662c1ee25b2d59b0b63f45c50201 100644 (file)
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -205,8 +205,7 @@
 
 
 #define CONFIG_FLASH_BR_PRELIM \
-       (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
-       | BR_PS_16 | BR_V)
+       (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
 
 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
@@ -376,20 +375,20 @@
 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #endif
-#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
+#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
                               | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                               | BR_PS_8               /* Port Size = 8 bit */ \
                               | BR_MS_FCM             /* MSEL = FCM */ \
                               | BR_V)                 /* valid */
 #define CONFIG_SYS_OR4_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
+#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
                               | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                               | BR_PS_8               /* Port Size = 8 bit */ \
                               | BR_MS_FCM             /* MSEL = FCM */ \
                               | BR_V)                 /* valid */
 #define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 
-#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
+#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
                               | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                               | BR_PS_8               /* Port Size = 8 bit */ \
                               | BR_MS_FCM             /* MSEL = FCM */ \

diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 86217a46dbcfa8c6459350f27e09a3f73bcf0645..1d97e957202a101dd8a45dcfe16a24c92147a281 100644 (file)
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -134,7 +134,7 @@
 #endif
 
 #define CONFIG_FLASH_BR_PRELIM  \
-       (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
+       (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
 
 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */

diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 5fc956305d6b7b0ff364e42ff3b702ed59ede369..ae22acb27aac0c91d9c84cd1ca41f715d2733c02 100644 (file)
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -236,7 +236,8 @@
 #define CONFIG_SYS_FLASH_BASE_PHYS     CONFIG_SYS_FLASH_BASE
 #endif
 
-#define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
+#define CONFIG_FLASH_BR_PRELIM  \
+       (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
 
 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
@@ -338,20 +339,20 @@
 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM  /* NAND Base Address */
 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM  /* NAND Options */
 
-#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
+#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                                | BR_PS_8               /* Port Size = 8bit */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
                                | BR_V)                 /* valid */
 #define CONFIG_SYS_OR4_PRELIM  CONFIG_SYS_NAND_OR_PRELIM       /* NAND Options */
-#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
+#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                                | BR_PS_8               /* Port Size = 8bit */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
                                | BR_V)                 /* valid */
 #define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_NAND_OR_PRELIM       /* NAND Options */
 
-#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
+#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                                | BR_PS_8               /* Port Size = 8bit */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \

diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 5f6621209b28b48813a64b679207868252198720..f8f7a82aa969bbd95ba32aae4b377933a8e15677 100644 (file)
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -211,7 +211,7 @@
 #endif
 
 #define CONFIG_SYS_FLASH_BR_PRELIM \
-               (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
+               (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
                 | BR_PS_16 | BR_V)
 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
                                        | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 2cb942b4fe4872cf4d3a1100c1df6efe8d74861e..a8882d49da424e4fd19cf7532f98b43795833fcd 100644 (file)
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -357,7 +357,7 @@
 #define CONFIG_SYS_FLASH_BASE_PHYS     CONFIG_SYS_FLASH_BASE
 #endif
 
-#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
+#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
        | BR_PS_16 | BR_V)
 
 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
@@ -401,7 +401,7 @@
 #define CONFIG_SYS_NAND_U_BOOT_RELOC   0x00010000
 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP        (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
 
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS)) \
+#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
        | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
        | BR_PS_8       /* Port Size = 8 bit */ \
        | BR_MS_FCM     /* MSEL = FCM */ \