Enable the SSP base clock and set the divider

diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index 5f87a1efd6ce2c29190cc89108c5d7ee16b2bbcb..cac2312de9dfeadea2284c03134d56da832ec90e 100644 (file)
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -343,6 +343,8 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
         * CLOCK_DIVIDE has to be an even value from 2 to 254, and
         * CLOCK_RATE could be any integer from 0 to 255.
         */
+       writel(CLKCTRL_SSP_DIV_FRAC_EN | 29, priv->clkctrl_ssp);
+
        mmc->f_min = 400000;
        mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2;
        mmc->b_max = 0;