+commit 8993e54b6f397973794f3d6f47d3b3c0c98dd4f6
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date: Fri Jul 27 14:43:59 2007 +0200
+
+ [ADS5121] Support for the ADS5121 board
+
+ The following MPC5121e subsystems are supported:
+
+ - low-level CPU init
+ - NOR Boot Flash (common CFI driver)
+ - DDR SDRAM
+ - FEC
+ - I2C
+ - Watchdog
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+ Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+ Signed-off-by: Jan Wrobel <wrr@semihalf.com>
+
+commit 1863cfb7b100ba0ee3401799457a01dc058745f8
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date: Fri Jul 27 14:22:04 2007 +0200
+
+ [PPC] Remove unused MSR_USER definition
+
+ Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit cc3023b9f95d7ac959a764471a65001062aecf41
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date: Thu Jul 19 17:12:28 2007 +0200
+
+ Fix breakage of 8xx boards from recent commit.
+
+ This patch fixes the negative consequences for 8xx of the recent
+ "ppc4xx: Clean up 440 exceptions handling" commit.
+
+ Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit 3a6cab844cf74f76639d795e0be8717e02c86af7
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Jul 14 22:51:02 2007 +0200
+
+ Update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
commit 011595307731a7a67a7445d107c279d031e8ab97
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Sat Jul 14 01:06:58 2007 +0200
* According to MPC5121e RM, configuring local access windows should
* be followed by a dummy read of the config register that was
* modified last and an isync
- */
+ */
i = im->sysconf.ddrlaw.ar;
__asm__ __volatile__ ("isync");
uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
- brd_rev, cpld_rev);
+ brd_rev, cpld_rev);
return 0;
}
*
* NOTICE: TB needs to be enabled as early as possible in order to
* have udelay() working; if not enabled, usually leads to a hang, like
- * during FLASH chip identification etc.
+ * during FLASH chip identification etc.
*/
im->sysconf.spcr |= SPCR_TBEN;
}
* Trasmit BDs init
*/
for (ix = 0; ix < FEC_TBD_NUM; ix++) {
- fec->bdBase->tbd[ix].status = 0;
- }
+ fec->bdBase->tbd[ix].status = 0;
+ }
- /*
- * Have the last TBD to close the ring
- */
- fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
+ /*
+ * Have the last TBD to close the ring
+ */
+ fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
- /*
- * Initialize some indices
- */
- fec->tbdIndex = 0;
- fec->usedTbdIndex = 0;
- fec->cleanTbdNum = FEC_TBD_NUM;
+ /*
+ * Initialize some indices
+ */
+ fec->tbdIndex = 0;
+ fec->usedTbdIndex = 0;
+ fec->cleanTbdNum = FEC_TBD_NUM;
return 0;
}
fec->eth->r_cntrl = 0x05ee000c;
/* Half-duplex, heartbeat disabled */
- fec->eth->x_cntrl = 0x00000000;
+ fec->eth->x_cntrl = 0x00000000;
/* Enable MIB counters */
fec->eth->mib_control = 0x0;
/* Initilize addresses and status words of BDs */
mpc512x_fec_bd_init (fec);
- /* Descriptor polling active */
+ /* Descriptor polling active */
fec->eth->r_des_active = 0x01000000;
#if (DEBUG & 0x1)
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
*/
- fec->eth->mii_speed = (((gd->ipb_clk / 1000000) / 5) + 1) << 1;
+ fec->eth->mii_speed = (((gd->ipb_clk / 1000000) / 5) + 1) << 1;
/*
* Reset PHY, then delay 300ns
printf ("Forcing 10 Mbps ethernet link... ");
#endif
miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
-
+
miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
timeout = 20;
#if (DEBUG & 0x2)
printf ("done.\n");
#endif
- } else { /* MII100 */
+ } else { /* MII100 */
/*
* Set the auto-negotiation advertisement register bits
*/
pTbd->dataPointer = (uint32)eth_data;
pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
-
+
/* Activate transmit Buffer Descriptor polling */
fec->eth->x_des_active = 0x01000000; /* Descriptor polling active */
#if (DEBUG & 0x8)
printf( "-" );
#endif
-
+
/*
* Check if any critical events have happened
*/
}
if (!(pRbd->status & FEC_RBD_EMPTY)) {
- if ((pRbd->status & FEC_RBD_LAST) &&
+ if ((pRbd->status & FEC_RBD_LAST) &&
!(pRbd->status & FEC_RBD_ERR) &&
((pRbd->dataLength - 4) > 14)) {
-
+
/*
* Get buffer size
*/
* Initialize I\O pins
*/
reg = (uint32 *) &(im->io_ctrl.regs[PSC0_0_IDX]);
-
+
for (i = 0; i < 15; i++)
reg[i] = IOCTRL_MUX_FEC | 0x00000001;
/* Clean up space FEC's MIB and FIFO RAM ...*/
memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400);
-
- /*
+
+ /*
* Malloc space for BDs (must be quad word-aligned)
- * this pointer is lost, so cannot be freed
+ * this pointer is lost, so cannot be freed
*/
bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
- fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0);
+ fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0);
memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
/*
volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */
volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */
volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */
-
+
volatile uint32 RES1[3]; /* MBAR_ETH + 0x018-020 */
volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */
volatile uint32 RES4[7]; /* MBAR_ETH + 0x068-80 */
volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */
volatile uint32 r_hash; /* MBAR_ETH + 0x088 */
-
+
volatile uint32 RES5[14]; /* MBAR_ETH + 0x08c-0C0 */
volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */
-
+
volatile uint32 RES6[7]; /* MBAR_ETH + 0x0C8-0E0 */
volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */
volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */
volatile uint32 RES9[1]; /* MBAR_ETH + 0x148 */
volatile uint32 r_bound; /* MBAR_ETH + 0x14C */
volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */
-
+
volatile uint32 RES10[11]; /* MBAR_ETH + 0x154-17C */
volatile uint32 r_des_start; /* MBAR_ETH + 0x180 */
volatile uint32 x_des_start; /* MBAR_ETH + 0x184 */
spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
spll = ref_clk * spmf_mult[spmf];
-
+
sys_div = (im->clk.scfr[1] & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0];
csb_clk = sys_clk / 2;
- cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
- core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
+ cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
+ core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
if (ips_div != 0) {
*/
/* Boot CS/CS0 window range */
- lis r3, CFG_IMMR@h
- ori r3, r3, CFG_IMMR@l
+ lis r3, CFG_IMMR@h
+ ori r3, r3, CFG_IMMR@l
lis r4, START_REG(CFG_FLASH_BASE)
ori r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE)
lis r4, START_REG(CFG_SRAM_BASE) & 0xff00
stw r4, SRAMBAR(r3)
- /*
+ /*
* According to MPC5121e RM, configuring local access windows should
- * be followed by a dummy read of the config register that was
+ * be followed by a dummy read of the config register that was
* modified last and an isync
- */
+ */
lwz r4, SRAMBAR(r3)
isync
* config register so no params can be set for it
*/
lis r3, (CFG_IMMR + LPC_OFFSET)@h
- ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l
+ ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l
- lis r4, CFG_CS0_CFG@h
- ori r4, r4, CFG_CS0_CFG@l
- stw r4, CS0_CONFIG(r3)
+ lis r4, CFG_CS0_CFG@h
+ ori r4, r4, CFG_CS0_CFG@l
+ stw r4, CS0_CONFIG(r3)
/* Master enable all CS's */
lis r4, CS_CTRL_ME@h
#define CFG_SDRAM_BASE CFG_DDR_BASE
/* DDR Controller Configuration
-
-SYS_CFG:
- [31:31] MDDRC Soft Reset: Diabled
- [30:30] DRAM CKE pin: Enabled
- [29:29] DRAM CLK: Enabled
- [28:28] Command Mode: Enabled (For initialization only)
- [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
- [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
- [20:19] Read Test: DON'T USE
- [18:18] Self Refresh: Enabled
- [17:17] 16bit Mode: Disabled
- [16:13] Ready Delay: 2
- [12:12] Half DQS Delay: Disabled
- [11:11] Quarter DQS Delay: Disabled
- [10:08] Write Delay: 2
- [07:07] Early ODT: Disabled
- [06:06] On DIE Termination: Disabled
- [05:05] FIFO Overflow Clear: DON'T USE here
- [04:04] FIFO Underflow Clear: DON'T USE here
- [03:03] FIFO Overflow Pending: DON'T USE here
- [02:02] FIFO Underlfow Pending: DON'T USE here
- [01:01] FIFO Overlfow Enabled: Enabled
- [00:00] FIFO Underflow Enabled: Enabled
- TIME_CFG0
- [31:16] DRAM Refresh Time: 0 CSB clocks
- [15:8] DRAM Command Time: 0 CSB clocks
- [07:00] DRAM Precharge Time: 0 CSB clocks
- TIME_CFG1
- [31:26] DRAM tRFC:
- [25:21] DRAM tWR1:
- [20:17] DRAM tWRT1:
- [16:11] DRAM tDRR:
- [10:05] DRAM tRC:
- [04:00] DRAM tRAS:
- TIME_CFG2
- [31:28] DRAM tRCD:
- [27:23] DRAM tFAW:
- [22:19] DRAM tRTW1:
- [18:15] DRAM tCCD:
- [14:10] DRAM tRTP:
- [09:05] DRAM tRP:
- [04:00] DRAM tRPA */
+ *
+ * SYS_CFG:
+ * [31:31] MDDRC Soft Reset: Diabled
+ * [30:30] DRAM CKE pin: Enabled
+ * [29:29] DRAM CLK: Enabled
+ * [28:28] Command Mode: Enabled (For initialization only)
+ * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
+ * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
+ * [20:19] Read Test: DON'T USE
+ * [18:18] Self Refresh: Enabled
+ * [17:17] 16bit Mode: Disabled
+ * [16:13] Ready Delay: 2
+ * [12:12] Half DQS Delay: Disabled
+ * [11:11] Quarter DQS Delay: Disabled
+ * [10:08] Write Delay: 2
+ * [07:07] Early ODT: Disabled
+ * [06:06] On DIE Termination: Disabled
+ * [05:05] FIFO Overflow Clear: DON'T USE here
+ * [04:04] FIFO Underflow Clear: DON'T USE here
+ * [03:03] FIFO Overflow Pending: DON'T USE here
+ * [02:02] FIFO Underlfow Pending: DON'T USE here
+ * [01:01] FIFO Overlfow Enabled: Enabled
+ * [00:00] FIFO Underflow Enabled: Enabled
+ * TIME_CFG0
+ * [31:16] DRAM Refresh Time: 0 CSB clocks
+ * [15:8] DRAM Command Time: 0 CSB clocks
+ * [07:00] DRAM Precharge Time: 0 CSB clocks
+ * TIME_CFG1
+ * [31:26] DRAM tRFC:
+ * [25:21] DRAM tWR1:
+ * [20:17] DRAM tWRT1:
+ * [16:11] DRAM tDRR:
+ * [10:05] DRAM tRC:
+ * [04:00] DRAM tRAS:
+ * TIME_CFG2
+ * [31:28] DRAM tRCD:
+ * [27:23] DRAM tFAW:
+ * [22:19] DRAM tRTW1:
+ * [18:15] DRAM tCCD:
+ * [14:10] DRAM tRTP:
+ * [09:05] DRAM tRP:
+ * [04:00] DRAM tRPA
+ */
#define CFG_MDDRC_SYS_CFG 0xF8604200
#define CFG_MDDRC_SYS_CFG_RUN 0xE8604200
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_NET \
| CFG_CMD_PING \
- | CFG_CMD_MII \
+ | CFG_CMD_MII \
| CFG_CMD_I2C)
#endif
"bootm\0" \
"load=tftp 100000 /tftpboot/ads5121/u-boot.bin\0" \
"update=protect off fff00000 fff3ffff; " \
- "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
+ "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
"upd=run load;run update\0" \
""
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CS_CTRL 0x00020
#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */
-#define CS_CTRL_IE 0x08000000 /* CS Interrupt Enable bit */
+#define CS_CTRL_IE 0x08000000 /* CS Interrupt Enable bit */
/* SPRIDR - System Part and Revision ID Register
*/
projects / karo-tx-uboot.git / commitdiff