/u-boot.ldr
/u-boot.ldr.hex
/u-boot.ldr.srec
+/u-boot-onenand.bin
+/u-boot-flexonenand.bin
#
# Generated files
# cscope files
cscope.*
+
+# OneNAND IPL files
+/onenand_ipl/onenand-ipl*
+/onenand_ipl/board/*/onenand*
+/onenand_ipl/board/*/*.S
ATSTK1006 AT32AP7000
ATNGW100 AT32AP7000
+Alex Raimondi <alex.raimondi@miromico.ch>
+Julien May <julien.may@miromico.ch>
+
+ HAMMERHEAD AT32AP7000
+
#########################################################################
# SuperH Systems: #
# #
#########################################################################
LIST_pxa=" \
- adsvix \
cerf250 \
cradle \
csb226 \
atstk1004 \
atstk1006 \
atngw100 \
+ hammerhead \
"
#########################################################################
actux4_config : unconfig
@$(MKCONFIG) $(@:_config=) arm ixp actux4
-adsvix_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm pxa adsvix
-
cerf250_config : unconfig
@$(MKCONFIG) $(@:_config=) arm pxa cerf250
atstk1006_config : unconfig
@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
+hammerhead_config : unconfig
+ @$(MKCONFIG) $(@:_config=) avr32 at32ap hammerhead miromico at32ap700x
+
#========================================================================
# SH3 (SuperH)
#========================================================================
/*
- * (C) Copyright 2007 Semihalf
+ * (C) Copyright 2007-2008 Semihalf
*
* Written by: Rafal Jaworowski <raj@semihalf.com>
*
#define ENUM_USB 1
#define ENUM_SCSI 2
#define ENUM_MMC 3
-#define ENUM_MAX 4
+#define ENUM_SATA 4
+#define ENUM_MAX 5
struct stor_spec {
int max_dev;
int enum_started;
int enum_ended;
int type; /* "external" type: DT_STOR_{IDE,USB,etc} */
- char name[4];
+ char *name;
};
static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, "" }, };
specs[ENUM_IDE].type = DEV_TYP_STOR | DT_STOR_IDE;
specs[ENUM_IDE].name = "ide";
#endif
-#if defined(CONFIG_CMD_USB)
- specs[ENUM_USB].max_dev = USB_MAX_STOR_DEV;
- specs[ENUM_USB].enum_started = 0;
- specs[ENUM_USB].enum_ended = 0;
- specs[ENUM_USB].type = DEV_TYP_STOR | DT_STOR_USB;
- specs[ENUM_USB].name = "usb";
+#if defined(CONFIG_CMD_MMC)
+ specs[ENUM_MMC].max_dev = CFG_MMC_MAX_DEVICE;
+ specs[ENUM_MMC].enum_started = 0;
+ specs[ENUM_MMC].enum_ended = 0;
+ specs[ENUM_MMC].type = DEV_TYP_STOR | DT_STOR_MMC;
+ specs[ENUM_MMC].name = "mmc";
+#endif
+#if defined(CONFIG_CMD_SATA)
+ specs[ENUM_SATA].max_dev = CFG_SATA_MAX_DEVICE;
+ specs[ENUM_SATA].enum_started = 0;
+ specs[ENUM_SATA].enum_ended = 0;
+ specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA;
+ specs[ENUM_SATA].name = "sata";
#endif
#if defined(CONFIG_CMD_SCSI)
specs[ENUM_SCSI].max_dev = CFG_SCSI_MAX_DEVICE;
specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI;
specs[ENUM_SCSI].name = "scsi";
#endif
+#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
+ specs[ENUM_USB].max_dev = USB_MAX_STOR_DEV;
+ specs[ENUM_USB].enum_started = 0;
+ specs[ENUM_USB].enum_ended = 0;
+ specs[ENUM_USB].type = DEV_TYP_STOR | DT_STOR_USB;
+ specs[ENUM_USB].name = "usb";
+#endif
}
/*
if (first) {
di->cookie = (void *)get_dev(specs[type].name, 0);
- found = 1;
+ if (di->cookie == NULL)
+ return 0;
+ else
+ found = 1;
} else {
for (i = 0; i < specs[type].max_dev; i++)
}
di->cookie = (void *)get_dev(specs[type].name, i);
- found = 1;
+ if (di->cookie == NULL)
+ return 0;
+ else
+ found = 1;
/* provide hint if there are more devices in
* this group to enumerate */
return 0;
if ((dd->block_read) == NULL) {
- debugf("no block_read() for device 0x%08x\n");
+ debugf("no block_read() for device 0x%08x\n", cookie);
return 0;
}
/*
- * (C) Copyright 2007 Semihalf
+ * (C) Copyright 2007-2008 Semihalf
*
* Written by: Rafal Jaworowski <raj@semihalf.com>
*
#define errf(fmt, args...) do { printf("ERROR @ %s(): ", __func__); printf(fmt, ##args); } while (0)
-void test_dump_si(struct sys_info *);
+#define BUF_SZ 2048
+#define WAIT_SECS 5
+
+void test_dump_buf(void *, int);
void test_dump_di(int);
+void test_dump_si(struct sys_info *);
void test_dump_sig(struct api_signature *);
-char buf[2048];
-
-#define WAIT_SECS 5
+static char buf[BUF_SZ];
int main(int argc, char *argv[])
{
if (sig->version > API_SIG_VERSION)
return -3;
- printf("API signature found @%x\n", sig);
+ printf("API signature found @%x\n", (unsigned int)sig);
test_dump_sig(sig);
printf("\n*** Consumer API test ***\n");
- printf("syscall ptr 0x%08x@%08x\n", syscall_ptr, &syscall_ptr);
+ printf("syscall ptr 0x%08x@%08x\n", (unsigned int)syscall_ptr,
+ (unsigned int)&syscall_ptr);
/* console activities */
ub_putc('B');
if (i == devs_no)
printf("No storage devices available\n");
else {
+ memset(buf, 0, BUF_SZ);
+
if ((rv = ub_dev_open(i)) != 0)
errf("open device %d error %d\n", i, rv);
- else if ((rv = ub_dev_read(i, &buf, 200, 20)) != 0)
+
+ else if ((rv = ub_dev_read(i, buf, 1, 0)) != 0)
errf("could not read from device %d, error %d\n", i, rv);
+ printf("Sector 0 dump (512B):\n");
+ test_dump_buf(buf, 512);
+
ub_dev_close(i);
}
printf("signature:\n");
printf(" version\t= %d\n", sig->version);
printf(" checksum\t= 0x%08x\n", sig->checksum);
- printf(" sc entry\t= 0x%08x\n", sig->syscall);
+ printf(" sc entry\t= 0x%08x\n", (unsigned int)sig->syscall);
}
void test_dump_si(struct sys_info *si)
int i;
printf("sys info:\n");
- printf(" clkbus\t= 0x%08x\n", si->clk_bus);
- printf(" clkcpu\t= 0x%08x\n", si->clk_cpu);
- printf(" bar\t\t= 0x%08x\n", si->bar);
+ printf(" clkbus\t= 0x%08x\n", (unsigned int)si->clk_bus);
+ printf(" clkcpu\t= 0x%08x\n", (unsigned int)si->clk_cpu);
+ printf(" bar\t\t= 0x%08x\n", (unsigned int)si->bar);
printf("---\n");
for (i = 0; i < si->mr_no; i++) {
}
}
-static char * test_stor_typ(int type)
+static char *test_stor_typ(int type)
{
if (type & DT_STOR_IDE)
return "IDE";
+ if (type & DT_STOR_MMC)
+ return "MMC";
+
+ if (type & DT_STOR_SATA)
+ return "SATA";
+
if (type & DT_STOR_SCSI)
return "SCSI";
if (type & DT_STOR_USB)
return "USB";
- if (type & DT_STOR_MMC);
- return "MMC";
-
return "Unknown";
}
+void test_dump_buf(void *buf, int len)
+{
+ int i;
+ int line_counter = 0;
+ int sep_flag = 0;
+ int addr = 0;
+
+ printf("%07x:\t", addr);
+
+ for (i = 0; i < len; i++) {
+ if (line_counter++ > 15) {
+ line_counter = 0;
+ sep_flag = 0;
+ addr += 16;
+ i--;
+ printf("\n%07x:\t", addr);
+ continue;
+ }
+
+ if (sep_flag++ > 1) {
+ sep_flag = 1;
+ printf(" ");
+ }
+
+ printf("%02x", *((char *)buf++));
+ }
+
+ printf("\n");
+}
+
void test_dump_di(int handle)
{
int i;
} else if (di->type & DEV_TYP_STOR) {
printf(" type\t\t= %s\n", test_stor_typ(di->type));
- printf(" blk size\t\t= %d\n", di->di_stor.block_size);
- printf(" blk count\t\t= %d\n", di->di_stor.block_count);
+ printf(" blk size\t\t= %d\n", (unsigned int)di->di_stor.block_size);
+ printf(" blk count\t\t= %d\n", (unsigned int)di->di_stor.block_count);
}
}
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
-
- /* arch number of ADSVIX-Board */
- gd->bd->bi_arch_number = 620;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa000003c;
-
- return 0;
-}
-
-int board_late_init(void)
-{
- setenv("stdout", "serial");
- setenv("stderr", "serial");
- return 0;
-}
-
-
-int dram_init (void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
- return 0;
-}
+++ /dev/null
-TEXT_BASE = 0xa1700000
+++ /dev/null
-/*
- * This was originally from the Lubbock u-boot port.
- *
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-
-/*
- * Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CFG_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CFG_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CFG_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPSR3
- ldr r1, =CFG_GPSR3_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CFG_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CFG_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CFG_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR3
- ldr r1, =CFG_GPCR3_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CFG_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CFG_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CFG_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR3
- ldr r1, =CFG_GPDR3_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CFG_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CFG_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CFG_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CFG_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CFG_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CFG_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR3_L
- ldr r1, =CFG_GAFR3_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR3_U
- ldr r1, =CFG_GAFR3_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CFG_PSSR_VAL
- str r1, [r0]
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CFG_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CFG_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CFG_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CFG_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CFG_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CFG_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CFG_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CFG_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CFG_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CFG_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
- ldr r2, =CFG_FLYCNFG_VAL
- str r2, [r1, #FLYCNFG_OFFSET]
- str r2, [r1, #FLYCNFG_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field. */
-
- ldr r4, [r1, #MDREFR_OFFSET]
- ldr r2, =0xFFF
- bic r4, r4, r2
-
- ldr r3, =CFG_MDREFR_VAL
- and r3, r3, r2
-
- orr r4, r4, r3
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
-
- orr r4, r4, #MDREFR_K0RUN
- orr r4, r4, #MDREFR_K0DB4
- orr r4, r4, #MDREFR_K0FREE
- orr r4, r4, #MDREFR_K0DB2
- orr r4, r4, #MDREFR_K1DB2
- bic r4, r4, #MDREFR_K1FREE
- bic r4, r4, #MDREFR_K2FREE
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Note: preserve the mdrefr value in r4 */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- ldr r2, =CFG_SXCNFG_VAL
- str r2, [r1, #SXCNFG_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
-
- orr r4, r4, #MDREFR_K1RUN
- bic r4, r4, #MDREFR_K2DB2
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- bic r4, r4, #MDREFR_SLFRSH
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- orr r4, r4, #MDREFR_E1PIN
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- nop
- nop
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CFG_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
- bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
-
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- ldr r3, =CFG_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- mov r4, r3
- orr r3, r3, #MDCNFG_DE0
- str r3, [r1, #MDCNFG_OFFSET]
- mov r0, r3
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CFG_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
- /* enable APD */
- ldr r3, [r1, #MDREFR_OFFSET]
- orr r3, r3, #MDREFR_APD
- str r3, [r1, #MDREFR_OFFSET]
-
- /* We are finished with Intel's memory controller initialisation */
-
-setvoltage:
-
- mov r10, lr
- bl initPXAvoltage /* In case the board is rebooting with a */
- mov lr, r10 /* low voltage raise it up to a good one. */
-
-wakeup:
- /* Are we waking from sleep? */
- ldr r0, =RCSR
- ldr r1, [r0]
- and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
- str r1, [r0]
- teq r1, #RCSR_SMR
-
- bne initirqs
-
- ldr r0, =PSSR
- mov r1, #PSSR_PH
- str r1, [r0]
-
- /* if so, resume at PSPR */
- ldr r0, =PSPR
- ldr r1, [r0]
- mov pc, r1
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
-
- /* Turn Off on-chip peripheral clocks (except for memory) */
- /* for re-configuration. */
- ldr r1, =CKEN
- ldr r2, =CFG_CKEN
- str r2, [r1]
-
- /* ... and write the core clock config register */
- ldr r2, =CFG_CCCR
- ldr r1, =CCCR
- str r2, [r1]
-
- /* Turn on turbo mode */
- mrc p14, 0, r2, c6, c0, 0
- orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/
- mcr p14, 0, r2, c6, c0, 0
-
- /* Re-write MDREFR */
- ldr r1, =MEMC_BASE
- ldr r2, [r1, #MDREFR_OFFSET]
- str r2, [r1, #MDREFR_OFFSET]
-#ifdef RTC
- /* enable the 32Khz oscillator for RTC and PowerManager */
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#else
-#error "RTC not defined"
-#endif
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
- /* FIXME */
-
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End lowlevel_init */
- /* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
- mov pc, lr
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/pxa-regs.h>
-
-void pcmcia_power_on(void)
-{
-#if 0
- if (!(GPLR(20) & GPIO_bit(20))) { /* 3.3V */
- GPCR(81) = GPIO_bit(81);
- GPSR(82) = GPIO_bit(82);
- }
- else if (!(GPLR(21) & GPIO_bit(21))) { /* 5.0V */
- GPCR(81) = GPIO_bit(81);
- GPCR(82) = GPIO_bit(82);
- }
-#else
-#warning "Board will only supply 5V, wait for next HW spin for selectable power"
- /* 5.0V */
- GPCR(81) = GPIO_bit(81);
- GPCR(82) = GPIO_bit(82);
-#endif
-
- udelay(300000);
-
- /* reset the card */
- GPSR(52) = GPIO_bit(52);
-
- /* enable PCMCIA */
- GPCR(83) = GPIO_bit(83);
-
- /* clear reset */
- udelay(10);
- GPCR(52) = GPIO_bit(52);
-
- udelay(20000);
-}
-
-void pcmcia_power_off(void)
-{
- /* 0V */
- GPSR(81) = GPIO_bit(81);
- GPSR(82) = GPIO_bit(82);
- /* disable PCMCIA */
- GPSR(83) = GPIO_bit(83);
-}
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/pxa-regs.h>
-
-#define LTC1663_ADDR 0x20
-
-#define LTC1663_SY 0x01 /* Sync ACK */
-#define LTC1663_SD 0x04 /* shutdown */
-#define LTC1663_BG 0x04 /* Internal Voltage Ref */
-
-#define VOLT_1_55 18 /* DAC value for 1.55V */
-
- .global initPXAvoltage
-
-@ Set the voltage to 1.55V early in the boot process so we can run
-@ at a high clock speed and boot quickly. Note that this is necessary
-@ because the reset button does not reset the CPU voltage, so if the
-@ voltage was low (say 0.85V) then the CPU would crash without this
-@ routine
-
-@ This routine clobbers r0-r4
-
-initializei2c:
-
- ldr r2, =CKEN
- ldr r3, [r2]
- orr r3, r3, #CKEN15_PWRI2C
- str r3, [r2]
-
- ldr r2, =PCFR
- ldr r3, [r2]
- orr r3, r3, #PCFR_PI2C_EN
- str r3, [r2]
-
- /* delay for about 250msec
- */
- ldr r3, =OSCR
- mov r2, #0
- str r2, [r3]
- ldr r1, =0xC0000
-
-1:
- ldr r2, [r3]
- cmp r1, r2
- bgt 1b
- ldr r0, =PWRICR
- ldr r1, [r0]
- bic r1, r1, #(ICR_MA | ICR_START | ICR_STOP)
- str r1, [r0]
-
- orr r1, r1, #ICR_UR
- str r1, [r0]
-
- ldr r2, =PWRISR
- ldr r3, =0x7ff
- str r3, [r2]
-
- bic r1, r1, #ICR_UR
- str r1, [r0]
-
- mov r1, #(ICR_GCD | ICR_SCLE)
- str r1, [r0]
-
- orr r1, r1, #ICR_IUE
- str r1, [r0]
-
- orr r1, r1, #ICR_FM
- str r1, [r0]
-
- /* delay for about 1msec
- */
- ldr r3, =OSCR
- mov r2, #0
- str r2, [r3]
- ldr r1, =0xC00
-
-1:
- ldr r2, [r3]
- cmp r1, r2
- bgt 1b
- mov pc, lr
-
-sendbytei2c:
- ldr r3, =PWRIDBR
- str r0, [r3]
- ldr r3, =PWRICR
- ldr r0, [r3]
- orr r0, r0, r1
- bic r0, r0, r2
- str r0, [r3]
- orr r0, r0, #ICR_TB
- str r0, [r3]
-
- mov r2, #0x100000
-
-waitfortxemptyi2c:
-
- ldr r0, =PWRISR
- ldr r1, [r0]
-
- /* take it from the top if we don't get empty after a while */
- subs r2, r2, #1
- moveq lr, r4
- beq initPXAvoltage
-
- tst r1, #ISR_ITE
-
- beq waitfortxemptyi2c
-
- orr r1, r1, #ISR_ITE
- str r1, [r0]
-
- mov pc, lr
-
-initPXAvoltage:
-
- mov r4, lr
-
- bl setleds
-
- bl initializei2c
-
- bl setleds
-
- /* now send the real message to set the correct voltage */
- ldr r0, =LTC1663_ADDR
- mov r0, r0, LSL #1
- mov r1, #ICR_START
- ldr r2, =(ICR_STOP | ICR_ALDIE | ICR_ACKNAK)
- bl sendbytei2c
-
- bl setleds
-
- mov r0, #LTC1663_BG
- mov r1, #0
- mov r2, #(ICR_STOP | ICR_START)
- bl sendbytei2c
-
- bl setleds
-
- ldr r0, =VOLT_1_55
- and r0, r0, #0xff
- mov r1, #0
- mov r2, #(ICR_STOP | ICR_START)
- bl sendbytei2c
-
- bl setleds
-
- ldr r0, =VOLT_1_55
- mov r0, r0, ASR #8
- and r0, r0, #0xff
- mov r1, #ICR_STOP
- mov r2, #ICR_START
- bl sendbytei2c
-
- bl setleds
-
- @ delay a little for the volatage to stablize
- ldr r3, =OSCR
- mov r2, #0
- str r2, [r3]
- ldr r1, =0xC0
-
-1:
- ldr r2, [r3]
- cmp r1, r2
- bgt 1b
- mov pc, r4
-
-setleds:
- mov pc, lr
-
- ldr r5, =0x40e00058
- ldr r3, [r5]
- bic r3, r3, #0x3
- str r3, [r5]
- ldr r5, =0x40e0000c
- ldr r3, [r5]
- orr r3, r3, #0x00010000
- str r3, [r5]
-
- @ inner loop
- mov r0, #0x2
-1:
-
- ldr r5, =0x40e00018
- mov r3, #0x00010000
- str r3, [r5]
-
- @ outer loop
- mov r3, #0x00F00000
-2:
- subs r3, r3, #1
- bne 2b
-
- ldr r5, =0x40e00024
- mov r3, #0x00010000
- str r3, [r5]
-
- @ outer loop
- mov r3, #0x00F00000
-3:
- subs r3, r3, #1
- bne 3b
-
- subs r0, r0, #1
- bne 1b
-
- mov pc, lr
printf ("%4lu MB\n", totlen >>20);
}
-#endif /* CFG_CMD_NAND */
+#endif /* CONFIG_CMD_NAND */
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
/*
#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright (C) 2008 Miromico AG
#
-# See file CREDITS for list of people who contributed to this
-# project.
+# See file CREDITS for list of people who contributed to this project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
-#
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB := $(obj)lib$(BOARD).a
-COBJS := adsvix.o pcmcia.o
-SOBJS := lowlevel_init.o pxavoltage.o
+COBJS := $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
--- /dev/null
+TEXT_BASE = 0x00000000
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+PLATFORM_LDFLAGS += --gc-sections
--- /dev/null
+/*
+ * Copyright (C) 2008 Miromico AG
+ *
+ * Mostly copied form atmel ATNGW100 sources
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "../cpu/at32ap/at32ap700x/sm.h"
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/memory-map.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct sdram_config sdram_config = {
+ .data_bits = SDRAM_DATA_32BIT,
+ .row_bits = 13,
+ .col_bits = 9,
+ .bank_bits = 2,
+ .cas = 3,
+ .twr = 2,
+ .trc = 7,
+ .trp = 2,
+ .trcd = 2,
+ .tras = 5,
+ .txsr = 5,
+ /* 7.81 us */
+ .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
+};
+
+extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ return macb_eth_initialize(0, (void *)MACB0_BASE, bis->bi_phy_id[0]);
+}
+#endif
+
+int board_early_init_f(void)
+{
+ /* Enable SDRAM in the EBI mux */
+ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+ gpio_enable_ebi();
+ gpio_enable_usart1();
+
+#if defined(CONFIG_MACB)
+ gpio_enable_macb0();
+#endif
+#if defined(CONFIG_MMC)
+ gpio_enable_mmci();
+#endif
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ unsigned long expected_size;
+ unsigned long actual_size;
+ void *sdram_base;
+
+ sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
+
+ expected_size = sdram_init(sdram_base, &sdram_config);
+ actual_size = get_ram_size(sdram_base, expected_size);
+
+ unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return actual_size;
+}
+
+void board_init_info(void)
+{
+ gd->bd->bi_phy_id[0] = 0x01;
+}
+
+void gclk_init(void)
+{
+ /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
+
+ /* Select GCLK3 peripheral function */
+ gpio_select_periph_A(GPIO_PIN_PB29, 0);
+
+ /* Enable GCLK3 with no input divider, from OSC0 (crystal) */
+ sm_writel(PM_GCCTRL(3), SM_BIT(CEN));
+}
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+/* -*- Fundamental -*-
+ *
+ * Copyright (C) 2005-2006 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+OUTPUT_ARCH(avr32)
ENTRY(_start)
+
SECTIONS
{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- cpu/pxa/start.o (.text)
- *(.text)
+ . = 0;
+ _text = .;
+ .text : {
+ *(.exception.text)
+ *(.text)
+ *(.text.*)
}
+ _etext = .;
- . = ALIGN(4);
- .rodata : { *(.rodata) }
+ .rodata : {
+ *(.rodata)
+ *(.rodata.*)
+ }
- . = ALIGN(4);
- .data : { *(.data) }
+ . = ALIGN(8);
+ _data = .;
+ .data : {
+ *(.data)
+ *(.data.*)
+ }
. = ALIGN(4);
- .got : { *(.got) }
-
- . = .;
__u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
+ .u_boot_cmd : {
+ KEEP(*(.u_boot_cmd))
+ }
__u_boot_cmd_end = .;
. = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) }
+ _got = .;
+ .got : {
+ *(.got)
+ }
+ _egot = .;
+
+ . = ALIGN(8);
+ _edata = .;
+
+ .bss : {
+ *(.bss)
+ *(.bss.*)
+ }
+ . = ALIGN(8);
_end = .;
}
#include <lmb.h>
#include <asm/byteorder.h>
-#if (CONFIG_COMMANDS & CFG_CMD_USB)
+#if (CONFIG_CMD_USB)
#include <usb.h>
#endif
*/
iflag = disable_interrupts();
-#if (CONFIG_COMMANDS & CFG_CMD_USB)
+#if (CONFIG_CMD_USB)
/*
* turn off USB to prevent the host controller from writing to the
* SDRAM while Linux is booting. This could happen (at least for OHCI
puts ("Bad sector specification\n");
return 1;
}
- printf ("Erase Flash Sectors %d-%d in Bank # %d ",
+ printf ("Erase Flash Sectors %d-%d in Bank # %zu ",
sect_first, sect_last, (info-flash_info)+1);
rcode = flash_erase(info, sect_first, sect_last);
return rcode;
puts ("Bad sector specification\n");
return 1;
}
- printf("%sProtect Flash Sectors %d-%d in Bank # %d\n",
+ printf("%sProtect Flash Sectors %d-%d in Bank # %zu\n",
p ? "" : "Un-", sect_first, sect_last,
(info-flash_info)+1);
for (i = sect_first; i <= sect_last; i++) {
#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
-void inline ide_outb(int dev, int port, unsigned char val);
-unsigned char inline ide_inb(int dev, int port);
static void input_data(int dev, ulong *sect_buf, int words);
static void output_data(int dev, ulong *sect_buf, int words);
static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
/* ------------------------------------------------------------------------- */
+void inline
+__ide_outb(int dev, int port, unsigned char val)
+{
+ debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
+ dev, port, val, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)));
+ outb(val, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)));
+}
+void inline ide_outb (int dev, int port, unsigned char val)
+ __attribute__((weak, alias("__ide_outb")));
+
+unsigned char inline
+__ide_inb(int dev, int port)
+{
+ uchar val;
+ val = inb((ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)));
+ debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
+ dev, port, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)), val);
+ return val;
+}
+unsigned char inline ide_inb(int dev, int port)
+ __attribute__((weak, alias("__ide_inb")));
+
void ide_init (void)
{
/* ------------------------------------------------------------------------- */
-void inline
-__ide_outb(int dev, int port, unsigned char val)
-{
- debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
- dev, port, val, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)));
- outb(val, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)));
-}
-void inline ide_outb (int dev, int port, unsigned char val)
- __attribute__((weak, alias("__ide_outb")));
-
-unsigned char inline
-__ide_inb(int dev, int port)
-{
- uchar val;
- val = inb((ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)));
- debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
- dev, port, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)), val);
- return val;
-}
-unsigned char inline ide_inb(int dev, int port)
- __attribute__((weak, alias("__ide_inb")));
-
#ifdef __PPC__
# ifdef CONFIG_AMIGAONEG3SE
static void
#define SM_PM_IMR 0x0048
#define SM_PM_ISR 0x004c
#define SM_PM_ICR 0x0050
-#define SM_PM_GCCTRL 0x0060
+#define SM_PM_GCCTRL(x) (0x0060 + 4 * x)
#define SM_RTC_CTRL 0x0080
#define SM_RTC_VAL 0x0084
#define SM_RTC_TOP 0x0088
sysreg_write(EVBA, (unsigned long)&_evba);
asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET));
+ if(gclk_init)
+ gclk_init();
+
return 0;
}
sd = (*sys_powerctrl & 0x03) + 2;
/* calulate 2x baudrate and round */
- divisorx2 = ((CFG_HZ/(sd * 16 * CONFIG_BAUDRATE)));
+ divisorx2 = ((CFG_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE)));
if (divisorx2 & 0x01)
divisorx2 = divisorx2 + 1;
set_GPIO_mode(GPIO8_MMCCS0_MD);
#endif
CKEN |= CKEN12_MMC; /* enable MMC unit clock */
-#if defined(CONFIG_ADSVIX)
- /* turn on the power */
- GPCR(114) = GPIO_bit(114);
- udelay(1000);
-#endif
MMC_CLKRT = MMC_CLKRT_0_3125MHZ;
MMC_RESTO = MMC_RES_TO_MAX;
i2c_init(int speed, int slaveadd)
{
struct fsl_i2c *dev;
+ unsigned int temp;
dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET);
writeb(0, &dev->cr); /* stop I2C controller */
udelay(5); /* let it shutdown in peace */
- i2c_bus_speed[0] = set_i2c_bus_speed(dev, gd->i2c1_clk, speed);
+ temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed);
+ if (gd->flags & GD_FLG_RELOC)
+ i2c_bus_speed[0] = temp;
writeb(slaveadd << 1, &dev->adr); /* write slave address */
writeb(0x0, &dev->sr); /* clear status register */
writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
writeb(0, &dev->cr); /* stop I2C controller */
udelay(5); /* let it shutdown in peace */
- i2c_bus_speed[1] = set_i2c_bus_speed(dev, gd->i2c2_clk, speed);
+ temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed);
+ if (gd->flags & GD_FLG_RELOC)
+ i2c_bus_speed[1] = temp;
writeb(slaveadd << 1, &dev->adr); /* write slave address */
writeb(0x0, &dev->sr); /* clear status register */
writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
struct urb *urb;
if (!(urb = (struct urb *) malloc (sizeof (struct urb)))) {
- usberr (" F A T A L: malloc(%u) FAILED!!!!",
+ usberr (" F A T A L: malloc(%zu) FAILED!!!!",
sizeof (struct urb));
return NULL;
}
#define DT_STOR_SCSI 0x0020
#define DT_STOR_USB 0x0040
#define DT_STOR_MMC 0x0080
+#define DT_STOR_SATA 0x0100
#define DEV_STA_CLOSED 0x0000 /* invalid, closed */
#define DEV_STA_OPEN 0x0001 /* open i.e. active */
#endif
extern void clk_init(void);
+extern void gclk_init(void) __attribute__((weak));
/* Board code may need the SDRAM base clock as a compile-time constant */
#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
#ifndef __COMMAND_H
#define __COMMAND_H
+#include <config.h>
+
#ifndef NULL
#define NULL 0
#endif
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 KB for Monitor */
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */
#ifdef CONFIG_BZIP2
#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
#else
#define CONFIG_MISC_INIT_R 1
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if (CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5
#endif
#define CFG_PROMPT_HUSH_PS2 "> "
#undef CFG_LONGHELP
#define CFG_PROMPT "=> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if (CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024
#else
#define CFG_CBSIZE 256
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuation settings for the LUBBOCK board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */
-#define CONFIG_ADSVIX 1 /* on a Adsvix Board */
-#define CONFIG_MMC 1
-#define BOARD_LATE_INIT 1
-
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
-#define RTC
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_FFUART 1 /* we use FFUART on ADSVIX */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE 38400
-
-#define CONFIG_DOS_PARTITION 1
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_PCMCIA
-
-#undef CONFIG_CMD_NET
-
-
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_SERVERIP 192.168.1.99
-#define CONFIG_BOOTCOMMAND "run boot_flash"
-#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\
- " rw root=/dev/ram initrd=0xa0800000,5m"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "program_boot_cf=" \
- "mw.b 0xa0010000 0xff 0x20000; " \
- "if pinit on && " \
- "ide reset && " \
- "fatload ide 0 0xa0010000 u-boot.bin; " \
- "then " \
- "protect off 0x0 0x1ffff; " \
- "erase 0x0 0x1ffff; " \
- "cp.b 0xa0010000 0x0 0x20000; " \
- "fi\0" \
- "program_uzImage_cf=" \
- "mw.b 0xa0010000 0xff 0x180000; " \
- "if pinit on && " \
- "ide reset && " \
- "fatload ide 0 0xa0010000 uzImage; " \
- "then " \
- "protect off 0x40000 0x1bffff; " \
- "erase 0x40000 0x1bffff; " \
- "cp.b 0xa0010000 0x40000 0x180000; " \
- "fi\0" \
- "program_ramdisk_cf=" \
- "mw.b 0xa0010000 0xff 0x500000; " \
- "if pinit on && " \
- "ide reset && " \
- "fatload ide 0 0xa0010000 ramdisk.gz; " \
- "then " \
- "protect off 0x1c0000 0x6bffff; " \
- "erase 0x1c0000 0x6bffff; " \
- "cp.b 0xa0010000 0x1c0000 0x500000; " \
- "fi\0" \
- "boot_cf=" \
- "if pinit on && " \
- "ide reset && " \
- "fatload ide 0 0xa0030000 uzImage && " \
- "fatload ide 0 0xa0800000 ramdisk.gz; " \
- "then " \
- "bootm 0xa0030000; " \
- "fi\0" \
- "program_boot_mmc=" \
- "mw.b 0xa0010000 0xff 0x20000; " \
- "if mmcinit && " \
- "fatload mmc 0 0xa0010000 u-boot.bin; " \
- "then " \
- "protect off 0x0 0x1ffff; " \
- "erase 0x0 0x1ffff; " \
- "cp.b 0xa0010000 0x0 0x20000; " \
- "fi\0" \
- "program_uzImage_mmc=" \
- "mw.b 0xa0010000 0xff 0x180000; " \
- "if mmcinit && " \
- "fatload mmc 0 0xa0010000 uzImage; " \
- "then " \
- "protect off 0x40000 0x1bffff; " \
- "erase 0x40000 0x1bffff; " \
- "cp.b 0xa0010000 0x40000 0x180000; " \
- "fi\0" \
- "program_ramdisk_mmc=" \
- "mw.b 0xa0010000 0xff 0x500000; " \
- "if mmcinit && " \
- "fatload mmc 0 0xa0010000 ramdisk.gz; " \
- "then " \
- "protect off 0x1c0000 0x6bffff; " \
- "erase 0x1c0000 0x6bffff; " \
- "cp.b 0xa0010000 0x1c0000 0x500000; " \
- "fi\0" \
- "boot_mmc=" \
- "if mmcinit && " \
- "fatload mmc 0 0xa0030000 uzImage && " \
- "fatload mmc 0 0xa0800000 ramdisk.gz; " \
- "then " \
- "bootm 0xa0030000; " \
- "fi\0" \
- "boot_flash=" \
- "cp.b 0x1c0000 0xa0800000 0x500000; " \
- "bootm 0x40000\0" \
-
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-/* #define CONFIG_INITRD_TAG 1 */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_HUSH_PARSER 1
-#define CFG_PROMPT_HUSH_PS2 "> "
-
-#define CFG_LONGHELP /* undef to save memory */
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT "$ " /* Monitor Command Prompt */
-#else
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#endif
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_DEVICE_NULLDEV 1
-
-#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR 0xa1000000 /* default load address */
-
-#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
-
- /* valid baudrates */
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-#define CFG_MMC_BASE 0xF0000000
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-
-#define CFG_DRAM_BASE 0xa0000000
-#define CFG_DRAM_SIZE 0x04000000
-
-#define CFG_FLASH_BASE PHYS_FLASH_1
-
-/*
- * GPIO settings
- */
-
-#define CFG_GPSR0_VAL 0x00018004
-#define CFG_GPSR1_VAL 0x004F0080
-#define CFG_GPSR2_VAL 0x13EFC000
-#define CFG_GPSR3_VAL 0x0006E032
-#define CFG_GPCR0_VAL 0x084AFE1A
-#define CFG_GPCR1_VAL 0x003003F2
-#define CFG_GPCR2_VAL 0x0C014000
-#define CFG_GPCR3_VAL 0x00000C00
-#define CFG_GPDR0_VAL 0xCBC3BFFC
-#define CFG_GPDR1_VAL 0x00FFABF3
-#define CFG_GPDR2_VAL 0x1EEFFC00
-#define CFG_GPDR3_VAL 0x0187EC32
-#define CFG_GAFR0_L_VAL 0x84400000
-#define CFG_GAFR0_U_VAL 0xA51A8010
-#define CFG_GAFR1_L_VAL 0x699A955A
-#define CFG_GAFR1_U_VAL 0x0005A0AA
-#define CFG_GAFR2_L_VAL 0x40000000
-#define CFG_GAFR2_U_VAL 0x0109A400
-#define CFG_GAFR3_L_VAL 0x54000000
-#define CFG_GAFR3_U_VAL 0x00001409
-
-#define CFG_PSSR_VAL 0x20
-
-/*
- * Clock settings
- */
-#define CFG_CKEN 0x00400200
-#define CFG_CCCR 0x02000290 /* 520Mhz */
-/* #define CFG_CCCR 0x02000210 416 Mhz */
-
-/*
- * Memory settings
- */
-
-#define CFG_MSC0_VAL 0x23F2B3DB
-#define CFG_MSC1_VAL 0x0000CCD1
-#define CFG_MSC2_VAL 0x0000B884
-#define CFG_MDCNFG_VAL 0x08000AC8
-#define CFG_MDREFR_VAL 0x0000001E
-#define CFG_MDMRS_VAL 0x00000000
-
-#define CFG_FLYCNFG_VAL 0x00010001
-#define CFG_SXCNFG_VAL 0x40044004
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CFG_MECR_VAL 0x00000002
-#define CFG_MCMEM0_VAL 0x00004204
-#define CFG_MCMEM1_VAL 0x00000000
-#define CFG_MCATT0_VAL 0x00010504
-#define CFG_MCATT1_VAL 0x00000000
-#define CFG_MCIO0_VAL 0x00008407
-#define CFG_MCIO1_VAL 0x00000000
-
-#define CONFIG_PXA_PCMCIA 1
-#define CONFIG_PXA_IDE 1
-
-#define CONFIG_PCMCIA_SLOT_A 1
-/* just to keep build system happy */
-
-#define CFG_PCMCIA_MEM_ADDR 0x28000000
-#define CFG_PCMCIA_MEM_SIZE 0x04000000
-
-
-#define CFG_IDE_MAXBUS 1
-/* max. 1 IDE bus */
-#define CFG_IDE_MAXDEVICE 1
-/* max. 1 drive per IDE bus */
-
-#define CFG_ATA_IDE0_OFFSET 0x0000
-
-#define CFG_ATA_BASE_ADDR 0x20000000
-
-/* Offset for data I/O */
-#define CFG_ATA_DATA_OFFSET 0x1f0
-
-/* Offset for normal register accesses */
-#define CFG_ATA_REG_OFFSET 0x1f0
-
-/* Offset for alternate registers */
-#define CFG_ATA_ALT_OFFSET 0x3f0
-
-/*
- * FLASH and environment organization
- */
-
-#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER 1
-
-#define CFG_MONITOR_BASE 0
-#define CFG_MONITOR_LEN 0x20000
-
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
-
-/* write flash less slowly */
-#define CFG_FLASH_USE_BUFFER_WRITE 1
-
-/* Flash environment locations */
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */
-#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */
-#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
-
-#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2008 Miromico AG
+ *
+ * Configuration settings for the Miromico Hammerhead AVR32 board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_AVR32 1
+#define CONFIG_AT32AP 1
+#define CONFIG_AT32AP7000 1
+#define CONFIG_HAMMERHEAD 1
+
+#define CFG_HZ 1000
+
+/*
+ * Set up the PLL to run at 125 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
+ * and the PBA bus to run at 1/4 the PLL frequency.
+ */
+#define CONFIG_PLL 1
+#define CFG_POWER_MANAGER 1
+#define CFG_OSC0_HZ 25000000
+#define CFG_PLL0_DIV 1
+#define CFG_PLL0_MUL 5
+#define CFG_PLL0_SUPPRESS_CYCLES 16
+#define CFG_CLKDIV_CPU 0
+#define CFG_CLKDIV_HSB 1
+#define CFG_CLKDIV_PBA 2
+#define CFG_CLKDIV_PBB 1
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ * icp = PLLOPT<2>
+ * ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CFG_PLL0_OPT 0x04
+
+#define CONFIG_USART1 1
+
+#define CONFIG_HOSTNAME hammerhead
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION 1
+
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_STACKSIZE (2048)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTARGS \
+ "console=ttyS0 root=mtd1 rootfstype=jffs2"
+#define CONFIG_BOOTCOMMAND \
+ "fsload; bootm"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_AUTOBOOT 1
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * After booting the board for the first time, new ethernet address
+ * should be generated and assigned to the environment variables
+ * "ethaddr". This is normally done during production.
+ */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+#define CONFIG_NET_MULTI 1
+
+/*
+ * BOOTP/DHCP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+
+#define CONFIG_ATMEL_USART 1
+#define CONFIG_MACB 1
+#define CONFIG_PIO2 1
+#define CFG_NR_PIOS 5
+#define CFG_HSDRAMC 1
+#define CONFIG_MMC 1
+#define CONFIG_ATMEL_MCI 1
+
+#define CFG_DCACHE_LINESZ 32
+#define CFG_ICACHE_LINESZ 32
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+
+#define CFG_FLASH_BASE 0x00000000
+#define CFG_FLASH_SIZE 0x800000
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 135
+
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+
+#define CFG_INTRAM_BASE 0x24000000
+#define CFG_INTRAM_SIZE 0x8000
+
+#define CFG_SDRAM_BASE 0x10000000
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 65536
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
+
+#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+
+#define CFG_MALLOC_LEN (256*1024)
+
+#define CFG_DMA_ALLOC_LEN (16384)
+
+/* Allow 4MB for the kernel run-time image */
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000)
+#define CFG_BOOTPARAMS_LEN (16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CFG_PROMPT "Hammerhead> "
+#define CFG_CBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP 1
+
+#define CFG_MEMTEST_START CFG_SDRAM_BASE
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000)
+
+#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
#define CONFIG_EXTRA_ENV_SETTINGS \
"unlock=yes\0"
-#define CFG_CMD_JFFS2
+#define CONFIG_CMD_JFFS2
#undef CONFIG_CMD_EEPROM
#define CONFIG_CMD_NET
#define CONFIG_CMD_RUN
}
#endif
+#ifdef CONFIG_SKIP_RELOCATE_UBOOT
+/*
+ * This routine sets the relocation done flag, because even if
+ * relocation is skipped, the flag is used by other generic code.
+ */
+static int reloc_init(void)
+{
+ gd->flags |= GD_FLG_RELOC;
+ return 0;
+}
+#endif
+
/*
* Breathe some life into the board...
*
init_fnc_t *init_sequence[] = {
cpu_init, /* basic cpu dependent setup */
+#if defined(CONFIG_SKIP_RELOCATE_UBOOT)
+ reloc_init, /* Set the relocation done flag, must
+ do this AFTER cpu_init(), but as soon
+ as possible */
+#endif
board_init, /* basic board dependent setup */
interrupt_init, /* set up exceptions */
env_init, /* initialize environment */
if ((s = getenv("bootfile")) != NULL) {
copy_filename(BootFile, s, sizeof(BootFile));
}
-#endif /* CFG_CMD_NET */
+#endif /* CONFIG_CMD_NET */
WATCHDOG_RESET();
WATCHDOG_RESET();
puts("IDE: ");
ide_init();
-#endif /* CFG_CMD_IDE */
+#endif /* CONFIG_CMD_IDE */
#ifdef CONFIG_LAST_STAGE_INIT
WATCHDOG_RESET();
# create symbolic links for common files
# from cpu directory
-$(obj)44x_spd_ddr2.c: ecc.h
+$(obj)44x_spd_ddr2.c: $(obj)ecc.h
@rm -f $(obj)44x_spd_ddr2.c
ln -s $(SRCTREE)/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c
projects / karo-tx-uboot.git / commitdiff