arm: mx6: ddr: add pd_fast_exit flag to system information

DDR3 has a special Precharge power-down mode: fast-exit vs slow-exit.

In slow-exit mode the DLL is off but in some quiescent state that makes it easy
to turn on again in tXPDLL cycles (about 10tCK) vs the full tDLLK (512tCK).
In fast-exist mode the DLL is maintained such that it is ready again in about
3tCK.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index bd89e63e0f78407641c3ba24ed2d8c522490657a..b3031e9a9d97749b583bd9fefaf36199399022f2 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -514,17 +514,21 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
                /* MR2 */
                val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
                      ((tcwl - 3) & 3) << 3;
+               debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
                mmdc0->mdscr = MR(val, 2, 3, cs);
                /* MR3 */
+               debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
                mmdc0->mdscr = MR(0, 3, 3, cs);
                /* MR1 */
                val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
                      ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
+               debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
                mmdc0->mdscr = MR(val, 1, 3, cs);
                /* MR0 */
                val = ((tcl - 1) << 4) |        /* CAS */
                      (1 << 8)   |              /* DLL Reset */
                      ((twr - 3) << 9);         /* Write Recovery */
+               debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
                mmdc0->mdscr = MR(val, 0, 3, cs);
                /* ZQ calibration */
                val = (1 << 10);
@@ -535,10 +539,11 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
        mmdc0->mdpdc = (tcke & 0x7) << 16 |
                        5            << 12 |  /* PWDT_1: 256 cycles */
                        5            <<  8 |  /* PWDT_0: 256 cycles */
-                       1            <<  7 |  /* SLOW_PD */
                        1            <<  6 |  /* BOTH_CS_PD */
                        (tcksrx & 0x7) << 3 |
                        (tcksre & 0x7);
+       if (!sysinfo->pd_fast_exit)
+               mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
        mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
 
        /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */

diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index aeb9ef62b0e53ab702278be112211de5ffcb5909..6eaff95ad0e010745c88d406a58e46e57550fef8 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -250,6 +250,7 @@ struct mx6_ddr_sysinfo {
        u8 mif3_mode;   /* Command prediction working mode */
        u8 rst_to_cke;  /* Time from SDE enable to CKE rise */
        u8 sde_to_rst;  /* Time from SDE enable until DDR reset# is high */
+       u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
 };
 
 /*