cscope.*
# tags files
+/tags
/ctags
/etags
+commit 9689ddcca6e01f3637b4442fa8575f29ef4d7aa3
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Jul 27 10:06:39 2009 +0200
+
+ cpu/arm920t/start.S: include <common.h> to have ROUND() defined
+
+ Commit fcd3c87e made include/common.h usable by assembler code but
+ failed to update cpu/arm920t/start.S
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit c9ed38cb6de50fdb4aaa60b668c555002903b211
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Jul 27 10:01:11 2009 +0200
+
+ at91cap9adk: fix #ifdef/#endif pairing (2nd try)
+
+ Commit 7024aa14 was supposed to fix the #ifdef/#endif pairing in
+ include/configs/at91cap9adk.h, but did not cate all problems.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit fb364bec5f29164d3ee681fcd9d187be8435db12
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Jul 27 09:58:14 2009 +0200
+
+ Fix include/common.h for boards with CONFIG_STATUS_LED
+
+ The reordering of include/common.h by commit fcd3c87e495f3c48 broke
+ boards with status LED support, resulting in
+ error: #error Status LED configuration missing
+ errors. Undo this reordering to avoid this issue.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 942828a0980b3cea7db698784cc7f6a3e7740b2b
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Jul 27 09:19:15 2009 +0200
+
+ ABI: fix build problems due to now needed div64 routine.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 85d6bf0bdc8ccad2d67a9160472f6f8c6bb482fb
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Jul 27 08:50:59 2009 +0200
+
+ PMC405DE: fix out of tree building
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 10c7604d021949464b1e4ba903df95e6b2f0d2ff
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Jul 27 00:24:55 2009 +0200
+
+ Prepare 2009.08-rc1
+
+ Update CHANGELOG, minor coding style fix.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit fafbb2c3e4b35b60ca303ed2ad1c6cf400cd9a22
+Author: rhabarber1848@web.de <rhabarber1848@web.de>
+Date: Fri Jul 24 08:16:30 2009 +0200
+
+ add WATCHDOG_RESET to allow LZMA kernel decompression on slow machines
+
+ Signed-off-by: rhabarber1848@web.de
+
+commit 3c972849f2becbf19c13a24f090d293f37ecf616
+Author: Niklaus Giger <niklaus.giger@member.fsf.org>
+Date: Thu Jul 23 23:31:58 2009 +0200
+
+ Less verbose output when loading vxworks 6.x images
+
+ Loading vxWorks 5.x images resulted just into 3 or 4 lines of output.
+ With vxWorks 6.x and the new GCC it emits about 30 lines, which is
+ far too noisy in my opinion.
+
+ Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
+
+commit fcd3c87e495f3c48b70c919869fb1e0b93d4880b
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri Jul 24 00:17:48 2009 +0200
+
+ Make include/common.h usable by assembler code
+
+ Commit 70ebf316 factored out the ROUND() macro into include/common.h,
+ not realizing that the primary use of this macro on AT91 systems was
+ in start.S where common.h was not included, and could not be included
+ because it contains a lot of C code which the assembler doesn't
+ understand.
+
+ This patch wraps such code in common.h in a "#ifndef __ASSEMBLY__"
+ construct, and then adds an include to cpu/arm926ejs/start.S thus
+ solving the problem.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit deec15b3064d3bb0189aede3c2921fd7ee401a0f
+Author: Heiko Schocher <heiko.schocher@invitel.hu>
+Date: Thu Jul 23 13:27:04 2009 +0200
+
+ arm: add _lshrdi3.S
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 52b1bf2c5cd2f8af880dab503d0039b35570665b
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Jul 23 13:15:59 2009 +0200
+
+ Make linking against libgcc configurable
+
+ Many (especially ARM) tool chains seem to come with broken or
+ otherwise unusable (for the purposes of builing U-Boot) run-time
+ support libraries `libgcc.a'. By using the "USE_PRIVATE_LIBGCC"
+ setting we allow to use alternative libraries instead.
+
+ "USE_PRIVATE_LIBGCC" can either be set as an environment variable in
+ the shell, or as a command line argument when running "make", i. e.
+ $ make USE_PRIVATE_LIBGCC=yes
+ or
+ $ USE_PRIVATE_LIBGCC=yes
+ $ export USE_PRIVATE_LIBGCC
+ $ make
+
+ The value of "USE_PRIVATE_LIBGCC" is the name of the directory which
+ contains the alternative run-time support library `libgcc.a'. The
+ special value "yes" selects the directory $(OBJTREE)/lib_$(ARCH) .
+
+ Note that not all architectures provide an alternative `libgcc.a' in
+ their lib_$(ARCH) directories - so far, only ARM does.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Cc: Prafulla Wadaskar <prafulla@marvell.com>
+ cc: Stefan Roese <sr@denx.de>
+
+commit 479105065d965121f57b55dcfe83a940cba46ac1
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Wed Jul 22 17:51:56 2009 +0200
+
+ Use do_div from div64.h for vsprintf
+
+ Use do_div from div64.h for vsprintf in case of 64bit division.
+ For 32bit division, do_div from div64.h can't be used as it
+ needs a 64bit parameter.
+
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+ Acked-by: Stefan Roese <sr@denx.de>
+ CC: Simon Kagstrom <simon.kagstrom@netinsight.net>
+
+commit 48287792384a93d77d43aaaa1c06cac275bbe1bb
+Author: Kyungmin Park <kmpark@infradead.org>
+Date: Mon Jul 20 09:47:47 2009 +0900
+
+ Fix compiler warnings after loff_t change
+
+ Now 'env_addr' type is loff_t so use correct field type.
+
+ Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit 9c67352f727a5b5eff531c852f9cff59fcb17f7f
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jul 26 23:28:02 2009 +0200
+
+ Revert "ppc: Unlock cache-as-ram in a consistent manner"
+
+ This reverts commit 982adfc610669482a32127282fe489857a92cfe3.
+
+ This patch causes problems on MPC83xx boards - flash recognition stops
+ working.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 35cf3b57eafe3ee1f693e24267e0ecfefab60251
+Author: Jens Scharsig <esw@bus-elektronik.de>
+Date: Fri Jul 24 10:31:48 2009 +0200
+
+ update the EB+MCF-EV123 board support
+
+ This patch updates the support for EB+MCF-EV123 board and needs
+ the [PATCH 1/2 V3] new video driver for bus vcxk framebuffers
+
+ * remove the board framebuffer driver
+ * use the common bus_vcxk framebuffer driver
+ * adds bmp support
+ * adds splashimage support
+ * fix serveral cosmetical errors
+
+ Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
+ [agust@denx.de: fixed some style issues before applying]
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 04538cdb752eeea8fd23cf7ac3394439f189fb77
+Author: Anatolij Gustschin <agust@denx.de>
+Date: Sun Jul 26 12:05:25 2009 +0200
+
+ video: bus_vcxk.c: fix style issues added by 50217dee
+
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 50217deeb07911d686790d34d468eb9a5245f68d
+Author: Jens Scharsig <esw@bus-elektronik.de>
+Date: Fri Jul 24 10:09:02 2009 +0200
+
+ new video driver for bus vcxk framebuffers
+
+ This patch adds a new video driver
+
+ * adds common bus_vcxk framebuffer driver
+
+ Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
+ [agust@denx.de: fixed lots of style issues before applying]
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 60e97419246d0a3615758ad6af40680aefb5f7f1
+Author: Alessandro Rubini <rubini@gnudd.com>
+Date: Tue Jul 21 14:09:45 2009 +0200
+
+ lcd.h: define extern vidinfo_t for all cases
+
+ include/lcd.h has different vidinfo for different platforms,
+ and several extern declaration, but one for the default case was
+ missing. This makes them a single extern declaration for everyone.
+
+ Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
+
+commit bcf0b5248952c6b03081dc5cc4ff9e0b2299c5fa
+Author: Anatolij Gustschin <agust@denx.de>
+Date: Sun Jul 26 11:04:59 2009 +0200
+
+ mimc200.c: fix too long lines added by f68378d6
+
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit f68378d60a905d43155f2e89bf81999d3c93a90a
+Author: Mark Jackson <mpfj-list@mimc.co.uk>
+Date: Tue Jul 21 11:35:22 2009 +0100
+
+ Add LCD support to MIMC200 board
+
+ This patch updates the MIMC200 files to enable the LCD.
+
+ Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
+
+commit 69f32e6c24d41fcdf347ff64e9c13b25059ace58
+Author: Mark Jackson <mpfj-list@mimc.co.uk>
+Date: Tue Jul 21 11:18:44 2009 +0100
+
+ Add 16bit colour support in lcd.h
+
+ This patch adds support for LCD_COLOR16 in include/lcd.h.
+
+ Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
+
+commit bdc873ea063b8cc6d44c6ab748b7723a97d8d7b3
+Author: Anatolij Gustschin <agust@denx.de>
+Date: Sun Jul 26 10:34:58 2009 +0200
+
+ lib_avr32/board.c: fix too long line added by 716ece1d
+
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 716ece1de9a7d43a61d8698ac41b71b64f66f9e9
+Author: Mark Jackson <mpfj-list@mimc.co.uk>
+Date: Tue Jul 21 11:11:37 2009 +0100
+
+ Add AVR32 LCD support
+
+ This patch adds support for the AVR32 LCD controller. This patch is
+ based off the latest u-boot-video.
+
+ A quick summary of what's going on:-
+
+ Enable LCDC pixel clock
+ Enable LCDC port pins
+ Add framebuffer pointer to global_data struct
+ Allocate framebuffer
+
+ To use the new code, update your board config to include something like
+ this:-
+
+ #define CONFIG_LCD 1
+
+ #if defined(CONFIG_LCD)
+ #define CONFIG_CMD_BMP
+ #define CONFIG_ATMEL_LCD 1
+ #define LCD_BPP LCD_COLOR16
+ #define CONFIG_BMP_16BPP 1
+ #define CONFIG_FB_ADDR 0x10600000
+ #define CONFIG_WHITE_ON_BLACK 1
+ #define CONFIG_VIDEO_BMP_GZIP 1
+ #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE 262144
+ #define CONFIG_ATMEL_LCD_BGR555 1
+ #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+ #define CONFIG_SPLASH_SCREEN 1
+ #endif
+
+ The standard U-Boot BMP and Splash-screen features should just work.
+
+ Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
+ [agust@denx.de: fixed some style issues]
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 6111722a9281c6e04a7304d502556afff6a5a1f8
+Author: Alessandro Rubini <rubini@gnudd.com>
+Date: Sun Jul 19 17:52:27 2009 +0200
+
+ video: move extern declarations from C to headers
+
+ This moves some extern declaration from lcd.c to lcd.h, removing
+ unneeded ifdef around a pair of them. Additionally, since
+ gunzip_bmp() was declared static in cmd_bmp.c but extern in lcd.c, I
+ removed the static. The extra "#include <lcd.h>" in cmd_bmp.c is
+ added to ensure the header is consistent with the source.
+
+ This has been compile-tested on both ARM (at91 boards) and PowerPC
+ (HH405_config, TQM823L_LCD_config, mcc200_config), to test all use
+ combinations.
+
+ Signed-off-by: Alessandro Rubini <rubini@gnudd.it>
+ [agust@denx.de: removed gunzip_bmp() fixes as commit c01171ea did it]
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit f51e001143c58447eb50e7aefa2b09eb4cc1410c
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Jul 23 16:26:58 2009 -0400
+
+ Blackfin: restore EVT1 handling in linker script
+
+ Sadly, the Blackfin linker script unification lost a small #ifdef logic
+ needed on older parts. Restore that CONFIG_BFIN_BOOTROM_USES_EVT1 logic.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit f33b325af666b12eafa9ab235b2cd59832d6e51c
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri Jul 24 14:24:07 2009 +0200
+
+ Revert "zlib: updated to v.1.2.3"
+
+ This reverts commit b201171f2b4d509f3ad510b214bee70ff902e3d6.
+
+ The commit caused problems for example when unpacking kernel images:
+
+ Uncompressing Kernel Image ... Error: inflate() returned -2
+ GUNZIP: uncompress, out-of-mem or overwrite error - must
+ RESET board to recover
+
+ Conflicts:
+
+ include/u-boot/zlib.h
+ lib_generic/zlib.c
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 4b1389e0ceb19e9b50b96fd3908483a6c2274fb0
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Jul 21 14:06:29 2009 +0200
+
+ ppc4xx: Add chip_config command to AMCC Kilauea eval board
+
+ This patch removes the "alterpll" command and replaces it with the now
+ ppc4xx standard "chip_config" command to configure the I2C bootstrap
+ EEPROM.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f6af8ce0c80327cb6aaa347642026ad838335c23
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Jul 21 14:33:52 2009 +0200
+
+ ppc4xx: Fix EEPROM configuration on Kilauea
+
+ Kilauea has an AT24C02 EEPROM which has an 8 byte page. Without defining
+ CONFIG_SYS_EEPROM_PAGE_WRITE_BITS to 3 the "eeprom" command doesn't
+ work correctly.
+
+ Additionally the page write delay (CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
+ is set to a more defensive value of 10ms.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 99d8b23bc7e2be04fcbf49c5cec9f5ae76df290c
+Author: Matthias Fuchs <matthias.fuchs@esd.eu>
+Date: Wed Jul 22 13:56:21 2009 +0200
+
+ ppc4xx: Add 405EP based PMC405DE board
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit da799f66ad1d4fc36dd20cc2d7e584493fda8546
+Author: Matthias Fuchs <matthias.fuchs@esd.eu>
+Date: Mon Jul 20 12:15:38 2009 +0200
+
+ ppc4xx: Add struct for 4xx GPIO controller registers
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 58ea142fb2e969f32306c8da1dabfaebd6fa141a
+Author: Matthias Fuchs <matthias.fuchs@esd.eu>
+Date: Wed Jul 22 17:27:56 2009 +0200
+
+ ppc4xx: Replace 4xx lowercase SPR references
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 87c0b72908e05662b8b415e26e1042f4779629da
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Jul 20 06:57:27 2009 +0200
+
+ Add "chip_config" command for PPC4xx bootstrap configuration
+
+ This patch adds a generic command for programming I2C bootstrap
+ eeproms on PPC4xx. An implementation for Canyonlands board is
+ included.
+
+ The command name is intentionally chosen not to be PPC4xx specific.
+ This way other CPU's/SoC's can implement a similar command under
+ the same name, perhaps with a different syntax.
+
+ Usage on Canyonlands:
+
+ => chip_config
+ Available configurations (I2C address 0x52):
+ 600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100
+ 600-nand - NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100
+ 800-nor - NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100
+ 800-nand - NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100
+ 1000-nor - NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100
+ 1000-nand - NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100
+ 1066-nor - NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88 ***
+ 1066-nand - NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88
+ => chip_config 600-nor
+ Using configuration:
+ 600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100
+ done (dump via 'i2c md 52 0.1 10')
+ Reset the board for the changes to take effect
+
+ Other 4xx boards will be migrated to use this command soon
+ as well.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Signed-off-by: Dirk Eibach <eibach@gdsys.de>
+ Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+
+commit 10c1b218556ed9871f36bc0c407f4f2f6196353b
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 19:01:16 2009 -0500
+
+ xpedite1k: Move to X-ES vendor directory
+
+ The XPedite1000 is an X-ES product thus it can be put in board/xes along
+ with other X-ES boards. Along with the move, the board was renamed to
+ XPedite1000 from XPedite1K to fit X-ES's standard naming convention.
+ Maintainership was also transfered to Peter Tyser.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 54381b79d268e1bead5d78ed8423df31a3cb0e2c
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 19:01:15 2009 -0500
+
+ xpedite1k: Sync checkboard() with other X-ES boards
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 9b4ef1f5dc0daab64f46249a32e67279c4d44fd2
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 19:01:14 2009 -0500
+
+ xpedite1k: Sync up board config options with other X-ES boards
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 4cdad5f43ae67e4ceeac69ef4af4392bd2f7381f
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 19:01:13 2009 -0500
+
+ xpedite1k: Sync organization of board config with other X-ES boards
+
+ This change should have no functional effect
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c4ae1a0257a0f5008ee2686e8aa92fba3992f279
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 19:01:12 2009 -0500
+
+ xpedite1k: Sync up commands and environment with other X-ES boards
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit fbc7951ea84c2fe6da0f6007b672ed35bae91acb
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 19:01:11 2009 -0500
+
+ xpedite1k: Disable unused ethernet port 1
+
+ The XPedite1000 only has 2 available ethernet ports:
+ ppc_4xx_eth2 (EMAC2) and ppc_4xx_eth3 (EMAC3)
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 767e32ad369d83f55f950e6938e68b6dba7fa65f
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 19:01:10 2009 -0500
+
+ xpedite1k: Store environment in flash
+
+ Previously an I2C EEPROM was used. The EEPROM had size, reliability,
+ and access issues which are resolved by storing the environment in
+ flash.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit b88da157f9990cd2cb081e4faea4b9581b5d0e2f
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 19:01:09 2009 -0500
+
+ xpedite1k: Add support for additional GPIO pins
+
+ Enable GPIO pins for an I2C EEPROM write protect, a system reset pin,
+ and a PMC #MONARCH pin. These pins are not currently used in U-Boot,
+ but are used in OSes and may be used in U-Boot in the future.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 42735815dd9ba39efe51203868aebce04053c8de
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 19:01:08 2009 -0500
+
+ xpedite1k: Add support for optional flashes
+
+ The XPedite1000 can be built with 4 total flashes:
+ - 512KB AMD socketed
+ - 16MB Intel soldered
+ - 2 x 32MB AMD MirrorBit flashes
+
+ Add support for the optional 2 32MB CFI-compliant AMD flashes
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e02990764c7415c84668823a0fc8c5b4dd8d8cf0
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 19:01:07 2009 -0500
+
+ xpedite1k: Cleanup coding style
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 086ff34a3a7e5e595630d658c1c13778399452d1
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 19:01:06 2009 -0500
+
+ xpedite1k: Remove support for reading MACs from EEPROM
+
+ By default, the XPedite1000 comes installed with xMon, a proprietary
+ bootloader. xMon stores its MAC address in an onboard EEPROM. Rather
+ than requiring a non-standard location in the EEPROM to be reserved for
+ MAC addresses, store the MAC addresses in U-Boot's standard environment.
+ A U-Boot application or OS application can be used to migrate xMon MAC
+ addresses to U-Boot's environment if necessary.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 108d6d0099372f9f6532c3198fbaacabc121c9b3
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 19:01:05 2009 -0500
+
+ xpedite1k: Remove support for fixed SDRAM configuration
+
+ All XPedite1000's have SPD EEPROMs present and no fixed configuration
+ parameters are currently defined or used
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c86d00a2ed923002f1ab0bfb0a925522628302e9
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 19:01:04 2009 -0500
+
+ xpedite1k: Remove CONFIG_SYS_DRAM_TEST support
+
+ POST or command line tests provide similar functionality
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 11ad309c183b176d8866944026a63c0f1c626f56
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 19:01:03 2009 -0500
+
+ xpedite1k: Use standard CFI flash driver
+
+ Using the CFI flash driver will allow write access to the 16MB Intel
+ StrataFlash present on the XPedite1000. The 512KB socketed (non
+ CFI-compliant flash) will no longer be writable.
+
+ The mapping of the 16MB Strata flash was moved to 0xff000000 and the
+ 512KB AMD socketed flash was moved to 0xfe000000.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit d4d2e79bb433fc7ec18c68cc49cc6b7433d1320c
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Thu Jul 16 22:13:57 2009 +0200
+
+ ppc4xx: Cleanup PLU405 board code
+
+ Some Coding style cleanup (braces, whitespaces, long lines)
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit b209a114829dc8a7a0e39a9335b6e4aebf9742cb
+Author: Dirk Eibach <eibach@gdsys.de>
+Date: Fri Jul 17 14:16:40 2009 +0200
+
+ ppc4xx: Add DL-Vision 405EP board support
+
+ Board support for the Guntermann & Drunck DL-Vision.
+
+ Signed-off-by: Dirk Eibach <eibach@gdsys.de>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 9b1b8c8a1bf52e9b65e1958e5205838576066cbc
+Author: Dirk Eibach <eibach@gdsys.de>
+Date: Fri Jul 10 14:47:32 2009 +0200
+
+ ppc4xx: Fix missing freqOPB for 405EP
+
+ In cpu/ppc4xx/speed.c initialization of sysInfo->freqOPB for 405EP was
+ left out for no obvious reason.
+
+ Signed-off-by: Dirk Eibach <eibach@gdsys.de>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 0a371ca08908c9b2a58171223a79bffea1f7c6f5
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Jul 14 15:53:08 2009 +0200
+
+ ppc4xx: Fix TLB reset problem with recent 44x images
+
+ Patch d873133f [ppc4xx: Add Sequoia RAM-booting target] broke "normal"
+ booting on some 44x platforms. This breakage is only noticed in some
+ cases while powercycling. As it seems, the code in question in start.S
+ didn't invalidate TLB #0. This makes sense since this TLB is used for
+ the bootrom mapping. With the patch mentioned above even TLB #0 got
+ invalidated resulting in an error later on.
+
+ This patch now fixes this issue by only invalidating TLB #0 in the RAM-
+ booting case.
+
+ Tested succesfully on Sequoia and Canyonlands.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Dirk Eibach <Eibach@gdsys.de>
+
+commit 44259bb9e696d22bf1773181111855a29f00cf33
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Fri Jul 17 19:56:30 2009 +0530
+
+ usb: bugfix driver/usb/host/ehci-hcd.c function ehci_submit_root
+
+ This change is cheked in Linux source and fix found to be in sync.
+ This patch is tested for USB host interface on Kirkwood based
+ Sheevaplug platform (ARM little endian board)
+
+ Risk: the impact of this patch is not validated on big endian board.
+ This need to be checked...
+
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 28958b8bea4c66629c5a22fd3c8b0d49df90383d
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Jul 23 22:23:23 2009 +0200
+
+ Coding Style cleanup; update CHANGELOG.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 2632c008e2c2cd61fefb622ed671ea3e6bd2e2a6
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Tue Jul 21 22:59:36 2009 -0400
+
+ autoconf.mk: include before config.mk for top level files
+
+ By including autoconf.mk before config.mk, all top level files can use any
+ config options it sets up (like <arch>_config.mk) or the Makefile itself
+ without being forced to use lazy evaluation.
+
+commit c01171eaecc963d2c1f56a0984a0cbcdd8a3ab3c
+Author: Mark Jackson <mpfj-list@mimc.co.uk>
+Date: Tue Jul 21 11:30:53 2009 +0100
+
+ Remove static declaration from gunzip_bmp()
+
+ This patch removes the static declaration from gunzip_bmp()
+
+ Without it, the gunzip_bmp() function is not visible to
+ common/lcd.c and fails to compile with an error.
+
+ Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
+
+commit 2d4a43e230a3c8bfd03b9beaa0eb2a95e779c03b
+Author: Peter Tyser <ptyser@gmail.com>
+Date: Mon Jul 20 21:51:38 2009 -0500
+
+ cmd_tsi148: General cleanup
+
+ - Fix command help message
+ - Disable DEBUG by default
+ - Fix whitespace issues
+ - Fix lines > 80 characters
+
+ Signed-off-by: Peter Tyser <ptyser@gmail.com>
+ Acked-by: Stefan Roese <sr@denx.de>
+
+commit 9aef73888509d10193615ee5cd9cf439ca44e937
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Jul 19 15:17:03 2009 -0400
+
+ unify HOST_CFLAGS and HOSTCFLAGS
+
+ The top build system sets up HOSTCFLAGS a bit and exports it, but other
+ places use HOST_CFLAGS instead. Unify the two as HOSTCFLAGS so that the
+ values stay in sync.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 2e9393f500065f940e5e4ac7fe375e4c0b77b936
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Jul 23 21:16:59 2009 +0200
+
+ Update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit e3b39f84e974df70065fa248f0f63993b1708c9d
+Author: André Schwarz <andre.schwarz@matrix-vision.de>
+Date: Fri Jul 17 14:50:24 2009 +0200
+
+ update config for mvBC-P (MPC5200)
+
+ This patch adds I2C support for mvBC-P and defines flash layout
+ matching the shipped product.
+
+ Signed-off-by: André Schwarz <andre.schwarz@matrix-vision.de>
+
+commit cb6d0b72c2c4f13c0075a7ae92e11682ec94a311
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Mon Jul 13 09:24:00 2009 -0500
+
+ ahci: Fix gcc 4.4 compiler warning
+
+ ahci.c: In function 'ata_scsiop_read_capacity10':
+ ahci.c:616: warning: dereferencing type-punned pointer will break strict-aliasing rules
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 51d91e1a253c97713c7f3e5c0b910a4db4979283
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Mon Jul 13 09:23:59 2009 -0500
+
+ drivers/bios_emulator: Fix gcc 4.4 compiler warning
+
+ biosemu.c: In function 'BE_setVGA':
+ biosemu.c:147: warning: dereferencing type-punned pointer will break strict-aliasing rules
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit f97ec30bb3c5a4a456159eb2b75b3bc68772bf2a
+Author: Detlev Zundel <dzu@denx.de>
+Date: Mon Jul 13 16:01:19 2009 +0200
+
+ Re-add support for image type 'Standalone Program'
+
+ Support for this type was lost during the bootm refactoring.
+
+ Signed-off-by: Detlev Zundel <dzu@denx.de>
+
+commit ca95c9df0280f40e8e4befadbaae21fa67d92331
+Author: Detlev Zundel <dzu@denx.de>
+Date: Mon Jul 13 16:01:18 2009 +0200
+
+ Add error checking for unsupported OS types.
+
+ Signed-off-by: Detlev Zundel <dzu@denx.de>
+
+commit 982adfc610669482a32127282fe489857a92cfe3
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 10 18:46:10 2009 -0500
+
+ ppc: Unlock cache-as-ram in a consistent manner
+
+ Previously, non-e500 architectures only unlocked their data cache which
+ was used as early RAM when booting to Linux using the "bootm" command.
+ This change causes all PPC boards with CONFIG_SYS_INIT_RAM_LOCK defined
+ to unlock their data cache during U-Boot's initialization. This
+ improves U-Boot performance and provides a common cache state when
+ booting to different OSes.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit b201171f2b4d509f3ad510b214bee70ff902e3d6
+Author: Giuseppe CONDORELLI <giuseppe.condorelli@st.com>
+Date: Thu Jul 23 04:54:45 2009 -0400
+
+ zlib: updated to v.1.2.3
+
+ This patch updates zlib to the latest stable version.
+
+ Only relevant zlib parts were ported to u-boot tree, as was done for
+ the previously used version of zlib (0.95). New zlib gives faster
+ inflate performance and other improvements, see www.zlib.net
+
+ Signed-off-by: Giuseppe Condorelli <giuseppe.condorelli@st.com>
+ Reviewed-by: Angelo Castello <angelo.castello@st.com>
+
+ Edited commit message
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 97cfe86163505ea18e7ff7b71e78df5bb03dad57
+Author: Robin Getz <rgetz@blackfin.uclinux.org>
+Date: Tue Jul 21 12:15:28 2009 -0400
+
+ Save server's MAC address in environment
+
+ Linux's netconsole works much better when you can pass it the MAC address of
+ the server. (otherwise it just uses broadcast, which everyone else on my
+ network complains about :)
+
+ This sets the env var "serveraddr" (to match ethaddr), so that you can pass
+ it to linux with whatever bootargs you want to....
+
+ addnetconsole=set bootargs $(bootargs) netconsole=@$(ipaddr)/eth0,@$(serverip)/$(serveraddr)
+
+ Signed-of-by: Robin Getz <rgetz@blackfin.uclinux.org>
+
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 0b23fb368d08c9669fac647971ff249c3f9fee8f
+Author: Ilya Yanok <yanok@emcraft.com>
+Date: Tue Jul 21 19:32:21 2009 +0400
+
+ fec_mxc: driver for FEC ethernet controller on i.MX27
+
+ Signed-off-by: Ilya Yanok <yanok@emcraft.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 0544c63681d2ea3607faf374e9c56f101e365b42
+Author: Alessio Centazzo <centazzo@gmail.com>
+Date: Sat Jul 11 11:56:06 2009 -0700
+
+ ppc4xx: Fixed compilation warning in 4xx_enet.c
+
+ This patch fixes a compilation warning for some Ethernet PHY-less
+ PPC4xx platforms (440SPE based ones) and a potential compilation
+ error for 440SP platforms (use of undefined 'ethgroup' variable).
+ In the original code and in case of 440SPE platforms, 'ethgroup'
+ is initialized to -1 and never modified. Later in the function,
+ within an #ifdef statement, an 'if statement' executes code only
+ if 'ethgroup' is set to 4, therefore it is harmless to avoid
+ executing the 'if statement' by removing the CONFIG_440SPE from
+ the affected #ifdefs. In case of 440SP platforms with on-board
+ Ethernet PHY, 'ethgroup' is undefined but used (there are not such
+ platforms in the repository yet). All other architectures are not
+ affected by this change.
+
+ Signed-off-by: Alessio Centazzo acpatin@yahoo.com
+ Acked-by: Stefan Roese <sr@denx.de>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 09133f8580f0106429ba3600f1855bd3577ae58b
+Author: Michael Zaidman <michael.zaidman@gmail.com>
+Date: Tue Jul 14 23:37:12 2009 +0300
+
+ DHCP regression on 2009-06
+
+ Fixed the DHCP/BOOTP/RARP regression introduced in u-boot-2009.06
+ by initializing our IP addr to 0 in order to accept any IP addr
+ assigned to us by the DHCP/BOOTP/RARP server.
+
+ Ack-by: Robin Getz <rgetz@blackfin.uclinux.org>
+ Signed-off-by: Michael Zaidman <michael.zaidman@gmail.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 443ce4ac9d1138ae5ae6863b2d40a96fd6edf523
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Thu Jul 16 20:58:02 2009 +0530
+
+ net: phy: bugfixes: mv88E61xx multichip addressing support
+
+ With these fixes, this driver works properly for multi chip
+ addressging mode
+
+ Bugfixes:
+ 1. Build error fixed for function mv88e61xx_busychk_multic-fixed
+ 2. PHY dev address error detection- fixed
+ 3. wrong busy bit was refered in function mv88e61xx_busychk -fixed
+ 4. invalid data read ptr was refered for RD_PHY in case of
+ multichip addressing mode -fixed
+
+ The Multichip Address mode is tested with RD6281A board having
+ MV88E6165 switch on it
+
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 16025ea45539219f2a7c750c6f0ae983ea5c2737
+Author: Simon Kagstrom <simon.kagstrom@netinsight.net>
+Date: Wed Jul 8 13:05:11 2009 +0200
+
+ arm: Kirkwood: Check the error summary bit for error detection
+
+ The Marvell documentation for the 88f6281 states that the error coding
+ is only valid if the error summary and last frame bits in the transmit
+ descriptor status field are set. This patch adds checks for these for
+ transmit (I would get transmit errors on bootp with the current check,
+ which I believe are spurious).
+
+ Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 7b05f5e027b81cd3a9a41c6c6d3fe09c72fa93f6
+Author: Simon Kagstrom <simon.kagstrom@netinsight.net>
+Date: Wed Jul 8 13:03:18 2009 +0200
+
+ arm: Kirkwood: Fix compiler optimization bug for kwgbe_send
+
+ kwgbe_send/recv both have loops waiting for the hardware to set a bit.
+ GCC 4.3.3 cleverly optimizes the send case to ... a while(1); loop. This
+ patch uses readl to force a read from device memory. Other volatile
+ accesses have also been replaced with readl/writel where appropriate
+ (as per suggestions on the U-boot mailing list).
+
+ Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 3f6b18ffd94621625de961bc566022b0266790f5
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date: Thu Jul 2 13:21:22 2009 -0400
+
+ MIIPHYBB: Return 0xFFFF if the PHY is not asserting TA.
+
+ This patch sets the returned value to 0xFFFF if the PHY does not exist
+ and does not assert Transfer Acknowledge. A NULL check for the value
+ pointer is also added for buffer overflow protection.
+
+ Without this patch 'mii info' will show 'phantom' devices because the
+ value will be not be initialized and return with some random value.
+
+ Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 736fead8fdbf8a8407048bebc373cd551d01ec98
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date: Mon Jul 20 22:01:11 2009 -0700
+
+ Convert SMC911X Ethernet driver to CONFIG_NET_MULTI API
+
+ All in-tree boards that use this controller have CONFIG_NET_MULTI added
+ Also:
+ - changed CONFIG_DRIVER_SMC911X* to CONFIG_SMC911X*
+ - cleaned up line lengths
+ - modified all boards that override weak function in this driver
+ - added
+
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+ Tested-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 3bd0a877b74b9c005ae7cb892480ccedfa308c20
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date: Fri Jul 17 00:50:15 2009 -0700
+
+ Add warning about upcoming removal of old Ethernet API
+
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit b7fe25d2a8d1cede401d09e1f9c84f8fe47bdbb1
+Author: Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Date: Thu Jul 2 16:15:13 2009 +0530
+
+ P2020RDB Added support of Vitesse PHYs VSC8641(RGMII) and VSC8221(SGMII)
+
+ These PHYs are on P2020RDB platform.
+
+ Also revamped Freescale copyright message in drivers/net/tsec.c.
+
+ Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 1a32bf41881b5dbe3119cb77a33572b4d462cabf
+Author: Robin Getz <rgetz@blackfin.uclinux.org>
+Date: Mon Jul 20 14:53:54 2009 -0400
+
+ Add DNS support
+
+ On 04 Oct 2008 Pieter posted a dns implementation for U-Boot.
+
+ http://www.mail-archive.com/u-boot-users@lists.sourceforge.net/msg10216.html
+ >
+ > DNS can be enabled by setting CFG_CMD_DNS. After performing a query,
+ > the serverip environment var is updated.
+ >
+ > Probably there are some cosmetic issues with the patch. Unfortunatly I
+ > do not have the time to correct these. So if anybody else likes DNS
+ > support in U-Boot and has the time, feel free to patch it in the main tree.
+
+ Here it is again - slightly modified & smaller:
+ - update to 2009-06 (Pieter's patch was for U-Boot 1.2.0)
+ - README.dns is added
+ - syntax is changed (now takes a third option, the env var to store
+ the result in)
+ - add a random port() function in net.c
+ - sort Makefile in ./net/Makefile
+ - dns just returns unless a env var is given
+ - run through checkpatch, and clean up style issues
+ - remove packet from stack
+ - cleaned up some comments
+ - failure returns much faster (if server responds, don't wait for
+ timeout)
+ - use built in functions (memcpy) rather than byte copy.
+
+ Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
+ Signed-off-by: Pieter Voorthuijsen <pieter.voorthuijsen@prodrive.nl>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 88ad3fd91c83a4343b25385fd78fd8e29ebb723f
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Fri Jul 17 12:17:00 2009 -0500
+
+ net: tsec - fix dereferencing type-punned pointer will break strict-aliasing rules warning
+
+ fix this gcc 4.4 warning:
+
+ tsec.c: In function 'tsec_init':
+ tsec.c:200: warning: dereferencing type-punned pointer will break strict-aliasing rules
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit d9bec9f42ab34383737c8a94429aa02fe76d7946
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Jul 18 21:04:08 2009 -0400
+
+ net: rename NetRxPkt to NetRxPacket
+
+ The net code is mostly consistent in using 'Packet' rather than 'Pkt', so
+ rename the minor detractor to follow suite.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 88a4c2e77cd5674db745d0c2ebbad68c9baf760c
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date: Thu Jun 25 16:33:04 2009 +0900
+
+ sh: sh_eth: Remove garbage from printf
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 2ea20efa47da9d98ff38223ff51dea5439ad8708
+Author: Andreas Pretzsch <apr@cn-eng.de>
+Date: Thu Jul 9 21:50:05 2009 +0200
+
+ smc911x: add support for LAN9221
+
+ Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 7168eba729b9e6d730db7cd1028767f7b1a6128b
+Author: David Brownell <david-b@pacbell.net>
+Date: Tue Jun 9 11:14:24 2009 -0700
+
+ rm9200 ethernet driver: board-specific quirk (csb337)
+
+ CSB337 boards originally shipped with MicroMonitor, not U-Boot;
+ and with a version using a different convention for recording
+ Ethernet addresses than anyone else. To avoid breaking Linux
+ when it uses U-Boot, have it use the same convention on that
+ hardware.
+
+ Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 57215cd2e59fd403248df8f2f195e382900d5fc2
+Author: Heiko Schocher <hs@denx.de>
+Date: Thu Jul 16 09:58:31 2009 +0200
+
+ arm, kirkwood: added kw_gpio_set_valid() in gpio.h
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit ec16441085f471c03a8c0909579463e31e5b947a
+Author: Dieter Kiermaier <dk-arm-linux@gmx.de>
+Date: Mon Jun 29 14:45:08 2009 +0200
+
+ Kirkwood: add Marvell Kirkwood gpio driver
+
+ Signed-off-by: Dieter Kiermaier <dk-arm-linux@gmx.de>
+ Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
+ Tested-by: Heiko Schocher <hs@denx.de>
+
+commit 688b6a0ff2dcbb0c7e63ef63cbbcc291f14f321f
+Author: Heiko Schocher <hs@denx.de>
+Date: Thu Jul 16 09:59:10 2009 +0200
+
+ arm, kirkwood: added KW_TWSI_BASE in kirkwood.h
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit fbc8365ad7ab0afd4143bdbffab2fd0b24df004f
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Thu Jul 16 21:02:24 2009 +0530
+
+ Marvell RD6281A Board support
+
+ This is Marvell's 88F6281_A0 based reference design board
+
+ This patch is tested for-
+ 1. Boot from DRAM/NAND flash/NFS
+ 2. File transfer using tftp and loadb
+ 3. NAND flash read/write/erase
+
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 2906e6d654fcc7f2451fde225e4e8b3f20c9555f
+Author: Piotr Ziecik <kosmo@semihalf.com>
+Date: Fri Jul 17 16:35:19 2009 +0200
+
+ api: Fix broken build on ARM.
+
+ This patch fixes broken build introduced by commit
+ 84bf7ca522e94ec402a1264b01971b924b7e268f (api: remove un-needed
+ ifdef CONFIG_API already handle by the Makefile).
+
+ Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
+
+commit 48677a1ef5f82adca49145a7baf11ece77f51945
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Jul 22 23:53:23 2009 +0200
+
+ Fix "ld: cannot find -lstubs" build error
+
+ Commit 1bc15386 moved the examples/ to examples/standalone but failed
+ to adapt the Makefiles that need to link against libstubs.a
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit ae71121a111ddf9dd057cacbbdd0f51054be428a
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Jul 18 20:47:36 2009 +0200
+
+ at91cap9adk: fix #ifdef/#endif pairing
+
+ The #ifdef/#endif pairing in this file was obviously messed up.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 6b96a20d512b04a808438553874c00cf40812c44
+Author: Minkyu Kang <mk7.kang@samsung.com>
+Date: Mon Jul 20 11:40:01 2009 +0900
+
+ ARM Cortex A8: Move OMAP3 specific reset handler
+
+ Because of the reset_cpu is soc specific, should be move to soc
+
+ Cc: Dirk Behme <dirk.behme@googlemail.com>
+ Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
+
+commit 048e7efe91f66094f868281c12e488ce2bae8976
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Wed Jul 22 10:12:39 2009 -0500
+
+ 85xx/86xx: Replace in8/out8 with in_8/out_8 on FSL boards
+
+ The pixis code used in8/out8 all over the place. Replace it with
+ in_8/out_8 macros.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 0a6d0c6320b77bd6572393a93e6b8ccdf39c7100
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jul 21 13:51:08 2009 -0500
+
+ xpedite5370: Enable NAND command support
+
+ Use the MPC8572's eLBC to access 1 GB (or greater) onboard NAND flash
+ via the 'nand' command.
+
+ Previously, the XPedite5370's NAND chip selects were properly
+ configured, but NAND support was not enabled.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 39121c0896a6760bd436d88c17892f49a97902d0
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jul 21 13:51:07 2009 -0500
+
+ xes: Increase CONFIG_SYS_BOOTM_LEN to 16MB
+
+ Increasing CONFIG_SYS_BOOTM_LEN from 8 MB to 16 MB is necessary to
+ support uncompressing images larger than 8 MB when using the bootm
+ command.
+
+ Note that recent Linux kernels for the 85xx and 86xx map greater than
+ 16MB of memory on bootup, but we use 16MB to maintain compatibility with
+ older Linux kernels for now.
+
+ Signed-off-by: Nate Case <ncase@xes-inc.com>
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 58f31b602dfd52eb7836ab82caa587514e046f02
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Sun Jul 19 19:17:41 2009 -0500
+
+ xpedite5370: Fix I2C GPIO initialization typo
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Acked-by: Heiko Schocher<hs@denx.de>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 5ff821006c6e7647d183ea95817044943bb22e7e
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Sun Jul 19 19:17:40 2009 -0500
+
+ xpedite5200,5370: Use buffered NOR flash writes
+
+ Buffered writes are possible on the XPedite5200 and XPedite5370 and greatly
+ improve NOR flash write speeds
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit d9c147f371800a479a507a816b2fe572c97da197
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 10:14:48 2009 -0500
+
+ 85xx, 86xx: Add common board_add_ram_info()
+
+ Previously, 85xx and 86xx boards would display DRAM information on
+ bootup such as:
+
+ ...
+ I2C: ready
+ DRAM:
+ Memory controller interleaving enabled: Bank interleaving!
+ 2 GB
+ FLASH: 256 MB
+ ...
+
+ This patch moves the printing of the DRAM controller configuration to a
+ common board_add_ram_info() function which prints out DDR type, width,
+ CAS latency, and ECC mode. It also makes the DDR interleaving
+ information print out in a more sane manner:
+
+ ...
+ I2C: ready
+ DRAM: 2 GB (DDR2, 64-bit, CL=4, ECC on)
+ DDR Controller Interleaving Mode: bank
+ FLASH: 256 MB
+ ...
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 12a440ae6d09445140f1a0c2023dba76a9f1a617
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 10:14:47 2009 -0500
+
+ tqm85xx: Remove board_add_ram_info()
+
+ This is in preparation for adding one common 8xxx board_add_ram_info()
+ function for all 8xxx boards
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit ed2c9488bbe389b7b25cada1e42bdae5d0976327
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 10:14:46 2009 -0500
+
+ xes: Remove 8xxx board_add_ram_info() function
+
+ This is in preparation for adding one common 8xxx board_add_ram_info()
+ fuction for all 8xxx boards
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit e7ee23ec1788d8cf269a4cf6b9cd3722cbc7d592
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 17 10:14:45 2009 -0500
+
+ 86xx: Rename ccsr_ddr's sdram_mode_1, sdram_cfg_1 fields
+
+ Rename sdram_mode_1 to sdram_mode and sdram_cfg_1 to sdram_cfg to match
+ the 86xx user's manual and other Freescale architectures
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit f6155c6fbb1d85f517b7c160570f0995ef14c43f
+Author: Roy Zang <tie-fei.zang@freescale.com>
+Date: Thu Jul 9 10:05:48 2009 +0800
+
+ 85xx: Add pci/pcie E1000 ethernet support for MPC8544DS and MPC8536 boards
+
+ Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 6bb5b412291177e6edd42f9a80e5c5afe57a6a0f
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Tue Jul 14 22:42:01 2009 -0500
+
+ 85xx: Report which "bank" of NOR flash we are booting from on FSL boards
+
+ The p2020DS, MPC8536DS, MPC8572DS, MPC8544DS boards are capable of
+ swizzling the upper address bits of the NOR flash we boot out of which
+ creates the concept of "virtual" banks. This is useful in that we can
+ flash a test of image of u-boot and reset to one of the virtual banks
+ while still maintaining a working image in "bank 0".
+
+ The PIXIS FPGA exposes registers on LBC which we can use to determine
+ which "bank" we are booting out of (as well as setting which bank to
+ boot out of).
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 9af9c6bdc16da53772c56b1a79c2c91701fe94e6
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Wed Jul 15 13:45:00 2009 -0500
+
+ 86xx: Report which "bank" of NOR flash we are booting from on MPC8641HPCN
+
+ The MPC8641HPCN board is capable of swizzling the upper address bit of
+ the NOR flash we boot out of which creates the concept of "virtual"
+ banks. This is useful in that we can flash a test of image of u-boot
+ and reset to one of the virtual banks while still maintaining a
+ working image in "bank 0".
+
+ The PIXIS FPGA exposes registers on LBC which we can use to determine
+ which "bank" we are booting out of (as well as setting which bank to
+ boot out of).
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit caf72ff329759b4da71352ab098537c7698c0e9f
+Author: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
+Date: Tue Jul 21 10:45:49 2009 +0200
+
+ Refresh LZMA-lib to v4.65
+
+ Signed-off-by: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
+
+commit 70ebf31633f372a24505e47846b2628e8435ea37
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri Jul 17 23:35:29 2009 +0200
+
+ AT91: factor out ROUND() macro
+
+ A large number of boards (all AT91 based) duplicated the ROUND()
+ macro in their board specific config files. Add the definition to
+ include/common.h and clean up the board config files.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 89188a62333c0841a7166783d2ebdd39d7044eb2
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Wed Jul 15 08:54:50 2009 -0500
+
+ 85xx: Bump up the BOOTMAP to 16M on FSL 85xx boards
+
+ We have always mapped at least 16M in the kernel and we have seen cases
+ with new kernel features that a kernel image needs more than 8M of
+ memory.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit d4abc757c26c531293f5bbc4262ade44a317eec9
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Mon Jul 20 19:02:21 2009 -0500
+
+ Move api_examples to examples/api
+
+ Also add a rule to remove demo.bin which was previously leftover
+ after a "make clean"
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit af1d7d984a23a0faa1f436ebfeb55c876b1a99e1
+Author: Heiko Schocher <hs@denx.de>
+Date: Tue Jul 21 06:37:28 2009 +0200
+
+ 83xx, kmeter: fix compile error
+
+ CONFIG_SYS_MALLOC_LEN is defined in the board config, and
+ the keymile-common.h, which collects common options used
+ by all keymile-boards. This results in a compile error
+ when compiling the kmeter1 board. So remove this define
+ in the board config file.
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 39df00d9aecfb465b9eec9af593f9b763fb5209a
+Author: Heiko Schocher <hs@denx.de>
+Date: Thu Jul 9 12:04:26 2009 +0200
+
+ i2c, mpc83xx: add CONFIG_SYS_I2C_INIT_BOARD for fsl_i2c
+
+ This patch adds the possibility to call a board specific
+ i2c bus reset routine for the fsl_i2c bus driver, and adds
+ this option for the keymile kmeter1 board.
+
+ The deblock sequence for this board is implemented and
+ tested in the following way:
+
+ CR = 0x20 (release SDA and SCL pin)
+ CR = 0xa0 (start read)
+ dummy read
+ dummy read
+ if 2. dummy read == 0x00
+ 3. dummy read
+
+ CR = 0x80 (SDA and SCL now 1 SR = 0x86)
+ CR = 0x00 (Modul reset SR=0x81)
+ CR = 0x80 (SDA and SCL = 1, SR = 0x81)
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 1bc1538613d66cef3cbce680fc8d7c3561a0fbd0
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 10 11:03:19 2009 -0500
+
+ Move examples/ to examples/standalone
+
+ The current files in examples are all standalone application examples,
+ so put them in their own subdirectory for organizational purposes
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit b220c64d86f7c705a183302c3b50076d7e5d876c
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jul 10 11:03:15 2009 -0500
+
+ Move architecture specific config.mk files into subdirs
+
+ This cleans up U-Boot's toplevel directory a bit and makes the
+ architecture 'config.mk' file naming and location similar to board
+ and cpu 'config.mk' files
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 082becd0d546399637fa94fdf9f1730a0f7bf348
+Author: Po-Yu Chuang <ratbert@faraday-tech.com>
+Date: Fri Jul 10 18:25:34 2009 +0800
+
+ Add "tags" to .gitignore file.
+
+ Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit dc71b248ef0d5e12b19f33c6efb873e31df91fa9
+Author: Heiko Schocher <hs@denx.de>
+Date: Thu Jul 9 12:04:18 2009 +0200
+
+ powerpc: updates for the keymile boards
+
+ - CONFIG_SYS_MAX_I2C_BUS changed to 1
+ We use only one I2C hardwarecontroller on this boards, so
+ change the CONFIG_SYS_MAX_I2C_BUS to 1.
+ - common: dont print errormsg if second IVM Block lacks.
+ - 82xx, mgcoge: fix double mtdpart entry in environment
+ - 82xx, mgcoge: activate on second Flash the second bank.
+ - common: CONFIG_ENV_SIZE 0x4000 for all keymile boards
+ - common: Change malloc size to 1MByte for all Keymile boards
+ We need a bigger malloc area for the environment support (128k)
+ on some Keymile boards (kmeter1) and the upcoming UBI support.
+ Change it to 1MB for all Keymile boards to be on the save side.
+ Also define CONFIG_SYS_64BIT_VSPRINTF which is needed for
+ UBI/UBIFS support.
+ - Add UBI support to all Keymile boards
+ - change manner of writing "/localbus/ranges" node
+ instead of writting the complete "/localbus/ranges" node
+ before booting Linux, only update the ranges entries
+ which gets dynamical detected (size of flashes).
+ This is needed, because keymile adds in the DTS
+ "/localbus/ranges" node entries, which u-boot must
+ not overwrite/delete.
+ - kmeter, mgcoge: define 2 seperate regions needed for the Intel P30 chips
+ The Intel P30 chip has 2 non-identical chips on
+ one die, so we need to define 2 seperate regions
+ that are scanned by physmap_of independantly.
+ - kmeter1: Add MTD concat support to Keymile boards
+ - 82xx, mgcoge: add "unlock=yes" to default environment
+ - added CONFIG_MTD_DEVICE to get in sync with mainline code
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f14d81050a9e0fa57aedb1bc746c60a07c1ad67f
+Author: galak <galak@ducky.am.freescale.net>
+Date: Tue Jul 7 15:53:21 2009 -0500
+
+ fsl_sata: Fix compiler warnings shown by gcc-4.4
+
+ Update fsl_sata to use common structures instead of casting
+ back and forth between the fsl specific ones and the common ones
+ (which are identical).
+
+ fsl_sata.c: In function 'scan_sata':
+ fsl_sata.c:550: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
+ fsl_sata.c:549: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
+ fsl_sata.c:548: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
+ fsl_sata.c:545: note: initialized from here
+ fsl_sata.c:592: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
+ fsl_sata.c:590: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
+ fsl_sata.c:588: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
+ fsl_sata.c:586: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
+ fsl_sata.c:579: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
+ ...
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 20938e54a207472a090f04f20f30c9e32b14137e
+Author: Simon Kagstrom <simon.kagstrom@netinsight.net>
+Date: Tue Jul 7 15:58:51 2009 +0200
+
+ Add unaligned.h for arm
+
+ This patch adds unaligned.h for ARM (needed to build with LZO
+ compression). The file is taken from the linux kernel, but includes
+ u-boot headers instead.
+
+ Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ Acked-by: Stefan Roese <sr@denx.de>
+
+commit 433ea8abd6adfae3138dd4ce238237a037e1e537
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Sun Jul 19 19:17:42 2009 -0500
+
+ Remove last remanants of unused CONFIG_I2C_CMD_TREE
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit f6ca3b70949790ab5438d6c9a592216cc3616110
+Author: Andrzej Wolski <awolski@poczta.fm>
+Date: Fri Jul 17 22:26:54 2009 +0200
+
+ ubi: help message correction
+
+ Fix incorrect information about size units and correct typo.
+
+ Signed-off-by: Andrzej Wolski <awolski@poczta.fm>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 22f2017c31bc682e9b15612a5c2580ab5b84418e
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Sun Jul 19 19:17:42 2009 -0500
+
+ Remove last remanants of unused CONFIG_I2C_CMD_TREE
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit f99a292aa6083057f5db8283d2ce4a2be22b8856
+Author: Andrzej Wolski <awolski@poczta.fm>
+Date: Fri Jul 17 22:26:54 2009 +0200
+
+ ubi: help message correction
+
+ Fix incorrect information about size units and correct typo.
+
+ Signed-off-by: Andrzej Wolski <awolski@poczta.fm>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit b86b85e2611d57d834795a92453431a1a340c3c9
+Author: Ilya Yanok <yanok@emcraft.com>
+Date: Mon Jun 29 17:53:16 2009 +0400
+
+ mmc: set bus width to 1 and clock to minimum early during initialization
+
+ We need to switch back to 1-bit before initialization or SD 2.0 cards
+ will fail to send SCR if we've switched to 4-bit already.
+
+ Signed-off-by: Ilya Yanok <yanok@emcraft.com>
+
+commit cff80f2cd12bf9767509b5334ecfc90cd7de5502
+Author: Shinya Kuribayashi <skuribay@pobox.com>
+Date: Sat Jun 20 19:14:33 2009 +0900
+
+ config.mk: Remove unused HPATH
+
+ This variable is not unused anywhere.
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
+
+commit a781de12700e2cb3d3011fc83b47f7dd8cc3c154
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Wed Jun 17 16:20:14 2009 +0200
+
+ digsy mtc: Enable command line history.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 37566090766d61beef70c62986b90749920255d8
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Jul 2 19:23:25 2009 -0400
+
+ compiler.h: unify system ifdef cruft here
+
+ Shove a lot of the HOSTCC and related #ifdef checking crap into the new
+ compiler.h header so that we can keep all other headers nice and clean.
+
+ Also introduce custom uswap functions so we don't have to rely on the non
+ standard implementations that a host may (or may not in the case of OS X)
+ provide. This allows mkimage to finally build cleanly on an OS X system.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 2a2ed845c085eb093b69fa6382fcf7534bb1f4b0
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Mon Jun 15 11:50:40 2009 -0500
+
+ common: fix 'dummy' is used uninitialized in this function warning
+
+ fix this gcc 4.4 warning:
+
+ xyzModem.c: In function 'xyzModem_stream_open':
+ xyzModem.c:564: warning: 'dummy' is used uninitialized in this function
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 1ea6bcd8590b3ff9fe2bfbb0eb29a3b0edaa9460
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Jun 14 23:33:14 2009 -0400
+
+ push CROSS_COMPILE out to $(ARCH)_config.mk
+
+ Each arch should handle setting a proper default CROSS_COMPILE value in
+ their own config.mk file rather than having to maintain a large ugly list
+ in the Makefile. By using conditional assignment, we don't have to worry
+ about the variable already being set (env/cmdline/etc...).
+
+ The common config.mk file takes care of exporting CROSS_COMPILE already,
+ and while a few variables (toolchain ones) utilize CROSS_COMPILE before
+ including the arch config.mk, they do so with deferred assignment.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 60a3f404acbf8238a3138fe1f80a6bac75da4582
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Jun 13 12:55:37 2009 +0200
+
+ malloc.h: protect it against multiple include
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 7640f41988a456a0b1f05263d2e2dc5cd7d93984
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jul 19 19:37:24 2009 +0200
+
+ Fix boards broken after removal of legacy NAND and DoC support
+
+ Commit 2419169f removed support for legacy NAND and disk on chip but
+ missed to update the code for a few boards. This patch fixes the
+ resulting build issues.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 1a4664b53aaf23687b52d64b94be06a9aa260b86
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jul 19 19:32:37 2009 +0200
+
+ cmd_flash.c: fix fix compile error for boards with DataFlash
+
+ Commit 5669ed45 ("cmd_flash.c: fix warning: unused variable
+ 'addr_first'/'addr_last'") changed the #ifdef logic areound the
+ declaration of these variables and missed a combination of settings
+ of HAS_DATAFLASH with SYS_NO_FLASH; this patch fixes this.
+
+ Also spotted by Alessandro Rubini <rubini@gnudd.com>
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 341245a28830d3261c41b09d958eeea7bb93587a
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jul 19 12:05:15 2009 +0200
+
+ pcm030: fix out-of-tree building
+
+ Commit 0a87dd90 that was supposed to fix out-of-tree building for the
+ pcm030 board was unfortunately incomplete.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 8bf29b59fce8cc381114929082202d800e313ad5
+Author: Simon Kagstrom <simon.kagstrom@netinsight.net>
+Date: Tue Jul 7 13:58:51 2009 +0200
+
+ Add unaligned.h for arm
+
+ This patch adds unaligned.h for ARM (needed to build with LZO
+ compression). The file is taken from the linux kernel, but includes
+ u-boot headers instead.
+
+ Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ Acked-by: Stefan Roese <sr@denx.de>
+
+commit e405afab1dda66c9df3733f6b779d72fc36a0162
+Author: Kazuaki Ichinohe <kazuichi@fsi.co.jp>
+Date: Fri Jun 12 18:10:12 2009 +0900
+
+ Canyonlands SATA harddisk driver
+
+ This patch adds a SATA harddisk driver for the canyonlands.
+ This patch is kernel driver's porting.
+ This patch corresponded to not cmd_scsi but cmd_sata.
+ This patch divided an unused member with ifndef __U_BOOT__ in the structure.
+
+ [environment variable, boot script]
+ setenv bootargs root=/dev/sda7 rw
+ setenv bootargs ${bootargs} console=ttyS0,115200
+ ext2load sata 0:2 0x400000 /canyonlands/uImage
+ ext2load sata 0:2 0x800000 /canyonlands/canyonlands.dtb
+ fdt addr 0x800000 0x4000
+ bootm 0x400000 - 0x800000
+
+ If you drive SATA-2 disk on Canyonlands, you must change parts from
+ PI2PCIE212 to PI2PCIE2212 on U25. We confirmed to boot by using
+ following disks:
+
+ 1.Vendor: Fujitsu Type: MHW2040BS
+ 2.Vendor: Fujitsu Type: MHW2060BK
+ 3.Vendor: HAGIWARA SYS-COM:HFD25S-032GT
+ 4.Vendor: WesternDigital Type: WD3200BJKT (CONFIG_LBA48 required)
+ 5.Vendor: WesternDigital Type: WD3200BEVT (CONFIG_LBA48 required)
+ 6.Vendor: Hitachi Type: HTS543232L9A300 (CONFIG_LBA48 required)
+ 7.Vendor: Seagate Type: ST31000333AS (CONFIG_LBA48 required)
+ 8.Vendor: Transcend Type: TS32GSSD25S-M
+ 9.Vendor: MTRON Type: MSD-SATA1525-016
+
+ Signed-off-by: Kazuaki Ichinohe <kazuichi at fsi.co.jp>
+
+commit 52a0e2dee90c17e39634de814b16b96061cfb472
+Author: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Date: Wed Jun 10 19:09:40 2009 +0200
+
+ Add support for the Tundra TSI148 VME-bridge
+
+ From: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+ This patch adds support for the Tundra TSI148 VME-bridge. It's used on
+ the upcoming esd VME8349 board.
+
+ Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 8d1fea2c4041e665c96944e3f6fcffbde55db34b
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Jul 16 19:05:30 2009 -0400
+
+ Blackfin: bf537-{minotaur,srv1}: do not hardcode CONFIG_ETHADDR
+
+ MAC addresses should not be hardcoded in boards to avoid random link level
+ conflicts.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit baf357050353aee30c04f3f4b868426cb54468ca
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Fri Jul 10 10:42:06 2009 -0400
+
+ Blackfin: bf533-stamp: back down SCLK a bit
+
+ While the 1.0 and 1.2 spin of the bf533-stamp boards can handle the higher
+ SCLK speeds just fine, the 1.1 spin cannot due to the bugs introduced with
+ the shortened SDRAM traces. So lower the SCLK speed down to a value that
+ all three can handle.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 490fe7349102012c48730f6fc14ef36c8d155068
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Jul 9 20:56:56 2009 -0400
+
+ Blackfin: split cpu COBJS into multilines
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 909878fd3fda056d19b8b51a5cc51cb1c0b563d1
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Jul 9 01:15:05 2009 -0400
+
+ Blackfin: add os log functions
+
+ Part of the mini Blackfin ABI with operating systems is that they can use
+ 0x4f0-0x4f8 to pass log buffers to/from bootloaders. So add support to
+ U-Boot for reading the log buffer.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 9993e196da707a0a1cd4584f1fcef12382c1c144
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Sat Jul 18 18:42:13 2009 -0500
+
+ mpc83xx: convert all remaining boards over to 83XX_GENERIC_PCI
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit d39041fcadb1231430201d298c31f6be03d654f7
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jul 19 01:15:52 2009 +0200
+
+ PATI board: fix compiler warnings
+
+ Fix these:
+ pati.c: In function 'checkboard':
+ pati.c:358: warning: pointer targets in passing argument 2 of 'getenv_r' differ in signedness
+ ../common/flash.c: In function 'write_word':
+ ../common/flash.c:824: warning: dereferencing type-punned pointer will break strict-aliasing rules
+ cmd_pati.c: In function 'do_pati':
+ cmd_pati.c:279: warning: 'value' may be used uninitialized in this function
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 28c345042eafc550a34b9f52431bd4a22af6ac25
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat May 16 12:14:56 2009 +0200
+
+ mpl: printing current stdio devices cleanup
+
+ Currently the mpl boards duplicate the code to print the current
+ devices from common/console.c; use stdio_print_current_devices()
+ instead
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+ Edited commit message.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 7e3be7cf3bb344f717b6ec3d47a081269ea67ead
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat May 16 12:14:55 2009 +0200
+
+ console: unify printing current devices
+
+ Create stdio_print_current_devices() for this purpose
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 5669ed4557edf2714203aa8625c9fcd5a753b338
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Jul 18 23:18:14 2009 +0200
+
+ cmd_flash.c: fix warning: unused variable 'addr_first'/'addr_last'
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 6bb6e6c75ec4ef496f00f7f530e549d3e073c5de
+Author: Tom Rix <Tom.Rix@windriver.com>
+Date: Tue Jun 30 15:04:13 2009 -0500
+
+ OMAP3 Fix compiler warning for v7_flush_dcache_all
+
+ On build of omap3 targets in MAKEALL, the *.ERR files have
+
+ cpu.c: In function 'cleanup_before_linux':
+ cpu.c:64: warning: implicit declaration of function 'v7_flush_dcache_all'
+ cpu.c:64: warning: implicit declaration of function 'get_device_type
+
+ The functions v7_flush_dcache_all and get_device_type are declared
+ in include/asm-arm/arch-omap3/sys_proto.h, so use this file to
+ declare the functions.
+
+ Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
+
+commit dba107b967332fc8a35867f4d58038626c968800
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Jul 18 22:09:38 2009 +0200
+
+ ARM: make split_by_variant.sh output more useful
+
+ The board/armltd/integrator/split_by_variant.sh script used to print
+ "Configuring for integrator*p board..." no matter which board name
+ was being compiled. This made it difficult to match MAKEALL output to
+ board names. This patch fixes this.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 2eb99ca8029b44c988d5f6312f97e68d3b9cb2bd
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Jul 18 21:52:24 2009 +0200
+
+ NAND: Part 2: Fix warning Please define CONFIG_SYS_64BIT_VSPRINTF...
+
+ Commit 8d2effea added a warning for configurations that use NAND
+ without defining the (then necessary) CONFIG_SYS_64BIT_VSPRINTF but
+ failed to fix the affected boards.
+
+ This patch covers the non-PPC boards that were missed in the previous
+ patch (commit 170c1972).
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 7024aa14df2981b4e65c6189909da9aadb1c22da
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Jul 18 20:46:38 2009 +0200
+
+ at91cap9adk: fix #ifdef/#endif pairing
+
+ The #ifdef/#endif pairing in this file was obviously messed up.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 4abc5bffea244589fa1097e4c899a63efc609c8e
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Thu Jul 16 20:58:01 2009 +0530
+
+ Marvell MV88F6281GTW_GE Board support
+
+ This is Marvell's 88F6281_A0 based custom board developed
+ for wireless access point product
+
+ This patch is tested for-
+ 1. Boot from DRAM/SPI flash/NFS
+ 2. File transfer using tftp and loadb
+ 3. SPI flash read/write/erase
+ 4. Booting Linux kernel and RFS from SPI flash
+ 5. Boot from USB supported
+
+ Reviewed-by: Ronen Shitrit <rshitrit@marvell.com>
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+commit 55dd4ba5413b14e8ee24058c89ac5c05376c331c
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Thu Jul 16 20:58:00 2009 +0530
+
+ Marvell Sheevaplug Board support
+
+ Reference:
+ http://plugcomputer.org/
+ http://openplug.org/plugwiki/index.php/Das_U-boot_plug_support
+
+ This patch is tested for-
+ 1. Boot from DRAM/NAND flash
+ 2. File transfer using tftp
+ 3. NAND flash read/write/erase
+ 4. Linux kernel and RFS Boot from NAND
+ 5. Enabled USB PHY init for kernel need
+ 6. Boot from USB supported
+
+ Note: to boot Kirkwood kernel with USB support,
+ you should add "usb start" in the boot sequence
+
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+commit 0a87dd90a75d034301496285026fbd8106c7c6d5
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Jul 18 18:00:25 2009 +0200
+
+ pcm030: fix out-of-tree building
+
+ Commit c9969947, which added support for the pcm030 board
+ (aka phyCORE-MPC5200B-tiny), broke out-of-tree building.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 9ff59601c71e800b9d0dfde22fa70d12c71c12b4
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Jul 18 16:36:11 2009 +0200
+
+ MPC837XERDB: fix warning: "CONFIG_SYS_MONITOR_LEN" redefined
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 2b5243fc24a724e83409c0b70caa1a3180e997ae
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Jul 18 16:13:18 2009 +0200
+
+ 8xxx: fix warning: implicit declaration of function 'uec_standard_init'
+
+ Commit 8e55258f created function uec_standard_init() to initialize
+ all UEC interfaces for 83xx and 85xx but failed to provide a
+ prototype for it.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 5b54df2674fdad5e7d316484c67efc68e79f3f0d
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Jul 18 15:46:02 2009 +0200
+
+ MIP405T: fix compile problem
+
+ The "stdio/device: rework function naming convention" patch
+ (commit 52cb4d4f) broke the MIP405T board; this patch fixes it.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 170c19725ecd3a0e2e517dfd49979ca8822edec0
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Jul 18 15:32:10 2009 +0200
+
+ NAND: Fix warning Please define CONFIG_SYS_64BIT_VSPRINTF...
+
+ Commit 8d2effea added a warning for configurations that use NAND
+ without defining the (then necessary) CONFIG_SYS_64BIT_VSPRINTF but
+ failed to fix the affected boards.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 6e897a661fb9968ce354165a12cce82e4b889e04
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Jul 18 15:05:44 2009 +0200
+
+ CPCI750: fix compile problem
+
+ Commit bc0d3296 removed ppc_error_no.h from Marvell boards
+ but forgot to update board/esd/cpci750/mv_eth.h
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 6aee3048348f1b19ab89156da98bfa4f7babf24b
+Author: Alessandro Rubini <rubini-list@gnudd.com>
+Date: Fri Jul 17 14:42:11 2009 +0200
+
+ cmd_i2c: bugfix: add missing brace
+
+ The sub-command parser missed a brace, so "return 0;" is always
+ taken and no error message is diplayed if you say "i2c scan"
+ instead of "i2c probe", for example.
+
+ Proper brace is added. Also, a misleading and unneeded else
+ is removed.
+
+ Signed-off-by: Alessandro Rubini <rubini@gnudd.com.it>
+
+commit 52cb4d4fb3487313f5a72ea740f527a4aefaa365
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat May 16 12:14:54 2009 +0200
+
+ stdio/device: rework function naming convention
+
+ So far the console API uses the following naming convention:
+
+ ======Extract======
+ typedef struct device_t;
+
+ int device_register (device_t * dev);
+ int devices_init (void);
+ int device_deregister(char *devname);
+ struct list_head* device_get_list(void);
+ device_t* device_get_by_name(char* name);
+ device_t* device_clone(device_t *dev);
+ =======
+
+ which is too generic and confusing.
+
+ Instead of using device_XX and device_t we change this
+ into stdio_XX and stdio_dev
+
+ This will also allow to add later a generic device mechanism in order
+ to have support for multiple devices and driver instances.
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+ Edited commit message.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit f732a7598fa36d48241df20b1a1f4cdbf09f75ee
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Wed Jul 15 00:01:08 2009 -0500
+
+ ppc: Fix compile error for boards with CONFIG_DDR_ECC
+
+ A bug was introduced by commit e94e460c6e8741f42dab6d8dd4b596ba5d9d79ae
+ which affected non-MPC83xx/85xx/86xx ppc boards which had CONFIG_DDR_ECC
+ defined and resulted in errors such as:
+
+ Configuring for canyonlands board...
+ fsl_dma.c:50:2: error: #error "Freescale DMA engine not supported on your
+ processor"
+ make[1]: *** No rule to make target `.depend', needed by `libdma.a'. Stop.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 18e067de9b6ed087fa60496e64887f0b7458dbaa
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Thu Jul 16 20:57:59 2009 +0530
+
+ include/config_cmd_default.h cleanup
+
+ arranged configurations in alphabetical order
+ CONFIG_CMD_FLASH moved under ifndef CONFIG_SYS_NO_FLASH
+
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+commit 569460ebf14b87bd8fdb2352bde95d35ee96e13b
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Jun 14 21:35:22 2009 -0400
+
+ sata: namespace curr_device variable
+
+ The curr_device variable really should be namespaced with a "sata_" prefix
+ since it is only used by the sata code. It also avoids random conflicts
+ with other pieces of code (like cmd_mmc):
+ common/libcommon.a(cmd_sata.o):(.data.curr_device+0x0):
+ multiple definition of `curr_device'
+ common/libcommon.a(cmd_mmc.o):(.data.curr_device+0x0): first defined here
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 02e22c2de1ce2312f2636fa473a60c8d8f18d8aa
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Jun 14 21:35:21 2009 -0400
+
+ cmd_mmc: make curr_device static
+
+ The curr_device variable isn't used outside of cmd_mmc, so mark it static
+ to avoid conflicts with other pieces of code (like sata which also exports
+ a curr_device). Otherwise we end up with stuff like:
+ common/libcommon.a(cmd_sata.o):(.data.curr_device+0x0):
+ multiple definition of `curr_device'
+ common/libcommon.a(cmd_mmc.o):(.data.curr_device+0x0): first defined here
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 2d8d2adde3fce1152e4ad9f47238f07e70793c53
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Jun 14 21:35:16 2009 -0400
+
+ envcrc: add missing dependencies on env storage
+
+ When the envcrc building was made conditional, it missed a bunch of env
+ storage types, so add all currently supported types.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 2419169f5749d7af501b3b77a5336d1d535320de
+Author: Scott Wood <scottwood@freescale.com>
+Date: Thu Jul 16 19:08:04 2009 -0500
+
+ Remove legacy NAND and disk on chip references from boards.
+
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 12e9043c7ed961b60df865f45d9a3c74d6a38199
+Author: Shinya Kuribayashi <skuribay@pobox.com>
+Date: Sat Jun 20 19:10:14 2009 +0900
+
+ config.mk: Remove $(PCI_CLOCK) reference
+
+ The following commit introduced $(PCI_CLOCK) reference so that
+ we could tweak `PCI_66M' definition via an environment variable.
+
+ > commit f046ccd15c8bc9613bfd72916b761a127d36e5c6
+ > Author: Eran Liberty <liberty@freescale.com>
+ > Date: Thu Jul 28 10:08:46 2005 -0500
+ >
+ > * Patch by Eran Liberty
+ > Add support for the Freescale MPC8349ADS board.
+
+ But I suggest a removal of it for the following reasons:
+
+ * In 2006, MPC8349ADS was merged into MPC8349EMDS port,
+ and it seems that MPC8349EMDS port is PCI_66M free.
+
+ * OTOH, PCI_66M is used by MPC832XEMDS an MPC8360EMDS ports,
+ but they don't need $(PCI_CLOCK) environment variable at all.
+ PCI_66M is automatically configured via $(BOARD)_config names
+ with the help of $(findstring _66_,$@).
+
+ * Unfortunately $(PCI_CLOCK) has been undocumented anywhere,
+ so only a few people know the existence of it these days.
+
+ * Keep config.mk independent from $(BOARD) as much as possible.
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
+ Acked-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 3db75d9c11d37cc1d28bebd91b19f4e548b68155
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat May 23 21:42:36 2009 +0200
+
+ fix: missing autoconfig.mk from general Makefile
+
+ At the first run of make we generate the autoconf.mk and
+ autoconf.mk.dep if not already the case and we currently include only
+ to .dep
+
+ In order to use these autogenerated values we need to include it also
+ even if it's included in config.mk but it's done before their
+ generation
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 1ca298ced07327749b54321815f76fcddb2f9479
+Author: Matthias Weisser <matthias.weisser@graf-syteco.de>
+Date: Thu Jul 9 16:07:30 2009 +0200
+
+ Added support for splash screen positioning
+
+ This patch adds support splash image positioning by adding an
+ additional variable "splashpos" to the environment. Please see
+ README for details.
+
+ Signed-off-by: Matthias Weisser <matthias.weisser@graf-syteco.de>
+ Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 9d173e0233493113c9b1aa81bd2208d0057ab9db
+Author: Anatolij Gustschin <agust@denx.de>
+Date: Tue Jul 7 13:11:36 2009 +0200
+
+ video: mb862xx: replace printf with puts
+
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit cce99b2a7dd80683d61360aee56a6ece344950b2
+Author: Anatolij Gustschin <agust@denx.de>
+Date: Tue Jul 7 13:27:07 2009 +0200
+
+ video: mb862xx: use macros instead of magic numbers
+
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit e86528671ece6d5c1162656a37fc68a8e0bf67f8
+Author: Anatolij Gustschin <agust@denx.de>
+Date: Tue Jul 7 13:24:08 2009 +0200
+
+ video: mb862xx: fix coding style and remove dead code
+
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 292ed489dba8cc97b458579003a8001cd4703cd8
+Author: Michal Simek <monstr@monstr.eu>
+Date: Tue Jun 30 12:03:50 2009 +0200
+
+ microblaze: Remove ignored return type for __arch__swab16 function
+
+ This change remove compilation warnings.
+
+ Signed-off-by: Michal Simek <monstr@monstr.eu>
+
+commit e2776587c0eac131954ae100fda89cc3e7ed8b57
+Author: Michal Simek <monstr@monstr.eu>
+Date: Tue Jun 30 12:02:45 2009 +0200
+
+ microblaze: Removed unused variables
+
+ Signed-off-by: Michal Simek <monstr@monstr.eu>
+
+commit be33b046b549ad88c204c209508cd7657232ffbd
+Author: Scott Wood <scottwood@freescale.com>
+Date: Wed Apr 1 15:02:13 2009 -0500
+
+ Remove legacy NAND and disk on chip code.
+
+ Legacy NAND had been scheduled for removal. Any boards that use this
+ were already not building in the previous release due to an #error.
+
+ The disk on chip code in common/cmd_doc.c relies on legacy NAND,
+ and it has also been removed. There is newer disk on chip code
+ in drivers/mtd/nand; someone with access to hardware and sufficient
+ time and motivation can try to get that working, but for now disk
+ on chip is not supported.
+
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit fbdaafaee71e2c7f2c31b3582ab6d8679efee8d3
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Jun 4 16:40:36 2009 +0200
+
+ nand: Change NAND_MAX_OOBSIZE to 218 as needed for some 4k page devices
+
+ This is needed for the MPC512x NAND driver (fsl_nfc_nand.c) which already
+ defines such a 4k plus 218 bytes ECC layout.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Scott Wood <scottwood@freescale.com>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit f2f376ab956c17d4a0c42a993133ca25cdc87278
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Jul 16 15:13:04 2009 +0200
+
+ nand: ndfc: Remove unnecessary #ifdef's
+
+ Now that the 4xx NAND driver ndfc is moved to the common NAND driver
+ directory we don't need this #ifdef's anymore.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Scott Wood <scottwood@freescale.com>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 12582ac771b0bf3852817c3bfa4be326522a0665
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Jul 16 15:12:48 2009 +0200
+
+ nand/ppc4xx: Move PPC4xx NAND driver to common NAND driver directory
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Scott Wood <scottwood@freescale.com>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 3ebf70db5452d3d47c316ddef09f40e76553bcba
+Author: Valeriy Glushkov <gvv@lstec.com>
+Date: Tue Jul 14 13:51:10 2009 +0300
+
+ nand: fixed failed reads on corrected ECC errors in nand_util.c
+
+ Signed-off-by: Valeriy Glushkov <gvv@lstec.com>
+ Signed-off-by: Paulraj, Sandeep <s-paulraj@ti.com>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit ed727d394c5ab139033719772dc95dc25cfa14f7
+Author: David Brownell <david-b@pacbell.net>
+Date: Mon Jul 13 16:29:04 2009 -0700
+
+ Typo fix: use CONFIG_SOC_DM644X, not CONFIG_SOC_DM646.
+
+ Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 937076f84c5064f0a79105fce352ac7cf7b33643
+Author: Kyungmin Park <kmpark@infradead.org>
+Date: Sat Jul 11 16:49:55 2009 +0900
+
+ MTD: OneNAND: Increase the environment size to 4KiB
+
+ Also use mtd operation instead of onenand functions
+
+ Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit bfadb17f69c256196620c32164775f063a59c34f
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Wed Jun 10 00:25:38 2009 +0400
+
+ mpc83xx: MPC837xEMDS: Use hwconfig instead of pci_external_arbiter variable
+
+ Since we have simple hwconfig interface now, we don't need
+ pci_external_arbiter variable any longer.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+ Acked-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit b8b71ffbc35fde6905e65ffdbf4e4b87efc26b7e
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Wed Jun 10 00:25:36 2009 +0400
+
+ mpc83xx: MPC8315ERDB: Use hwconfig for board type selection
+
+ This patch simply converts the board to the hwconfig infrastructure.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+ Acked-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit c78c678354c8321737aa07e86831ff14176f4ed5
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Wed Jun 10 00:25:31 2009 +0400
+
+ mpc83xx: MPC837XEMDS: Fixup eSDHC nodes in device tree
+
+ fdt_fixup_esdhc() will either disable or enable eSDHC nodes, and
+ also will fixup clock-frequency property.
+
+ Plus, since DR USB and eSDHC are mutually exclusive, we should
+ only configure the eSDHC if asked through hwconfig.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+ Acked-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit c9646ed758804fa1fa6c1425369a4eee5d618b1d
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Wed Jun 10 00:25:30 2009 +0400
+
+ mpc83xx: MPC837XERDB: Add support for FSL eSDHC
+
+ This patch adds support for eSDHC on MPC837XERDB boards. The WP
+ switch doesn't seem to work on RDB boards though, the WP pin is
+ always asserted (can see the pin state when it's in GPIO mode).
+
+ FSL DR USB and FSL eSDHC are mutually exclusive because of pins
+ multiplexing, so user should specify 'esdhc' or 'dr_usb' options
+ in the hwconfig environment variable to choose between the
+ devices.
+
+ p.s.
+ Now we're very close to a monitor len limit (196 bytes left using
+ gcc-4.2.0), so also increase the monitor len by one sector (64 KB).
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+ Acked-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit b33433a63fe08c9e723ea15a7c7c7143bf527c6d
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Wed Jun 10 00:25:29 2009 +0400
+
+ fsl_esdhc: Add device tree fixups
+
+ This patch implements fdt_fixup_esdhc() function that is used to fixup
+ the device tree.
+
+ The function adds status = "disabled" propery if esdhc pins muxed away,
+ otherwise it fixups clock-frequency for esdhc nodes.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+ Acked-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 93f9dcf9e8b8182e97aeb7965c687176cbd0b933
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Wed Jun 10 00:25:27 2009 +0400
+
+ Add simple hwconfig infrastructure
+
+ This patch implements simple hwconfig infrastructure: an
+ interface for software knobs to control a hardware.
+
+ This is very simple implementation, i.e. it is implemented
+ via `hwconfig' environment variable. Later we could write
+ some "hwconfig <enable|disable|list>" commands, ncurses
+ interface for Award BIOS-like interface, and frame-buffer
+ interface for AMI GUI[1] BIOS-like interface with mouse
+ support[2].
+
+ Current implementation details/limitations:
+
+ 1. Doesn't support options dependencies and mutual exclusion.
+ We can implement this by integrating apt-get[3] into the
+ u-boot. But I didn't bother yet.
+
+ 2. Since we don't implement hwconfig command, i.e. we're working
+ with the environement directly, there is no way to tell that
+ toggling a particular option will need a reboot to take
+ an effect. So, for now it's advised to always reboot the
+ target after modifying hwconfig variable.
+
+ 3. We support hwconfig options with arguments. For example,
+
+ set hwconfig dr_usb:mode=peripheral,phy_type=ulpi
+
+ That means:
+ - dr_usb - enable Dual-Role USB controller;
+ - dr_usb:mode=peripheral - USB in Function mode;
+ - dr_usb:phy_type=ulpi - USB should work with ULPI PHYs;
+
+ The purpose of this simple implementation is to define some
+ internal API and then we can continue improving user experience
+ by adding more mature interface, like hwconfig command with
+ bells and whistles. Or not adding, if we feel that current
+ interface fits its needs.
+
+ [1] http://en.wikipedia.org/wiki/American_Megatrends
+ [2] Regarding ncurses and GUI with mouse support -- I'm just
+ kidding.
+ [3] The comment regarding apt-get is also a joke, meaning that
+ dependency tracking could be non-trivial. For example, for
+ enabling HW feature X we may need to disable Y, and turn Z
+ into reduced mode (like RMII-only interface for ethernet,
+ no MII).
+
+ It's quite trivial to implement simple cases though.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+ Acked-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 6c3fef28b9fff0d7f3fa4c51c3ee0ae8c2a3b043
+Author: Jerry Van Baren <gvb.uboot@gmail.com>
+Date: Wed Jul 15 20:42:59 2009 -0400
+
+ Improve U-Boot Porting Guide in the README
+
+ Update for...
+ * BDI2000 -> BDI3000 (BDI2000 is obsolete).
+ * Add a line to read the doc/README.* files
+ * Fix coding standard violations
+
+ Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
+
+commit 9578718c1b085cac73017d834001bc5cb0b2f73f
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Tue Jul 14 16:00:24 2009 -0500
+
+ mtd: cfi - if defined, use MAX_FLASH_BANKS_DETECT for static declarations
+
+ a.k.a cfi_mtd.c does as cfi_flash.c does. This also prevents
+ the TQM834x build from doing a:
+
+ cfi_mtd.c:36: error: variably modified 'cfi_mtd_info' at file scope
+ cfi_mtd.c:37: error: variably modified 'cfi_mtd_names' at file scope
+
+ using gcc 4.4.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 4a9932a4364b548773bc131bf85e24a2ec15f2b0
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Tue Jul 7 18:04:21 2009 -0500
+
+ mpc83xx: increase MONITOR_LEN to offset growing pains
+
+ Saving the environment leads to overwriting u-boot itself,
+ bricking boards. Increase u-boot's image size so the environment
+ base address doesn't end up overlapping u-boot text.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit c31e13260bcd048a94412a47b004386ea6112acf
+Author: Valeriy Glushkov <gvv@lstec.com>
+Date: Tue Jun 30 15:48:41 2009 +0300
+
+ usb: mpx8349itx: added support of loading images from USB storage (MPH/DR)
+
+ Signed-off-by: Valeriy Glushkov <gvv@lstec.com>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit d89e1c36891de793a20a929282acc0fc7b98feac
+Author: Valeriy Glushkov <gvv@lstec.com>
+Date: Tue Jun 30 15:48:40 2009 +0300
+
+ usb: mpc834x: added support of the MPH USB controller in addition to the DR one
+
+ Signed-off-by: Valeriy Glushkov <gvv@lstec.com>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit d9ac3d5a17ecef0beb70073018925e011b11684e
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Mon Jun 15 11:51:47 2009 -0500
+
+ mpc83xx: set 64BIT_VSPRINTF for boards using nand_util
+
+ When enabling NAND support for a board, one must also define
+ CONFIG_SYS_64BIT_VSPRINTF because this is needed in nand_util.c
+ for correct output.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+ Cc: Dave Liu <daveliu@freescale.com>
+ Cc: Ron Madrid <ron_madrid@sbcglobal.net>
+ Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit 7d4450a9773673052fcd7fdf0a4a88c089126ac1
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jun 14 20:58:53 2009 +0200
+
+ mpc5121ads: add JFFS2 and MTDPARTS support; adjust flash map
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 1f1f82f3de1660f398bf42bfd709b9859582ce5e
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jun 14 20:58:52 2009 +0200
+
+ aria: add JFFS2 and MTDPARTS support; adjust flash map
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit a6d6d46a4fef876455e11b45ed699c0fb3bd1ca1
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jun 14 20:58:51 2009 +0200
+
+ aria: enable NAND flash support
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 13946925e850db5351982acb691d51716fc754e2
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jun 14 20:58:50 2009 +0200
+
+ MPC512x: fix typo in comment listing the NAND driver name
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: Stefan Roese <sr@denx.de>
+ Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+commit 2ca6f74d09653f8041b52cafd0d650fdc2a56c51
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jun 14 20:58:49 2009 +0200
+
+ mecp5123: cleanup - remove dead code
+
+ Remove dead code that was obviously a left-over from copy & paste.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: Stefan Roese <sr@denx.de>
+ Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+commit 25671c8672f2d7b39555416a6b7a6b7b39b810bf
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jun 14 20:58:48 2009 +0200
+
+ aria: adjust memory controller initialization
+
+ Needed for Rev. 2 silicon at 400 MHz
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 7629f1c06b6dea36bbc7bf70820b824e9b6d2227
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jun 14 20:58:47 2009 +0200
+
+ MPC512x: factor out common code
+
+ Now that we have 3 boards for the MPC512x it turns out that they all
+ use the very same fixed_sdram() code.
+
+ This patch factors out this common code into cpu/mpc512x/fixed_sdram.c
+ and adds a new header file, include/asm-ppc/mpc512x.h, with some
+ macros, inline functions and prototype definitions specific to MPC512x
+ systems.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: Stefan Roese <sr@denx.de>
+ Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+commit 0549353a6ba5aa03420c0962b9072e9cf1fa49d9
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jun 14 20:58:46 2009 +0200
+
+ mecp5123: fix build error
+
+ The mecp5123 board did not compile because the MSCAN Clock Control
+ Registers were missing; these got added, but as an array instead
+ of 4 individual registers. Adapt the code so it builds.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: Stefan Roese <sr@denx.de>
+ Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+commit a9905db5d29a56aedd7db5bcb56b0385873aa6a3
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jun 14 20:58:45 2009 +0200
+
+ MPC512x: Add MSCAN1...4 Clock Control Registers
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: Stefan Roese <sr@denx.de>
+ Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+commit f5489c4200b37c9a1d6dbde116f5adc0539610de
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jun 14 20:58:44 2009 +0200
+
+ MPC512x: enabling NAND support requires CONFIG_SYS_64BIT_VSPRINTF
+
+ When enabling NAND support for a board, one must also define
+ CONFIG_SYS_64BIT_VSPRINTF because this is needed in nand_util.c
+ for correct output.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: Stefan Roese <sr@denx.de>
+ Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+commit b4db4a7638ef90cf0aacf7b954d9bf3043dda780
+Author: Po-Yu Chuang <ratbert@faraday-tech.com>
+Date: Fri Jul 10 18:03:57 2009 +0800
+
+ issue write command to base for JEDEC flash
+
+ For JEDEC flash, we should issue word programming command relative to
+ base address rather than sector base address. Original source makes
+ SST Flash fails to program sectors which are not on the 0x10000 boundaries.
+
+ e.g.
+ SST39LF040 uses addr1=0x5555 and addr2=0x2AAA, however, each sector
+ is 0x1000 bytes.
+
+ Thus, if we issue command to "sector base (0x41000) + offset(0x5555)",
+ it sends to 0x46555 and the chip fails to recognize that address.
+
+ This patch is tested with SST39LF040.
+
+ Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 986922714ffd21ad39f48522d285fffc7aed56b1
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat May 2 11:53:50 2009 +0200
+
+ versatile: update config and merge to cfi flash driver
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Peter Pearse <peter.pearse@arm.com>
+ Cc: Catalin Marinas <catalin.marinas@arm.com>
+
+commit d6e8ed832b25d5db4fdd3fb91e73028e494dcd6e
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat May 2 11:53:49 2009 +0200
+
+ versatile: specify the board type on the prompt
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Peter Pearse <peter.pearse@arm.com>
+ Cc: Catalin Marinas <catalin.marinas@arm.com>
+
+commit 5ccc2d99d61c81805348b0cd9f79731b271f7daf
+Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
+Date: Thu Jun 25 17:04:15 2009 +0200
+
+ at91: Introduction of at91sam9g10 SOC.
+
+ AT91sam9g10 is an ARM 926ej-s SOC. It is an evolution of the at91sam9261 with a
+ faster clock speed: 266/133MHz.
+
+ Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
+
+commit 22ee647380c42f44528f99b7c1b423725e542102
+Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
+Date: Thu Jul 9 10:16:29 2009 +0200
+
+ at91: Introduction of at91sam9g45 SOC.
+
+ AT91sam9g45 series is an ARM 926ej-s SOC family clocked at 400/133MHz.
+ It embeds USB high speed host and device, LCD, DDR2 RAM, and a full set of
+ peripherals.
+
+ The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES.
+ On the board you can find 2 USART, USB high speed,
+ a 480*272 LG lcd, ethernet, gpio/joystick/buttons.
+
+ Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
+
+commit c33c5990cec7ced9ef1ef148debbca34adafa12b
+Author: Daniel Mack <daniel@caiaq.de>
+Date: Tue Jun 23 17:30:05 2009 +0200
+
+ pxa: fix CKEN_B register bits
+
+ The current defition for CKEN_B register bits is nonsense. Adding 32 to
+ the shifted value is equal to '| (1 << 5)', and this bit is marked
+ 'reserved' in the PXA docs.
+
+ Signed-off-by: Daniel Mack <daniel@caiaq.de>
+
+commit bd876be46f28b5fc2896537f6d01353f332789f7
+Author: Daniel Mack <daniel@caiaq.de>
+Date: Tue Jun 23 17:30:04 2009 +0200
+
+ pxa: add clock for system bus 2 arbiter
+
+ This clock is needed for systems using the USB2 device unit or the 2d
+ graphics accelerator.
+
+ Signed-off-by: Daniel Mack <daniel@caiaq.de>
+
+commit b016000a95514c08cab50e1cba00b019c0801bc4
+Author: Grazvydas Ignotas <notasas@gmail.com>
+Date: Wed Jul 8 00:30:01 2009 +0300
+
+ OMAP3 pandora: Fix CKE1 MUX setting to allow self-refresh
+
+ Pandora is using both SDRC CSes. The MUX setting is needed
+ for the second CS clock signal to allow the 2 RAM parts to
+ be put in self-refresh correctly.
+
+ Based on similar patch for beagle and overo by
+ Jean Pihet and Steve Sakoman.
+
+commit 8672c288703f3c51c829851c8fe6608c7869faaa
+Author: Grazvydas Ignotas <notasas@gmail.com>
+Date: Wed Jul 8 00:30:00 2009 +0300
+
+ OMAP3 pandora: setup pulls for various GPIOs
+
+ Set pullups or pulldowns for GPIOs which need them.
+ Disable them for others, which have external pulls.
+ Also make disabled pull setting consistent (some pins had
+ type set to "up" even if pull type selection was disabled).
+
+commit 5ff78122f229946862a3f67a2f50a329e8e1bcf5
+Author: Grazvydas Ignotas <notasas@gmail.com>
+Date: Wed Jul 8 00:29:59 2009 +0300
+
+ OMAP3 pandora: setup pin mux for pins used on rev3 boards
+
+ Setup pin mux for GPIO pins connected on rev3 or later
+ boards. Also change NUB2 IRQ pin. This should not affect
+ older boards because they don't have any nubs (analog
+ controllers) attached to them.
+
+commit 67c97c346b27c586a7263564f7afff6d1f8d8d0a
+Author: Grazvydas Ignotas <notasas@gmail.com>
+Date: Wed Jul 8 00:29:58 2009 +0300
+
+ OMAP3 pandora: pin mux cleanup
+
+ Remove configuration of not unused pins, effectively
+ leaving them in safe mode.
+
+commit b996165f5a1623a055c03b22d64d6d5da81835d0
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Mon Jul 6 15:50:47 2009 +0530
+
+ arm: Kirkwood: bugfix: UART1 bar correction
+
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+commit 50243e3e7a96a96c5418ce6c90b7252d26fdd5b0
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Tue Jul 7 15:48:58 2009 -0500
+
+ usb: Fix compiler warning with gcc4.4
+
+ ehci-hcd.c: In function 'ehci_submit_root':
+ ehci-hcd.c:719: warning: value computed is not used
+ ehci-hcd.c:748: warning: value computed is not used
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 04366d070a1a3f7affddf15aaaea87bcf44cdbb0
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Wed Jul 8 11:42:19 2009 +0900
+
+ sh: Update pci config for Renesas r7780mp board
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 74d9c16a681aa24bb4125191fe39dc7c75cde56a
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date: Thu Jun 25 16:31:26 2009 +0900
+
+ sh: Add support ESPT-GIGA borad
+
+ ESPT-Giga is SH7763-based reference board.
+ Board support is relatively sparse, presently supporting serial,
+ gigabit ethernet, USB host, and MTD.
+
+ More information (in Japanese) available at:
+ http://www.cente.jp/product/cente_hard/ESPT-Giga.html
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit dae4e0148a1146a5610025ae4b445e841410b659
+Author: Matthias Fuchs <matthias.fuchs@esd.eu>
+Date: Fri Jul 3 16:06:37 2009 +0200
+
+ Add ESD PCI vendor ID
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+
+commit 876b3cef537aab2cba8c19505db2876f6057f818
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Mon Jun 22 18:01:41 2009 -0500
+
+ api_examples/Makefile: General cleanup
+
+ * Remove symlinking of files located outside api_examples/
+
+ * Auto generate dependencies for files located outside api_examples/
+
+ * Update names of variables to be similar to those in tools/Makefile
+
+ * Fix out of tree build error
+ Dependencies are calculated for all files in the SRCS variable.
+ Previously, the SRCS variable contained files which were symlinked
+ into the api_examples/ directory. These symlinked files did not exist
+ when dependencies were calculated when building out of tree. This
+ resulted in errors such as:
+ make[1]: *** No rule to make target `/work/wd/tmp-ppc/api_examples/.depend', needed by `_depend'. Stop.
+ make[1]: Leaving directory `/home/wd/git/u-boot/work/api_examples'
+ make: *** [depend] Error 2
+
+ Since symlinked source files are no longer used, this bug no longer
+ exists.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Acked-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit 522f6f02adb93194e337016fe2e4e53c58d5d5ea
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Mon Jun 22 18:01:40 2009 -0500
+
+ api_examples/Makefile: Get rid of unnecessary intermediate LIB target
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Acked-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit 117d0ab5e6f3b3dd48fc346df4919555a78afd39
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Mon Jun 22 18:01:39 2009 -0500
+
+ api_examples/Makefile: Combine ELF and BIN targets
+
+ Combining the two rules cleans up the Makefile a bit
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Acked-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit 644cb38108b8dc22e0ef3cf5f404fe310d1995f8
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Mon Jun 22 18:01:38 2009 -0500
+
+ api_examples/Makefile: Split up variable declarations
+
+ This cleans up the Makefile a bit and simplifies future changes
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Acked-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit 890d242facc4079ed21e979ced2e8c6d6974f6d3
+Author: Timur Tabi <timur@freescale.com>
+Date: Fri Jun 19 14:10:52 2009 -0500
+
+ remove _IO_BASE and KSEG1ADDR from board configuration files
+
+ The KSEG1ADDR macro used to be necessary for the RTL8139 Ethernet
+ driver, but the code that used that macro was removed over a year
+ ago, so board configuration files no longer need to define it.
+
+ The _IO_BASE macro is also automatically defined to 0 if it isn't
+ already set, so there's no need to define that macro either in the
+ board configuration files.
+
+ Signed-off-by: Timur Tabi <timur@freescale.com>
+ Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ Acked-by: Andy Fleming <afleming@freescale.com>
+ Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
+ Acked-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit c9969947a4687de90e2bb58e76842b491aa0e0b9
+Author: Jon Smirl <jonsmirl@gmail.com>
+Date: Sun Jun 14 18:21:28 2009 -0400
+
+ board support patch for phyCORE-MPC5200B-tiny
+
+ Add support for the Phytec phyCORE-MPC5200B-tiny.
+ Code originally from Pengutronix.de.
+ Created CONFIG_SYS_ATA_CS_ON_TIMER01 define for when IDE CS is on
+ Timer 0/1
+
+ Signed-off-by: Jon Smirl <jonsmirl@gmail.com>
+ Acked-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 7bd49ad12cc36a4de6995ddabbc65ffa1aa1933d
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Jun 15 13:37:20 2009 -0400
+
+ kallsyms: fix escaping of NUL char in strings
+
+ The current kallsyms code is using \\0 to escape the backslash in the awk
+ code, but the shell too needs escaping. This way we make sure gcc is
+ passed the \0. Then gcc itself will consume this as an octal, so we have
+ to use 000 so gcc will create the final NUL.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit ed540f07b8ad86909704e9806c1762462cb4995a
+Author: Harald Krapfenbauer <Harald.Krapfenbauer@bluetechnix.at>
+Date: Fri Jun 26 10:18:49 2009 -0400
+
+ Blackfin: cm-bf561: add example settings for EXT-BF5xx-USB-ETH2 add-on
+
+ The cm-bf561 module can easily hook up to the EXT-BF5xx-USB-ETH2 extender
+ board, so add a simple example of how to do that in the board config.
+
+ Signed-off-by: Harald Krapfenbauer <Harald.Krapfenbauer@bluetechnix.at>
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit f8bf54b4081c3c3d518830df0017a23ec672a841
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Jun 25 19:40:28 2009 -0400
+
+ Blackfin: blackstamp: update spi flash settings
+
+ The latest blackstamp boards can only run the SPI flash at 15MHz before
+ they start to crap out, so lower the max speeds accordingly. The new SPI
+ flash also has different sector requirements, so update the environment
+ sizes as well.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 286070ddc8339666c09bd7912e960b850a8a0318
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Oct 6 03:31:52 2008 -0400
+
+ Blackfin: add cache_dump commands
+
+ A few debug-type commands used to dump the raw icache/dcache data. Useful
+ when trying to track down cache-related bugs.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 632e9b671efb0a6c900499f7a49fe5b63292b5fc
+Author: Matthias Fuchs <matthias.fuchs@esd.eu>
+Date: Wed Jul 8 15:31:57 2009 +0200
+
+ ppc4xx: Set default PCI device ID for 405EP boards
+
+ Current code only sets the PCI vendor id to 0x1014 and
+ leaved device id to 0x0000.
+
+ Ths patch ....
+ a) uses the correct PCI_VENDOR_ID_IBM macro for this
+ b) sets the default device ID as stated in the UM to 0x0156
+ by using PCI_DEVICE_ID_IBM_405GP for this.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 123f102ec093fba6967066acdf9beb637df2e2d1
+Author: Matthias Fuchs <matthias.fuchs@esd.eu>
+Date: Wed Jul 8 13:43:55 2009 +0200
+
+ ppc4xx: Move 405EP pci code from cpu_init_f() to __pci_pre_init()
+
+ This patch moves some basic PCI initialisation from the 4xx cpu_init_f()
+ to cpu/ppc4xx/4xx_pci.c.
+
+ The original cpu_init_f() function enabled the 405EP's internal arbiter
+ in all situations. Also the HCE bit in cpc0_pci is always set.
+ The first is not really wanted for PCI adapter designs and the latter
+ is a general bug for PCI adapter U-Boots. Because it enables
+ PCI configuration by the system CPU even when the PCI configuration has
+ not been setup by the 405EP. The one and only correct place is
+ in pci_405gp_init() (see "Set HCE bit" comment).
+
+ So for compatibility reasons the arbiter is still enabled in any case,
+ but from weak pci_pre_init() so that it can be replaced by board specific
+ code.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c71103f9dc66dfcce8ad6df942364043bf27ade8
+Author: Matthias Fuchs <matthias.fuchs@esd.eu>
+Date: Wed Jul 8 13:43:23 2009 +0200
+
+ ppc4xx: Make is_pci_host() available for all 440 and 405 CPUs
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 1d8937a469bfeb55ca1f6d89a4e7cd2dfee3cf17
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Mon Jun 29 20:56:43 2009 +0530
+
+ usb: add Marvell Kirkwood ehci host controller driver
+
+ This driver is tested on Sheevaplug platform
+
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit db7b43e4681f6f93c336132708157a8a0cca1f8b
+Author: Vivek Mahajan <vivek.mahajan@freescale.com>
+Date: Wed Jun 24 10:08:40 2009 +0530
+
+ mpc83xx: USB: fix: access of ehci struct elements
+
+ It fixes the access to the 'ehci' struct elements for mpc83xx which
+ should have been taken care of in 4ef01010aa4799c759d75e67007fdd3a38c88c8a
+ Sorry about that.
+
+ Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 08066152735417fc55a5c9de2cec0714c529e4f3
+Author: Vivek Mahajan <vivek.mahajan@freescale.com>
+Date: Fri Jun 19 17:56:00 2009 +0530
+
+ mpc8xxx: USB: fix: access of ehci struct elements
+
+ This patch fixes the access to the 'ehci' struct elements which should
+ have been taken care off in 4ef01010aa4799c759d75e67007fdd3a38c88c8a
+ Sorry about that.
+
+ Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit c3a012ce65818beb274195cd47f31ed80d0fbaa5
+Author: Bryan Wu <bryan.wu@analog.com>
+Date: Tue Jun 16 05:26:27 2009 -0400
+
+ usb: musb: add timeout via CONFIG_MUSB_TIMEOUT
+
+ Signed-off-by: Bryan Wu <bryan.wu@analog.com>
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 7984967a9405672db1581402d2c2cfae268d1a67
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Tue Jun 16 05:26:25 2009 -0400
+
+ usb: musb: drop old musb read/write prototypes
+
+ These functions are no longer defined, so remove their prototypes.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 4e04f16020115ab5ccf53158e100de58bcaf29bd
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Mon Jun 15 11:50:07 2009 -0500
+
+ usb: fix CONFIG_SYS_MPC83xx_USB_ADDR not defined error
+
+ fix a stray CONFIG_MPC83XX that escaped commit
+ 0f898604945af4543c1525fc33b6bae621a3b805.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit bc0d3296f1780b50e6b9630aee5eb368f2afb6cb
+Author: Michal Simek <monstr@monstr.eu>
+Date: Tue Jun 30 23:47:30 2009 +1000
+
+ asm-generic: Consolidate errno.h to asm-generic/errno.h
+
+ This patch use blackfin errno.h implementation which
+ correspond Linux kernel one.
+
+ MIPS implemetation is different that's why I keep it.
+
+ I removed ppc_error_no.h from Marvell boards which
+ was the same too.
+
+ I have got ack from ppc40x, blackfin, arm, coldfire and avr custodians.
+
+ Acked-by: Stefan Roese <sr@denx.de>
+ Signed-off-by: Michal Simek <monstr@monstr.eu>
+
+commit 2896b5851f0430bf16529376a4193630e966c788
+Author: Simon Kagstrom <simon.kagstrom@netinsight.net>
+Date: Tue Jul 7 16:01:02 2009 +0200
+
+ Command improvements for ubifs
+
+ Check that an argument is passed to ubifsmount and that addresses and
+ sizes are actually numbers for ubifsload. Also improve the instructions
+ a bit.
+
+ Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 25c8f4005979ab2d190713ba341d96a5fa905cdb
+Author: Simon Kagstrom <simon.kagstrom@netinsight.net>
+Date: Tue Jul 7 16:59:46 2009 +0200
+
+ Handle VID header offset in ubi part command
+
+ The VID header offset is sometimes needed to initialize the UBI
+ partition. This patch adds it (optionally) to the command line
+ for the ubi part command.
+
+ (Lines have been properly wrapped since last version)
+
+ Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ Acked-by: Stefan Roese <sr@denx.de>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 3672cd5c3b53d219d33345eebad4e25ad5bf6d52
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Jul 9 09:56:16 2009 +0200
+
+ MAINTAINERS: fix sorting, remove duplicates.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit efbf14e9a2394a154b12643d4a011994b5096b5a
+Author: Heiko Schocher <heiko.schocher@invitel.hu>
+Date: Wed Dec 10 08:27:01 2008 +0100
+
+ all platforms: make show_boot_progress() work again
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 205a0988d8fd778c60746c34c2f17dbd2b7cd0d2
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date: Mon Jun 29 15:25:18 2009 +0530
+
+ nand: Add Marvell Kirkwood NAND driver
+
+ This patch adds a NAND driver for the Marvell Kirkwood SoC's
+
+ Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+ Acked-by: Scott Wood <scottwood@freescale.com>
+
+commit 0580e48f53f972783e56fcedadb9ce6e5b0b6f32
+Author: Matthias Fuchs <matthias.fuchs@esd.eu>
+Date: Mon Jul 6 16:27:33 2009 +0200
+
+ ppc4xx: Make pll_write global
+
+ This patch makes pll_write on PPC405EP boards
+ global and callable from C code.
+
+ pll_write can be used to dynamically modify the PLB:PCI divider
+ as it is required for 33/66 MHz pci adapters based on the 405EP.
+
+ board_early_init_f() is a good place to do that (check M66EN signal
+ and call pll_write() when it is required).
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 20b3c4b528606d51799aed5e4c71783720cd2b72
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Jul 6 11:44:33 2009 +0200
+
+ ppc4xx: Remove compilation warning "pci_async_enabled defined but not used"
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit d0a1364f91c80d29daff6b27a7904a50cdc00b35
+Author: Matthias Fuchs <matthias.fuchs@esd.eu>
+Date: Fri Jul 3 16:06:06 2009 +0200
+
+ ppc4xx: Implement is_pci_host() for 405 CPUs
+
+ This patch implements the is_pci_host() function in a similiar way
+ as it is used on 440 targets.
+
+ The former path with CONFIG_PCI_HOST == PCI_HOST_AUTO does not
+ build on 405EP targets because checking the PCI arbiter is different.
+ So putting the fixed code into a separate function makes the code
+ more readable.
+
+ Also using is_pci_host() on 405 brings 405 and 440 PCI code
+ a little bit closer.
+
+ In preparation for an upcoming 405EP based PMC module I made this
+ function weak so that it can be overwritten from board specific code.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 04ddae915f295dee301f15c32100533a48e3b433
+Author: Alessio Centazzo <centazzo@gmail.com>
+Date: Wed Jul 1 22:20:51 2009 -0700
+
+ ppc4xx: Fixed PPC4xx debug compilation error in uic.c
+
+ This patch fixes a debug compilation error for PPC4xx platforms, all
+ other architectures are not affected by this change. The 'handler'
+ pointer was undefined. The fix is exercised and has effect only if
+ DEBUG is defined.
+
+ Signed-off-by: Alessio Centazzo acpatin@yahoo.com
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 48e2b535a0dd3a7b77b674130934a24f9de6f48d
+Author: Felix Radensky <felix@embedded-sol.com>
+Date: Wed Jul 1 11:37:46 2009 +0300
+
+ 4xx: Fix compilation warnings and MQ registers dump in SPD DDR2 code
+
+ This patch fixes printf format string compilation warnings in several
+ debug statements. It also fixes the dump of DDR controller MQ registers
+ found on some 44x and 46x platforms. The current register dump code
+ uses incorrect DCRs to access these registers.
+
+ Signed-off-by: Felix Radensky <felix@embedded-sol.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 26d37f0061ad05e5c383c910f00e6006f3c89a3a
+Author: Felix Radensky <felix@embedded-sol.com>
+Date: Mon Jun 22 15:30:42 2009 +0300
+
+ ppc4xx: Fix FDT EBC mappings on Canyonlands
+
+ This patch fixes 2 problems with FDT EBC mappings on Canyonlands.
+ First, NAND EBC mapping was missing, making Linux NAND driver
+ unusable on this board. Second, NOR remapping code assumed that
+ NOR is always on CS0, however when booting from NAND NOR is on CS3.
+
+ Signed-off-by: Felix Radensky <felix@embedded-sol.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit baa9f9ba4345ed6dc5c403871c32e6295316ea52
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Tue Jun 16 22:29:15 2009 +0900
+
+ sh: Revised the build with newest compiler
+
+ The check of data became severe from newest gcc.
+ This patch checked in gcc-4.2 and 4.3 .
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit be45c632568ba76343c1453b3951ad793f482fd5
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Thu Jun 4 12:06:48 2009 +0200
+
+ sh3/sh4: rename config option TMU_CLK_DIVIDER to CONFIG_SYS_TMU_CLK_DIV
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 8dd29c87ba370072a8464b8cc19e0a1e6e0497b4
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Thu Jun 4 12:06:47 2009 +0200
+
+ sh3/sh4: fix CONFIG_SYS_HZ to 1000
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit add380f51f34ed1e2678c2abac8d53c91d652f26
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Thu Jun 4 12:06:46 2009 +0200
+
+ sh: introduce clock framework
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 3931a375de2c381d9ff5ec2767b2da9f62a41aef
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Thu Jun 4 12:06:45 2009 +0200
+
+ sh: unify linker script
+
+ all sh boards use the same cpu linker script so move it to cpu/$(CPU)
+
+ that could be overwrite in following order
+ SOC
+ BOARD
+ via the corresponding config.mk
+
+ tested on r2dplus
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 236aad875817771eb1f25ed32784b3cd7760b2e6
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Thu Jun 4 12:06:44 2009 +0200
+
+ sh: make the linker scripts more generic
+
+ currently we need to sync the linker script enty and TEXT_BASE manualy
+ and the reloc_dst is based on it
+
+ instead provide it now from the ldflags
+
+ tested on r2dplus
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit ce29817212792113cd2d67a9767049a2e262c406
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Thu Jun 4 12:06:43 2009 +0200
+
+ sh7785lcr: fix out of tree build
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 2e8a6f551cba550e9220dca4d8504066203b1f74
+Author: HeungJun Kim <riverful.kim@gmail.com>
+Date: Tue Jun 30 14:42:22 2009 +0900
+
+ env_onenand: change env_address type from unsigned long to loff_t
+
+ If use the onenand boot, the env_relocate_spec() calls mtd->read(),
+ and the type of the argument #2 of mtd->read() was changed to loff_t.
+ But, the "env_addr" type is still unsigned long, thus this patch change
+ the type from unsigned long to loff_t.
+
+ Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
+ Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 66372fe2ab11cdeb0e841ad9eb6ba79769db4909
+Author: Mingkai Hu <Mingkai.hu@freescale.com>
+Date: Thu Jun 18 18:23:27 2009 +0800
+
+ fsl_elbc_nand: redirect the pointer of bbt pattern to RAM
+
+ The bbt descriptors contains the pointer to the bbt pattern which
+ are statically initialized memory struct. When relocated to RAM,
+ these pointers will continue point to NOR flash(or L2 SRAM, or
+ other boot device). If the contents of NOR flash changed or L2
+ SRAM disabled, it'll hang the system.
+
+ Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 1dac3a51875967f32641bbc0d26dc382ef02330a
+Author: Scott Wood <scottwood@freescale.com>
+Date: Wed Jun 24 17:23:49 2009 -0500
+
+ nand_spl: Fix cmd_ctrl usage in nand_boot.c.
+
+ When adding large page NAND support to this file, I had a misunderstanding
+ about the exact semantics of NAND_CTRL_CHANGE (which isn't documented
+ anywhere I can find) -- it is apparently just a hint to drivers,
+ which aren't required to preserve the old value for subsequent
+ non-"change" invocations.
+
+ This change makes nand_boot.c no longer assume this. Note that this
+ happened to work by chance with some NAND drivers, which don't preserve
+ the value, but treat 0 equivalently to NAND_CTRL_ALE.
+
+ I don't have hardware to test this, so any testing is appreciated.
+
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 98713d2663d5d30dde74f48f547114a2bfd9d463
+Author: kevin.morfitt@fearnside-systems.co.uk <kevin.morfitt@fearnside-systems.co.uk>
+Date: Thu Jun 18 18:41:03 2009 +0100
+
+ Bug-fix in drivers mtd nand Makefile
+
+ The S3C2410 NAND driver source file is included in the makefile instead of
+ the object file.
+
+ Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit b74ab737369bbbe66c15cbe6c0d0b6a351b00c96
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date: Mon May 18 16:07:22 2009 +0200
+
+ nand_spl: read environment early, when booting from NAND using nand_spl
+
+ Currently, when booting from NAND using nand_spl, in the beginning the default
+ environment is used until later in boot process the dynamic environment is read
+ out. This way environment variables that must be interpreted early, like the
+ baudrate or "silent", cannot be modified dynamically and remain at their
+ default values. Fix this problem by reading out main and redundand (if used)
+ copies of the environment in the nand_spl code.
+
+ Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 378adfcdf4bbd77ee4cbc3276d4733e218308a21
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat May 16 14:27:40 2009 +0200
+
+ mtd: nand: use loff_t for offset
+
+ nand_util currently uses size_t which is arch dependent and not always a
+ unsigned long. Now use loff_t, as does the linux mtd layer.
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 8360b66bac9567701027a0087274d0c9b2fe8d6b
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun May 24 17:34:33 2009 +0200
+
+ nand/onenand: Fix missing argument checking for "markbad" command
+
+ The "nand markbad" and "onenand markbad" commands did not check if an
+ argument was passed; if this was forgotten, no error was raised but
+ block 0 was marked as bad.
+
+ While fixing this bug, clean up the code a bit and allow to pass more
+ than one block address, thus allowing to mark several blocks as bad
+ in a single command invocation.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit cd84423a09f3a08029fe41c1db96168debd0b51f
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon May 25 22:42:28 2009 -0400
+
+ mtd: nand: new base driver for memory mapped nand devices
+
+ The BF537-STAMP Blackfin board had a driver for working with NAND devices
+ that are simply memory mapped. Since there is nothing Blackfin specific
+ about this, generalize the driver a bit so that everyone can leverage it.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit d27bc728cf35e7d7996fbd77154335e66615b213
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date: Mon May 18 16:06:45 2009 +0200
+
+ env_nand: remove unused variable.
+
+ Remove an unused "total" variable in multiple functions.
+
+ Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 154b5484ac7dcbcd0fb5ba388d930b02f87fa302
+Author: David Brownell <dbrownell@users.sourceforge.net>
+Date: Sun May 10 15:43:01 2009 -0700
+
+ davinci_nand chipselect/init cleanup
+
+ Update chipselect handling in davinci_nand.c so that it can
+ handle 2 GByte chips the same way Linux does: as one device,
+ even though it has two halves with independent chip selects.
+ For such chips the "nand info" command reports:
+
+ Device 0: 2x nand0, sector size 128 KiB
+
+ Switch to use the default chipselect function unless the board
+ really needs its own. The logic for the Sonata board moves out
+ of the driver into board-specific code. (Which doesn't affect
+ current build breakage if its NAND support is enabled...)
+
+ Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 496863b2440dd7cd69a1ad2443a9badd5f8968d1
+Author: Sandeep Paulraj <s-paulraj@ti.com>
+Date: Sat May 9 12:35:20 2009 -0400
+
+ NAND DaVinci: Update to ALE/CLE Mask values
+
+ All DaVinci SOC's use a CLE mask of 0x10 and an ALE mask of 0x8
+ except the DM646x. This was decided by the design team driving the design.
+ This patch updates the CLE and ALE values for DM646x.
+ Updated patches for DM646x will be sent shortly.
+ This applies to u-boot-nand-flash git
+
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 0c1684437ef810c503df29e8d73f63191aa63862
+Author: Sandeep Paulraj <s-paulraj@ti.com>
+Date: Wed Apr 29 09:47:09 2009 -0400
+
+ ARM DaVinci: Changing ALE Mask Value
+
+ The ALE mask used by DaVinci SOCs is wrong. The patch changes the mask value
+ from '0xa' to '0x8'. This is the mask we use for all TI releases.
+
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 6e29ed8e576a6900c5d8dcde36b423ac576894dc
+Author: David Brownell <dbrownell@users.sourceforge.net>
+Date: Tue Apr 28 13:19:53 2009 -0700
+
+ davinci_nand: cleanup II (CONFIG_SYS_DAVINCI_BROKEN_ECC)
+
+ Remove CONFIG_SYS_DAVINCI_BROKEN_ECC option. It's not just nasty;
+ it's also unused by any current boards, and doesn't even match the
+ main U-Boot distributions from TI (which use soft ECC, or 4-bit ECC
+ on newer chips that support it).
+
+ DaVinci GIT kernels since 2.6.24, and mainline Linux since 2.6.30,
+ match non-BROKEN code paths for 1-bit HW ECC. The BROKEN code paths
+ do seem to partially match what MontaVista/TI kernels (4.0/2.6.10,
+ and 5.0/2.6.18) do ... but only for small pages. Large page support
+ is really broken (and it's unclear just what software it was trying
+ to match!), and the ECC layout was making three more bytes available
+ for use by filesystem (or whatever) code.
+
+ Since this option itself seems broken, remove it. Add a comment
+ about the MV/TI compat issue, and the most straightforward way to
+ address it (should someone really need to solve it).
+
+ Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit fcb774777562bb7bcdc53c608d0e6bae906ce0f6
+Author: David Brownell <dbrownell@users.sourceforge.net>
+Date: Tue Apr 28 13:19:50 2009 -0700
+
+ davinci_nand: cleanup I (minor)
+
+ Minor cleanup for DaVinci NAND code:
+
+ - Use I/O addresses from nand_chip; CONFIG_SYS_NAND_BASE won't
+ be defined when there are multiple chipselect lines in use
+ (as with common 2 GByte chips).
+
+ - Cleanup handling of EMIF control registers
+ * Only need one pointer pointing to them
+ * Remove incorrect and unused struct supersetting them
+
+ - Use the standard waitfunc; we don't need a custom version
+
+ - Partial legacy cleanup:
+ * Don't initialize every board like it's a DM6446 EVM
+ * #ifdef a bit more code for BROKEN_ECC
+
+ Sanity checked with small page NAND on dm355 and dm6446 EVMs;
+ and large page on dm355 EVM (packaged as two devices, not one).
+
+ Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 8e5e9b940cdede0debe528cdd7edccccbb3ebf2a
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Jul 7 22:35:02 2009 +0200
+
+ Coding style cleanup; update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
commit d318d0c44d8e91e937c4dad0c5b1d2f6bb9d9fd8
Author: Stefan Roese <sr@denx.de>
Date: Mon Jun 29 13:30:50 2009 +0200
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+commit 6bbced671719518d0e28ff422623cd7ce396cbda
+Author: Mark Jackson <mpfj-list@mimc.co.uk>
+Date: Mon Jun 29 15:59:10 2009 +0100
+
+ Atmel LCD driver GUARDTIME fix
+
+ This patch allows the guard time parameter to be set in
+ the Atmel LCDC driver.
+
+ By default, the previous value of 1 is used, unless the
+ setting is defined elsewhere.
+
+ Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
+
commit 29c35182462feea09f322e51913759a53359a3e0
Author: Roy Zang <tie-fei.zang@freescale.com>
Date: Tue Jun 30 13:56:23 2009 +0800
mecp5200 MPC5200
pf5200 MPC5200
+ vme8349 MPC8349
+
CPCI750 PPC750FX/GX
Yuli Barcohen <yuli@arabellasw.com>
Dirk Eibach <eibach@gdsys.de>
+ compactcenter PPC460EX
+ devconcenter PPC460EX
+ dlvision PPC405EP
gdppc440etx PPC440EP/GR
neo PPC405EP
PCI405 PPC405GP
PLU405 PPC405EP
PMC405 PPC405GP
+ PMC405DE PPC405EP
PMC440 PPC440EPx
VOH405 PPC405EP
VOM405 PPC405EP
KAREF PPC440GX
METROBOX PPC440GX
- XPEDITE1K PPC440GX
Georg Schardt <schardt@team-ctech.de>
Peter Tyser <ptyser@xes-inc.com>
+ XPEDITE1000 PPC440GX
XPEDITE5170 MPC8640
XPEDITE5200 MPC8548
XPEDITE5370 MPC8572
meesc ARM926EJS (AT91SAM9263 SoC)
Sedji Gaouaou<sedji.gaouaou@atmel.com>
- at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC)
+ at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC)
at91sam9m10g45ek ARM926EJS (AT91SAM9G45 SoC)
Marius Gröger <mag@sysgo.de>
SFFSDR ARM926EJS
+Prafulla Wadaskar <prafulla@marvell.com>
+
+ mv88f6281gtw_ge ARM926EJS (Kirkwood SoC)
+ rd6281a ARM926EJS (Kirkwood SoC)
+ sheevaplug ARM926EJS (Kirkwood SoC)
+
Richard Woodruff <r-woodruff2@ti.com>
omap2420h4 ARM1136EJS
canyonlands \
canyonlands_nand \
CMS700 \
+ compactcenter \
CPCI2DP \
CPCI405 \
CPCI4052 \
csb272 \
csb472 \
DASA_SIM \
+ devconcenter \
+ dlvision \
DP405 \
DU405 \
DU440 \
PIP405 \
PLU405 \
PMC405 \
+ PMC405DE \
PMC440 \
PPChameleonEVB \
quad100hd \
WUH405 \
xilinx-ppc440-generic \
xilinx-ppc440-generic_flash \
- XPEDITE1K \
+ XPEDITE1000 \
yellowstone \
yosemite \
yucca \
sbc8349 \
SIMPC8313_LP \
TQM834x \
+ vme8349 \
"
cp946es \
cp966 \
lpd7a400 \
+ mv88f6281gtw_ge \
mx1ads \
mx1fs2 \
netstar \
omap1610inn \
omap5912osk \
omap730p2 \
+ rd6281a \
sbc2410x \
scb9328 \
+ sheevaplug \
smdk2400 \
smdk2410 \
trab \
#
VERSION = 2009
-PATCHLEVEL = 06
+PATCHLEVEL = 08
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
# The "tools" are needed early, so put this first
# Don't include stuff already done in $(LIBS)
SUBDIRS = tools \
- examples \
- api_examples
+ examples/standalone \
+ examples/api
.PHONY : $(SUBDIRS)
ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk))
+# Include autoconf.mk before config.mk so that the config options are available
+# to all top level build files. We need the dummy all: target to prevent the
+# dependency target in autoconf.mk.dep from being the default.
+all:
+sinclude $(obj)include/autoconf.mk.dep
+sinclude $(obj)include/autoconf.mk
+
# load ARCH, BOARD, and CPU configuration
include $(obj)include/config.mk
export ARCH CPU BOARD VENDOR SOC
-ifndef CROSS_COMPILE
+# set default to nothing for native builds
ifeq ($(HOSTARCH),$(ARCH))
-CROSS_COMPILE =
-else
-ifeq ($(ARCH),ppc)
-CROSS_COMPILE = ppc_8xx-
-endif
-ifeq ($(ARCH),arm)
-CROSS_COMPILE = arm-linux-
-endif
-ifeq ($(ARCH),i386)
-CROSS_COMPILE = i386-linux-
-endif
-ifeq ($(ARCH),mips)
-CROSS_COMPILE = mips_4KC-
-endif
-ifeq ($(ARCH),nios)
-CROSS_COMPILE = nios-elf-
-endif
-ifeq ($(ARCH),nios2)
-CROSS_COMPILE = nios2-elf-
+CROSS_COMPILE ?=
endif
-ifeq ($(ARCH),m68k)
-CROSS_COMPILE = m68k-elf-
-endif
-ifeq ($(ARCH),microblaze)
-CROSS_COMPILE = mb-
-endif
-ifeq ($(ARCH),blackfin)
-CROSS_COMPILE = bfin-uclinux-
-endif
-ifeq ($(ARCH),avr32)
-CROSS_COMPILE = avr32-linux-
-endif
-ifeq ($(ARCH),sh)
-CROSS_COMPILE = sh4-linux-
-endif
-ifeq ($(ARCH),sparc)
-CROSS_COMPILE = sparc-elf-
-endif # sparc
-endif # HOSTARCH,ARCH
-endif # CROSS_COMPILE
-
-export CROSS_COMPILE
# load other configuration
include $(TOPDIR)/config.mk
LIBS += drivers/mmc/libmmc.a
LIBS += drivers/mtd/libmtd.a
LIBS += drivers/mtd/nand/libnand.a
-LIBS += drivers/mtd/nand_legacy/libnand_legacy.a
LIBS += drivers/mtd/onenand/libonenand.a
LIBS += drivers/mtd/ubi/libubi.a
LIBS += drivers/mtd/spi/libspi_flash.a
LIBS += drivers/net/sk98lin/libsk98lin.a
LIBS += drivers/pci/libpci.a
LIBS += drivers/pcmcia/libpcmcia.a
+LIBS += drivers/power/libpower.a
LIBS += drivers/spi/libspi.a
ifeq ($(CPU),mpc83xx)
LIBS += drivers/qe/qe.a
LIBBOARD := $(addprefix $(obj),$(LIBBOARD))
# Add GCC lib
-PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
+ifdef USE_PRIVATE_LIBGCC
+ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
+PLATFORM_LIBGCC = -L $(OBJTREE)/lib_$(ARCH) -lgcc
+else
+PLATFORM_LIBGCC = -L $(USE_PRIVATE_LIBGCC) -lgcc
+endif
+else
+PLATFORM_LIBGCC = -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
+endif
+PLATFORM_LIBS += $(PLATFORM_LIBGCC)
+export PLATFORM_LIBS
ifeq ($(CONFIG_NAND_U_BOOT),y)
NAND_SPL = nand_spl
TAG_SUBDIRS += drivers/mmc
TAG_SUBDIRS += drivers/mtd
TAG_SUBDIRS += drivers/mtd/nand
-TAG_SUBDIRS += drivers/mtd/nand_legacy
TAG_SUBDIRS += drivers/mtd/onenand
TAG_SUBDIRS += drivers/mtd/spi
TAG_SUBDIRS += drivers/net
@$(XECHO) Generating $@ ; \
set -e ; \
: Generate the dependancies ; \
- $(CC) -x c -DDO_DEPS_ONLY -M $(HOST_CFLAGS) $(CPPFLAGS) \
+ $(CC) -x c -DDO_DEPS_ONLY -M $(HOSTCFLAGS) $(CPPFLAGS) \
-MQ $(obj)include/autoconf.mk include/common.h > $@
$(obj)include/autoconf.mk: $(obj)include/config.h
sed -n -f tools/scripts/define2mk.sed > $@.tmp && \
mv $@.tmp $@
-sinclude $(obj)include/autoconf.mk.dep
-
#########################################################################
else # !config.mk
all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
pcm030_config \
pcm030_LOWBOOT_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include $(obj)board/phytec/pcm030
+ @ >$(obj)include/config.h
@[ -z "$(findstring LOWBOOT_,$@)" ] || \
{ echo "TEXT_BASE = 0xFF000000" >$(obj)board/phytec/pcm030/config.tmp ; \
echo "... with LOWBOOT configuration" ; \
CMS700_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cms700 esd
+# Compact-Center & DevCon-Center use different U-Boot images
+compactcenter_config \
+devconcenter_config: unconfig
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
+ tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
+ @$(MKCONFIG) -n $@ -a compactcenter ppc ppc4xx compactcenter gdsys
+
CPCI2DP_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd
DASA_SIM_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx dasa_sim esd
+dlvision_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx dlvision gdsys
+
DP405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx dp405 esd
PMC405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc405 esd
+PMC405DE_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc405de esd
+
PMC440_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc440 esd
>> $(obj)board/xilinx/ppc440-generic/config.tmp
@$(MKCONFIG) xilinx-ppc440-generic ppc ppc4xx ppc440-generic xilinx
-XPEDITE1K_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx xpedite1k
+XPEDITE1000_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx xpedite1000 xes
yosemite_config \
yellowstone_config: unconfig
TQM834x_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc
+vme8349_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc mpc83xx vme8349 esd
#########################################################################
## MPC85xx Systems
lpd7a404_config: unconfig
@$(MKCONFIG) $(@:_config=) arm lh7a40x lpd7a40x
+mv88f6281gtw_ge_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood
+
mx1ads_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t mx1ads NULL imx
fi;
@$(MKCONFIG) -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 NULL omap
+rd6281a_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood
+
sbc2410x_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0
scb9328_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t scb9328 NULL imx
+sheevaplug_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood
+
smdk2400_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t smdk2400 samsung s3c24x0
qong_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 qong davedenx mx31
-
#########################################################################
## ARM1176 Systems
#########################################################################
#########################################################################
clean:
- @rm -f $(obj)examples/82559_eeprom $(obj)examples/eepro100_eeprom \
- $(obj)examples/hello_world $(obj)examples/interrupt \
- $(obj)examples/mem_to_mem_idma2intr \
- $(obj)examples/sched $(obj)examples/smc91111_eeprom \
- $(obj)examples/test_burst $(obj)examples/timer
+ @rm -f $(obj)examples/standalone/82559_eeprom \
+ $(obj)examples/standalone/eepro100_eeprom \
+ $(obj)examples/standalone/hello_world \
+ $(obj)examples/standalone/interrupt \
+ $(obj)examples/standalone/mem_to_mem_idma2intr \
+ $(obj)examples/standalone/sched \
+ $(obj)examples/standalone/smc91111_eeprom \
+ $(obj)examples/standalone/test_burst \
+ $(obj)examples/standalone/timer
+ @rm -f $(obj)examples/api/demo{,.bin}
@rm -f $(obj)tools/bmp_logo $(obj)tools/easylogo/easylogo \
$(obj)tools/env/{fw_printenv,fw_setenv} \
$(obj)tools/envcrc \
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl-4k.bin,ipl.map}
- @rm -f $(obj)api_examples/demo $(TIMESTAMP_FILE) $(VERSION_FILE)
+ @rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
@find $(OBJTREE) -type f \
\( -name 'core' -o -name '*.bak' -o -name '*~' \
-o -name '*.o' -o -name '*.a' -o -name '*.exe' \) -print \
CONFIG_CMD_DATE * support for RTC, date/time...
CONFIG_CMD_DHCP * DHCP support
CONFIG_CMD_DIAG * Diagnostics
- CONFIG_CMD_DOC * Disk-On-Chip Support
CONFIG_CMD_DS4510 * ds4510 I2C gpio commands
CONFIG_CMD_DS4510_INFO * ds4510 I2C info command
CONFIG_CMD_DS4510_MEM * ds4510 I2C eeprom/sram commansd
allows for a "silent" boot where a splash screen is
loaded very quickly after power-on.
+ CONFIG_SPLASH_SCREEN_ALIGN
+
+ If this option is set the splash image can be freely positioned
+ on the screen. Environment variable "splashpos" specifies the
+ position as "x,y". If a positive number is given it is used as
+ number of pixel from left/top. If a negative number is given it
+ is used as number of pixel from right/bottom. You can also
+ specify 'm' for centering the image.
+
+ Example:
+ setenv splashpos m,m
+ => image at center of screen
+
+ setenv splashpos 30,20
+ => image at x = 30 and y = 20
+
+ setenv splashpos -10,m
+ => vertically centered image
+ at x = dspWidth - bmpWidth - 9
+
- Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP
If this option is set, additionally to standard BMP
Defines a default value for the IP address of a TFTP
server to contact when using the "tftboot" command.
+ CONFIG_KEEP_SERVERADDR
+
+ Keeps the server's MAC address, in the env 'serveraddr'
+ for passing to bootargs (like Linux's netconsole option)
+
- Multicast TFTP Mode:
CONFIG_MCAST_TFTP
list, October 2002]
-int main (int argc, char *argv[])
+int main(int argc, char *argv[])
{
sighandler_t no_more_time;
- signal (SIGALRM, no_more_time);
- alarm (PROJECT_DEADLINE - toSec (3 * WEEK));
+ signal(SIGALRM, no_more_time);
+ alarm(PROJECT_DEADLINE - toSec (3 * WEEK));
if (available_money > available_manpower) {
- pay consultant to port U-Boot;
+ Pay consultant to port U-Boot;
return 0;
}
Subscribe to u-boot mailing list;
- if (clueless) {
- email ("Hi, I am new to U-Boot, how do I get started?");
- }
+ if (clueless)
+ email("Hi, I am new to U-Boot, how do I get started?");
while (learning) {
Read the README file in the top level directory;
- Read http://www.denx.de/twiki/bin/view/DULG/Manual ;
+ Read http://www.denx.de/twiki/bin/view/DULG/Manual;
+ Read applicable doc/*.README;
Read the source, Luke;
+ /* find . -name "*.[chS]" | xargs grep -i <keyword> */
}
- if (available_money > toLocalCurrency ($2500)) {
- Buy a BDI2000;
- } else {
+ if (available_money > toLocalCurrency ($2500))
+ Buy a BDI3000;
+ else
Add a lot of aggravation and time;
- }
-
- Create your own board support subdirectory;
- Create your own board config file;
-
- while (!running) {
- do {
- Add / modify source code;
- } until (compiles);
- Debug;
- if (clueless)
- email ("Hi, I am having problems...");
+ if (a similar board exists) { /* hopefully... */
+ cp -a board/<similar> board/<myboard>
+ cp include/configs/<similar>.h include/configs/<myboard>.h
+ } else {
+ Create your own board support subdirectory;
+ Create your own board include/configs/<myboard>.h file;
+ }
+ Edit new board/<myboard> files
+ Edit new include/configs/<myboard>.h
+
+ while (!accepted) {
+ while (!running) {
+ do {
+ Add / modify source code;
+ } until (compiles);
+ Debug;
+ if (clueless)
+ email("Hi, I am having problems...");
+ }
+ Send patch file to the U-Boot email list;
+ if (reasonable critiques)
+ Incorporate improvements from email list code review;
+ else
+ Defend code as written;
}
- Send patch file to Wolfgang;
return 0;
}
return 1;
}
-
-#endif /* CONFIG_API */
/*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2009
* BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* (C) Copyright 2000-2003
#include <common.h>
#include <command.h>
#include "asm/m5282.h"
-#include "VCxK.h"
+#include <bmp_layout.h>
+#include <status_led.h>
+#include <bus_vcxk.h>
+
+/*---------------------------------------------------------------------------*/
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned long display_width;
+unsigned long display_height;
+
+/*---------------------------------------------------------------------------*/
int checkboard (void)
{
return size;
}
-
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
int misc_init_r(void)
{
- init_vcxk();
+#ifdef CONFIG_HW_WATCHDOG
+ hw_watchdog_init();
+#endif
+#ifndef CONFIG_VIDEO
+ vcxk_init(16, 16);
+#endif
return 1;
}
+#if defined(CONFIG_VIDEO)
+
+/*
+ ****h* EB+CPU5282-T1/drv_video_init
+ * FUNCTION
+ ***
+ */
+
+int drv_video_init(void)
+{
+ char *s;
+ unsigned long splash;
+
+ printf("Init Video as ");
+
+ if ((s = getenv("displaywidth")) != NULL)
+ display_width = simple_strtoul(s, NULL, 10);
+ else
+ display_width = 256;
+
+ if ((s = getenv("displayheight")) != NULL)
+ display_height = simple_strtoul(s, NULL, 10);
+ else
+ display_height = 256;
+
+ printf("%lu x %lu pixel matrix\n", display_width, display_height);
+
+ MCFCCM_CCR &= ~MCFCCM_CCR_SZEN;
+ MCFGPIO_PEPAR &= ~MCFGPIO_PEPAR_PEPA2;
+
+ vcxk_init(display_width, display_height);
+
+#ifdef CONFIG_SPLASH_SCREEN
+ if ((s = getenv("splashimage")) != NULL) {
+ debug("use splashimage: %s\n", s);
+ splash = simple_strtoul(s, NULL, 16);
+ debug("use splashimage: %x\n", splash);
+ vcxk_acknowledge_wait();
+ video_display_bitmap(splash, 0, 0);
+ }
+#endif
+ return 0;
+}
+#endif
+
/*---------------------------------------------------------------------------*/
-int do_vcimage (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+#ifdef CONFIG_VIDEO
+int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int rcode = 0;
- ulong source;
+ ulong side;
+ ulong bright;
switch (argc) {
- case 2:
- source = simple_strtoul(argv[1],NULL,16);
- vcxk_loadimage(source);
- rcode = 0;
+ case 3:
+ side = simple_strtoul(argv[1], NULL, 10);
+ bright = simple_strtoul(argv[2], NULL, 10);
+ if ((side >= 0) && (side <= 3) &&
+ (bright >= 0) && (bright <= 1000)) {
+ vcxk_setbrightness(side, bright);
+ rcode = 0;
+ } else {
+ printf("parameters out of range\n");
+ printf("Usage:\n%s\n", cmdtp->usage);
+ rcode = 1;
+ }
break;
default:
- cmd_usage(cmdtp);
+ printf("Usage:\n%s\n", cmdtp->usage);
rcode = 1;
break;
}
return rcode;
}
-/***************************************************/
+/*---------------------------------------------------------------------------*/
U_BOOT_CMD(
- vcimage, 2, 0, do_vcimage,
- "loads an image to Display",
- "vcimage addr"
+ bright, 3, 0, do_brightness,
+ "sets the display brightness\n",
+ " <side> <0..1000>\n side: 0/3=both; 1=first; 2=second\n"
);
-/* EOF EB+MCF-EV123c */
+#endif
+
+/* EOF EB+MCF-EV123.c */
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o
+COBJS = $(BOARD).o cfm_flash.o flash.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
+++ /dev/null
-/*
- * (C) Copyright 2005
- * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/m5282.h>
-#include "VCxK.h"
-
-vu_char *vcxk_bws = (vu_char *)(CONFIG_SYS_CS3_BASE);
-#define VCXK_BWS vcxk_bws
-
-static ulong vcxk_driver;
-
-
-ulong search_vcxk_driver(void);
-void vcxk_cls(void);
-void vcxk_setbrightness(short brightness);
-int vcxk_request(void);
-int vcxk_acknowledge_wait(void);
-void vcxk_clear(void);
-
-int init_vcxk(void)
-{
- VIDEO_Invert_CFG &= ~VIDEO_Invert_IO;
- VIDEO_INVERT_PORT |= VIDEO_INVERT_PIN;
- VIDEO_INVERT_DDR |= VIDEO_INVERT_PIN;
-
- VIDEO_REQUEST_PORT |= VIDEO_REQUEST_PIN;
- VIDEO_REQUEST_DDR |= VIDEO_REQUEST_PIN;
-
- VIDEO_ACKNOWLEDGE_DDR &= ~VIDEO_ACKNOWLEDGE_PIN;
-
- vcxk_driver = search_vcxk_driver();
- if (vcxk_driver)
- {
- /* use flash resist driver */
- }
- else
- {
- vcxk_cls();
- vcxk_cls();
- vcxk_setbrightness(1000);
- }
- VIDEO_ENABLE_DDR |= VIDEO_ENABLE_PIN;
- VIDEO_ENABLE_PORT |= VIDEO_ENABLE_PIN;
- VIDEO_ENABLE_PORT &= ~VIDEO_ENABLE_PIN;
- return 1;
-}
-
-void vcxk_loadimage(ulong source)
-{
- int cnt;
- vcxk_acknowledge_wait();
- for (cnt=0; cnt<16384; cnt++)
- {
- VCXK_BWS[cnt*2] = (*(vu_char*) source);
- source++;
- }
- vcxk_request();
-}
-
-void vcxk_cls(void)
-{
- vcxk_acknowledge_wait();
- vcxk_clear();
- vcxk_request();
-}
-
-void vcxk_clear(void)
-{
- int cnt;
- for (cnt=0; cnt<16384; cnt++)
- {
- VCXK_BWS[cnt*2] = 0x00;
- }
-}
-
-void vcxk_setbrightness(short brightness)
-{
- VCXK_BWS[0x8000]=(brightness >> 4) +2;
- VCXK_BWS[0xC000]= (brightness + 23) >> 8;
- VCXK_BWS[0xC001]= (brightness + 23) & 0xFF;
-}
-
-int vcxk_request(void)
-{
- if (vcxk_driver)
- {
- /* use flash resist driver */
- }
- else
- {
- VIDEO_REQUEST_PORT &= ~VIDEO_REQUEST_PIN;
- VIDEO_REQUEST_PORT |= VIDEO_REQUEST_PIN;
- }
- return 1;
-}
-
-int vcxk_acknowledge_wait(void)
-{
- if (vcxk_driver)
- {
- /* use flash resist driver */
- }
- else
- {
- while (!(VIDEO_ACKNOWLEDGE_PORT & VIDEO_ACKNOWLEDGE_PIN));
- }
- return 1;
-}
-
-ulong search_vcxk_driver(void)
-{
- return 0;
-}
-
-/* eof */
*/
#include <common.h>
#include <asm/processor.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include "ps2kbd.h"
int drv_isa_kbd_init (void)
{
int error;
- device_t kbddev ;
+ struct stdio_dev kbddev ;
char *stdinname = getenv ("stdin");
if(isa_kbd_init() == -1)
kbddev.getc = kbd_getc ;
kbddev.tstc = kbd_testc ;
- error = device_register (&kbddev);
+ error = stdio_register (&kbddev);
if(error==0) {
/* check if this is the standard input device */
if(strcmp(stdinname,DEVNAME)==0) {
*/
#include <common.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include "memio.h"
#include <part.h>
int drv_video_init(void)
{
int error, devices = 1 ;
- device_t vgadev ;
+ struct stdio_dev vgadev ;
if (video_inited) return 1;
video_inited = 1;
video_init();
vgadev.tstc = NULL;
vgadev.start = video_start;
- error = device_register (&vgadev);
+ error = stdio_register (&vgadev);
if (error == 0)
{
#include <common.h>
#include <net.h>
#include "mv_regs.h"
-#include "../common/ppc_error_no.h"
-
+#include <asm/errno.h>
/*************************************************************************
**************************************************************************
#include <common.h>
#include <net.h>
#include "mv_regs.h"
-#include "../common/ppc_error_no.h"
+#include <asm/errno.h>
/*************************************************************************
--- /dev/null
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := mv88f6281gtw_ge.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+TEXT_BASE = 0x00600000
--- /dev/null
+/*
+ * Maintainer : Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "mv88f6281gtw_ge.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ kw_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW,
+ MV88F6281GTW_GE_OE_VAL_HIGH,
+ MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ u32 kwmpp_config[] = {
+ MPP0_SPI_SCn,
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ MPP4_GPIO,
+ MPP5_GPO,
+ MPP6_SYSRST_OUTn,
+ MPP7_SPI_SCn,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO,
+ MPP13_GPIO,
+ MPP14_GPIO,
+ MPP15_GPIO,
+ MPP16_GPIO,
+ MPP17_GPIO,
+ MPP18_GPO,
+ MPP19_GPO,
+ MPP20_GPIO,
+ MPP21_GPIO,
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO,
+ MPP49_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config);
+
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_MV88F6281GTW_GE;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = kw_sdram_bar(i);
+ gd->bd->bi_dram[i].size = kw_sdram_bs(i);
+ }
+ return 0;
+}
+
+#ifdef CONFIG_MV88E61XX_SWITCH
+void reset_phy(void)
+{
+ /* configure and initialize switch */
+ struct mv88e61xx_config swcfg = {
+ .name = "egiga0",
+ .vlancfg = MV88E61XX_VLANCFG_ROUTER,
+ .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
+ .led_init = MV88E61XX_LED_INIT_EN,
+ .mdip = MV88E61XX_MDIP_REVERSE,
+ .portstate = MV88E61XX_PORTSTT_FORWARDING,
+ .cpuport = (1 << 5),
+ .ports_enabled = 0x3f
+ };
+
+ mv88e61xx_switch_initialize(&swcfg);
+}
+#endif /* CONFIG_MV88E61XX_SWITCH */
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __MV88F6281GTW_GE_H
+#define __MV88F6281GTW_GE_H
+
+#define MV88F6281GTW_GE_OE_LOW (~((1 << 7) | (1 << 12) \
+ |(1 << 20) | (1 << 21))) /*enable GLED,RLED */
+#define MV88F6281GTW_GE_OE_HIGH (~((1 << 4)|(1 << 6)|(1 << 7)|(1 << 12) \
+ |(1 << 13)|(1 << 16)|(1 << 17)))
+#define MV88F6281GTW_GE_OE_VAL_LOW (1 << 20) /*make GLED on */
+#define MV88F6281GTW_GE_OE_VAL_HIGH ((1 << 6)|(1 << 13)|(1 << 16)|(1 << 17))
+
+
+#endif /* __MV88F6281GTW_GE_H */
--- /dev/null
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := rd6281a.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+TEXT_BASE = 0x00600000
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "rd6281a.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ kw_config_gpio(RD6281A_OE_VAL_LOW,
+ RD6281A_OE_VAL_HIGH,
+ RD6281A_OE_LOW, RD6281A_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GE1_0,
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GE1_14,
+ MPP35_GPIO,
+ MPP36_AUDIO_SPDIFI,
+ MPP37_AUDIO_SPDIFO,
+ MPP38_GPIO,
+ MPP39_TDM_SPI_CS0,
+ MPP40_TDM_SPI_SCK,
+ MPP41_TDM_SPI_MISO,
+ MPP42_TDM_SPI_MOSI,
+ MPP43_TDM_CODEC_INTn,
+ MPP44_GPIO,
+ MPP45_TDM_PCLK,
+ MPP46_TDM_FS,
+ MPP47_TDM_DRX,
+ MPP48_TDM_DTX,
+ MPP49_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config);
+
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_RD88F6281;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = kw_sdram_bar(i);
+ gd->bd->bi_dram[i].size = kw_sdram_bs(i);
+ }
+ return 0;
+}
+
+void mv_phy_88e1116_init(char *name)
+{
+ u16 reg;
+ u16 devadr;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ if (miiphy_read (name, devadr, PHY_BMCR, ®) != 0) {
+ printf("Err..(%s) PHY status read failed\n", __FUNCTION__);
+ return;
+ }
+ if (miiphy_write (name, devadr, PHY_BMCR, reg | 0x8000) != 0) {
+ printf("Err..(%s) PHY reset failed\n", __FUNCTION__);
+ return;
+ }
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+
+/* Configure and enable Switch and PHY */
+void reset_phy(void)
+{
+ /* configure and initialize switch */
+ struct mv88e61xx_config swcfg = {
+ .name = "egiga0",
+ .vlancfg = MV88E61XX_VLANCFG_ROUTER,
+ .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
+ .led_init = MV88E61XX_LED_INIT_EN,
+ .portstate = MV88E61XX_PORTSTT_FORWARDING,
+ .cpuport = (1 << 5),
+ .ports_enabled = 0x3f,
+ };
+
+ mv88e61xx_switch_initialize(&swcfg);
+
+ /* configure and initialize PHY */
+ mv_phy_88e1116_init("egiga1");
+}
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __RD6281A_H
+#define __RD6281A_H
+
+#define RD6281A_OE_LOW (~(1 << 7))
+#define RD6281A_OE_HIGH (~(1 << 2 | 1 << 12))
+#define RD6281A_OE_VAL_LOW (0)
+#define RD6281A_OE_VAL_HIGH (1 << 12)
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __RD6281A_H */
--- /dev/null
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := sheevaplug.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+TEXT_BASE = 0x00600000
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "sheevaplug.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ kw_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
+ SHEEVAPLUG_OE_VAL_HIGH,
+ SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_UART0_RTS,
+ MPP9_UART0_CTS,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO,
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_TSMP9,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO,
+ MPP49_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config);
+
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = kw_sdram_bar(i);
+ gd->bd->bi_dram[i].size = kw_sdram_bs(i);
+ }
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __SHEEVAPLUG_H
+#define __SHEEVAPLUG_H
+
+#define SHEEVAPLUG_OE_LOW (~(0))
+#define SHEEVAPLUG_OE_HIGH (~(0))
+#define SHEEVAPLUG_OE_VAL_LOW (1 << 29) /* USB_PWEN low */
+#define SHEEVAPLUG_OE_VAL_HIGH (1 << 17) /* LED pin high */
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __SHEEVAPLUG_H */
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o
-COBJS += bootstrap.o
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
SOBJS := init.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-#include <asm/io.h>
-
-/*
- * NOR and NAND boot options change bytes 5, 6, 8, 9, 11. The
- * values are independent of the rest of the clock settings.
- */
-
-#define NAND_COMPATIBLE 0x01
-#define NOR_COMPATIBLE 0x02
-
-#define I2C_EEPROM_ADDR 0x52
-
-static char *config_labels[] = {
- "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
- "CPU: 800 PLB: 200 OPB: 100 EBC: 100",
- "CPU:1000 PLB: 200 OPB: 100 EBC: 100",
- "CPU:1066 PLB: 266 OPB: 88 EBC: 88",
- NULL
-};
-
-static u8 boot_configs[][17] = {
- {
- (NAND_COMPATIBLE | NOR_COMPATIBLE),
- 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, 0x40, 0x08,
- 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- },
- {
- (NAND_COMPATIBLE | NOR_COMPATIBLE),
- 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, 0x40, 0x08,
- 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- },
- {
- (NAND_COMPATIBLE | NOR_COMPATIBLE),
- 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0, 0x40, 0x08,
- 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- },
- {
- (NAND_COMPATIBLE | NOR_COMPATIBLE),
- 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0, 0x40, 0x08,
- 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- },
- {
- 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
- }
-};
-
-/*
- * Bytes 5,6,8,9,11 change for NAND boot
- */
-#if 0
-/*
- * Values for 512 page size NAND chips, not used anymore, just
- * keep them here for reference
- */
-static u8 nand_boot[] = {
- 0x90, 0x01, 0xa0, 0x68, 0x58
-};
-#else
-/*
- * Values for 2k page size NAND chips
- */
-static u8 nand_boot[] = {
- 0x90, 0x01, 0xa0, 0xe8, 0x58
-};
-#endif
-
-static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- u8 *buf, b_nand;
- int x, y, nbytes, selcfg;
- extern char console_buffer[];
-
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
-
- if ((strcmp(argv[1], "nor") != 0) &&
- (strcmp(argv[1], "nand") != 0)) {
- printf("Unsupported boot-device - only nor|nand support\n");
- return 1;
- }
-
- /* set the nand flag based on provided input */
- if ((strcmp(argv[1], "nand") == 0))
- b_nand = 1;
- else
- b_nand = 0;
-
- printf("Available configurations: \n\n");
-
- if (b_nand) {
- for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
- /* filter on nand compatible */
- if (boot_configs[x][0] & NAND_COMPATIBLE) {
- printf(" %d - %s\n", (y+1), config_labels[x]);
- y++;
- }
- }
- } else {
- for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
- /* filter on nor compatible */
- if (boot_configs[x][0] & NOR_COMPATIBLE) {
- printf(" %d - %s\n", (y+1), config_labels[x]);
- y++;
- }
- }
- }
-
- do {
- nbytes = readline(" Selection [1-x / quit]: ");
-
- if (nbytes) {
- if (strcmp(console_buffer, "quit") == 0)
- return 0;
- selcfg = simple_strtol(console_buffer, NULL, 10);
- if ((selcfg < 1) || (selcfg > y))
- nbytes = 0;
- }
- } while (nbytes == 0);
-
-
- y = (selcfg - 1);
-
- for (x = 0; boot_configs[x][0] != 0; x++) {
- if (b_nand) {
- if (boot_configs[x][0] & NAND_COMPATIBLE) {
- if (y > 0)
- y--;
- else if (y < 1)
- break;
- }
- } else {
- if (boot_configs[x][0] & NOR_COMPATIBLE) {
- if (y > 0)
- y--;
- else if (y < 1)
- break;
- }
- }
- }
-
- buf = &boot_configs[x][1];
-
- if (b_nand) {
- buf[5] = nand_boot[0];
- buf[6] = nand_boot[1];
- buf[8] = nand_boot[2];
- buf[9] = nand_boot[3];
- buf[11] = nand_boot[4];
- }
-
- if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
- printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
- udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
-
- printf("Done\n");
- printf("Please power-cycle the board for the changes to take effect\n");
-
- return 0;
-}
-
-U_BOOT_CMD(
- bootstrap, 2, 0, do_bootstrap,
- "program the I2C bootstrap EEPROM",
- "<nand|nor> - strap to boot from NAND or NOR flash"
-);
#define BOARD_GLACIER 3
#define BOARD_ARCHES 4
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+#if defined(CONFIG_ARCHES)
+u32 ddr_wrdtr(u32 default_val) {
+ return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
+}
+#else
+u32 ddr_wrdtr(u32 default_val) {
+ return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
+}
+
+u32 ddr_clktr(u32 default_val) {
+ return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
+}
+#endif
+
#if defined(CONFIG_ARCHES)
/*
* FPGA read/write helper macros
out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
}
+#else
+static int pvr_460ex(void)
+{
+ u32 pvr = get_pvr();
+
+ if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
+ (pvr == PVR_460EX_RB))
+ return 1;
+
+ return 0;
+}
#endif /* defined(CONFIG_ARCHES) */
int board_early_init_f(void)
{
#if !defined(CONFIG_ARCHES)
u32 sdr0_cust0;
- u32 pvr = get_pvr();
#endif
/*
mtdcr(AHB_TOP, 0x8000004B);
mtdcr(AHB_BOT, 0x8000004B);
- if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
+ if (pvr_460ex()) {
/*
* Configure USB-STP pins as alternate and not GPIO
* It seems to be neccessary to configure the STP pins as GPIO
int checkboard(void)
{
char *s = getenv("serial#");
- u32 pvr = get_pvr();
- if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) {
- printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
- gd->board_type = BOARD_GLACIER;
- } else {
+ if (pvr_460ex()) {
printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
gd->board_type = BOARD_CANYONLANDS_PCIE;
else
gd->board_type = BOARD_CANYONLANDS_SATA;
+ } else {
+ printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
+ gd->board_type = BOARD_GLACIER;
}
switch (gd->board_type) {
}
#endif /* !defined(CONFIG_ARCHES) */
-/*
- * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
- * board specific values.
- */
-u32 ddr_wrdtr(u32 default_val) {
- return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
-}
-
-u32 ddr_clktr(u32 default_val) {
- return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
-}
-
#if defined(CONFIG_NAND_U_BOOT)
/*
* NAND booting U-Boot version uses a fixed initialization, since the whole
{
u32 sdr0_srst1 = 0;
u32 eth_cfg;
- u32 pvr = get_pvr();
u8 val;
/*
/* Set the for 2 RGMII mode */
/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
- if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
+ if (pvr_460ex())
eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
else
eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
void ft_board_setup(void *blob, bd_t *bd)
{
- u32 val[4];
- int rc;
-
__ft_board_setup(blob, bd);
- /* Fixup NOR mapping */
- val[0] = CONFIG_SYS_NOR_CS; /* chip select number */
- val[1] = 0; /* always 0 */
- val[2] = CONFIG_SYS_FLASH_BASE_PHYS_L; /* we fixed up this address */
- val[3] = gd->bd->bi_flashsize;
- rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
- val, sizeof(val), 1);
- if (rc) {
- printf("Unable to update property NOR mapping, err=%s\n",
- fdt_strerror(rc));
- }
-
if (gd->board_type == BOARD_CANYONLANDS_SATA) {
/*
* When SATA is selected we need to disable the first PCIe
--- /dev/null
+/*
+ * (C) Copyright 2008-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+ {
+ "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "800-nor", "NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1000-nor", "NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1066-nor", "NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88",
+ {
+ 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1066-nand", "NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88",
+ {
+ 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o cmd_pll.o
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+ {
+ "333-nor","NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83",
+ {
+ 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66",
+ {
+ 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
+ {
+ 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
+ {
+ 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00,
+ 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00,
+ 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111",
+ {
+ 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-/*
- * ehnus: change pll frequency.
- * Wed Sep 5 11:45:17 CST 2007
- * hsun@udtech.com.cn
- */
-
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <i2c.h>
-
-#ifdef CONFIG_CMD_EEPROM
-
-#define EEPROM_CONF_OFFSET 0
-#define EEPROM_TEST_OFFSET 16
-#define EEPROM_SDSTP_PARAM 16
-
-#define PLL_NAME_MAX 12
-#define BUF_STEP 8
-
-/* eeprom_wirtes 8Byte per op. */
-#define EEPROM_ALTER_FREQ(freq) \
- do { \
- int __i; \
- for (__i = 0; __i < 2; __i++) \
- eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, \
- EEPROM_CONF_OFFSET + __i*BUF_STEP, \
- pll_select[freq], \
- BUF_STEP + __i*BUF_STEP); \
- } while (0)
-
-#define PDEBUG
-#ifdef PDEBUG
-#define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET)
-#else
-#define PLL_DEBUG
-#endif
-
-typedef enum {
- PLL_ebc20,
- PLL_333,
- PLL_4001,
- PLL_4002,
- PLL_533,
- PLL_600,
- PLL_666, /* For now, kilauea can't support */
- RCONF,
- WTEST,
- PLL_TOTAL
-} pll_freq_t;
-
-static const char
-pll_name[][PLL_NAME_MAX] = {
- "PLL_ebc20",
- "PLL_333",
- "PLL_400@1",
- "PLL_400@2",
- "PLL_533",
- "PLL_600",
- "PLL_666",
- "RCONF",
- "WTEST",
- ""
-};
-
-/*
- * ehnus:
- */
-static uchar
-pll_select[][EEPROM_SDSTP_PARAM] = {
- /* 0: CPU 333MHz EBC 20MHz, for test only */
- {
- 0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- },
-
- /* 0: 333 */
- {
- 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- },
-
- /* 1: 400_266 */
- {
- 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- },
-
- /* 2: 400 */
- {
- 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- },
-
- /* 3: 533 */
- {
- 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- },
-
- /* 4: 600 */
- {
- 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- },
-
- /* 5: 666 */
- {
- 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- },
-
- {}
-};
-
-static uchar
-testbuf[EEPROM_SDSTP_PARAM] = {
- 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
- 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
-};
-
-static void
-pll_debug(int off)
-{
- int i;
- uchar buffer[EEPROM_SDSTP_PARAM];
-
- memset(buffer, 0, sizeof(buffer));
- eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off,
- buffer, EEPROM_SDSTP_PARAM);
-
- printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
- for (i = 0; i < EEPROM_SDSTP_PARAM; i++)
- printf("%02x ", buffer[i]);
- printf("\n");
-}
-
-static void
-test_write(void)
-{
- printf("Debug: test eeprom_write ... ");
-
- /*
- * Write twice, 8 bytes per write
- */
- eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
- testbuf, 8);
- eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
- testbuf, 16);
- printf("done\n");
-
- pll_debug(EEPROM_TEST_OFFSET);
-}
-
-int
-do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- char c = '\0';
- pll_freq_t pll_freq;
- if (argc < 2) {
- cmd_usage(cmdtp);
- goto ret;
- }
-
- for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++)
- if (!strcmp(pll_name[pll_freq], argv[1]))
- break;
-
- switch (pll_freq) {
- case PLL_ebc20:
- case PLL_333:
- case PLL_4001:
- case PLL_4002:
- case PLL_533:
- case PLL_600:
- EEPROM_ALTER_FREQ(pll_freq);
- break;
-
- case PLL_666: /* not support */
- printf("Choose this option will result in a boot failure."
- "\nContinue? (Y/N): ");
-
- c = getc(); putc('\n');
-
- if ((c == 'y') || (c == 'Y')) {
- EEPROM_ALTER_FREQ(pll_freq);
- break;
- }
- goto ret;
-
- case RCONF:
- pll_debug(EEPROM_CONF_OFFSET);
- goto ret;
- case WTEST:
- printf("DEBUG: write test\n");
- test_write();
- goto ret;
-
- default:
- printf("Invalid options\n\n");
- cmd_usage(cmdtp);
- goto ret;
- }
-
- printf("PLL set to %s, "
- "reset the board to take effect\n", pll_name[pll_freq]);
-
- PLL_DEBUG;
-ret:
- return 0;
-}
-
-U_BOOT_CMD(
- pllalter, CONFIG_SYS_MAXARGS, 1, do_pll_alter,
- "change pll frequence",
- "pllalter <selection> - change pll frequence \n\n\
- ** New freq take effect after reset. ** \n\
- ----------------------------------------------\n\
- PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\
- \t Same as PLL_333 \n\
- \t except \n\
- \t EBC: 20 MHz \n\
- ----------------------------------------------\n\
- PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\
- \t VCO: 666 MHz \n\
- \t CPU: 333 MHz \n\
- \t PLB: 166 MHz \n\
- \t OPB: 83 MHz \n\
- \t DDR: 83 MHz \n\
- ------------------------------------------------\n\
- PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\
- \t VCO: 800 MHz \n\
- \t CPU: 400 MHz \n\
- \t PLB: 133 MHz \n\
- \t OPB: 66 MHz \n\
- \t DDR: 133 MHz \n\
- ------------------------------------------------\n\
- PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\
- \t VCO: 800 MHz \n\
- \t CPU: 400 MHz \n\
- \t PLB: 200 MHz \n\
- \t OPB: 100 MHz \n\
- \t DDR: 200 MHz \n\
- ----------------------------------------------\n\
- PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\
- \t VCO: 1066 MHz \n\
- \t CPU: 533 MHz \n\
- \t PLB: 177 MHz \n\
- \t OPB: 88 MHz \n\
- \t DDR: 177 MHz \n\
- ----------------------------------------------\n\
- PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\
- \t VCO: 1200 MHz \n\
- \t CPU: 600 MHz \n\
- \t PLB: 200 MHz \n\
- \t OPB: 100 MHz \n\
- \t DDR: 200 MHz \n\
- ----------------------------------------------\n\
- PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\
- \t VCO: 1333 MHz \n\
- \t CPU: 666 MHz \n\
- \t PLB: 166 MHz \n\
- \t OPB: 83 MHz \n\
- \t DDR: 166 MHz \n\
- -----------------------------------------------\n\
- RCONF: Read current eeprom configuration. \n\
- -----------------------------------------------\n\
- WTEST: Test EEPROM write with predefined values\n\
- -----------------------------------------------"
-);
-
-#endif /* CONFIG_CMD_EEPROM */
# ---------------------------------------------------------
# Complete the configuration
# ---------------------------------------------------------
-$MKCONFIG -a integrator$1 arm $cpu integrator armltd;
-echo "Variant:: $variant with core $cpu"
+$MKCONFIG -a -n "${2%%_config}" integrator$1 arm $cpu integrator armltd
+echo "Variant: $variant with core $cpu"
#include <asm/mach-common/bits/dma.h>
#include <i2c.h>
#include <linux/types.h>
-#include <devices.h>
+#include <stdio_dev.h>
int gunzip(void *, int, unsigned char *, unsigned long *);
int drv_video_init(void)
{
int error, devices = 1;
- device_t videodev;
+ struct stdio_dev videodev;
u8 *dst;
u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
videodev.putc = video_putc; /* 'putc' function */
videodev.puts = video_puts; /* 'puts' function */
- error = device_register(&videodev);
+ error = stdio_register(&videodev);
return (error == 0) ? devices : error;
}
#include <asm/mach-common/bits/dma.h>
#include <i2c.h>
#include <linux/types.h>
-#include <devices.h>
+#include <stdio_dev.h>
int gunzip(void *, int, unsigned char *, unsigned long *);
int drv_video_init(void)
{
- device_t videodev;
+ struct stdio_dev videodev;
video_init((void *)NTSC_FRAME_ADDR);
videodev.ext = DEV_EXT_VIDEO;
videodev.flags = DEV_FLAGS_SYSTEM;
- return device_register(&videodev);
+ return stdio_register(&videodev);
}
*/
#include <common.h>
+#include <netdev.h>
#include <config.h>
#include <command.h>
#include <asm/blackfin.h>
return 0;
}
+
+#ifdef CONFIG_SMC911X
+int board_eth_init(bd_t *bis)
+{
+ return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
#include <asm/mach-common/bits/dma.h>
#include <i2c.h>
#include <linux/types.h>
-#include <devices.h>
+#include <stdio_dev.h>
int gunzip(void *, int, unsigned char *, unsigned long *);
int drv_video_init(void)
{
int error, devices = 1;
- device_t videodev;
+ struct stdio_dev videodev;
u8 *dst;
u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
videodev.putc = video_putc; /* 'putc' function */
videodev.puts = video_puts; /* 'puts' function */
- error = device_register(&videodev);
+ error = stdio_register(&videodev);
return (error == 0) ? devices : error;
}
#include <watchdog.h>
#include <command.h>
#include <malloc.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <net.h>
#include <timestamp.h>
#include <dtt.h>
LED_REG(3) = msg[0];
}
+#ifdef CONFIG_CMD_DOC
/*
* Map onboard TSOP-16MB DOC FLASH chip.
*/
{
doc_probe(DOC_BASE_ADDR);
}
+#endif
#define NV_ADDR ((volatile unsigned char *) CONFIG_ENV_ADDR)
#include <common.h>
#include <config.h>
#include <command.h>
+#include <netdev.h>
#include <asm/blackfin.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
#include <common.h>
#if defined(CONFIG_CMD_NAND)
-#if !defined(CONFIG_NAND_LEGACY)
#include <nand.h>
#include <asm/arch/pxa-regs.h>
return 0;
}
-#else
- #error "U-Boot legacy NAND support not available for Monahans DFC."
-#endif
#endif
#include <command.h>
#include <image.h>
#include <asm/byteorder.h>
-#if defined(CONFIG_NAND_LEGACY)
-#include <linux/mtd/nand_legacy.h>
-#endif
#include <fat.h>
#include <part.h>
extern int flash_sect_protect (int, ulong, ulong);
extern int flash_write (char *, ulong, ulong);
-#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
-/* references to names in cmd_nand.c */
-#define NANDRW_READ 0x01
-#define NANDRW_WRITE 0x00
-#define NANDRW_JFFS2 0x02
-#define NANDRW_JFFS2_SKIP 0x04
-extern struct nand_chip nand_dev_desc[];
-extern int nand_legacy_rw(struct nand_chip* nand, int cmd,
- size_t start, size_t len,
- size_t * retlen, u_char * buf);
-extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs,
- size_t len, int clean);
-#endif
-
extern block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
int au_check_cksum_valid(int i, long nbytes)
int off, rc;
uint nbytes;
int k;
-#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
- int total;
-#endif
hdr = (image_header_t *)LOAD_ADDR;
#if defined(CONFIG_FIT)
au_image[i].name);
debug ("flash_sect_erase(%lx, %lx);\n", start, end);
flash_sect_erase (start, end);
- } else {
-#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
- printf ("Updating NAND FLASH with image %s\n",
- au_image[i].name);
- debug ("nand_legacy_erase(%lx, %lx);\n", start, end);
- rc = nand_legacy_erase (nand_dev_desc, start,
- end - start + 1, 0);
- debug ("nand_legacy_erase returned %x\n", rc);
-#endif
}
udelay(10000);
rc = flash_write ((char *)addr, start,
(nbytes + 1) & ~1);
} else {
-#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
- debug ("nand_legacy_rw(%p, %lx, %x)\n",
- addr, start, nbytes);
- rc = nand_legacy_rw (nand_dev_desc,
- NANDRW_WRITE | NANDRW_JFFS2,
- start, nbytes, (size_t *)&total,
- (uchar *)addr);
- debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n",
- rc, total, nbytes);
-#else
rc = -1;
-#endif
}
if (rc != 0) {
printf ("Flashing failed due to error %d\n", rc);
if (au_image[i].type != AU_NAND) {
rc = crc32 (0, (uchar *)(start + off),
image_get_data_size (hdr));
- } else {
-#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
- rc = nand_legacy_rw (nand_dev_desc,
- NANDRW_READ | NANDRW_JFFS2 |
- NANDRW_JFFS2_SKIP,
- start, nbytes, (size_t *)&total,
- (uchar *)addr);
- rc = crc32 (0, (uchar *)(addr + off),
- image_get_data_size (hdr));
-#endif
}
if (rc != image_get_dcrc (hdr)) {
printf ("Image %s Bad Data Checksum After COPY\n",
#include <common.h>
#include <net.h>
#include "mv_regs.h"
-#include "../../Marvell/common/ppc_error_no.h"
+#include <asm/errno.h>
/*************************************************************************
#include <command.h>
#include <malloc.h>
-
-#if 0
-#define FPGA_DEBUG
-#endif
+#undef FPGA_DEBUG
DECLARE_GLOBAL_DATA_PTR;
*/
#include "../common/fpga.c"
-
/*
* include common auto-update code (for esd boards)
*/
/* Prototypes */
int gunzip(void *, int, unsigned char *, unsigned long *);
-int board_early_init_f (void)
+int board_early_init_f(void)
{
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
* EBC Configuration Register: set ready timeout to
* 512 ebc-clks -> ca. 15 us
*/
- mtebc (epcr, 0xa8400000); /* ebc always driven */
+ mtebc(epcr, 0xa8400000); /* ebc always driven */
return 0;
}
-int misc_init_r (void)
+int misc_init_r(void)
{
- unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
- unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
unsigned char *dst;
unsigned char fctr;
ulong len = sizeof(fpgadata);
gd->bd->bi_flashoffset = 0;
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
- printf ("GUNZIP ERROR - must RESET board to recover\n");
- do_reset (NULL, 0, 0, NULL);
+ if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
+ (uchar *)fpgadata, &len) != 0) {
+ printf("GUNZIP ERROR - must RESET board to recover\n");
+ do_reset(NULL, 0, 0, NULL);
}
status = fpga_boot(dst, len);
for (index=0;index<1000;index++)
udelay(1000);
}
- putc ('\n');
+ putc('\n');
do_reset(NULL, 0, 0, NULL);
}
printf("%s ", &(dst[index+1]));
index += len+3;
}
- putc ('\n');
+ putc('\n');
free(dst);
/*
* Reset external DUARTs
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
udelay(10);
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
udelay(1000);
/*
* Set NAND-FLASH GPIO signals to default
*/
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
+ in_be32((void*)GPIO0_OR) &
+ ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
/*
* Setup EEPROM write protection
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
- out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+ out_be32((void*)GPIO0_TCR,
+ in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
/*
* Enable interrupts in exar duart mcr[3]
*/
- out_8(duart0_mcr, 0x08);
- out_8(duart1_mcr, 0x08);
+ out_8((void *)DUART0_BA + 4, 0x08);
+ out_8((void *)DUART1_BA + 4, 0x08);
/*
* Enable auto RS485 mode in 2nd external uart
out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
out_8((void *)DUART1_BA + 3, 0); /* write LCR */
- return (0);
+ return 0;
}
/*
* Check Board Identity:
*/
-int checkboard (void)
+int checkboard(void)
{
char str[64];
- int i = getenv_r ("serial#", str, sizeof(str));
+ int i = getenv_r("serial#", str, sizeof(str));
- puts ("Board: ");
+ puts("Board: ");
- if (i == -1) {
- puts ("### No HW ID - assuming PLU405");
- } else {
+ if (i == -1)
+ puts("### No HW ID - assuming PLU405");
+ else
puts(str);
- }
- putc ('\n');
+ putc('\n');
return 0;
}
*/
if (on) { /* assert RESET */
out_be16((void *)FPGA_CTRL,
- in_be16((void *)FPGA_CTRL) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
+ in_be16((void *)FPGA_CTRL) &
+ ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
} else { /* release RESET */
out_be16((void *)FPGA_CTRL,
- in_be16((void *)FPGA_CTRL) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
+ in_be16((void *)FPGA_CTRL) |
+ CONFIG_SYS_FPGA_CTRL_CF_RESET);
}
}
#endif /* CONFIG_IDE_RESET */
#if defined(CONFIG_SYS_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
- * <state> -1: deliver current state
- * 0: disable write
- * 1: enable write
- * Returns: -1: wrong device address
- * 0: dis-/en- able done
- * 0/1: current state if <state> was -1.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
*/
-int eeprom_write_enable (unsigned dev_addr, int state)
+int eeprom_write_enable(unsigned dev_addr, int state)
{
if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
return -1;
case 1:
/* Enable write access, clear bit GPIO0. */
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
+ in_be32((void*)GPIO0_OR) &
+ ~CONFIG_SYS_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO0. */
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+ in_be32((void*)GPIO0_OR) |
+ CONFIG_SYS_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
- state = (0 == (in_be32((void*)GPIO0_OR) &
- CONFIG_SYS_EEPROM_WP));
+ state = ((in_be32((void*)GPIO0_OR) &
+ CONFIG_SYS_EEPROM_WP) == 0);
break;
}
}
return state;
}
-int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int query = argc == 1;
int state = 0;
if (query) {
/* Query write access state. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
if (state < 0) {
- puts ("Query of write access state failed.\n");
+ puts("Query of write access state failed.\n");
} else {
- printf ("Write access for device 0x%0x is %sabled.\n",
- CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ printf("Write access for device 0x%0x is %sabled.\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ state ? "en" : "dis");
state = 0;
}
} else {
- if ('0' == argv[1][0]) {
+ if (argv[1][0] == '0') {
/* Disable write access. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
+ 0);
} else {
/* Enable write access. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
- }
- if (state < 0) {
- puts ("Setup of write access state failed.\n");
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
+ 1);
}
+ if (state < 0)
+ puts("Setup of write access state failed.\n");
}
return state;
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y = $(BOARD).o
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+COBJS += ../common/cmd_loadpci.o
+
+COBJS := $(COBJS-y)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2008-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+ {
+ "133",
+ "CPU: 133 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66",
+ {
+ 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x40, 0x12, 0x12, 0x42, 0x3e, 0x00, 0x00
+ }
+ },
+ {
+ "266",
+ "CPU: 266 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66",
+ {
+ 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x50, 0x22, 0x2d, 0x42, 0x3e, 0x00, 0x00
+ }
+ },
+ {
+ "333",
+ "CPU: 333 PLB: 111 OPB: 55 EBC: 55 PCI: 55/111",
+ {
+ 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x60, 0x29, 0x2d, 0x42, 0xbe, 0x00, 0x00
+ }
+ },
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+TEXT_BASE = 0xFFFC0000
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/4xx_pci.h>
+#include <command.h>
+#include <malloc.h>
+
+/*
+ * PMC405-DE cpld registers
+ * - all registers are 8 bit
+ * - all registers are on 32 bit addesses
+ */
+struct pmc405de_cpld {
+ /* cpld design version */
+ u8 version;
+ u8 reserved0[3];
+
+ /* misc. status lines */
+ u8 status;
+ u8 reserved1[3];
+
+ /*
+ * gated control flags
+ * gate bit(s) must be written with '1' to
+ * access control flag
+ */
+ u8 control;
+ u8 reserved2[3];
+};
+
+#define CPLD_VERSION_MASK 0x0f
+#define CPLD_CONTROL_POSTLED_N 0x01
+#define CPLD_CONTROL_POSTLED_GATE 0x02
+#define CPLD_CONTROL_RESETOUT_N 0x40
+#define CPLD_CONTROL_RESETOUT_N_GATE 0x80
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void __ft_board_setup(void *blob, bd_t *bd);
+extern void pll_write(u32 a, u32 b);
+
+static int wait_for_pci_ready_done;
+
+static int is_monarch(void);
+static int pci_is_66mhz(void);
+static int board_revision(void);
+static int cpld_revision(void);
+static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div);
+
+int board_early_init_f(void)
+{
+ u32 pllmr0, pllmr1;
+
+ /*
+ * check M66EN and patch PLB:PCI divider for 66MHz PCI
+ *
+ * fCPU==333MHz && fPCI==66MHz (PLBDiv==3 && M66EN==1): PLB/PCI=1
+ * fCPU==333MHz && fPCI==33MHz (PLBDiv==3 && M66EN==0): PLB/PCI=2
+ * fCPU==133|266MHz && fPCI==66MHz (PLBDiv==1|2 && M66EN==1): PLB/PCI=2
+ * fCPU==133|266MHz && fPCI==33MHz (PLBDiv==1|2 && M66EN==0): PLB/PCI=3
+ *
+ * calling upd_plb_pci_div() may end in calling pll_write() which will
+ * do a chip reset and never return.
+ */
+ pllmr0 = mfdcr(CPC0_PLLMR0);
+ pllmr1 = mfdcr(CPC0_PLLMR1);
+
+ if ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) == PLLMR0_CPU_PLB_DIV_3) {
+ /* fCPU=333MHz, fPLB=111MHz */
+ if (pci_is_66mhz())
+ upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_1);
+ else
+ upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
+ } else {
+ /* fCPU=133|266MHz, fPLB=133MHz */
+ if (pci_is_66mhz())
+ upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
+ else
+ upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_3);
+ }
+
+ /*
+ * IRQ 25 (EXT IRQ 0) PCI-INTA#; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) PCI-INTB#; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) PCI-INTC#; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) PCI-INTD#; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) ETH0-PHY-IRQ#; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive
+ */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
+ mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
+ mtdcr(uictr, 0x10000000); /* set int trigger levels */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest prio */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register:
+ * - set ready timeout to 512 ebc-clks -> ca. 15 us
+ * - EBC lines are always driven
+ */
+ mtebc(epcr, 0xa8400000);
+
+ return 0;
+}
+
+static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div)
+{
+ if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != div)
+ pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | div, pllmr1);
+}
+
+int misc_init_r(void)
+{
+ int i;
+ struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+ struct pmc405de_cpld *cpld =
+ (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
+
+ if (!is_monarch()) {
+ /* PCI configuration done: release EREADY */
+ setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EREADY);
+ setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_EREADY);
+ }
+
+ /* turn off POST LED */
+ out_8(&cpld->control,
+ CPLD_CONTROL_POSTLED_N | CPLD_CONTROL_POSTLED_GATE);
+
+ /* turn on LEDs: RUN, A, B */
+ clrbits_be32(&gpio0->or,
+ CONFIG_SYS_GPIO_LEDRUN_N |
+ CONFIG_SYS_GPIO_LEDA_N |
+ CONFIG_SYS_GPIO_LEDB_N);
+
+ for (i=0; i < 200; i++)
+ udelay(1000);
+
+ /* turn off LEDs: A, B */
+ setbits_be32(&gpio0->or,
+ CONFIG_SYS_GPIO_LEDA_N |
+ CONFIG_SYS_GPIO_LEDB_N);
+
+ return (0);
+}
+
+static int is_monarch(void)
+{
+ struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+ return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_MONARCH_N) == 0;
+}
+
+static int pci_is_66mhz(void)
+{
+ struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+ return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_M66EN);
+}
+
+static int board_revision(void)
+{
+ struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+ return ((in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_HWREV_MASK) >>
+ CONFIG_SYS_GPIO_HWREV_SHIFT);
+}
+
+static int cpld_revision(void)
+{
+ struct pmc405de_cpld *cpld =
+ (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
+ return ((in_8(&cpld->version) & CPLD_VERSION_MASK));
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard(void)
+{
+ puts("Board: esd GmbH - PMC-CPU/405-DE");
+
+ gd->board_type = board_revision();
+ printf(", Rev 1.%ld, ", gd->board_type);
+
+ if (!is_monarch())
+ puts("non-");
+
+ printf("monarch, PCI=%s MHz, PLD-Rev 1.%d\n",
+ pci_is_66mhz() ? "66" : "33", cpld_revision());
+
+ return 0;
+}
+
+
+static void wait_for_pci_ready(void)
+{
+ struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+ int i;
+ char *s = getenv("pcidelay");
+
+ /* only wait once */
+ if (wait_for_pci_ready_done)
+ return;
+
+ /*
+ * We have our own handling of the pcidelay variable.
+ * Using CONFIG_PCI_BOOTDELAY enables pausing for host
+ * and adapter devices. For adapter devices we do not
+ * want this.
+ */
+ if (s) {
+ int ms = simple_strtoul(s, NULL, 10);
+ printf("PCI: Waiting for %d ms\n", ms);
+ for (i=0; i<ms; i++)
+ udelay(1000);
+ }
+
+ if (!(in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY)) {
+ printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
+ while (1) {
+ if (ctrlc()) {
+ puts("abort\n");
+ break;
+ }
+ if (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY) {
+ printf("done\n");
+ break;
+ }
+ }
+ }
+
+ wait_for_pci_ready_done = 1;
+}
+
+/*
+ * Overwrite weak is_pci_host()
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+int is_pci_host(struct pci_controller *hose)
+{
+ char *s;
+
+ if (!is_monarch()) {
+ /*
+ * Overwrite PCI identification when running in
+ * non-monarch mode
+ * This should be moved into pci_target_init()
+ * when it is sometimes available for 405 CPUs
+ */
+ pci_write_config_word(PCIDEVID_405GP,
+ PCI_SUBSYSTEM_ID,
+ CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
+ pci_write_config_word(PCIDEVID_405GP,
+ PCI_CLASS_SUB_CODE,
+ CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
+ }
+
+ s = getenv("pciscan");
+ if (s == NULL) {
+ if (is_monarch()) {
+ wait_for_pci_ready();
+ return 1;
+ } else {
+ return 0;
+ }
+ } else {
+ if (!strcmp(s, "yes"))
+ return 1;
+ }
+
+ return 0;
+}
+
+/*
+ * Overwrite weak pci_pre_init()
+ *
+ * The default implementation enables the 405EP
+ * internal PCI arbiter. We do not want that
+ * on a PMC module.
+ */
+int pci_pre_init(struct pci_controller *hose)
+{
+ return 1;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ int rc;
+
+ __ft_board_setup(blob, bd);
+
+ /*
+ * Disable PCI in non-monarch mode.
+ */
+ if (!is_monarch()) {
+ rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
+ "disabled", sizeof("disabled"), 1);
+ if (rc) {
+ printf("Unable to update property status in PCI node, "
+ "err=%s\n",
+ fdt_strerror(rc));
+ }
+ }
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+ struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+
+ if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO0. */
+ clrbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO0. */
+ setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32(&gpio0->or) &
+ CONFIG_SYS_GPIO_EEPROM_WP));
+ break;
+ }
+ }
+ return state;
+}
+
+int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 1);
+ if (state < 0) {
+ puts("Query of write access state failed.\n");
+ } else {
+ printf("Write access for device 0x%0x is %sabled.\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable(
+ CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable(
+ CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0)
+ puts ("Setup of write access state failed.\n");
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "Enable / disable / query EEPROM write access",
+ ""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+#if defined(CONFIG_PRAM)
+#include <environment.h>
+extern env_t *env_ptr;
+
+int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ u32 pram, nextbase, base;
+ char *v;
+ u32 param;
+ ulong *lptr;
+
+ v = getenv("pram");
+ if (v)
+ pram = simple_strtoul(v, NULL, 10);
+ else {
+ printf("Error: pram undefined. Please define pram in KiB\n");
+ return 1;
+ }
+
+ base = gd->bd->bi_memsize;
+#if defined(CONFIG_LOGBUFFER)
+ base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
+#endif
+ /*
+ * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MM_TOP_HIDE
+ */
+ param = base - (pram << 10);
+ printf("PARAM: @%08x\n", param);
+ debug("memsize=0x%08x, base=0x%08x\n", gd->bd->bi_memsize, base);
+
+ /* clear entire PA ram */
+ memset((void*)param, 0, (pram << 10));
+
+ /* reserve 4k for pointer field */
+ nextbase = base - 4096;
+ lptr = (ulong*)(base);
+
+ /*
+ * *(--lptr) = item_size;
+ * *(--lptr) = base - item_base = distance from field top;
+ */
+
+ /* env is first (4k aligned) */
+ nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
+ memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE);
+ *(--lptr) = CONFIG_ENV_SIZE; /* size */
+ *(--lptr) = base - nextbase; /* offset | type=0 */
+
+ /* free section */
+ *(--lptr) = nextbase - param; /* size */
+ *(--lptr) = (base - param) | 126; /* offset | type=126 */
+
+ /* terminate pointer field */
+ *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
+ *(--lptr) = 0; /* offset=0 -> terminator */
+ return 0;
+}
+U_BOOT_CMD(
+ painit, 1, 1, do_painit,
+ "prepare PciAccess system",
+ ""
+);
+#endif /* CONFIG_PRAM */
+
+int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+ setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_SELFRST_N);
+ return 0;
+}
+U_BOOT_CMD(
+ selfreset, 1, 1, do_selfreset,
+ "assert self-reset# signal",
+ ""
+);
+
+int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ struct pmc405de_cpld *cpld =
+ (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
+
+ if (argc > 1) {
+ if (argv[1][0] == '0') {
+ /* assert */
+ printf("PMC-RESETOUT# asserted\n");
+ out_8(&cpld->control,
+ CPLD_CONTROL_RESETOUT_N_GATE);
+ } else {
+ /* deassert */
+ printf("PMC-RESETOUT# deasserted\n");
+ out_8(&cpld->control,
+ CPLD_CONTROL_RESETOUT_N |
+ CPLD_CONTROL_RESETOUT_N_GATE);
+ }
+ } else {
+ printf("PMC-RESETOUT# is %s\n",
+ (in_8(&cpld->control) & CPLD_CONTROL_RESETOUT_N) ?
+ "inactive" : "active");
+ }
+ return 0;
+}
+U_BOOT_CMD(
+ resetout, 2, 1, do_resetout,
+ "assert PMC-RESETOUT# signal",
+ ""
+);
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/ppc4xx/start.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.eh_frame)
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
reg |= CPR0_ICFG_RLI_MASK;
mtcpr(clk_icfg, reg);
- mtspr(dbcr0, 0x20000000); /* do chip reset */
+ mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
}
/*
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
+# Copyright (c) 2009 esd gmbh hannover germany.
+#
# See file CREDITS for list of people who contributed to this
# project.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)board/$(VENDOR)/common)
-endif
-
-LIB = $(obj)lib$(VENDOR).a
+LIB = $(obj)lib$(BOARD).a
-COBJS-$(CONFIG_OMAP3_BEAGLE) += power.o
-COBJS-$(CONFIG_OMAP3_OVERO) += power.o
-COBJS-$(CONFIG_OMAP3_PANDORA) += power.o
-COBJS-$(CONFIG_OMAP3_ZOOM1) += power.o
-COBJS-$(CONFIG_OMAP3_ZOOM2) += power.o
+COBJS-y += $(BOARD).o caddy.o
+COBJS-$(CONFIG_PCI) += pci.o
COBJS := $(COBJS-y)
-SRCS := $(COBJS:.o=.c)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-
-all: $(LIB)
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
#########################################################################
# defines $(obj).depend target
--- /dev/null
+/*
+ * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <pci.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+
+#include "caddy.h"
+
+static struct caddy_interface *caddy_interface;
+
+void generate_answer(struct caddy_cmd *cmd, uint32_t status, uint32_t *result)
+{
+ struct caddy_answer *answer;
+ uint32_t ptr;
+
+ answer = &caddy_interface->answer[caddy_interface->answer_in];
+ memset((void *)answer, 0, sizeof(struct caddy_answer));
+ answer->answer = cmd->cmd;
+ answer->issue = cmd->issue;
+ answer->status = status;
+ memcpy(answer->par, result, 5 * sizeof(result[0]));
+ ptr = caddy_interface->answer_in + 1;
+ ptr = ptr & (ANSWER_SIZE - 1);
+ if (ptr != caddy_interface->answer_out)
+ caddy_interface->answer_in = ptr;
+}
+
+int do_caddy(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned long base_addr;
+ uint32_t ptr;
+ struct caddy_cmd *caddy_cmd;
+ uint32_t result[5];
+ uint16_t data16;
+ uint8_t data8;
+ uint32_t status;
+ pci_dev_t dev;
+ void *pci_ptr;
+
+ if (argc < 2) {
+ puts("Missing parameter\n");
+ return 1;
+ }
+
+ base_addr = simple_strtoul(argv[1], NULL, 16);
+ caddy_interface = (struct caddy_interface *) base_addr;
+
+ memset((void *)caddy_interface, 0, sizeof(struct caddy_interface));
+ memcpy((void *)&caddy_interface->magic[0], &CADDY_MAGIC, 16);
+
+ while (ctrlc() == 0) {
+ if (caddy_interface->cmd_in != caddy_interface->cmd_out) {
+ memset(result, 0, 5 * sizeof(result[0]));
+ status = 0;
+ caddy_cmd = &caddy_interface->cmd[caddy_interface->cmd_out];
+ pci_ptr = (void *)CONFIG_SYS_PCI1_IO_PHYS +
+ (caddy_cmd->addr & 0x001fffff);
+
+ switch (caddy_cmd->cmd) {
+ case CADDY_CMD_IO_READ_8:
+ result[0] = in_8(pci_ptr);
+ break;
+
+ case CADDY_CMD_IO_READ_16:
+ result[0] = in_be16(pci_ptr);
+ break;
+
+ case CADDY_CMD_IO_READ_32:
+ result[0] = in_be32(pci_ptr);
+ break;
+
+ case CADDY_CMD_IO_WRITE_8:
+ data8 = caddy_cmd->par[0] & 0x000000ff;
+ out_8(pci_ptr, data8);
+ break;
+
+ case CADDY_CMD_IO_WRITE_16:
+ data16 = caddy_cmd->par[0] & 0x0000ffff;
+ out_be16(pci_ptr, data16);
+ break;
+
+ case CADDY_CMD_IO_WRITE_32:
+ out_be32(pci_ptr, caddy_cmd->par[0]);
+ break;
+
+ case CADDY_CMD_CONFIG_READ_8:
+ dev = PCI_BDF(caddy_cmd->par[0],
+ caddy_cmd->par[1],
+ caddy_cmd->par[2]);
+ status = pci_read_config_byte(dev,
+ caddy_cmd->addr,
+ &data8);
+ result[0] = data8;
+ break;
+
+ case CADDY_CMD_CONFIG_READ_16:
+ dev = PCI_BDF(caddy_cmd->par[0],
+ caddy_cmd->par[1],
+ caddy_cmd->par[2]);
+ status = pci_read_config_word(dev,
+ caddy_cmd->addr,
+ &data16);
+ result[0] = data16;
+ break;
+
+ case CADDY_CMD_CONFIG_READ_32:
+ dev = PCI_BDF(caddy_cmd->par[0],
+ caddy_cmd->par[1],
+ caddy_cmd->par[2]);
+ status = pci_read_config_dword(dev,
+ caddy_cmd->addr,
+ &result[0]);
+ break;
+
+ case CADDY_CMD_CONFIG_WRITE_8:
+ dev = PCI_BDF(caddy_cmd->par[0],
+ caddy_cmd->par[1],
+ caddy_cmd->par[2]);
+ data8 = caddy_cmd->par[3] & 0x000000ff;
+ status = pci_write_config_byte(dev,
+ caddy_cmd->addr,
+ data8);
+ break;
+
+ case CADDY_CMD_CONFIG_WRITE_16:
+ dev = PCI_BDF(caddy_cmd->par[0],
+ caddy_cmd->par[1],
+ caddy_cmd->par[2]);
+ data16 = caddy_cmd->par[3] & 0x0000ffff;
+ status = pci_write_config_word(dev,
+ caddy_cmd->addr,
+ data16);
+ break;
+
+ case CADDY_CMD_CONFIG_WRITE_32:
+ dev = PCI_BDF(caddy_cmd->par[0],
+ caddy_cmd->par[1],
+ caddy_cmd->par[2]);
+ status = pci_write_config_dword(dev,
+ caddy_cmd->addr,
+ caddy_cmd->par[3]);
+ break;
+
+ default:
+ status = 0xffffffff;
+ break;
+ }
+
+ generate_answer(caddy_cmd, status, &result[0]);
+
+ ptr = caddy_interface->cmd_out + 1;
+ ptr = ptr & (CMD_SIZE - 1);
+ caddy_interface->cmd_out = ptr;
+ }
+
+ caddy_interface->heartbeat++;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ caddy, 2, 0, do_caddy,
+ "Start Caddy server.",
+ "Start Caddy server with Data structure a given addr\n"
+ );
--- /dev/null
+/*
+ * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __CADDY_H__
+#define __CADDY_H__
+
+#define CMD_SIZE 1024
+#define ANSWER_SIZE 1024
+#define CADDY_MAGIC "esd vme8349 V1.0"
+
+enum caddy_cmds {
+ CADDY_CMD_IO_READ_8,
+ CADDY_CMD_IO_READ_16,
+ CADDY_CMD_IO_READ_32,
+ CADDY_CMD_IO_WRITE_8,
+ CADDY_CMD_IO_WRITE_16,
+ CADDY_CMD_IO_WRITE_32,
+ CADDY_CMD_CONFIG_READ_8,
+ CADDY_CMD_CONFIG_READ_16,
+ CADDY_CMD_CONFIG_READ_32,
+ CADDY_CMD_CONFIG_WRITE_8,
+ CADDY_CMD_CONFIG_WRITE_16,
+ CADDY_CMD_CONFIG_WRITE_32,
+};
+
+struct caddy_cmd {
+ uint32_t cmd;
+ uint32_t issue;
+ uint32_t addr;
+ uint32_t par[5];
+};
+
+struct caddy_answer {
+ uint32_t answer;
+ uint32_t issue;
+ uint32_t status;
+ uint32_t par[5];
+};
+
+struct caddy_interface {
+ uint8_t magic[16];
+ uint32_t cmd_in;
+ uint32_t cmd_out;
+ uint32_t heartbeat;
+ uint32_t reserved1;
+ struct caddy_cmd cmd[CMD_SIZE];
+ uint32_t answer_in;
+ uint32_t answer_out;
+ uint32_t reserved2;
+ uint32_t reserved3;
+ struct caddy_answer answer[CMD_SIZE];
+};
+
+#endif /* of __CADDY_H__ */
--- /dev/null
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# VME8349E
+#
+
+TEXT_BASE = 0xFFF00000
--- /dev/null
+/*
+ * pci.c -- esd VME8349 PCI board support.
+ * Copyright (c) 2006 Wind River Systems, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * Based on MPC8349 PCI support but w/o PIB related code.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+};
+
+/*
+ * pci_init_board()
+ *
+ * NOTICE: PCI2 is not supported. There is only one
+ * physical PCI slot on the board.
+ *
+ */
+void
+pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ struct pci_region *reg[] = { pci1_regions };
+ u8 reg8;
+ int monarch = 0;
+
+ i2c_set_bus_num(1);
+ /* Read the PCI_M66EN jumper setting */
+ if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, 1) == 0) ||
+ (i2c_read(0x38 , 0, 0, ®8, 1) == 0)) {
+ if (reg8 & 0x40) {
+ clk->occr = 0xff000000; /* 66 MHz PCI */
+ printf("PCI: 66MHz\n");
+ } else {
+ clk->occr = 0xffff0003; /* 33 MHz PCI */
+ printf("PCI: 33MHz\n");
+ }
+ if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
+ monarch = 1;
+ } else {
+ clk->occr = 0xffff0003; /* 33 MHz PCI */
+ printf("PCI: 33MHz (I2C read failed)\n");
+ }
+ udelay(2000);
+
+ /*
+ * Assert/deassert PCI reset
+ */
+ setbits_be32(&immr->gpio[0].dat, 0x00800000);
+ setbits_be32(&immr->gpio[0].dir, 0x00800000);
+ setbits_be32(&immr->gpio[1].dir, 0x08800000);
+ udelay(200);
+ setbits_be32(&immr->gpio[1].dat, 0x08000000);
+ udelay(200);
+ setbits_be32(&immr->gpio[1].dat, 0x08800000);
+ udelay(600000);
+ clrbits_be32(&immr->gpio[1].dat, 0x00100000);
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+ udelay(2000);
+
+ if (monarch == 0)
+ mpc83xx_pci_init(1, reg, 0);
+}
--- /dev/null
+/*
+ * vme8349.c -- esd VME8349 board support
+ *
+ * Copyright (c) 2008-2009 esd gmbh.
+ *
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#include <asm/io.h>
+#include <asm/mmu.h>
+
+void ddr_enable_ecc(unsigned int dram_size);
+
+int fixed_sdram(void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = 0;
+ u32 ddr_size;
+ u32 ddr_size_log2;
+
+ msize = CONFIG_SYS_DDR_SIZE;
+ for (ddr_size = msize << 20, ddr_size_log2 = 0;
+ (ddr_size > 1);
+ ddr_size = ddr_size>>1, ddr_size_log2++) {
+ if (ddr_size & 1)
+ return -1;
+ }
+
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
+ LAWAR_SIZE);
+
+#if (CONFIG_SYS_DDR_SIZE == 512)
+ im->ddr.csbnds[0].csbnds = 0x0000001f;
+#else
+#warning Currently any DDR size other than 512MiB is not supported
+#endif
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG | 0x00330000;
+
+ /* currently we use only one CS, so disable the other banks */
+ im->ddr.csbnds[1].csbnds = 0x00000000;
+ im->ddr.csbnds[2].csbnds = 0x00000000;
+ im->ddr.csbnds[3].csbnds = 0x00000000;
+ im->ddr.cs_config[1] = 0;
+ im->ddr.cs_config[2] = 0;
+ im->ddr.cs_config[3] = 0;
+
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ sync();
+ udelay(200);
+
+ /* enable DDR controller */
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+ return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = 0;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ /* DDR SDRAM - Main SODIMM */
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+
+ msize = fixed_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+
+ /* Now check memory size (after ECC is initialized) */
+ msize = get_ram_size(0, msize);
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+ puts("Board: esd VME8349\n");
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+}
+#endif
TEXT_BASE = 0xFE000000
PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/fads
-HOST_CFLAGS += -I$(TOPDIR)/board/fads
+HOSTCFLAGS += -I$(TOPDIR)/board/fads
HOST_ENVIRO_CFLAGS += -I$(TOPDIR)/board/fads
*/
void pixis_reset(void)
{
- out8(PIXIS_BASE + PIXIS_RST, 0);
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+ out_8(pixis_base + PIXIS_RST, 0);
}
int set_px_sysclk(ulong sysclk)
{
u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
switch (sysclk) {
case 33:
vclkh = (sysclk_s << 5) | sysclk_r;
vclkl = sysclk_v;
- out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
- out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
+ out_8(pixis_base + PIXIS_VCLKH, vclkh);
+ out_8(pixis_base + PIXIS_VCLKL, vclkl);
- out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);
+ out_8(pixis_base + PIXIS_AUX, sysclk_aux);
return 1;
}
{
u8 tmp;
u8 val;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
switch (mpxpll) {
case 2:
return 0;
}
- tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
+ tmp = in_8(pixis_base + PIXIS_VSPEED1);
tmp = (tmp & 0xF0) | (val & 0x0F);
- out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
+ out_8(pixis_base + PIXIS_VSPEED1, tmp);
return 1;
}
{
u8 tmp;
u8 val;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
switch ((int)corepll) {
case 20:
return 0;
}
- tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
+ tmp = in_8(pixis_base + PIXIS_VSPEED0);
tmp = (tmp & 0xE0) | (val & 0x1F);
- out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
+ out_8(pixis_base + PIXIS_VSPEED0, tmp);
return 1;
}
void read_from_px_regs(int set)
{
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
u8 mask = 0x1C; /* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */
- u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+ u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
if (set)
tmp = tmp | mask;
else
tmp = tmp & ~mask;
- out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
+ out_8(pixis_base + PIXIS_VCFGEN0, tmp);
}
void read_from_px_regs_altbank(int set)
{
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
u8 mask = 0x04; /* FLASHBANK and FLASHMAP controlled by PIXIS */
- u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
+ u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
if (set)
tmp = tmp | mask;
else
tmp = tmp & ~mask;
- out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
+ out_8(pixis_base + PIXIS_VCFGEN1, tmp);
}
#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
void clear_altbank(void)
{
u8 tmp;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
+ tmp = in_8(pixis_base + PIXIS_VBOOT);
tmp &= ~CONFIG_SYS_PIXIS_VBOOT_MASK;
- out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
+ out_8(pixis_base + PIXIS_VBOOT, tmp);
}
void set_altbank(void)
{
u8 tmp;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
+ tmp = in_8(pixis_base + PIXIS_VBOOT);
tmp |= CONFIG_SYS_PIXIS_VBOOT_MASK;
- out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
+ out_8(pixis_base + PIXIS_VBOOT, tmp);
}
void set_px_go(void)
{
u8 tmp;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = in_8(pixis_base + PIXIS_VCTL);
tmp = tmp & 0x1E; /* clear GO bit */
- out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+ out_8(pixis_base + PIXIS_VCTL, tmp);
- tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = in_8(pixis_base + PIXIS_VCTL);
tmp = tmp | 0x01; /* set GO bit - start reset sequencer */
- out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+ out_8(pixis_base + PIXIS_VCTL, tmp);
}
void set_px_go_with_watchdog(void)
{
u8 tmp;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = in_8(pixis_base + PIXIS_VCTL);
tmp = tmp & 0x1E;
- out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+ out_8(pixis_base + PIXIS_VCTL, tmp);
- tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = in_8(pixis_base + PIXIS_VCTL);
tmp = tmp | 0x09;
- out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+ out_8(pixis_base + PIXIS_VCTL, tmp);
}
int flag, int argc, char *argv[])
{
u8 tmp;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = in_8(pixis_base + PIXIS_VCTL);
tmp = tmp & 0x1E;
- out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+ out_8(pixis_base + PIXIS_VCTL, tmp);
/* setting VCTL[WDEN] to 0 to disable watch dog */
- tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = in_8(pixis_base + PIXIS_VCTL);
tmp &= ~0x08;
- out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+ out_8(pixis_base + PIXIS_VCTL, tmp);
return 0;
}
int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int which_tsec = -1;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
uchar mask;
uchar switch_mask;
/* Toggle whether the switches or FPGA control the settings */
if (!strcmp(argv[argc - 1], "switch"))
- clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1,
- switch_mask);
+ clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
else
- setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1,
- switch_mask);
+ setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
/* If it's not the switches, enable or disable SGMII, as specified */
if (!strcmp(argv[argc - 1], "on"))
- clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask);
+ clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
else if (!strcmp(argv[argc - 1], "off"))
- setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask);
+ setbits_8(pixis_base + PIXIS_VSPEED2, mask);
return 0;
}
*/
#include <common.h>
+#include <hwconfig.h>
#include <i2c.h>
#include <libfdt.h>
#include <fdt_support.h>
#if defined(CONFIG_OF_BOARD_SETUP)
void fdt_tsec1_fixup(void *fdt, bd_t *bd)
{
- char *mpc8315erdb = getenv("mpc8315erdb");
const char disabled[] = "disabled";
const char *path;
int ret;
- if (!mpc8315erdb)
+ if (hwconfig_arg_cmp("board_type", "tsec1")) {
return;
-
- if (!strcmp(mpc8315erdb, "tsec1")) {
- return;
- } else if (strcmp(mpc8315erdb, "ulpi")) {
- printf("WARNING: wrong `mpc8315erdb' environment "
- "variable specified: `%s'. Should be `ulpi' "
- "or `tsec1'.\n", mpc8315erdb);
+ } else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
+ printf("NOTICE: No or unknown board_type hwconfig specified.\n"
+ " Assuming board with TSEC1.\n");
return;
}
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o pci.o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
+#include <mpc83xx.h>
#include <pci.h>
#include <i2c.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
#include <asm/fsl_i2c.h>
+#include "../common/pq-mds-pib.h"
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_PCI)
-#define PCI_FUNCTION_CONFIG 0x44
-#define PCI_FUNCTION_CFG_LOCK 0x20
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+};
-/*
- * Initialize PCI Devices, report devices found
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc83xxemds_config_table[] = {
+#ifdef CONFIG_MPC83XX_PCI2
+static struct pci_region pci2_regions[] = {
{
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- pci_cfgfunc_config_device,
- {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
+ bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+ size: CONFIG_SYS_PCI2_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
- {}
-}
-#endif
-static struct pci_controller hose[] = {
{
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc83xxemds_config_table,
-#endif
+ bus_start: CONFIG_SYS_PCI2_IO_BASE,
+ phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+ size: CONFIG_SYS_PCI2_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+ size: CONFIG_SYS_PCI2_MMIO_SIZE,
+ flags: PCI_REGION_MEM
},
};
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
-/**********************************************************************
- * pci_init_board()
- *********************************************************************/
void pci_init_board(void)
#ifdef CONFIG_PCISLAVE
{
- u16 reg16;
- volatile immap_t *immr;
- volatile law83xx_t *pci_law;
- volatile pot83xx_t *pci_pot;
- volatile pcictrl83xx_t *pci_ctrl;
- volatile pciconf83xx_t *pci_conf;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
+ struct pci_region *reg[] = { pci1_regions };
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+ mpc83xx_pci_init(1, reg, 0);
- immr = (immap_t *) CONFIG_SYS_IMMR;
- pci_law = immr->sysconf.pcilaw;
- pci_pot = immr->ios.pot;
- pci_ctrl = immr->pci_ctrl;
- pci_conf = immr->pci_conf;
/*
* Configure PCI Inbound Translation Windows
*/
pci_ctrl[0].piebar2 = 0x0;
pci_ctrl[0].piwar2 &= ~PIWAR_EN;
- hose[0].first_busno = 0;
- hose[0].last_busno = 0xff;
- pci_setup_indirect(&hose[0],
- (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
- reg16 = 0xff;
-
- pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0),
- PCI_LATENCY_TIMER, 0x80);
-
- /*
- * Unlock configuration lock in PCI function configuration register.
- */
- pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_FUNCTION_CONFIG, ®16);
- reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
- pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_FUNCTION_CONFIG, reg16);
-
- printf("Enabled PCI 32bit Agent Mode\n");
+ /* Unlock the configuration bit */
+ mpc83xx_pcislave_unlock(0);
+ printf("PCI: Agent mode enabled\n");
}
#else
{
- volatile immap_t *immr;
- volatile clk83xx_t *clk;
- volatile law83xx_t *pci_law;
- volatile pot83xx_t *pci_pot;
- volatile pcictrl83xx_t *pci_ctrl;
- volatile pciconf83xx_t *pci_conf;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+#ifndef CONFIG_MPC83XX_PCI2
+ struct pci_region *reg[] = { pci1_regions };
+#else
+ struct pci_region *reg[] = { pci1_regions, pci2_regions };
+#endif
- u16 reg16;
- u32 val32;
- u32 dev;
+ /* initialize the PCA9555PW IO expander on the PIB board */
+ pib_init();
- immr = (immap_t *) CONFIG_SYS_IMMR;
- clk = (clk83xx_t *) & immr->clk;
- pci_law = immr->sysconf.pcilaw;
- pci_pot = immr->ios.pot;
- pci_ctrl = immr->pci_ctrl;
- pci_conf = immr->pci_conf;
- /*
- * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
- */
- val32 = clk->occr;
- udelay(2000);
#if defined(PCI_66M)
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
printf("PCI clock is 66MHz\n");
#endif
udelay(2000);
- /*
- * Configure PCI Local Access Windows
- */
- pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
- pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
- /*
- * Configure PCI Outbound Translation Windows
- */
-
- /* PCI mem space - prefetch */
- pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[0].pocmr =
- POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /* PCI mmio - non-prefetch mem space */
- pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /* PCI IO space */
- pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
- pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
- pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 =
- PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
- PIWAR_IWS_2G;
-
- /*
- * Release PCI RST Output signal
- */
udelay(2000);
- pci_ctrl[0].gcr = 1;
- udelay(2000);
-
- hose[0].first_busno = 0;
- hose[0].last_busno = 0xff;
-
- /* PCI memory prefetch space */
- pci_set_region(hose[0].regions + 0,
- CONFIG_SYS_PCI_MEM_BASE,
- CONFIG_SYS_PCI_MEM_PHYS,
- CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
-
- /* PCI memory space */
- pci_set_region(hose[0].regions + 1,
- CONFIG_SYS_PCI_MMIO_BASE,
- CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose[0].regions + 2,
- CONFIG_SYS_PCI_IO_BASE,
- CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(hose[0].regions + 3,
- CONFIG_SYS_PCI_SLV_MEM_LOCAL,
- CONFIG_SYS_PCI_SLV_MEM_BUS,
- CONFIG_SYS_PCI_SLV_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
- hose[0].region_count = 4;
-
- pci_setup_indirect(&hose[0],
- (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
-
- pci_register_hose(hose);
-
- /*
- * Write command register
- */
- reg16 = 0xff;
- dev = PCI_BDF(0, 0, 0);
- pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
- pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
-
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
+#ifndef CONFIG_MPC83XX_PCI2
+ mpc83xx_pci_init(1, reg, 0);
+#else
+ mpc83xx_pci_init(2, reg, 0);
+#endif
}
#endif /* CONFIG_PCISLAVE */
-
-#if defined(CONFIG_OF_LIBFDT)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
- int nodeoffset;
- int tmp[2];
- const char *path;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
- path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(hose[0].first_busno);
- tmp[1] = cpu_to_be32(hose[0].last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
- }
-}
-#endif /* CONFIG_OF_LIBFDT */
-#endif /* CONFIG_PCI */
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o pci.o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_PCI
-
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
printf("PCI: Agent mode enabled\n");
}
#endif /* CONFIG_PCISLAVE */
-
-#endif /* CONFIG_PCI */
#
-# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+# Copyright (C) Freescale Semiconductor, Inc. 2006.
#
# See file CREDITS for list of people who contributed to this
# project.
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o pci.o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
#
-# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+# Copyright (C) Freescale Semiconductor, Inc. 2006.
#
# See file CREDITS for list of people who contributed to this
# project.
/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
*
* See file CREDITS for list of people who contributed to this
* project.
/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <common.h>
-#ifdef CONFIG_PCI
-
#include <asm/mmu.h>
-#include <asm/global_data.h>
+#include <asm/io.h>
+#include <mpc83xx.h>
#include <pci.h>
-#include <asm/mpc8349_pci.h>
#include <i2c.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
+#include <asm/fsl_i2c.h>
DECLARE_GLOBAL_DATA_PTR;
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc8349itx_config_table[] = {
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
{
- PCI_ANY_ID,
- PCI_ANY_ID,
- PCI_ANY_ID,
- PCI_ANY_ID,
- PCI_IDSEL_NUMBER,
- PCI_ANY_ID,
- pci_cfgfunc_config_device,
- {
- PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
- },
- {}
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
};
-#endif
-static struct pci_controller pci_hose[] = {
+#ifdef CONFIG_MPC83XX_PCI2
+static struct pci_region pci2_regions[] = {
{
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc8349itx_config_table,
-#endif
- },
+ bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+ size: CONFIG_SYS_PCI2_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
{
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc8349itx_config_table,
-#endif
- }
+ bus_start: CONFIG_SYS_PCI2_IO_BASE,
+ phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+ size: CONFIG_SYS_PCI2_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+ size: CONFIG_SYS_PCI2_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
};
+#endif
-/**************************************************************************
- * pci_init_board()
- *
- * NOTICE: PCI2 is not currently supported
- *
- */
void pci_init_board(void)
{
- volatile immap_t *immr;
- volatile clk83xx_t *clk;
- volatile law83xx_t *pci_law;
- volatile pot83xx_t *pci_pot;
- volatile pcictrl83xx_t *pci_ctrl;
- volatile pciconf83xx_t *pci_conf;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+#ifndef CONFIG_MPC83XX_PCI2
+ struct pci_region *reg[] = { pci1_regions };
+#else
+ struct pci_region *reg[] = { pci1_regions, pci2_regions };
+#endif
u8 reg8;
- u16 reg16;
- u32 reg32;
- u32 dev;
- struct pci_controller *hose;
-
- immr = (immap_t *) CONFIG_SYS_IMMR;
- clk = (clk83xx_t *) & immr->clk;
- pci_law = immr->sysconf.pcilaw;
- pci_pot = immr->ios.pot;
- pci_ctrl = immr->pci_ctrl;
- pci_conf = immr->pci_conf;
-
- hose = &pci_hose[0];
-
- /*
- * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
- */
-
- reg32 = clk->occr;
- udelay(2000);
#ifdef CONFIG_HARD_I2C
i2c_set_bus_num(1);
#else
clk->occr = 0xff000000; /* 66 MHz PCI */
#endif
-
- udelay(2000);
-
- /*
- * Release PCI RST Output signal
- */
- pci_ctrl[0].gcr = 0;
- udelay(2000);
- pci_ctrl[0].gcr = 1;
-
-#ifdef CONFIG_MPC83XX_PCI2
- pci_ctrl[1].gcr = 0;
udelay(2000);
- pci_ctrl[1].gcr = 1;
-#endif
-
- /* We need to wait at least a 1sec based on PCI specs */
- {
- int i;
- for (i = 0; i < 1000; i++)
- udelay(1000);
- }
-
- /*
- * Configure PCI Local Access Windows
- */
+ /* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
- /*
- * Configure PCI Outbound Translation Windows
- */
-
- /* PCI1 mem space - prefetch */
- pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M;
-
- /* PCI1 IO space */
- pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
-
- /* PCI1 mmio - non-prefetch mem space */
- pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
-
- /*
- * Configure PCI Inbound Translation Windows
- */
-
- /* we need RAM mapped to PCI space for the devices to
- * access main memory */
- pci_ctrl[0].pitar1 = 0x0;
- pci_ctrl[0].pibar1 = 0x0;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* PCI memory prefetch space */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI1_MEM_BASE,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
-
- /* PCI memory space */
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI1_MMIO_BASE,
- CONFIG_SYS_PCI1_MMIO_PHYS, CONFIG_SYS_PCI1_MMIO_SIZE, PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose->regions + 2,
- CONFIG_SYS_PCI1_IO_BASE,
- CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(hose->regions + 3,
- CONFIG_PCI_SYS_MEM_BUS,
- CONFIG_PCI_SYS_MEM_PHYS,
- gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- hose->region_count = 4;
-
- pci_setup_indirect(hose,
- (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
-
- pci_register_hose(hose);
-
- /*
- * Write to Command register
- */
- reg16 = 0xff;
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
-#endif
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
-
-#ifdef CONFIG_MPC83XX_PCI2
- hose = &pci_hose[1];
-
- /*
- * Configure PCI Outbound Translation Windows
- */
-
- /* PCI2 mem space - prefetch */
- pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M;
-
- /* PCI2 IO space */
- pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M;
-
- /* PCI2 mmio - non-prefetch mem space */
- pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M;
-
- /*
- * Configure PCI Inbound Translation Windows
- */
-
- /* we need RAM mapped to PCI space for the devices to
- * access main memory */
- pci_ctrl[1].pitar1 = 0x0;
- pci_ctrl[1].pibar1 = 0x0;
- pci_ctrl[1].piebar1 = 0x0;
- pci_ctrl[1].piwar1 =
- PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
- (__ilog2(gd->ram_size) - 1);
-
- hose->first_busno = pci_hose[0].last_busno + 1;
- hose->last_busno = 0xff;
-
- /* PCI memory prefetch space */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI2_MEM_BASE,
- CONFIG_SYS_PCI2_MEM_PHYS,
- CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
-
- /* PCI memory space */
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI2_MMIO_BASE,
- CONFIG_SYS_PCI2_MMIO_PHYS, CONFIG_SYS_PCI2_MMIO_SIZE, PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose->regions + 2,
- CONFIG_SYS_PCI2_IO_BASE,
- CONFIG_SYS_PCI2_IO_PHYS, CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(hose->regions + 3,
- CONFIG_PCI_SYS_MEM_BUS,
- CONFIG_PCI_SYS_MEM_PHYS,
- gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- hose->region_count = 4;
-
- pci_setup_indirect(hose,
- (CONFIG_SYS_IMMR + 0x8380), (CONFIG_SYS_IMMR + 0x8384));
-
- pci_register_hose(hose);
-
- /*
- * Write to Command register
- */
- reg16 = 0xff;
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
-#endif
-}
-
-#if defined(CONFIG_OF_LIBFDT)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
- int nodeoffset;
- int tmp[2];
- const char *path;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
- path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
- tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
-#ifdef CONFIG_MPC83XX_PCI2
- path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
- tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
+ udelay(2000);
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
+#ifndef CONFIG_MPC83XX_PCI2
+ mpc83xx_pci_init(1, reg, 0);
+#else
+ mpc83xx_pci_init(2, reg, 0);
#endif
- }
}
-#endif /* CONFIG_OF_LIBFDT */
-#endif /* CONFIG_PCI */
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o pci.o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
/*
* PCI Configuration space access support for MPC83xx PCI Bridge
*/
+
#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
+#include <mpc83xx.h>
#include <pci.h>
#include <i2c.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
#include <asm/fsl_i2c.h>
+#include "../common/pq-mds-pib.h"
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_PCI)
-#define PCI_FUNCTION_CONFIG 0x44
-#define PCI_FUNCTION_CFG_LOCK 0x20
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+};
-/*
- * Initialize PCI Devices, report devices found
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc83xxemds_config_table[] = {
+#ifdef CONFIG_MPC83XX_PCI2
+static struct pci_region pci2_regions[] = {
{
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- pci_cfgfunc_config_device,
- {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
- },
- {}
-}
-#endif
-static struct pci_controller hose[] = {
+ bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+ size: CONFIG_SYS_PCI2_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
{
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc83xxemds_config_table,
-#endif
- },
+ bus_start: CONFIG_SYS_PCI2_IO_BASE,
+ phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+ size: CONFIG_SYS_PCI2_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+ size: CONFIG_SYS_PCI2_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
};
+#endif
-/**********************************************************************
- * pci_init_board()
- *********************************************************************/
void pci_init_board(void)
#ifdef CONFIG_PCISLAVE
{
- u16 reg16;
- volatile immap_t *immr;
- volatile law83xx_t *pci_law;
- volatile pot83xx_t *pci_pot;
- volatile pcictrl83xx_t *pci_ctrl;
- volatile pciconf83xx_t *pci_conf;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
+ struct pci_region *reg[] = { pci1_regions };
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
+
+ mpc83xx_pci_init(1, reg, 0);
- immr = (immap_t *) CONFIG_SYS_IMMR;
- pci_law = immr->sysconf.pcilaw;
- pci_pot = immr->ios.pot;
- pci_ctrl = immr->pci_ctrl;
- pci_conf = immr->pci_conf;
/*
* Configure PCI Inbound Translation Windows
*/
pci_ctrl[0].piebar2 = 0x0;
pci_ctrl[0].piwar2 &= ~PIWAR_EN;
- hose[0].first_busno = 0;
- hose[0].last_busno = 0xff;
- pci_setup_indirect(&hose[0],
- (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
- reg16 = 0xff;
-
- pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0),
- PCI_LATENCY_TIMER, 0x80);
-
- /*
- * Unlock configuration lock in PCI function configuration register.
- */
- pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_FUNCTION_CONFIG, ®16);
- reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
- pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_FUNCTION_CONFIG, reg16);
-
- printf("Enabled PCI 32bit Agent Mode\n");
+ /* Unlock the configuration bit */
+ mpc83xx_pcislave_unlock(0);
+ printf("PCI: Agent mode enabled\n");
}
#else
{
- volatile immap_t *immr;
- volatile clk83xx_t *clk;
- volatile law83xx_t *pci_law;
- volatile pot83xx_t *pci_pot;
- volatile pcictrl83xx_t *pci_ctrl;
- volatile pciconf83xx_t *pci_conf;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+#ifndef CONFIG_MPC83XX_PCI2
+ struct pci_region *reg[] = { pci1_regions };
+#else
+ struct pci_region *reg[] = { pci1_regions, pci2_regions };
+#endif
- u16 reg16;
- u32 val32;
- u32 dev;
+ /* initialize the PCA9555PW IO expander on the PIB board */
+ pib_init();
- immr = (immap_t *) CONFIG_SYS_IMMR;
- clk = (clk83xx_t *) & immr->clk;
- pci_law = immr->sysconf.pcilaw;
- pci_pot = immr->ios.pot;
- pci_ctrl = immr->pci_ctrl;
- pci_conf = immr->pci_conf;
- /*
- * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
- */
- val32 = clk->occr;
- udelay(2000);
#if defined(PCI_66M)
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
printf("PCI clock is 66MHz\n");
#endif
udelay(2000);
- /*
- * Configure PCI Local Access Windows
- */
- pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
- pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
- /*
- * Configure PCI Outbound Translation Windows
- */
-
- /* PCI mem space - prefetch */
- pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[0].pocmr =
- POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /* PCI mmio - non-prefetch mem space */
- pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /* PCI IO space */
- pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
- pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
- pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 =
- PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
- PIWAR_IWS_2G;
-
- /*
- * Release PCI RST Output signal
- */
- udelay(2000);
- pci_ctrl[0].gcr = 1;
udelay(2000);
- hose[0].first_busno = 0;
- hose[0].last_busno = 0xff;
-
- /* PCI memory prefetch space */
- pci_set_region(hose[0].regions + 0,
- CONFIG_SYS_PCI_MEM_BASE,
- CONFIG_SYS_PCI_MEM_PHYS,
- CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
-
- /* PCI memory space */
- pci_set_region(hose[0].regions + 1,
- CONFIG_SYS_PCI_MMIO_BASE,
- CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose[0].regions + 2,
- CONFIG_SYS_PCI_IO_BASE,
- CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(hose[0].regions + 3,
- CONFIG_SYS_PCI_SLV_MEM_LOCAL,
- CONFIG_SYS_PCI_SLV_MEM_BUS,
- CONFIG_SYS_PCI_SLV_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- hose[0].region_count = 4;
-
- pci_setup_indirect(&hose[0],
- (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
-
- pci_register_hose(hose);
-
- /*
- * Write command register
- */
- reg16 = 0xff;
- dev = PCI_BDF(0, 0, 0);
- pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
- pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
-
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
+#ifndef CONFIG_MPC83XX_PCI2
+ mpc83xx_pci_init(1, reg, 0);
+#else
+ mpc83xx_pci_init(2, reg, 0);
+#endif
}
#endif /* CONFIG_PCISLAVE */
-
-#if defined(CONFIG_OF_LIBFDT)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
- int nodeoffset;
- int tmp[2];
- const char *path;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
- path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(hose[0].first_busno);
- tmp[1] = cpu_to_be32(hose[0].last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
- }
-}
-#endif /* CONFIG_OF_LIBFDT */
-#endif /* CONFIG_PCI */
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o pci.o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
*/
#include <common.h>
+#include <hwconfig.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <tsec.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <fsl_esdhc.h>
#include "pci.h"
#include "../common/pq-mds-pib.h"
int board_early_init_f(void)
{
- struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
/* Enable flash write */
/* Clear all of the interrupt of BCSR */
bcsr[0xe] = 0xff;
-#ifdef CONFIG_MMC
- /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
- bcsr[0xc] |= 0x4c;
-
- /* Set proper bits in SICR to allow SD signals through */
- clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
-
- clrsetbits_be32(&im->sysconf.sicrh, (SICRH_GPIO2_E | SICRH_SPI),
- (SICRH_GPIO2_E_SD | SICRH_SPI_SD));
-
-#endif
-
#ifdef CONFIG_FSL_SERDES
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
u32 spridr = in_be32(&immr->sysconf.spridr);
return 0;
}
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+ struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
+
+ if (!hwconfig("esdhc"))
+ return 0;
+
+ /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
+ bcsr[0xc] |= 0x4c;
+
+ /* Set proper bits in SICR to allow SD signals through */
+ clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
+ clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
+ SICRH_GPIO2_E_SD | SICRH_SPI_SD);
+
+ return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
int board_eth_init(bd_t *bd)
{
{
struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
- const char *pci_ea = getenv("pci_external_arbiter");
/* It's always OK in case of external arbiter. */
- if (pci_ea && !strcmp(pci_ea, "yes"))
+ if (hwconfig_subarg_cmp("pci", "arbiter", "external"))
return 0;
if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
ft_cpu_setup(blob, bd);
ft_tsec_fixup(blob, bd);
fdt_fixup_dr_usb(blob, bd);
+ fdt_fixup_esdhc(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
if (board_pci_host_broken())
/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <asm/fsl_i2c.h>
#include <asm/fsl_serdes.h>
-#if defined(CONFIG_PCI)
static struct pci_region pci_regions[] = {
{
bus_start: CONFIG_SYS_PCI_MEM_BASE,
do_fixup_by_path(blob, "pci2", "status", status,
strlen(status) + 1, 1);
}
-#endif /* CONFIG_PCI */
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o pci.o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
*/
#include <common.h>
+#include <hwconfig.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <fdt_support.h>
#include <spd_sdram.h>
#include <vsc7385.h>
+#include <fsl_esdhc.h>
#if defined(CONFIG_SYS_DRAM_TEST)
int
return 0;
}
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+ struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+
+ if (!hwconfig("esdhc"))
+ return 0;
+
+ clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
+ clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
+
+ return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
/*
* Miscellaneous late-boot configurations
*
#endif
ft_cpu_setup(blob, bd);
fdt_fixup_dr_usb(blob, bd);
+ fdt_fixup_esdhc(blob, bd);
}
#endif /* CONFIG_OF_BOARD_SETUP */
/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <pci.h>
#include <asm/io.h>
-#if defined(CONFIG_PCI)
static struct pci_region pci_regions[] = {
{
bus_start: CONFIG_SYS_PCI_MEM_BASE,
mpc83xx_pcie_init(2, pcie_reg, 0);
}
-#endif /* CONFIG_PCI */
int checkboard (void)
{
- printf ("Board: MPC8536DS, System ID: 0x%02x, "
- "System Version: 0x%02x, FPGA Version: 0x%02x\n",
- in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
- in8(PIXIS_BASE + PIXIS_PVER));
+ u8 vboot;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+ puts("Board: MPC8536DS ");
+#ifdef CONFIG_PHYS_64BIT
+ puts("(36-bit addrmap) ");
+#endif
+
+ printf ("Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+ in_8(pixis_base + PIXIS_PVER));
+
+ vboot = in_8(pixis_base + PIXIS_VBOOT);
+ switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
+ case PIXIS_VBOOT_LBMAP_NOR0:
+ puts ("vBank: 0\n");
+ break;
+ case PIXIS_VBOOT_LBMAP_NOR1:
+ puts ("vBank: 1\n");
+ break;
+ case PIXIS_VBOOT_LBMAP_NOR2:
+ puts ("vBank: 2\n");
+ break;
+ case PIXIS_VBOOT_LBMAP_NOR3:
+ puts ("vBank: 3\n");
+ break;
+ case PIXIS_VBOOT_LBMAP_PJET:
+ puts ("Promjet\n");
+ break;
+ case PIXIS_VBOOT_LBMAP_NAND:
+ puts ("NAND\n");
+ break;
+ }
+
return 0;
}
unsigned long
get_board_sys_clk(ulong dummy)
{
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
return ics307_clk_freq (
- in8(PIXIS_BASE + PIXIS_VSYSCLK0),
- in8(PIXIS_BASE + PIXIS_VSYSCLK1),
- in8(PIXIS_BASE + PIXIS_VSYSCLK2)
+ in_8(pixis_base + PIXIS_VSYSCLK0),
+ in_8(pixis_base + PIXIS_VSYSCLK1),
+ in_8(pixis_base + PIXIS_VSYSCLK2)
);
}
unsigned long
get_board_ddr_clk(ulong dummy)
{
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
return ics307_clk_freq (
- in8(PIXIS_BASE + PIXIS_VDDRCLK0),
- in8(PIXIS_BASE + PIXIS_VDDRCLK1),
- in8(PIXIS_BASE + PIXIS_VDDRCLK2)
+ in_8(pixis_base + PIXIS_VDDRCLK0),
+ in_8(pixis_base + PIXIS_VDDRCLK1),
+ in_8(pixis_base + PIXIS_VDDRCLK2)
);
}
#else
{
u8 i;
ulong val = 0;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- i = in8(PIXIS_BASE + PIXIS_SPD);
+ i = in_8(pixis_base + PIXIS_SPD);
i &= 0x07;
switch (i) {
{
u8 i;
ulong val = 0;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- i = in8(PIXIS_BASE + PIXIS_SPD);
+ i = in_8(pixis_base + PIXIS_SPD);
i &= 0x38;
i >>= 3;
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+ u8 vboot;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
if ((uint)&gur->porpllsr != 0xe00e0000) {
printf("immap size error %lx\n",(ulong)&gur->porpllsr);
}
- printf ("Board: MPC8544DS, System ID: 0x%02x, "
- "System Version: 0x%02x, FPGA Version: 0x%02x\n",
- in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
- in8(PIXIS_BASE + PIXIS_PVER));
+ printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+ in_8(pixis_base + PIXIS_PVER));
+
+ vboot = in_8(pixis_base + PIXIS_VBOOT);
+ if (vboot & PIXIS_VBOOT_FMAP)
+ printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
+ else
+ puts ("Promjet\n");
lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
{
u8 i, go_bit, rd_clks;
ulong val = 0;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
+ go_bit = in_8(pixis_base + PIXIS_VCTL);
go_bit &= 0x01;
- rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+ rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
rd_clks &= 0x1C;
/*
if (go_bit) {
if (rd_clks == 0x1c)
- i = in8(PIXIS_BASE + PIXIS_AUX);
+ i = in_8(pixis_base + PIXIS_AUX);
else
- i = in8(PIXIS_BASE + PIXIS_SPD);
+ i = in_8(pixis_base + PIXIS_SPD);
} else {
- i = in8(PIXIS_BASE + PIXIS_SPD);
+ i = in_8(pixis_base + PIXIS_SPD);
}
i &= 0x07;
/*
- * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
/*
- * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#
-# Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+# Copyright (C) 2009 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
int checkboard (void)
{
+ u8 vboot;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
puts ("Board: MPC8572DS ");
#ifdef CONFIG_PHYS_64BIT
puts ("(36-bit addrmap) ");
#endif
printf ("Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
- in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
- in8(PIXIS_BASE + PIXIS_PVER));
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+ in_8(pixis_base + PIXIS_PVER));
+
+ vboot = in_8(pixis_base + PIXIS_VBOOT);
+ switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
+ case PIXIS_VBOOT_LBMAP_NOR0:
+ puts ("vBank: 0\n");
+ break;
+ case PIXIS_VBOOT_LBMAP_PJET:
+ puts ("Promjet\n");
+ break;
+ case PIXIS_VBOOT_LBMAP_NAND:
+ puts ("NAND\n");
+ break;
+ case PIXIS_VBOOT_LBMAP_NOR1:
+ puts ("vBank: 1\n");
+ break;
+ }
+
return 0;
}
unsigned long get_board_sys_clk(ulong dummy)
{
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
return ics307_clk_freq (
- in8(PIXIS_BASE + PIXIS_VSYSCLK0),
- in8(PIXIS_BASE + PIXIS_VSYSCLK1),
- in8(PIXIS_BASE + PIXIS_VSYSCLK2)
+ in_8(pixis_base + PIXIS_VSYSCLK0),
+ in_8(pixis_base + PIXIS_VSYSCLK1),
+ in_8(pixis_base + PIXIS_VSYSCLK2)
);
}
unsigned long get_board_ddr_clk(ulong dummy)
{
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
return ics307_clk_freq (
- in8(PIXIS_BASE + PIXIS_VDDRCLK0),
- in8(PIXIS_BASE + PIXIS_VDDRCLK1),
- in8(PIXIS_BASE + PIXIS_VDDRCLK2)
+ in_8(pixis_base + PIXIS_VDDRCLK0),
+ in_8(pixis_base + PIXIS_VDDRCLK1),
+ in_8(pixis_base + PIXIS_VDDRCLK2)
);
}
#else
{
u8 i;
ulong val = 0;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- i = in8(PIXIS_BASE + PIXIS_SPD);
+ i = in_8(pixis_base + PIXIS_SPD);
i &= 0x07;
switch (i) {
{
u8 i;
ulong val = 0;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- i = in8(PIXIS_BASE + PIXIS_SPD);
+ i = in_8(pixis_base + PIXIS_SPD);
i &= 0x38;
i >>= 3;
int misc_init_r(void)
{
u8 tmp_val, version;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
/*Do not use 8259PIC*/
- tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
- out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80);
+ tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
+ out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
- version = in8(PIXIS_BASE + PIXIS_PVER);
+ version = in_8(pixis_base + PIXIS_PVER);
if(version >= 0x07) {
- tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
- out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf);
+ tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
+ out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
}
/* Using this for DIU init before the driver in linux takes over
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
"System Version: 0x%02x, FPGA Version: 0x%02x\n",
- in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
- in8(PIXIS_BASE + PIXIS_PVER));
+ in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+ in_8(pixis_base + PIXIS_PVER));
mcm->abcr |= 0x00010000; /* 0 */
mcm->hpmr3 = 0x80000008; /* 4c */
ddr->timing_cfg_0 = 0x00260802;
ddr->timing_cfg_1 = 0x3935d322;
ddr->timing_cfg_2 = 0x14904cc8;
- ddr->sdram_mode_1 = 0x00480432;
+ ddr->sdram_mode = 0x00480432;
ddr->sdram_mode_2 = 0x00000000;
ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
ddr->sdram_data_init = 0xDEADBEEF;
udelay(500);
- ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/
+ ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
{
u8 i;
ulong val = 0;
- ulong a;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- a = PIXIS_BASE + PIXIS_SPD;
- i = in8(a);
+ i = in_8(pixis_base + PIXIS_SPD);
i &= 0x07;
switch (i) {
void board_reset(void)
{
- out8(PIXIS_BASE + PIXIS_RST, 0);
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+ out_8(pixis_base + PIXIS_RST, 0);
while (1)
;
#include "../common/fsl_diu_fb.h"
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
-#include <devices.h>
+#include <stdio_dev.h>
#include <video_fb.h>
#endif
unsigned int pixel_format;
unsigned char tmp_val;
unsigned char pixis_arch;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
- pixis_arch = in8(PIXIS_BASE + PIXIS_VER);
+ tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
+ pixis_arch = in_8(pixis_base + PIXIS_VER);
monitor_port = getenv("monitor");
if (!strncmp(monitor_port, "0", 1)) { /* 0 - DVI */
else
pixel_format = 0x88883316;
gamma_fix = 0;
- out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08);
+ out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08);
} else if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
xres = 1024;
yres = 768;
pixel_format = 0x88883316;
gamma_fix = 0;
- out8(PIXIS_BASE + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10);
+ out_8(pixis_base + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10);
} else if (!strncmp(monitor_port, "2", 1)) { /* 2 - Double link LVDS */
xres = 1280;
yres = 1024;
pixel_format = 0x88883316;
gamma_fix = 1;
- out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xe7);
+ out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xe7);
} else { /* DVI */
xres = 1280;
yres = 1024;
pixel_format = 0x88882317;
gamma_fix = 0;
- out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08);
+ out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08);
}
fsl_diu_init(xres, pixel_format, gamma_fix,
int checkboard(void)
{
- printf ("Board: MPC8641HPCN, System ID: 0x%02x, "
- "System Version: 0x%02x, FPGA Version: 0x%02x\n",
- in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
- in8(PIXIS_BASE + PIXIS_PVER));
+ u8 vboot;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+ printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+ in_8(pixis_base + PIXIS_PVER));
+
+ vboot = in_8(pixis_base + PIXIS_VBOOT);
+ if (vboot & PIXIS_VBOOT_FMAP)
+ printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
+ else
+ puts ("Promjet\n");
+
#ifdef CONFIG_PHYS_64BIT
printf (" 36-bit physical address map\n");
#endif
ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
+ ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
- ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
+ ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
#else
- ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL;
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
#endif
asm("sync; isync");
{
u8 i, go_bit, rd_clks;
ulong val = 0;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
+ go_bit = in_8(pixis_base + PIXIS_VCTL);
go_bit &= 0x01;
- rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+ rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
rd_clks &= 0x1C;
/*
if (go_bit) {
if (rd_clks == 0x1c)
- i = in8(PIXIS_BASE + PIXIS_AUX);
+ i = in_8(pixis_base + PIXIS_AUX);
else
- i = in8(PIXIS_BASE + PIXIS_SPD);
+ i = in_8(pixis_base + PIXIS_SPD);
} else {
- i = in8(PIXIS_BASE + PIXIS_SPD);
+ i = in_8(pixis_base + PIXIS_SPD);
}
i &= 0x07;
void board_reset(void)
{
- out8(PIXIS_BASE + PIXIS_RST, 0);
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+ out_8(pixis_base + PIXIS_RST, 0);
while (1)
;
#include <common.h>
+#include <netdev.h>
#include <asm/arch/mx31.h>
#include <asm/arch/mx31-regs.h>
printf("Board: i.MX31 MAX PDK (3DS)\n");
return 0;
}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
int checkboard(void)
{
+ u8 sw7;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
puts("Board: P2020DS ");
#ifdef CONFIG_PHYS_64BIT
puts("(36-bit addrmap) ");
#endif
+
printf("Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
- in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
- in8(PIXIS_BASE + PIXIS_PVER));
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+ in_8(pixis_base + PIXIS_PVER));
+
+ sw7 = in_8(pixis_base + PIXIS_SW(7));
+ switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) {
+ case 0:
+ case 1:
+ printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
+ break;
+ case 2:
+ case 3:
+ puts ("Promjet\n");
+ break;
+ }
+
return 0;
}
calculate_board_sys_clk(ulong dummy)
{
ulong val;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
val = ics307_clk_freq(
- in8(PIXIS_BASE + PIXIS_VSYSCLK0),
- in8(PIXIS_BASE + PIXIS_VSYSCLK1),
- in8(PIXIS_BASE + PIXIS_VSYSCLK2));
+ in_8(pixis_base + PIXIS_VSYSCLK0),
+ in_8(pixis_base + PIXIS_VSYSCLK1),
+ in_8(pixis_base + PIXIS_VSYSCLK2));
debug("sysclk val = %lu\n", val);
return val;
}
calculate_board_ddr_clk(ulong dummy)
{
ulong val;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
val = ics307_clk_freq(
- in8(PIXIS_BASE + PIXIS_VDDRCLK0),
- in8(PIXIS_BASE + PIXIS_VDDRCLK1),
- in8(PIXIS_BASE + PIXIS_VDDRCLK2));
+ in_8(pixis_base + PIXIS_VDDRCLK0),
+ in_8(pixis_base + PIXIS_VDDRCLK1),
+ in_8(pixis_base + PIXIS_VDDRCLK2));
debug("ddrclk val = %lu\n", val);
return val;
}
{
u8 i;
ulong val = 0;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- i = in8(PIXIS_BASE + PIXIS_SPD);
+ i = in_8(pixis_base + PIXIS_SPD);
i &= 0x07;
switch (i) {
{
u8 i;
ulong val = 0;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- i = in8(PIXIS_BASE + PIXIS_SPD);
+ i = in_8(pixis_base + PIXIS_SPD);
i &= 0x38;
i >>= 3;
return ret;
}
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CONFIG_SYS_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
-
-
#if 0 /* test-only !!! */
int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
--- /dev/null
+#
+# (C) Copyright 2008
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+SOBJS := init.o
+
+COBJS := $(COBJS-y)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2008-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+ {
+ "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "800-nor", "NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1000-nor", "NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1066-nor", "NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88",
+ {
+ 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1066-nand", "NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88",
+ {
+ 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on board/amcc/canyonlands/canyonlands.c
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc440.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/4xx_pcie.h>
+#include <asm/gpio.h>
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CONFIG_SYS_BCSR3_PCIE 0x10
+
+int board_early_init_f(void)
+{
+ /*
+ * Setup the interrupt controller polarities, triggers, etc.
+ */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+ mtdcr(uic2er, 0x00000000); /* disable all */
+ mtdcr(uic2cr, 0x00000000); /* all non-critical */
+ mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic3sr, 0xffffffff); /* clear all */
+ mtdcr(uic3er, 0x00000000); /* disable all */
+ mtdcr(uic3cr, 0x00000000); /* all non-critical */
+ mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic3sr, 0xffffffff); /* clear all */
+
+ /*
+ * Configure PFC (Pin Function Control) registers
+ * enable GPIO 49-63
+ * UART0: 4 pins
+ */
+ mtsdr(SDR0_PFC0, 0x00007fff);
+ mtsdr(SDR0_PFC1, 0x00040000);
+
+ /* Enable PCI host functionality in SDR0_PCI0 */
+ mtsdr(SDR0_PCI0, 0xe0000000);
+
+ mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
+
+ /* Setup PLB4-AHB bridge based on the system address map */
+ mtdcr(AHB_TOP, 0x8000004B);
+ mtdcr(AHB_BOT, 0x8000004B);
+
+ /*
+ * Configure USB-STP pins as alternate and not GPIO
+ * It seems to be neccessary to configure the STP pins as GPIO
+ * input at powerup (perhaps while USB reset is asserted). So
+ * we configure those pins to their "real" function now.
+ */
+ gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+ gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+
+ /* Trigger board component reset */
+ out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
+ out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
+ udelay(50);
+ out_le16((void *)CONFIG_SYS_IO_BASE, 0xffbf);
+ out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffbf);
+ udelay(50);
+ out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
+ out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
+
+ return 0;
+}
+
+int get_cpu_num(void)
+{
+ int cpu = NA_OR_UNKNOWN_CPU;
+
+ return cpu;
+}
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+#ifdef CONFIG_DEVCONCENTER
+ printf("Board: DevCon-Center");
+#else
+ printf("Board: CompactCenter");
+#endif
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+/*
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ /*
+ * Disable everything
+ */
+ out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
+ out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
+ out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
+ out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
+
+ /*
+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
+ * strapping options to not support sizes such as 128/256 MB.
+ */
+ out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+ out_le32((void *)PCIX0_PIM0LAH, 0);
+ out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+ out_le32((void *)PCIX0_BAR0, 0);
+
+ /*
+ * Program the board's subsystem id/vendor id
+ */
+ out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+ out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+
+ out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+}
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
+
+#if defined(CONFIG_PCI)
+/*
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+int is_pci_host(struct pci_controller *hose)
+{
+ /* Board is always configured as host. */
+ return 1;
+}
+#endif /* CONFIG_PCI */
+
+int board_early_init_r(void)
+{
+ /*
+ * CompactCenter has 64MBytes, DevCon-Center 128MBytes of NOR FLASH
+ * (Spansion 29GL512), but the boot EBC mapping only supports a maximum
+ * of 16MBytes (4.ff00.0000 - 4.ffff.ffff).
+ * To solve this problem, the FLASH has to get remapped to another
+ * EBC address which accepts bigger regions:
+ *
+ * 0xfn00.0000 -> 4.cn00.0000
+ */
+
+ u32 bxcr_bw = (CONFIG_SYS_FLASH_SIZE == 128 << 20) ?
+ EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB;
+
+ /* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */
+ mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L
+ | bxcr_bw
+ | EBC_BXCR_BU_RW
+ | EBC_BXCR_BW_16BIT);
+
+ /* Remove TLB entry of boot EBC mapping */
+ remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
+
+ /* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
+ program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
+
+ /*
+ * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
+ * 0xfc00.0000 is possible
+ */
+
+ /*
+ * Clear potential errors resulting from auto-calibration.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ u32 sdr0_srst1 = 0;
+ u32 eth_cfg;
+
+ /*
+ * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
+ * This is board specific, so let's do it here.
+ */
+ mfsdr(SDR0_ETH_CFG, eth_cfg);
+ /* disable SGMII mode */
+ eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
+ SDR0_ETH_CFG_SGMII1_ENABLE |
+ SDR0_ETH_CFG_SGMII0_ENABLE);
+ /* Set the for 2 RGMII mode */
+ /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
+ eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
+ eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+ mtsdr(SDR0_ETH_CFG, eth_cfg);
+
+ /*
+ * The AHB Bridge core is held in reset after power-on or reset
+ * so enable it now
+ */
+ mfsdr(SDR0_SRST1, sdr0_srst1);
+ sdr0_srst1 &= ~SDR0_SRST1_AHB;
+ mtsdr(SDR0_SRST1, sdr0_srst1);
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ __ft_board_setup(blob, bd);
+
+ fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
+ "disabled", sizeof("disabled"), 1);
+
+ fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
+ "disabled", sizeof("disabled"), 1);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
--- /dev/null
+#
+# (C) Copyright 2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# G&D CompactCenter
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFA0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on board/amcc/canyonlands/init.S
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm-ppc/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
+ * use the speed up boot process. It is patched after relocation to
+ * enable SA_I
+ */
+ tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
+ 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
+ 0, AC_R|AC_W|AC_X|SA_G)
+#endif
+
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
+ AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC,
+ AC_R|AC_W|SA_G|SA_I)
+
+ /* TLB-entry for NVRAM */
+ tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4,
+ AC_R|AC_W|SA_G|SA_I)
+
+ /* TLB-entry for UART */
+ tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4,
+ AC_R|AC_W|SA_G|SA_I)
+
+ /* TLB-entry for IO */
+ tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4,
+ AC_R|AC_W|SA_G|SA_I)
+
+ /* TLB-entry for OCM */
+ tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
+ AC_R|AC_W|AC_X|SA_I)
+
+ /* TLB-entry for Local Configuration registers => peripherals */
+ tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS,
+ 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ /* AHB: Internal USB Peripherals (USB, SATA) */
+ tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4,
+ AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ tlbtab_end
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/gdsys/compactcenter/init.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ }
+
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o
+SOBJS =
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFFC0000
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+enum {
+ HWTYPE_DLVISION_CPU = 0,
+ HWTYPE_DLVISION_CON = 1,
+};
+
+#define HWREV_100 6
+
+int board_early_init_f(void)
+{
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
+ mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
+ mtdcr(uictr, 0x10000000); /* set int trigger levels */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks
+ * -> ca. 15 us
+ */
+ mtebc(epcr, 0xa8400000); /* ebc always driven */
+
+ /*
+ * setup io-latches
+ */
+ out_le16((void *)CONFIG_SYS_LATCH_BASE, 0x00f0);
+ out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x100), 0x0002);
+ out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x200), 0x0000);
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ /*
+ * set "startup-finished"-gpios
+ */
+ gpio_write_bit(21, 0);
+ gpio_write_bit(22, 1);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+ u8 channel2_msr = in_8((void *)CONFIG_UART_BASE + 0x26);
+ u8 channel3_msr = in_8((void *)CONFIG_UART_BASE + 0x36);
+ u8 channel7_msr = in_8((void *)CONFIG_UART_BASE + 0x76);
+ u8 unit_type;
+ u8 local_con;
+ u8 audio;
+ u8 hardware_version;
+
+ printf("Board: ");
+
+ unit_type = (channel2_msr & 0x80) ? 0x01 : 0x00;
+ local_con = (channel2_msr & 0x20) ? 0x01 : 0x00;
+ audio = (channel3_msr & 0x20) ? 0x01 : 0x00;
+ hardware_version =
+ ((channel7_msr & 0x20) ? 0x01 : 0x00)
+ | ((channel7_msr & 0x80) ? 0x02 : 0x00)
+ | ((channel7_msr & 0x40) ? 0x04 : 0x00);
+
+ switch (unit_type) {
+ case HWTYPE_DLVISION_CON:
+ printf("DL-Vision-CON");
+ break;
+
+ case HWTYPE_DLVISION_CPU:
+ printf("DL-Vision-CPU");
+ break;
+
+ default:
+ printf("UnitType %d, unsupported", unit_type);
+ break;
+ }
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ puts("\n ");
+
+ switch (hardware_version) {
+ case HWREV_100:
+ printf("HW-Ver 1.00");
+ break;
+
+ default:
+ printf("HW-Ver %d, unsupported",
+ hardware_version);
+ break;
+ }
+
+ if (local_con)
+ printf(", local console");
+
+ if (audio)
+ printf(", audio support");
+
+ puts("\n");
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/ppc4xx/start.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
#include <common.h>
+#include <netdev.h>
#include <asm/arch/mx31.h>
#include <asm/arch/mx31-regs.h>
printf("Board: i.MX31 Litekit\n");
return 0;
}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
#include <common.h>
#include <s6e63d6.h>
+#include <netdev.h>
#include <asm/arch/mx31.h>
#include <asm/arch/mx31-regs.h>
printf("Board: Phytec phyCore i.MX31\n");
return 0;
}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
crceeprom = (buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 1] + \
buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2] * 256);
if (crc != crceeprom) {
- printf ("Error CRC Block: %d EEprom: calculated: %lx EEprom: %lx\n",
- block, crc, crceeprom);
+ if (block == 0)
+ printf ("Error CRC Block: %d EEprom: calculated: \
+ %lx EEprom: %lx\n", block, crc, crceeprom);
return -1;
}
return 0;
GET_STRING("IVM_CustomerProductID", IVM_POS_CUSTOMER_PROD_ID, 32)
if (ivm_check_crc (&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], 2) != 0)
- return -2;
+ return 0;
ivm_analyze_block2 (&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], CONFIG_SYS_IVM_EEPROM_PAGE_LEN);
return 0;
#endif
+#if !defined(CONFIG_KMETER1)
static void writeStartSeq (void)
{
set_sda (1);
get_sda ();
return ret;
}
+#endif
/**
* i2c_init_board - reset i2c bus. When the board is powercycled during a
*/
void i2c_init_board(void)
{
+#if defined(CONFIG_KMETER1)
+ struct fsl_i2c *dev;
+ dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
+ uchar dummy;
+
+ out_8 (&dev->cr, (I2C_CR_MSTA));
+ out_8 (&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+ dummy = in_8(&dev->dr);
+ dummy = in_8(&dev->dr);
+ if (dummy != 0xff) {
+ dummy = in_8(&dev->dr);
+ }
+ out_8 (&dev->cr, (I2C_CR_MEN));
+ out_8 (&dev->cr, 0x00);
+ out_8 (&dev->cr, (I2C_CR_MEN));
+
+#else
#if defined(CONFIG_HARD_I2C)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
/* Set the PortPins back to use for I2C */
setports (0);
#endif
+#endif
}
#endif
#endif
}
return ret;
}
+int fdt_get_node_and_value (void *blob,
+ char *nodename,
+ char *propname,
+ void **var)
+{
+ int len;
+ int nodeoffset = 0;
+
+ nodeoffset = fdt_path_offset (blob, nodename);
+ if (nodeoffset >= 0) {
+ *var = (void *)fdt_getprop (blob, nodeoffset, propname, &len);
+ if (len == 0) {
+ /* no value */
+ printf ("%s no value\n", __FUNCTION__);
+ return -1;
+ } else if (len > 0) {
+ return len;
+ } else {
+ printf ("libfdt fdt_getprop(): %s\n",
+ fdt_strerror(len));
+ return -2;
+ }
+ } else {
+ printf("%s: cannot find %s node err:%s\n", __FUNCTION__,
+ nodename, fdt_strerror (nodeoffset));
+ return -3;
+ }
+}
#endif
int ethernet_present (void)
#ifdef CONFIG_KEYMILE_HDLC_ENET
int keymile_hdlc_enet_initialize (bd_t *bis);
#endif
+
+int fdt_set_node_and_value (void *blob,
+ char *nodename,
+ char *regname,
+ void *var,
+ int size);
+int fdt_get_node_and_value (void *blob,
+ char *nodename,
+ char *propname,
+ void **var);
#endif /* __KEYMILE_COMMON_H */
}
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-extern int fdt_set_node_and_value (void *blob,
- char *nodename,
- char *regname,
- void *var,
- int size);
-
/*
* update "memory" property in the blob
*/
{
ulong brg_data[1] = {0};
ulong memory_data[2] = {0};
- ulong flash_data[4] = {0};
+ ulong *flash_data = NULL;
ulong flash_reg[3] = {0};
- uchar enetaddr[6];
+ flash_info_t *info;
+ int len;
+ int i = 0;
memory_data[0] = cpu_to_be32 (bd->bi_memstart);
memory_data[1] = cpu_to_be32 (bd->bi_memsize);
fdt_set_node_and_value (blob, "/memory", "reg", memory_data,
sizeof (memory_data));
- flash_data[2] = cpu_to_be32 (bd->bi_flashstart);
- flash_data[3] = cpu_to_be32 (bd->bi_flashsize);
+ len = fdt_get_node_and_value (blob, "/localbus", "ranges",
+ (void *)&flash_data);
+
+ if (flash_data == NULL) {
+ printf ("%s: error /localbus/ranges entry\n", __FUNCTION__);
+ return;
+ }
+
+ /* update Flash addr, size */
+ while ( i < (len / 4)) {
+ switch (flash_data[i]) {
+ case 0:
+ info = flash_get_info(CONFIG_SYS_FLASH_BASE);
+ flash_data[i + 1] = 0;
+ flash_data[i + 2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
+ flash_data[i + 3] = cpu_to_be32 (info->size);
+ break;
+ default:
+ break;
+ }
+ i += 4;
+ }
fdt_set_node_and_value (blob, "/localbus", "ranges", flash_data,
- sizeof (flash_data));
+ len);
flash_reg[2] = cpu_to_be32 (bd->bi_flashsize);
fdt_set_node_and_value (blob, "/localbus/flash@0,0", "reg", flash_reg,
sizeof (flash_reg));
-
/* BRG */
brg_data[0] = cpu_to_be32 (bd->bi_busfreq);
fdt_set_node_and_value (blob, "/soc/cpm", "brg-frequency", brg_data,
sizeof (brg_data));
/* MAC adr */
- eth_getenv_enetaddr("ethaddr", enetaddr);
fdt_set_node_and_value (blob, "/soc/cpm/ethernet", "mac-address",
- enetaddr, sizeof (u8) * 6);
+ bd->bi_enetaddr, sizeof (u8) * 6);
}
void ft_board_setup(void *blob, bd_t *bd)
}
#if defined(CONFIG_OF_BOARD_SETUP)
+/*
+ * update "/localbus/ranges" property in the blob
+ */
+void ft_blob_update (void *blob, bd_t *bd)
+{
+ ulong *flash_data = NULL;
+ flash_info_t *info;
+ ulong flash_reg[6] = {0};
+ int len;
+ int size = 0;
+ int i = 0;
+
+ len = fdt_get_node_and_value (blob, "/localbus", "ranges",
+ (void *)&flash_data);
+
+ if (flash_data == NULL) {
+ printf ("%s: error /localbus/ranges entry\n", __FUNCTION__);
+ return;
+ }
+
+ /* update Flash addr, size */
+ while ( i < (len / 4)) {
+ switch (flash_data[i]) {
+ case 0:
+ info = flash_get_info(CONFIG_SYS_FLASH_BASE);
+ size = info->size;
+ info = flash_get_info(CONFIG_SYS_FLASH_BASE_1);
+ size += info->size;
+ flash_data[i + 1] = 0;
+ flash_data[i + 2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
+ flash_data[i + 3] = cpu_to_be32 (size);
+ break;
+ default:
+ break;
+ }
+ i += 4;
+ }
+ fdt_set_node_and_value (blob, "/localbus", "ranges", flash_data,
+ len);
+
+ info = flash_get_info(CONFIG_SYS_FLASH_BASE);
+ flash_reg[2] = cpu_to_be32 (size);
+ flash_reg[4] = flash_reg[2];
+ info = flash_get_info(CONFIG_SYS_FLASH_BASE_1);
+ flash_reg[5] = cpu_to_be32 (info->size);
+ fdt_set_node_and_value (blob, "/localbus/flash@f0000000,0", "reg", flash_reg,
+ sizeof (flash_reg));
+}
+
+
void ft_board_setup (void *blob, bd_t *bd)
{
ft_cpu_setup (blob, bd);
+ ft_blob_update (blob, bd);
}
#endif
}
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-extern int fdt_set_node_and_value (void *blob,
- char *nodename,
- char *regname,
- void *var,
- int size);
-
/*
* update "memory" property in the blob
*/
void ft_blob_update (void *blob, bd_t *bd)
{
ulong memory_data[2] = {0};
- ulong flash_data[8] = {0};
+ ulong *flash_data = NULL;
+ ulong flash_reg[6] = {0};
flash_info_t *info;
- uchar enetaddr[6];
+ int len;
+ int size;
+ int i = 0;
memory_data[0] = cpu_to_be32 (bd->bi_memstart);
memory_data[1] = cpu_to_be32 (bd->bi_memsize);
fdt_set_node_and_value (blob, "/memory", "reg", memory_data,
sizeof (memory_data));
+ len = fdt_get_node_and_value (blob, "/localbus", "ranges",
+ (void *)&flash_data);
+
+ if (flash_data == NULL) {
+ printf ("%s: error /localbus/ranges entry\n", __FUNCTION__);
+ return;
+ }
+
/* update Flash addr, size */
- info = flash_get_info(CONFIG_SYS_FLASH_BASE);
- flash_data[2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
- flash_data[3] = cpu_to_be32 (info->size);
- flash_data[4] = cpu_to_be32 (5);
- flash_data[5] = cpu_to_be32 (0);
- info = flash_get_info(CONFIG_SYS_FLASH_BASE_1);
- flash_data[6] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE_1);
- flash_data[7] = cpu_to_be32 (info->size);
+ while ( i < (len / 4)) {
+ switch (flash_data[i]) {
+ case 0:
+ info = flash_get_info(CONFIG_SYS_FLASH_BASE);
+ flash_data[i + 1] = 0;
+ flash_data[i + 2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
+ flash_data[i + 3] = cpu_to_be32 (info->size);
+ break;
+ case 5:
+ info = flash_get_info(CONFIG_SYS_FLASH_BASE_1);
+ size = info->size;
+ info = flash_get_info(CONFIG_SYS_FLASH_BASE_2);
+ size += info->size;
+ flash_data[i + 1] = 0;
+ flash_data[i + 2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE_1);
+ flash_data[i + 3] = cpu_to_be32 (size);
+ break;
+ default:
+ break;
+ }
+ i += 4;
+ }
fdt_set_node_and_value (blob, "/localbus", "ranges", flash_data,
- sizeof (flash_data));
+ len);
+
+ info = flash_get_info(CONFIG_SYS_FLASH_BASE_1);
+ flash_reg[0] = cpu_to_be32 (5);
+ flash_reg[2] = cpu_to_be32 (info->size);
+ flash_reg[3] = flash_reg[0];
+ flash_reg[4] = flash_reg[2];
+ info = flash_get_info(CONFIG_SYS_FLASH_BASE_2);
+ flash_reg[5] = cpu_to_be32 (info->size);
+ fdt_set_node_and_value (blob, "/localbus/flash@5,0", "reg", flash_reg,
+ sizeof (flash_reg));
+
/* MAC addr */
- eth_getenv_enetaddr("ethaddr", enetaddr);
fdt_set_node_and_value (blob, "/soc/cpm/ethernet", "mac-address",
- enetaddr, sizeof (u8) * 6);
+ bd->bi_enetaddr, sizeof (u8) * 6);
}
void ft_board_setup (void *blob, bd_t *bd)
*/
#include <common.h>
#include <ns16550.h>
-#include <console.h>
+#include <stdio_dev.h>
/* Button codes from the AVR */
#define PWRR 0x20 /* Power button release */
#
-# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+# Copyright (C) Freescale Semiconductor, Inc. 2006.
#
# See file CREDITS for list of people who contributed to this
# project.
#
-# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+# Copyright (C) Freescale Semiconductor, Inc. 2006.
#
# See file CREDITS for list of people who contributed to this
# project.
/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
*
* (C) Copyright 2008
* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
*
* (C) Copyright 2008
* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
#include "vct.h"
* Accessor functions replacing the "weak" functions in
* drivers/net/smc911x.c
*/
-u32 smc911x_reg_read(u32 addr)
+u32 smc911x_reg_read(struct eth_device *dev, u32 addr)
{
volatile u32 data;
+ addr += dev->iobase;
reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F);
ebi_wait();
reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr));
return (data);
}
-void smc911x_reg_write(u32 addr, u32 data)
+void smc911x_reg_write(struct eth_device *dev, u32 addr, u32 data)
{
+ addr += dev->iobase;
reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F);
ebi_wait();
reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data);
ebi_wait();
}
-void pkt_data_push(u32 addr, u32 data)
+void pkt_data_push(struct eth_device *dev, u32 addr, u32 data)
{
+ addr += dev->iobase;
reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A);
ebi_wait();
reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data);
return;
}
-u32 pkt_data_pull(u32 addr)
+u32 pkt_data_pull(struct eth_device *dev, u32 addr)
{
volatile u32 data;
+ addr += dev->iobase;
reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A);
ebi_wait();
reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr));
return data;
}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_DRIVER_SMC911X_BASE);
+#endif
+ return rc;
+}
#include <common.h>
#include <command.h>
+#include <netdev.h>
#include <asm/mipsregs.h>
#include "vct.h"
return 0;
}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix.h>
#include <asm/arch/portmux.h>
+#include <atmel_lcdc.h>
#include <lcd.h>
#include "../../../cpu/at32ap/hsmc3.h"
+#if defined(CONFIG_LCD)
+/* 480x272x16 @ 72 Hz */
+vidinfo_t panel_info = {
+ .vl_col = 480, /* Number of columns */
+ .vl_row = 272, /* Number of rows */
+ .vl_clk = 10000000, /* pixel clock in ps */
+ .vl_sync = ATMEL_LCDC_INVCLK_INVERTED |
+ ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+ .vl_bpix = LCD_COLOR16, /* Bits per pixel, BPP = 2^n */
+ .vl_tft = 1, /* 0 = passive, 1 = TFT */
+ .vl_hsync_len = 42, /* Length of horizontal sync */
+ .vl_left_margin = 1, /* Time from sync to picture */
+ .vl_right_margin = 1, /* Time from picture to sync */
+ .vl_vsync_len = 1, /* Length of vertical sync */
+ .vl_upper_margin = 12, /* Time from sync to picture */
+ .vl_lower_margin = 1, /* Time from picture to sync */
+ .mmio = LCDC_BASE, /* Memory mapped registers */
+};
+
+void lcd_enable(void)
+{
+}
+
+void lcd_disable(void)
+{
+}
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
static const struct sdram_config sdram_config = {
portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
+#if defined(CONFIG_LCD)
+ portmux_enable_lcdc(1);
+#endif
+
return 0;
}
#include <asm/processor.h>
#include <asm/byteorder.h>
#include <i2c.h>
-#include <devices.h>
#include <pci.h>
#include <malloc.h>
#include <bzlib.h>
}
}
-
-extern device_t *stdio_devices[];
-extern char *stdio_names[];
-
-void show_stdio_dev(void)
-{
- /* Print information */
- puts("In: ");
- if (stdio_devices[stdin] == NULL) {
- puts("No input devices available!\n");
- } else {
- printf ("%s\n", stdio_devices[stdin]->name);
- }
-
- puts("Out: ");
- if (stdio_devices[stdout] == NULL) {
- puts("No output devices available!\n");
- } else {
- printf ("%s\n", stdio_devices[stdout]->name);
- }
-
- puts("Err: ");
- if (stdio_devices[stderr] == NULL) {
- puts("No error devices available!\n");
- } else {
- printf ("%s\n", stdio_devices[stderr]->name);
- }
-}
-
#endif /* #if !defined(CONFIG_PATI) */
int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#define BOOT_PCI 0x02
#endif
-void show_stdio_dev(void);
void check_env(void);
#if defined(CONFIG_CMD_DOC)
void doc_init (void);
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
- volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+ volatile FLASH_WORD_SIZE *addr2 = (volatile FLASH_WORD_SIZE *)(info->start[0]);
+ volatile FLASH_WORD_SIZE *dest2 = (volatile FLASH_WORD_SIZE *)dest;
+ volatile FLASH_WORD_SIZE *data2;
ulong start;
+ ulong *data_p;
int flag;
int i;
+ data_p = &data;
+ data2 = (volatile FLASH_WORD_SIZE *)data_p;
+
/* Check if Flash is (sufficiently) erased */
if ((*((volatile FLASH_WORD_SIZE *)dest) &
(FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
#include <common.h>
#include <asm/processor.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include "isa.h"
#include "piix4_pci.h"
#include "kbd.h"
*/
#include <common.h>
#include <asm/processor.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include "isa.h"
#include "kbd.h"
int drv_isa_kbd_init (void)
{
int error;
- device_t kbddev ;
+ struct stdio_dev kbddev ;
char *stdinname = getenv ("stdin");
if(isa_kbd_init()==-1)
kbddev.getc = kbd_getc ;
kbddev.tstc = kbd_testc ;
- error = device_register (&kbddev);
+ error = stdio_register (&kbddev);
if(error==0) {
/* check if this is the standard input device */
if(strcmp(stdinname,DEVNAME)==0) {
#include <4xx_i2c.h>
#include <miiphy.h>
#include "../common/common_util.h"
+#include <stdio_dev.h>
#include <i2c.h>
#include <rtc.h>
start=get_timer(0);
/* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
if (mfdcr(strap) & PSR_ROM_LOC)
- mtspr(ccr0, (mfspr(ccr0) & ~0x80));
+ mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
return (0);
}
printf ("Error writing to the PHY\n");
}
print_mip405_rev ();
- show_stdio_dev ();
+ stdio_print_current_devices ();
check_env ();
/* check if RTC time is valid */
stop=get_timer(start);
static int pati_pci_eeprom_read(unsigned short offset, unsigned long addr, unsigned short size)
{
int i;
- unsigned short value;
+ unsigned short value = 0;
unsigned short *buffer =(unsigned short *)addr;
if((offset + size) > PATI_EEPROM_LAST_OFFSET) {
size = PATI_EEPROM_LAST_OFFSET - offset;
#include <common.h>
#include <mpc5xx.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <pci_ids.h>
#define PLX9056_LOC
#include "plx9056.h"
int checkboard (void)
{
- unsigned char s[50];
- unsigned long reg;
+ char s[50];
+ ulong reg;
char rev;
int i;
int recbuf[REC_BUFFER_SIZE];
static int r_ptr = 0;
int w_ptr;
-device_t pci_con_dev;
+struct stdio_dev pci_con_dev;
int conn=0;
int buff_full=0;
pci_con_dev.puts = pci_con_puts;
pci_con_dev.getc = pci_con_getc;
pci_con_dev.tstc = pci_con_tstc;
- device_register (&pci_con_dev);
+ stdio_register (&pci_con_dev);
printf("PATI ready for PCI connection, type ctrl-c for exit\n");
do {
udelay(10);
#include "pip405.h"
#include <asm/processor.h>
#include <i2c.h>
+#include <stdio_dev.h>
#include "../common/isa.h"
#include "../common/common_util.h"
/* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
if (mfdcr(strap) & PSR_ROM_LOC)
- mtspr(ccr0, (mfspr(ccr0) & ~0x80));
+ mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
return (0);
}
{
print_pip405_rev ();
isa_init ();
- show_stdio_dev ();
+ stdio_print_current_devices ();
check_env();
return 0;
}
#include <common.h>
#include <s3c2410.h>
+#include <stdio_dev.h>
#include <i2c.h>
#include "vcma9.h"
{
mem_test_reloc();
checkboard();
- show_stdio_dev();
+ stdio_print_current_devices();
check_env();
return 0;
}
return 0;
}
-#if defined(CONFIG_CMD_NAND)
-
-#include <linux/mtd/nand_legacy.h>
-
-extern ulong nand_probe(ulong physadr);
-extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- unsigned long totlen;
-
- totlen = nand_probe(CONFIG_SYS_NAND_BASE);
- printf ("%4lu MB\n", totlen >> 20);
-}
-#endif
-
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
#include <version.h>
#include <linux/types.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <sed156x.h>
int drv_phone_init(void)
{
- device_t console_dev;
+ struct stdio_dev console_dev;
console_init();
console_dev.tstc = phone_tstc; /* 'tstc' function */
console_dev.getc = phone_getc; /* 'getc' function */
- if (device_register(&console_dev) == 0)
+ if (stdio_register(&console_dev) == 0)
return 1;
return 0;
/*
* Initiate system reset in debug control register DBCR
*/
- dbcr = mfspr(dbcr0);
- mtspr(dbcr0, dbcr | CHIP_RESET);
+ dbcr = mfspr(SPRN_DBCR0);
+ mtspr(SPRN_DBCR0, dbcr | CHIP_RESET);
}
mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
#endif
/* We cannot easily enable trace before, as there are other
* routines messing around with sdr0_pfc1. And I do not need it.
*/
- if (mfspr(dbcr0) & 0x80000000) {
+ if (mfspr(SPRN_DBCR0) & 0x80000000) {
/* External debugger alive
* enable trace facilty for Lauterbach
* CCR0[DTB]=0 Enable broadcast of trace information
* SDR0_PFC0[TRE] Trace signals are enabled instead of
* GPIO49-63
*/
- mtspr(ccr0, mfspr(ccr0) &~ (CCR0_DTB));
+ mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) &~ (CCR0_DTB));
mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
}
return 0;
u32 *magicPtr;
u32 magic;
- if ((mfspr(dbcr0) & 0x80000000) == 0) {
+ if ((mfspr(SPRN_DBCR0) & 0x80000000) == 0) {
/* only if no external debugger is alive!
* Check whether vxWorks is using EDR logging, if yes zero
* also PostMortem and user reserved memory
* If not done, then we could get an interrupt later on when
* exceptions are enabled.
*/
- mtspr(mcsr, mfspr(mcsr));
+ mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
/* Set 'int_mask' parameter to functionnal value */
mfsdram(DDR0_01, val);
out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR );
out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR);
out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR);
- mtspr(ccr0, 0x00700000);
+ mtspr(SPRN_CCR0, 0x00700000);
return 0;
}
LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds
lnk = $(if $(obj),$(obj),.)
-HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+HOSTCFLAGS = -Wall -pedantic -I$(TOPDIR)/include
all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin \
$(obj)crcek.srec $(obj)crcek.bin $(obj)crcit
$(obj)eeprom.srec: $(obj)eeprom.o $(obj)eeprom_start.o
cd $(lnk) && $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \
-o $(<:.o=) -e eeprom eeprom.o eeprom_start.o \
- -L$(obj)../../examples -lstubs \
+ -L$(obj)../../examples/standalone -lstubs \
-L$(obj)../../lib_generic -lgeneric \
-L$(gcclibdir) -lgcc
$(OBJCOPY) -O srec $(<:.o=) $@
$(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
$(obj)crcit: $(obj)crcit.o $(obj)crc32.o
- $(HOSTCC) $(HOST_CFLAGS) -o $@ $^
+ $(HOSTCC) $(HOSTCFLAGS) -o $@ $^
$(obj)crcit.o: crcit.c
- $(HOSTCC) $(HOST_CFLAGS) -o $@ -c $<
+ $(HOSTCC) $(HOSTCFLAGS) -o $@ -c $<
$(obj)crc32.o: $(SRCTREE)/lib_generic/crc32.c
- $(HOSTCC) $(HOST_CFLAGS) -DUSE_HOSTCC -o $@ -c $<
+ $(HOSTCC) $(HOSTCFLAGS) -DUSE_HOSTCC -o $@ -c $<
clean:
rm -f $(SOBJS) $(OBJS) $(obj)eeprom $(obj)eeprom.srec \
return 0;
}
-#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
-
-#include <linux/mtd/nand_legacy.h>
-
-extern ulong nand_probe(ulong physadr);
-extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- unsigned long totlen = nand_probe(CONFIG_SYS_NAND_BASE);
-
- printf ("%4lu MB\n", totlen >> 20);
-}
-#endif
-
#if defined(CONFIG_CMD_PCMCIA)
int pcmcia_init(void)
return 0;
}
-#if defined(CONFIG_CMD_NAND)
-
-#include <linux/mtd/nand_legacy.h>
-
-extern ulong nand_probe(ulong physadr);
-extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- unsigned long totlen;
-
- totlen = nand_probe(CONFIG_SYS_NAND_BASE);
- printf ("%4lu MB\n", totlen >> 20);
-}
-#endif
-
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
return 0;
}
-
-#if defined(CONFIG_CMD_NAND)
-
-#include <linux/mtd/nand_legacy.h>
-
-extern ulong nand_probe(ulong physadr);
-extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- unsigned long totlen = nand_probe(CONFIG_SYS_NAND_BASE);
-
- printf ("%4lu MB\n", totlen >> 20);
-}
-#endif
#include <asm/arch/mem.h>
#include <i2c.h>
#include <asm/mach-types.h>
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
-#endif
DECLARE_GLOBAL_DATA_PTR;
}
}
}
-
-#if defined(CONFIG_CMD_NAND)
-void nand_init(void)
-{
- extern flash_info_t flash_info[];
-
- nand_probe(CONFIG_SYS_NAND_ADDR);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-
-#ifdef CONFIG_SYS_JFFS2_MEM_NAND
- flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id;
- flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].size = 1024*1024*2; /* only read kernel single meg partition */
- flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */
- flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */
-#endif
-}
-#endif
* MA 02111-1307 USA
*/
#include <common.h>
+#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
- power_init_r();
+ twl4030_power_init();
+ twl4030_led_init();
/* Configure GPIOs to output */
writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
+++ /dev/null
-/*
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <i2c.h>
-
-/******************************************************************************
- * Routine: power_init_r
- * Description: Configure power supply
- *****************************************************************************/
-void power_init_r(void)
-{
- unsigned char byte;
-
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
- /*
- * Configure OMAP3 supply voltages in power management
- * companion chip.
- */
-
- /* set VAUX3 to 2.8V */
- byte = DEV_GRP_P1;
- i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEV_GRP, 1, &byte, 1);
- byte = VAUX3_VSEL_28;
- i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEDICATED, 1, &byte, 1);
-
- /* set VPLL2 to 1.8V */
- byte = DEV_GRP_ALL;
- i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEV_GRP, 1, &byte, 1);
- byte = VPLL2_VSEL_18;
- i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEDICATED, 1, &byte, 1);
-
- /* set VDAC to 1.8V */
- byte = DEV_GRP_P1;
- i2c_write(PWRMGT_ADDR_ID4, VDAC_DEV_GRP, 1, &byte, 1);
- byte = VDAC_VSEL_18;
- i2c_write(PWRMGT_ADDR_ID4, VDAC_DEDICATED, 1, &byte, 1);
-
- /* enable LED */
- byte = LEDBPWM | LEDAPWM | LEDBON | LEDAON;
- i2c_write(PWRMGT_ADDR_ID3, LEDEN, 1, &byte, 1);
-}
* MA 02111-1307 USA
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
udelay(1);
writel(GPIO0, &gpio3_base->setdataout);
}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
* MA 02111-1307 USA
*/
#include <common.h>
+#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
*/
int misc_init_r(void)
{
- power_init_r();
+ twl4030_power_init();
+ twl4030_led_init();
dieid_num_r();
* MA 02111-1307 USA
*/
#include <common.h>
+#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
- power_init_r();
+ twl4030_power_init();
+ twl4030_led_init();
/* Configure GPIOs to output */
writel(~(GPIO14 | GPIO15 | GPIO16 | GPIO23), &gpio1_base->oe);
* MA 02111-1307 USA
*/
#include <common.h>
+#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
*/
int misc_init_r(void)
{
- power_init_r();
+ twl4030_power_init();
+ twl4030_led_init();
dieid_num_r();
+
+ /*
+ * Board Reset
+ * The board is reset by holding the red button on the
+ * top right front face for eight seconds.
+ */
+ twl4030_power_reset_init();
+
return 0;
}
#ifdef CONFIG_STATUS_LED
#include <status_led.h>
#endif
+#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mem.h>
int misc_init_r(void)
{
zoom2_identify();
- power_init_r();
+ twl4030_power_init();
+ twl4030_led_init();
dieid_num_r();
+
+ /*
+ * Board Reset
+ * The board is reset by holding the the large button
+ * on the top right side of the main board for
+ * eight seconds.
+ *
+ * There are reported problems of some beta boards
+ * continously resetting. For those boards, disable resetting.
+ */
+ if (ZOOM2_REVISION_PRODUCTION <= zoom2_get_revision())
+ twl4030_power_reset_init();
+
return 0;
}
cpc710_pci_enable_timeout ();
}
+#ifdef CONFIG_CMD_DOC
void doc_init (void)
{
doc_probe (pcippc2_fpga1_phys + HW_FPGA1_DOC);
}
+#endif
void pcippc2_cpci3264_init (void)
{
setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
}
#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
-
#include <common.h>
#include <net.h>
#include "mv_regs.h"
-#include "ppc_error_no.h"
+#include <asm/errno.h>
#include "../../Marvell/include/core.h"
/*************************************************************************
#include <common.h>
#include <watchdog.h>
#include <commproc.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <lcd.h>
DECLARE_GLOBAL_DATA_PTR;
int drv_keyboard_init(void)
{
int error = 0;
- device_t kbd_dev;
+ struct stdio_dev kbd_dev;
if (0) {
/* register the keyboard */
- memset (&kbd_dev, 0, sizeof(device_t));
+ memset (&kbd_dev, 0, sizeof(struct stdio_dev));
strcpy(kbd_dev.name, "kbd");
kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
kbd_dev.putc = NULL;
kbd_dev.puts = NULL;
kbd_dev.getc = smc1_getc;
kbd_dev.tstc = smc1_tstc;
- error = device_register (&kbd_dev);
+ error = stdio_register (&kbd_dev);
} else {
lcd_is_enabled = 0;
lcd_disable();
return (get_ram_size (base, maxsize));
}
+#ifdef CONFIG_CMD_DOC
void doc_init (void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
doc_probe (FLASH_BASE1_PRELIM);
}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/processor.h>
udelay(FPGA_NAND_RST_WAIT);
outw(FPGA_NAND_INIT, FPGA_NAND_CTL);
}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/processor.h>
* And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
* functions necessary to solve this problem.
*/
-u32 pkt_data_pull(u32 addr)
+u32 pkt_data_pull(struct eth_device *dev, u32 addr)
{
- volatile u16 *addr_16 = (u16 *)addr;
+ volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
| swab16(*(addr_16 + 1));
}
-void pkt_data_push(u32 addr, u32 val)
+void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
{
+ addr += dev->iobase;
*(volatile u16 *)(addr + 2) = swab16((u16)val);
*(volatile u16 *)(addr) = swab16((u16)(val >> 16));
}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
}
#endif
-#if defined(CONFIG_CMD_NAND) && defined(CONFIG_SYS_NAND_LEGACY)
-#include <linux/mtd/nand.h>
-extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
-void nand_init(void)
-{
- nand_probe(CONFIG_SYS_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN)
- print_size(nand_dev_desc[0].totlen, "\n");
-}
-#endif
-
ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info)
{
if (banknum == 0) { /* non-CFI boot flash */
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o pci.o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
# SBC8349E
#
-TEXT_BASE = 0xFFF00000
+TEXT_BASE = 0xFF800000
/*
* pci.c -- WindRiver SBC8349 PCI board support.
* Copyright (c) 2006 Wind River Systems, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Based on MPC8349 PCI support but w/o PIB related code.
*
*/
#include <asm/mmu.h>
+#include <asm/io.h>
#include <common.h>
-#include <asm/global_data.h>
+#include <mpc83xx.h>
#include <pci.h>
-#include <asm/mpc8349_pci.h>
#include <i2c.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
+#include <asm/fsl_i2c.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_PCI
-
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc8349emds_config_table[] = {
- {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
- }
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
},
- {}
-};
-#endif
-
-static struct pci_controller pci_hose[] = {
- {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc8349emds_config_table,
-#endif
- },
- {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc8349emds_config_table,
-#endif
- }
};
-/**************************************************************************
+/*
* pci_init_board()
*
* NOTICE: PCI2 is not supported. There is only one
void
pci_init_board(void)
{
- volatile immap_t * immr;
- volatile clk83xx_t * clk;
- volatile law83xx_t * pci_law;
- volatile pot83xx_t * pci_pot;
- volatile pcictrl83xx_t * pci_ctrl;
- volatile pciconf83xx_t * pci_conf;
- u16 reg16;
- u32 reg32;
- u32 dev;
- struct pci_controller * hose;
-
- immr = (immap_t *)CONFIG_SYS_IMMR;
- clk = (clk83xx_t *)&immr->clk;
- pci_law = immr->sysconf.pcilaw;
- pci_pot = immr->ios.pot;
- pci_ctrl = immr->pci_ctrl;
- pci_conf = immr->pci_conf;
-
- hose = &pci_hose[0];
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ struct pci_region *reg[] = { pci1_regions };
- /*
- * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
- */
-
- reg32 = clk->occr;
- udelay(2000);
+ /* Enable all 8 PCI_CLK_OUTPUTS */
clk->occr = 0xff000000;
udelay(2000);
- /*
- * Release PCI RST Output signal
- */
- pci_ctrl[0].gcr = 0;
- udelay(2000);
- pci_ctrl[0].gcr = 1;
-
-#ifdef CONFIG_MPC83XX_PCI2
- pci_ctrl[1].gcr = 0;
- udelay(2000);
- pci_ctrl[1].gcr = 1;
-#endif
-
- /* We need to wait at least a 1sec based on PCI specs */
- {
- int i;
-
- for (i = 0; i < 1000; ++i)
- udelay (1000);
- }
-
- /*
- * Configure PCI Local Access Windows
- */
+ /* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
- /*
- * Configure PCI Outbound Translation Windows
- */
-
- /* PCI1 mem space - prefetch */
- pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /* PCI1 IO space */
- pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
-
- /* PCI1 mmio - non-prefetch mem space */
- pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
-
- /* we need RAM mapped to PCI space for the devices to
- * access main memory */
- pci_ctrl[0].pitar1 = 0x0;
- pci_ctrl[0].pibar1 = 0x0;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* PCI memory prefetch space */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI1_MEM_BASE,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM|PCI_REGION_PREFETCH);
-
- /* PCI memory space */
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI1_MMIO_BASE,
- CONFIG_SYS_PCI1_MMIO_PHYS,
- CONFIG_SYS_PCI1_MMIO_SIZE,
- PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose->regions + 2,
- CONFIG_SYS_PCI1_IO_BASE,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(hose->regions + 3,
- CONFIG_PCI_SYS_MEM_BUS,
- CONFIG_PCI_SYS_MEM_PHYS,
- gd->ram_size,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- hose->region_count = 4;
-
- pci_setup_indirect(hose,
- (CONFIG_SYS_IMMR+0x8300),
- (CONFIG_SYS_IMMR+0x8304));
-
- pci_register_hose(hose);
-
- /*
- * Write to Command register
- */
- reg16 = 0xff;
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
-#endif
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
-
-#ifdef CONFIG_MPC83XX_PCI2
- hose = &pci_hose[1];
-
- /*
- * Configure PCI Outbound Translation Windows
- */
-
- /* PCI2 mem space - prefetch */
- pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /* PCI2 IO space */
- pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
-
- /* PCI2 mmio - non-prefetch mem space */
- pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
-
- /* we need RAM mapped to PCI space for the devices to
- * access main memory */
- pci_ctrl[1].pitar1 = 0x0;
- pci_ctrl[1].pibar1 = 0x0;
- pci_ctrl[1].piebar1 = 0x0;
- pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
-
- hose->first_busno = pci_hose[0].last_busno + 1;
- hose->last_busno = 0xff;
-
- /* PCI memory prefetch space */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI2_MEM_BASE,
- CONFIG_SYS_PCI2_MEM_PHYS,
- CONFIG_SYS_PCI2_MEM_SIZE,
- PCI_REGION_MEM|PCI_REGION_PREFETCH);
-
- /* PCI memory space */
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI2_MMIO_BASE,
- CONFIG_SYS_PCI2_MMIO_PHYS,
- CONFIG_SYS_PCI2_MMIO_SIZE,
- PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose->regions + 2,
- CONFIG_SYS_PCI2_IO_BASE,
- CONFIG_SYS_PCI2_IO_PHYS,
- CONFIG_SYS_PCI2_IO_SIZE,
- PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(hose->regions + 3,
- CONFIG_PCI_SYS_MEM_BUS,
- CONFIG_PCI_SYS_MEM_PHYS,
- gd->ram_size,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- hose->region_count = 4;
-
- pci_setup_indirect(hose,
- (CONFIG_SYS_IMMR+0x8380),
- (CONFIG_SYS_IMMR+0x8384));
-
- pci_register_hose(hose);
-
- /*
- * Write to Command register
- */
- reg16 = 0xff;
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
-#endif
-
-}
-
-#if defined(CONFIG_OF_LIBFDT)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
- int nodeoffset;
- int tmp[2];
- const char *path;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
- path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
- tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
-#ifdef CONFIG_MPC83XX_PCI2
- path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
- tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
+ udelay(2000);
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
-#endif
- }
+ mpc83xx_pci_init(1, reg, 0);
}
-#endif /* CONFIG_OF_LIBFDT */
-#endif /* CONFIG_PCI */
ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1A;
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
- ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
+ ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
udelay (500);
- ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1B;
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
asm ("sync; isync");
udelay (500);
ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
- ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1A;
+ ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
- ddr->sdram_mode_1 = CONFIG_SYS_DDR2_MODE_1;
+ ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
udelay (500);
- ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1B;
+ ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
asm ("sync; isync");
udelay (500);
# include <status_led.h>
#endif
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
#define ORMASK(size) ((-size) & OR_AM_MSK)
#TEXT_BASE = 0xFE000000
TEXT_BASE = 0xFFF00000
PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/spc1920
-HOST_CFLAGS += -I$(TOPDIR)/board/spc1920
+HOSTCFLAGS += -I$(TOPDIR)/board/spc1920
HOST_ENVIRO_CFLAGS += -I$(TOPDIR)/board/spc1920
#include <common.h>
#include <asm/io.h>
+#include <asm/arch/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
-int misc_init_r(void)
+int board_late_init(void)
{
- setenv("verify", "n");
+ /* Set the two I2C gpio lines to be gpio high */
+ nmk_gpio_set(__SCL, 1); nmk_gpio_set(__SDA, 1);
+ nmk_gpio_dir(__SCL, 1); nmk_gpio_dir(__SDA, 1);
+ nmk_gpio_af(__SCL, GPIO_GPIO); nmk_gpio_af(__SDA, GPIO_GPIO);
+
+ /* Reset the I2C port expander, on GPIO77 */
+ nmk_gpio_af(77, GPIO_GPIO);
+ nmk_gpio_dir(77, 1);
+ nmk_gpio_set(77, 0);
+ udelay(10);
+ nmk_gpio_set(77, 1);
+
return 0;
}
return 0;
}
-#if defined(CONFIG_CMD_NAND)
-
-#include <linux/mtd/nand_legacy.h>
-
-extern ulong nand_probe(ulong physadr);
-extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- unsigned long totlen;
-
- totlen = nand_probe(CONFIG_SYS_NAND_BASE);
- printf ("%4lu MB\n", totlen >> 20);
-}
-#endif
-
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o pci.o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
/*
* (C) Copyright 2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*/
#include <asm/mmu.h>
+#include <asm/io.h>
#include <common.h>
-#include <asm/global_data.h>
+#include <mpc83xx.h>
#include <pci.h>
-#include <asm/mpc8349_pci.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_PCI
-
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_tqm834x_config_table[] = {
- {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
- }
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
},
- {}
-};
-#endif
-
-static struct pci_controller pci1_hose = {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_tqm834x_config_table,
-#endif
};
-
-/**************************************************************************
+/*
* pci_init_board()
*
* NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
void
pci_init_board(void)
{
- volatile immap_t * immr;
- volatile clk83xx_t * clk;
- volatile law83xx_t * pci_law;
- volatile pot83xx_t * pci_pot;
- volatile pcictrl83xx_t * pci_ctrl;
- volatile pciconf83xx_t * pci_conf;
- u16 reg16;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ struct pci_region *reg[] = { pci1_regions };
u32 reg32;
- struct pci_controller * hose;
-
- immr = (immap_t *)CONFIG_SYS_IMMR;
- clk = (clk83xx_t *)&immr->clk;
- pci_law = immr->sysconf.pcilaw;
- pci_pot = immr->ios.pot;
- pci_ctrl = immr->pci_ctrl;
- pci_conf = immr->pci_conf;
-
- hose = &pci1_hose;
/*
* Configure PCI controller and PCI_CLK_OUTPUT
- */
-
- /*
+ *
* WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
* line actually used for clocking all external PCI devices in TQM83xx.
* Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
clk->occr = reg32;
udelay(2000);
- /*
- * Release PCI RST Output signal
- */
- pci_ctrl[0].gcr = 0;
- udelay(2000);
- pci_ctrl[0].gcr = 1;
- udelay(2000);
-
- /*
- * Configure PCI Local Access Windows
- */
+ /* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
- /*
- * Configure PCI Outbound Translation Windows
- */
-
- /* PCI1 mem space */
- pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
-
- /* PCI1 IO space */
- pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
-
- /* we need RAM mapped to PCI space for the devices to
- * access main memory */
- pci_ctrl[0].pitar1 = 0x0;
- pci_ctrl[0].pibar1 = 0x0;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_256M;
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* PCI memory space */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI1_MEM_BASE,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI1_IO_BASE,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(hose->regions + 2,
- CONFIG_PCI_SYS_MEM_BUS,
- CONFIG_PCI_SYS_MEM_PHYS,
- CONFIG_PCI_SYS_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- hose->region_count = 3;
-
- pci_setup_indirect(hose,
- (CONFIG_SYS_IMMR+0x8300),
- (CONFIG_SYS_IMMR+0x8304));
-
- pci_register_hose(hose);
-
- /*
- * Write to Command register
- */
- reg16 = 0xff;
- pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
- ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
- reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
- 0xffff);
- pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
- 0x80);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
-#endif
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
-}
-
-#if defined(CONFIG_OF_LIBFDT)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
- int nodeoffset;
- int tmp[2];
- const char *path;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
- path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(pci1_hose.first_busno);
- tmp[1] = cpu_to_be32(pci1_hose.last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
-#ifdef CONFIG_MPC83XX_PCI2
- path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(pci2_hose.first_busno);
- tmp[1] = cpu_to_be32(pci2_hose.last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
+ udelay(2000);
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
-#endif
- }
+ mpc83xx_pci_init(1, reg, 0);
}
-#endif /* CONFIG_OF_LIBFDT */
-#endif /* CONFIG_PCI */
return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
}
-void board_add_ram_info (int use_default)
-{
- int casl;
-
- if (use_default)
- casl = CONFIG_DDR_DEFAULT_CL;
- else
- casl = cas_latency ();
-
- puts (" (CL=");
- switch (casl) {
- case 20:
- puts ("2)");
- break;
-
- case 25:
- puts ("2.5)");
- break;
-
- case 30:
- puts ("3)");
- break;
- }
-}
-
phys_size_t initdram (int board_type)
{
long dram_size = 0;
/*
* Try again with default CAS latency
*/
- puts ("Problem with CAS lantency");
- board_add_ram_info (1);
- puts (", using default CL!\n");
- casl = CONFIG_DDR_DEFAULT_CL;
- dram_size = sdram_setup (casl);
+ printf ("Problem with CAS lantency, using default CL %d/10!\n",
+ CONFIG_DDR_DEFAULT_CL);
+ dram_size = sdram_setup (CONFIG_DDR_DEFAULT_CL);
puts (" ");
}
OBJS_FKT := $(addprefix $(obj),$(COBJS_FKT))
-gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
-
LOAD_ADDR = 0xc100000
#########################################################################
$(obj)trab_fkt.srec: $(OBJS_FKT) $(LIB)
$(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e trab_fkt $^ $(LIB) \
- -L$(obj)../../examples -lstubs \
+ -L$(obj)../../examples/standalone -lstubs \
-L$(obj)../../lib_generic -lgeneric \
$(obj)../../lib_arm/div0.o \
- $(obj)../../lib_arm/_*.o
+ $(PLATFORM_LIBS)
$(OBJCOPY) -O srec $(<:.o=) $@
$(obj)trab_fkt.bin: $(obj)trab_fkt.srec
#include <version.h>
#include <stdarg.h>
#include <linux/types.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <s3c2400.h>
DECLARE_GLOBAL_DATA_PTR;
$(obj)eeprom.srec: $(obj)eeprom.o $(obj)eeprom_start.o
cd $(lnk) && $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \
-o $(<:.o=) -e eeprom eeprom.o eeprom_start.o \
- -L$(obj)../../examples -lstubs \
+ -L$(obj)../../examples/standalone -lstubs \
-L$(obj)../../lib_generic -lgeneric \
-L$(gcclibdir) -lgcc
$(OBJCOPY) -O srec $(<:.o=) $@
return dram_size;
}
-
-#if defined(CONFIG_DDR_ECC) || (CONFIG_NUM_DDR_CONTROLLERS > 1)
-void board_add_ram_info(int use_default)
-{
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
-#if defined(CONFIG_MPC85xx)
- volatile ccsr_ddr_t *ddr1 = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-#elif defined(CONFIG_MPC86xx)
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
-#endif
-#endif
-
- puts(" (");
-
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
- /* Print interleaving information */
- if (ddr1->cs0_config & 0x20000000) {
- switch ((ddr1->cs0_config >> 24) & 0xf) {
- case 0:
- puts("cache line");
- break;
- case 1:
- puts("page");
- break;
- case 2:
- puts("bank");
- break;
- case 3:
- puts("super-bank");
- break;
- default:
- puts("invalid");
- break;
- }
- } else {
- puts("no");
- }
-
- puts(" interleaving");
-#endif
-
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1) && defined(CONFIG_DDR_ECC)
- puts(", ");
-#endif
-
-#if defined(CONFIG_DDR_ECC)
- puts("ECC enabled");
-#endif
-
- puts(")");
-}
-#endif /* CONFIG_DDR_ECC || CONFIG_NUM_DDR_CONTROLLERS > 1 */
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
/*
-* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
* project.
#include <config.h>
/* General */
-#define TLB_VALID 0x00000200
+#define TLB_VALID 0x00000200
/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
/* Some handy macros */
-
#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
+#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
+#define TLB1(rpn,erpn) (((rpn)&0xfffffc00) | (erpn))
+#define TLB2(a) ((a)&0x00000fbf)
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
+#define tlbtab_start \
+ mflr r1; \
+ bl 0f;
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
+#define tlbtab_end \
+ .long 0, 0, 0; \
+0: mflr r0; \
+ mtlr r1; \
+ blr;
#define tlbentry(epn,sz,rpn,erpn,attr)\
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-/**************************************************************************
+/*
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
+ * Pointer to the table is returned in r1
+ */
.section .bootpg,"ax"
.globl tlbtab
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- board/xpedite1k/init.o (.text)
+ board/xes/xpedite1000/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
-/* . = env_offset;*/
-/* common/env_embedded.o(.text)*/
-
*(.text)
*(.fixup)
*(.got1)
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- board/xpedite1k/init.o (.text)
+ board/xes/xpedite1000/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
--- /dev/null
+/*
+ * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ unsigned long sdrreg;
+
+ /*
+ * Enable GPIO for pins 18 - 24
+ * 18 = SEEPROM_WP
+ * 19 = #M_RST
+ * 20 = #MONARCH
+ * 21 = #LED_ALARM
+ * 22 = #LED_ACT
+ * 23 = #LED_STATUS1
+ * 24 = #LED_STATUS2
+ */
+ mfsdr(sdr_pfc0, sdrreg);
+ mtsdr(sdr_pfc0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00);
+ out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
+ LED0_OFF();
+ LED1_OFF();
+ LED2_OFF();
+ LED3_OFF();
+
+ /* Setup the external bus controller/chip selects */
+ mtebc(pb0ap, 0x04055200); /* 16MB Strata FLASH */
+ mtebc(pb0cr, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */
+ mtebc(pb1ap, 0x04055200); /* 512KB Socketed AMD FLASH */
+ mtebc(pb1cr, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */
+ mtebc(pb6ap, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */
+ mtebc(pb6cr, 0xf00da000); /* BAS=0xf00 64MB R/W i6-bit */
+ mtebc(pb7ap, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */
+ mtebc(pb7cr, 0xf40da000); /* BAS=0xf40 64MB R/W 16-bit */
+
+ /*
+ * Setup the interrupt controller polarities, triggers, etc.
+ *
+ * Because of the interrupt handling rework to handle 440GX interrupts
+ * with the common code, we needed to change names of the UIC registers.
+ * Here the new relationship:
+ *
+ * U-Boot name 440GX name
+ * -----------------------
+ * UIC0 UICB0
+ * UIC1 UIC0
+ * UIC2 UIC1
+ * UIC3 UIC2
+ */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */
+ mtdcr(uic1pr, 0xfffffe00); /* per ref-board manual */
+ mtdcr(uic1tr, 0x01c00000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+ mtdcr(uic2er, 0x00000000); /* disable all */
+ mtdcr(uic2cr, 0x00000000); /* all non-critical */
+ mtdcr(uic2pr, 0xffffc0ff); /* per ref-board manual */
+ mtdcr(uic2tr, 0x00ff8000); /* per ref-board manual */
+ mtdcr(uic2vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic3sr, 0xffffffff); /* clear all */
+ mtdcr(uic3er, 0x00000000); /* disable all */
+ mtdcr(uic3cr, 0x00000000); /* all non-critical */
+ mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic3tr, 0x00ff8c0f); /* per ref-board manual */
+ mtdcr(uic3vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic3sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic0sr, 0xfc000000); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000000); /* all non-critical */
+ mtdcr(uic0pr, 0xfc000000); /* */
+ mtdcr(uic0tr, 0x00000000); /* */
+ mtdcr(uic0vr, 0x00000001); /* */
+
+ LED0_ON();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char *s;
+
+ printf("Board: X-ES %s PMC SBC\n", CONFIG_SYS_BOARD_NAME);
+ printf(" ");
+ s = getenv("board_rev");
+ if (s)
+ printf("Rev %s, ", s);
+ s = getenv("serial#");
+ if (s)
+ printf("Serial# %s, ", s);
+ s = getenv("board_cfg");
+ if (s)
+ printf("Cfg %s", s);
+ printf("\n");
+
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ return spd_sdram();
+}
+
+/*
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ */
+
+#if defined(CONFIG_PCI)
+int pci_pre_init(struct pci_controller * hose)
+{
+ unsigned long strap;
+
+ /* See if we're supposed to setup the pci */
+ mfsdr(sdr_sdstp1, strap);
+ if ((strap & 0x00010000) == 0)
+ return 0;
+
+#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
+ /* Setup System Device Register PCIX0_XCR */
+ mfsdr(sdr_xcr, strap);
+ strap &= 0x0f000000;
+ mtsdr(sdr_xcr, strap);
+#endif
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
+/*
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
+void pci_target_init(struct pci_controller * hose)
+{
+ /* Disable everything */
+ out32r(PCIX0_PIM0SA, 0);
+ out32r(PCIX0_PIM1SA, 0);
+ out32r(PCIX0_PIM2SA, 0);
+ out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
+
+ /*
+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+ * options to not support sizes such as 128/256 MB.
+ */
+ out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+ out32r(PCIX0_PIM0LAH, 0);
+ out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+
+ out32r(PCIX0_BAR0, 0);
+
+ /* Program the board's subsystem id/vendor id */
+ out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+ out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+
+ out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+}
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
+
+#if defined(CONFIG_PCI)
+/*
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+int is_pci_host(struct pci_controller *hose)
+{
+ return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0);
+}
+#endif /* defined(CONFIG_PCI) */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ return ctrlc();
+}
+
+void post_word_store(ulong a)
+{
+ volatile ulong *save_addr =
+ (volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);
+
+ *save_addr = a;
+}
+
+ulong post_word_load(void)
+{
+ volatile ulong *save_addr =
+ (volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);
+
+ return *save_addr;
+}
+#endif
/* Initialize PCA9557 devices */
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
/*
* Remap NOR flash region to caching-inhibited
INCS := -I../common -I../xilinx_enet -I../xilinx_iic
CFLAGS += $(INCS)
-HOST_CFLAGS += $(INCS)
+HOSTCFLAGS += $(INCS)
LIB = $(obj)lib$(BOARD).a
INCS :=
CFLAGS += $(INCS)
-HOST_CFLAGS += $(INCS)
+HOSTCFLAGS += $(INCS)
LIB = $(obj)lib$(BOARD).a
INCS :=
CFLAGS += $(INCS)
-HOST_CFLAGS += $(INCS)
+HOSTCFLAGS += $(INCS)
LIB = $(obj)lib$(BOARD).a
+++ /dev/null
-/*
- * (C) Copyright 2002-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
- * Add support for Am29F016D and dynamic switch setting.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-/*
- * Ported to XPedite1000, 1/2 mb boot flash only
- * Travis B. Sawyer, <travis.sawyer@sandburst.com>
- */
-
-#include <common.h>
-#include <ppc4xx.h>
-#include <asm/processor.h>
-
-
-#undef DEBUG
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif /* DEBUG */
-
-#define BOOT_SMALL_FLASH 32 /* 00100000 */
-#define FLASH_ONBD_N 2 /* 00000010 */
-#define FLASH_SRAM_SEL 1 /* 00000001 */
-
-#define BOOT_SMALL_FLASH_VAL 4
-#define FLASH_ONBD_N_VAL 2
-#define FLASH_SRAM_SEL_VAL 1
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
- {0xfff80000}, /* 0:000: configuraton 3 */
- {0xfff90000}, /* 1:001: configuraton 4 */
- {0xfffa0000}, /* 2:010: configuraton 7 */
- {0xfffb0000}, /* 3:011: configuraton 8 */
- {0xfffc0000}, /* 4:100: configuraton 1 */
- {0xfffd0000}, /* 5:101: configuraton 2 */
- {0xfffe0000}, /* 6:110: configuraton 5 */
- {0xffff0000} /* 7:111: configuraton 6 */
-};
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-
-#ifdef CONFIG_XPEDITE1K
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long total_b = 0;
- unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
- unsigned short index = 0;
- int i;
-
-
- DEBUGF("\n");
- DEBUGF("FLASH: Index: %d\n", index);
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
-
- /* check whether the address is 0 */
- if (flash_addr_table[index][i] == 0) {
- continue;
- }
-
- /* call flash_get_size() to initialize sector address */
- size_b[i] = flash_get_size(
- (vu_long *)flash_addr_table[index][i], &flash_info[i]);
- flash_info[i].size = size_b[i];
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
- i, size_b[i], size_b[i]<<20);
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
- }
-
- total_b += flash_info[i].size;
- }
-
- return total_b;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMD016: printf ("AM29F016D (16 Mbit, uniform sector size)\n");
- break;
- case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
- break;
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
- break;
- case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count-1))
- size = info->start[i+1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++)
- {
- if (*flash++ != 0xffffffff)
- {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " "
- );
- }
- printf ("\n");
- return;
- }
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- FLASH_WORD_SIZE value;
- ulong base = (ulong)addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
-
- DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr );
-
- /* Write auto select command: read Manufacturer ID */
- udelay(10000);
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- udelay(1000);
- addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- udelay(1000);
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
- udelay(1000);
-
-#ifdef CONFIG_ADCIOP
- value = addr2[2];
-#else
- value = addr2[0];
-#endif
-
- DEBUGF("FLASH MANUFACT: %x\n", value);
-
- switch (value) {
- case (FLASH_WORD_SIZE)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FLASH_WORD_SIZE)FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (FLASH_WORD_SIZE)SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- case (FLASH_WORD_SIZE)STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
-#ifdef CONFIG_ADCIOP
- value = addr2[0]; /* device ID */
- debug ("\ndev_code=%x\n", value);
-#else
- value = addr2[1]; /* device ID */
-#endif
-
- DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
- switch (value) {
- case (FLASH_WORD_SIZE)AMD_ID_LV040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000; /* => 512 kb */
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- (info->flash_id == FLASH_AM040) ||
- (info->flash_id == FLASH_AMD016)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
-#ifdef CONFIG_ADCIOP
- addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- info->protect[i] = addr2[4] & 1;
-#else
- addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
-#endif
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
-#if 0 /* test-only */
-#ifdef CONFIG_ADCIOP
- addr2 = (volatile unsigned char *)info->start[0];
- addr2[ADDR0] = 0xAA;
- addr2[ADDR1] = 0x55;
- addr2[ADDR0] = 0xF0; /* reset bank */
-#else
- addr2 = (FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-#endif
-#else /* test-only */
- addr2 = (FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-#endif /* test-only */
- }
-
- return (info->size);
-}
-
-int wait_for_DQ7(flash_info_t *info, int sect)
-{
- ulong start, now, last;
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
-
- start = get_timer (0);
- last = start;
- while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
- volatile FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
- int i;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
- printf("Erasing sector %p\n", addr2);
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
- for (i=0; i<50; i++)
- udelay(1000); /* wait 1 ms */
- } else {
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
- }
- l_sect = sect;
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7(info, sect);
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
-#if 0
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
- wait_for_DQ7(info, l_sect);
-
-DONE:
-#endif
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
- volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
- ulong start;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((volatile FLASH_WORD_SIZE *) dest) &
- (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
-
- for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
- int flag;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
- * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <asm/processor.h>
-#include <spd_sdram.h>
-#include <i2c.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define BOOT_SMALL_FLASH 32 /* 00100000 */
-#define FLASH_ONBD_N 2 /* 00000010 */
-#define FLASH_SRAM_SEL 1 /* 00000001 */
-
-long int fixed_sdram (void);
-
-int board_early_init_f(void)
-{
- unsigned long sdrreg;
- /* TBS: Setup the GPIO access for the user LEDs */
- mfsdr(sdr_pfc0, sdrreg);
- mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00);
- out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
- LED0_OFF();
- LED1_OFF();
- LED2_OFF();
- LED3_OFF();
-
- /*--------------------------------------------------------------------
- * Setup the external bus controller/chip selects
- *-------------------------------------------------------------------*/
-
- /* set the bus controller */
- mtebc (pb0ap, 0x04055200); /* FLASH/SRAM */
- mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
- mtebc (pb1ap, 0x04055200); /* FLASH/SRAM */
- mtebc (pb1cr, 0xfe098000); /* BAS=0xff8 16MB R/W 8-bit */
-
- /*--------------------------------------------------------------------
- * Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
- /*
- * Because of the interrupt handling rework to handle 440GX interrupts
- * with the common code, we needed to change names of the UIC registers.
- * Here the new relationship:
- *
- * U-Boot name 440GX name
- * -----------------------
- * UIC0 UICB0
- * UIC1 UIC0
- * UIC2 UIC1
- * UIC3 UIC2
- */
- mtdcr (uic1sr, 0xffffffff); /* clear all */
- mtdcr (uic1er, 0x00000000); /* disable all */
- mtdcr (uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */
- mtdcr (uic1pr, 0xfffffe00); /* per ref-board manual */
- mtdcr (uic1tr, 0x01c00000); /* per ref-board manual */
- mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic1sr, 0xffffffff); /* clear all */
-
- mtdcr (uic2sr, 0xffffffff); /* clear all */
- mtdcr (uic2er, 0x00000000); /* disable all */
- mtdcr (uic2cr, 0x00000000); /* all non-critical */
- mtdcr (uic2pr, 0xffffc0ff); /* per ref-board manual */
- mtdcr (uic2tr, 0x00ff8000); /* per ref-board manual */
- mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic2sr, 0xffffffff); /* clear all */
-
- mtdcr (uic3sr, 0xffffffff); /* clear all */
- mtdcr (uic3er, 0x00000000); /* disable all */
- mtdcr (uic3cr, 0x00000000); /* all non-critical */
- mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
- mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
- mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic3sr, 0xffffffff); /* clear all */
-
- mtdcr (uic0sr, 0xfc000000); /* clear all */
- mtdcr (uic0er, 0x00000000); /* disable all */
- mtdcr (uic0cr, 0x00000000); /* all non-critical */
- mtdcr (uic0pr, 0xfc000000); /* */
- mtdcr (uic0tr, 0x00000000); /* */
- mtdcr (uic0vr, 0x00000001); /* */
-
- LED0_ON();
-
-
- return 0;
-}
-
-int checkboard (void)
-{
- printf ("Board: XES XPedite1000 440GX\n");
-
- return (0);
-}
-
-
-phys_size_t initdram (int board_type)
-{
- long dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram ();
-#else
- dram_size = fixed_sdram ();
-#endif
- return dram_size;
-}
-
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) 0x00000000;
- uint *pend = (uint *) 0x08000000;
- uint *p;
-
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
- return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- *
- * Assumes: 128 MB, non-ECC, non-registered
- * PLB @ 133 MHz
- *
- ************************************************************************/
-long int fixed_sdram (void)
-{
- uint reg;
-
- /*--------------------------------------------------------------------
- * Setup some default
- *------------------------------------------------------------------*/
- mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
- mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
- mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
-
- /*--------------------------------------------------------------------
- * Setup for board-specific specific mem
- *------------------------------------------------------------------*/
- /*
- * Following for CAS Latency = 2.5 @ 133 MHz PLB
- */
- mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
- mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
- /* RA=10 RD=3 */
- mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
- mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
- mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
- udelay (400); /* Delay 200 usecs (min) */
-
- /*--------------------------------------------------------------------
- * Enable the controller, then wait for DCEN to complete
- *------------------------------------------------------------------*/
- mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
- for (;;) {
- mfsdram (mem_mcsts, reg);
- if (reg & 0x80000000)
- break;
- }
-
- return (128 * 1024 * 1024); /* 128 MB */
-}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller * hose )
-{
- unsigned long strap;
- /* See if we're supposed to setup the pci */
- mfsdr(sdr_sdstp1, strap);
- if ((strap & 0x00010000) == 0) {
- return (0);
- }
-
-#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
- /* Setup System Device Register PCIX0_XCR */
- mfsdr(sdr_xcr, strap);
- strap &= 0x0f000000;
- mtsdr(sdr_xcr, strap);
-#endif
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0SA, 0 ); /* disable */
- out32r( PCIX0_PIM1SA, 0 ); /* disable */
- out32r( PCIX0_PIM2SA, 0 ); /* disable */
- out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIX0_PIM0LAH, 0 );
- out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
- out32r( PCIX0_BAR0, 0 );
-
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-
-/*************************************************************************
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0);
-}
-#endif /* defined(CONFIG_PCI) */
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
-
- return (ctrlc());
-}
-
-void post_word_store (ulong a)
-{
- volatile ulong *save_addr =
- (volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);
-
- *save_addr = a;
-}
-
-ulong post_word_load (void)
-{
- volatile ulong *save_addr =
- (volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);
-
- return *save_addr;
-}
-#endif
-
-/*-----------------------------------------------------------------------------
- * board_get_enetaddr -- Read the MAC Addresses in the I2C EEPROM
- *-----------------------------------------------------------------------------
- */
-static int read_i2c;
-static void board_get_enetaddr(uchar *enet)
-{
- int i;
- unsigned char buff[0x100], *cp;
-
- if (read_i2c)
- return;
-
- /* Initialize I2C */
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- /* Read 256 bytes in EEPROM */
- i2c_read (0x50, 0, 1, buff, 0x100);
-
- cp = &buff[0xF4];
- for (i = 0; i < 6; i++,cp++)
- enet[i] = *cp;
-
- printf("MAC address = %pM\n", enet);
- read_i2c = 1;
-}
-
-int misc_init_r(void)
-{
- uchar enetaddr[6], i2c_enetaddr[6];
-
- if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
- board_get_enetaddr(i2c_enetaddr);
- eth_setenv_enetaddr("ethaddr", i2c_enetaddr);
- }
-
-#ifdef CONFIG_HAS_ETH1
- if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
- board_get_enetaddr(i2c_enetaddr);
- eth_setenv_enetaddr("eth1addr", i2c_enetaddr);
- }
-#endif
-
-#ifdef CONFIG_HAS_ETH2
- if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
- board_get_enetaddr(i2c_enetaddr);
- eth_setenv_enetaddr("eth2addr", i2c_enetaddr);
- }
-#endif
-
-#ifdef CONFIG_HAS_ETH3
- if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
- board_get_enetaddr(i2c_enetaddr);
- eth_setenv_enetaddr("eth3addr", i2c_enetaddr);
- }
-#endif
-
- return 0;
-}
#include <common.h>
#if defined(CONFIG_CMD_NAND)
-#ifdef CONFIG_NEW_NAND_CODE
#include <nand.h>
#include <asm/arch/pxa-regs.h>
return 0;
}
-#else
- #error "U-Boot legacy NAND support not available for Monahans DFC."
-#endif
#endif
COBJS-y += circbuf.o
COBJS-y += console.o
COBJS-y += command.o
-COBJS-y += devices.o
COBJS-y += dlmalloc.o
COBJS-y += exports.o
COBJS-$(CONFIG_SYS_HUSH_PARSER) += hush.o
COBJS-y += memsize.o
COBJS-y += s_record.o
COBJS-$(CONFIG_SERIAL_MULTI) += serial.o
+COBJS-y += stdio.o
COBJS-y += xyzModem.o
# core command
COBJS-$(CONFIG_CMD_DIAG) += cmd_diag.o
endif
COBJS-$(CONFIG_CMD_DISPLAY) += cmd_display.o
-COBJS-$(CONFIG_CMD_DOC) += cmd_doc.o
COBJS-$(CONFIG_CMD_DTT) += cmd_dtt.o
COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += cmd_eeprom.o
COBJS-$(CONFIG_CMD_EEPROM) += cmd_eeprom.o
COBJS-$(CONFIG_CMD_SPIBOOTLDR) += cmd_spibootldr.o
COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o
COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o
+COBJS-$(CONFIG_CMD_TSI148) += cmd_tsi148.o
COBJS-$(CONFIG_CMD_UBI) += cmd_ubi.o
COBJS-$(CONFIG_CMD_UBIFS) += cmd_ubifs.o
COBJS-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o
# others
COBJS-$(CONFIG_DDR_SPD) += ddr_spd.o
-COBJS-$(CONFIG_CMD_DOC) += docecc.o
+COBJS-$(CONFIG_HWCONFIG) += hwconfig.o
COBJS-$(CONFIG_CONSOLE_MUX) += iomux.o
COBJS-y += flash.o
COBJS-$(CONFIG_CMD_KGDB) += kgdb.o
*/
#include <common.h>
+#include <lcd.h>
#include <bmp_layout.h>
#include <command.h>
#include <asm/byteorder.h>
* didn't contain a valid BMP signature.
*/
#ifdef CONFIG_VIDEO_BMP_GZIP
-static bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp)
+bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp)
{
void *dst;
unsigned long len;
return bmp;
}
#else
-static bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp)
+bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp)
{
return NULL;
}
/*
- * (C) Copyright 2000-2006
+ * (C) Copyright 2000-2009
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#endif
#ifdef CONFIG_LZMA
-#define _7ZIP_BYTE_DEFINED /* Byte already defined by zlib */
#include <lzma/LzmaTypes.h>
-#include <lzma/LzmaDecode.h>
+#include <lzma/LzmaDec.h>
#include <lzma/LzmaTools.h>
#endif /* CONFIG_LZMA */
int ret = lzmaBuffToBuffDecompress(
(unsigned char *)load, &unc_len,
(unsigned char *)image_start, image_len);
- if (ret != LZMA_RESULT_OK) {
+ if (ret != SZ_OK) {
printf ("LZMA: uncompress or overwrite error %d "
"- must RESET board to recover\n", ret);
show_boot_progress (-6);
return 0;
}
+static int bootm_start_standalone(ulong iflag, int argc, char *argv[])
+{
+ char *s;
+ int (*appl)(int, char *[]);
+
+ /* Don't start if "autostart" is set to "no" */
+ if (((s = getenv("autostart")) != NULL) && (strcmp(s, "no") == 0)) {
+ char buf[32];
+ sprintf(buf, "%lX", images.os.image_len);
+ setenv("filesize", buf);
+ return 0;
+ }
+ appl = (int (*)(int, char *[]))ntohl(images.ep);
+ (*appl)(argc-1, &argv[1]);
+
+ return 0;
+}
+
/* we overload the cmd field with our state machine info instead of a
* function pointer */
cmd_tbl_t cmd_bootm_sub[] = {
if (!relocated) {
int i;
for (i = 0; i < ARRAY_SIZE(boot_os); i++)
- boot_os[i] += gd->reloc_off;
+ if (boot_os[i] != NULL)
+ boot_os[i] += gd->reloc_off;
relocated = 1;
}
lmb_reserve(&images.lmb, images.os.load, (load_end - images.os.load));
+ if (images.os.type == IH_TYPE_STANDALONE) {
+ if (iflag)
+ enable_interrupts();
+ /* This may return when 'autostart' is 'no' */
+ bootm_start_standalone(iflag, argc, argv);
+ return 0;
+ }
+
show_boot_progress (8);
#ifdef CONFIG_SILENT_CONSOLE
#endif
boot_fn = boot_os[images.os.os];
+
+ if (boot_fn == NULL) {
+ if (iflag)
+ enable_interrupts();
+ printf ("ERROR: booting os '%s' (%d) is not supported\n",
+ genimg_get_os_name(images.os.os), images.os.os);
+ show_boot_progress (-8);
+ return 1;
+ }
+
boot_fn(0, argc, argv, &images);
show_boot_progress (-9);
case IH_TYPE_MULTI:
image_multi_getimg (hdr, 0, os_data, os_len);
break;
+ case IH_TYPE_STANDALONE:
+ if (argc >2) {
+ hdr->ih_load = htonl(simple_strtoul(argv[2], NULL, 16));
+ }
+ *os_data = image_get_data (hdr);
+ *os_len = image_get_data_size (hdr);
+ break;
default:
printf ("Wrong Image Type for %s command\n", cmdtp->name);
show_boot_progress (-5);
*/
#include <common.h>
#include <command.h>
-#include <devices.h>
+#include <stdio_dev.h>
extern void _do_coninfo (void);
int do_coninfo (cmd_tbl_t * cmd, int flag, int argc, char *argv[])
{
int l;
- struct list_head *list = device_get_list();
+ struct list_head *list = stdio_get_list();
struct list_head *pos;
- device_t *dev;
+ struct stdio_dev *dev;
/* Scan for valid output and input devices */
puts ("List of available devices:\n");
list_for_each(pos, list) {
- dev = list_entry(pos, device_t, list);
+ dev = list_entry(pos, struct stdio_dev, list);
printf ("%-8s %08x %c%c%c ",
dev->name,
+++ /dev/null
-/*
- * Driver for Disk-On-Chip 2000 and Millennium
- * (c) 1999 Machine Vision Holdings, Inc.
- * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org>
- *
- * $Id: doc2000.c,v 1.46 2001/10/02 15:05:13 dwmw2 Exp $
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <linux/mtd/nftl.h>
-#include <linux/mtd/doc2000.h>
-
-#error This code is broken and will be removed outright in the next release.
-#error If you need diskonchip support, please update the Linux driver in
-#error drivers/mtd/nand/diskonchip.c to work with u-boot.
-
-/*
- * ! BROKEN !
- *
- * TODO: must be implemented and tested by someone with HW
- */
-#if 0
-#ifdef CONFIG_SYS_DOC_SUPPORT_2000
-#define DoC_is_2000(doc) (doc->ChipID == DOC_ChipID_Doc2k)
-#else
-#define DoC_is_2000(doc) (0)
-#endif
-
-#ifdef CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-#define DoC_is_Millennium(doc) (doc->ChipID == DOC_ChipID_DocMil)
-#else
-#define DoC_is_Millennium(doc) (0)
-#endif
-
-/* CONFIG_SYS_DOC_PASSIVE_PROBE:
- In order to ensure that the BIOS checksum is correct at boot time, and
- hence that the onboard BIOS extension gets executed, the DiskOnChip
- goes into reset mode when it is read sequentially: all registers
- return 0xff until the chip is woken up again by writing to the
- DOCControl register.
-
- Unfortunately, this means that the probe for the DiskOnChip is unsafe,
- because one of the first things it does is write to where it thinks
- the DOCControl register should be - which may well be shared memory
- for another device. I've had machines which lock up when this is
- attempted. Hence the possibility to do a passive probe, which will fail
- to detect a chip in reset mode, but is at least guaranteed not to lock
- the machine.
-
- If you have this problem, uncomment the following line:
-#define CONFIG_SYS_DOC_PASSIVE_PROBE
-*/
-
-#undef DOC_DEBUG
-#undef ECC_DEBUG
-#undef PSYCHO_DEBUG
-#undef NFTL_DEBUG
-
-static struct DiskOnChip doc_dev_desc[CONFIG_SYS_MAX_DOC_DEVICE];
-
-/* Current DOC Device */
-static int curr_device = -1;
-
-/* Supported NAND flash devices */
-static struct nand_flash_dev nand_flash_ids[] = {
- {"Toshiba TC5816BDC", NAND_MFR_TOSHIBA, 0x64, 21, 1, 2, 0x1000, 0},
- {"Toshiba TC5832DC", NAND_MFR_TOSHIBA, 0x6b, 22, 0, 2, 0x2000, 0},
- {"Toshiba TH58V128DC", NAND_MFR_TOSHIBA, 0x73, 24, 0, 2, 0x4000, 0},
- {"Toshiba TC58256FT/DC", NAND_MFR_TOSHIBA, 0x75, 25, 0, 2, 0x4000, 0},
- {"Toshiba TH58512FT", NAND_MFR_TOSHIBA, 0x76, 26, 0, 3, 0x4000, 0},
- {"Toshiba TC58V32DC", NAND_MFR_TOSHIBA, 0xe5, 22, 0, 2, 0x2000, 0},
- {"Toshiba TC58V64AFT/DC", NAND_MFR_TOSHIBA, 0xe6, 23, 0, 2, 0x2000, 0},
- {"Toshiba TC58V16BDC", NAND_MFR_TOSHIBA, 0xea, 21, 1, 2, 0x1000, 0},
- {"Toshiba TH58100FT", NAND_MFR_TOSHIBA, 0x79, 27, 0, 3, 0x4000, 0},
- {"Samsung KM29N16000", NAND_MFR_SAMSUNG, 0x64, 21, 1, 2, 0x1000, 0},
- {"Samsung unknown 4Mb", NAND_MFR_SAMSUNG, 0x6b, 22, 0, 2, 0x2000, 0},
- {"Samsung KM29U128T", NAND_MFR_SAMSUNG, 0x73, 24, 0, 2, 0x4000, 0},
- {"Samsung KM29U256T", NAND_MFR_SAMSUNG, 0x75, 25, 0, 2, 0x4000, 0},
- {"Samsung unknown 64Mb", NAND_MFR_SAMSUNG, 0x76, 26, 0, 3, 0x4000, 0},
- {"Samsung KM29W32000", NAND_MFR_SAMSUNG, 0xe3, 22, 0, 2, 0x2000, 0},
- {"Samsung unknown 4Mb", NAND_MFR_SAMSUNG, 0xe5, 22, 0, 2, 0x2000, 0},
- {"Samsung KM29U64000", NAND_MFR_SAMSUNG, 0xe6, 23, 0, 2, 0x2000, 0},
- {"Samsung KM29W16000", NAND_MFR_SAMSUNG, 0xea, 21, 1, 2, 0x1000, 0},
- {"Samsung K9F5616Q0C", NAND_MFR_SAMSUNG, 0x45, 25, 0, 2, 0x4000, 1},
- {"Samsung K9K1216Q0C", NAND_MFR_SAMSUNG, 0x46, 26, 0, 3, 0x4000, 1},
- {"Samsung K9F1G08U0M", NAND_MFR_SAMSUNG, 0xf1, 27, 0, 2, 0, 0},
- {NULL,}
-};
-
-/* ------------------------------------------------------------------------- */
-
-int do_doc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- int rcode = 0;
-
- switch (argc) {
- case 0:
- case 1:
- cmd_usage(cmdtp);
- return 1;
- case 2:
- if (strcmp(argv[1],"info") == 0) {
- int i;
-
- putc ('\n');
-
- for (i=0; i<CONFIG_SYS_MAX_DOC_DEVICE; ++i) {
- if(doc_dev_desc[i].ChipID == DOC_ChipID_UNKNOWN)
- continue; /* list only known devices */
- printf ("Device %d: ", i);
- doc_print(&doc_dev_desc[i]);
- }
- return 0;
-
- } else if (strcmp(argv[1],"device") == 0) {
- if ((curr_device < 0) || (curr_device >= CONFIG_SYS_MAX_DOC_DEVICE)) {
- puts ("\nno devices available\n");
- return 1;
- }
- printf ("\nDevice %d: ", curr_device);
- doc_print(&doc_dev_desc[curr_device]);
- return 0;
- }
- cmd_usage(cmdtp);
- return 1;
- case 3:
- if (strcmp(argv[1],"device") == 0) {
- int dev = (int)simple_strtoul(argv[2], NULL, 10);
-
- printf ("\nDevice %d: ", dev);
- if (dev >= CONFIG_SYS_MAX_DOC_DEVICE) {
- puts ("unknown device\n");
- return 1;
- }
- doc_print(&doc_dev_desc[dev]);
- /*doc_print (dev);*/
-
- if (doc_dev_desc[dev].ChipID == DOC_ChipID_UNKNOWN) {
- return 1;
- }
-
- curr_device = dev;
-
- puts ("... is now current device\n");
-
- return 0;
- }
-
- cmd_usage(cmdtp);
- return 1;
- default:
- /* at least 4 args */
-
- if (strcmp(argv[1],"read") == 0 || strcmp(argv[1],"write") == 0) {
- ulong addr = simple_strtoul(argv[2], NULL, 16);
- ulong off = simple_strtoul(argv[3], NULL, 16);
- ulong size = simple_strtoul(argv[4], NULL, 16);
- int cmd = (strcmp(argv[1],"read") == 0);
- int ret, total;
-
- printf ("\nDOC %s: device %d offset %ld, size %ld ... ",
- cmd ? "read" : "write", curr_device, off, size);
-
- ret = doc_rw(doc_dev_desc + curr_device, cmd, off, size,
- (size_t *)&total, (u_char*)addr);
-
- printf ("%d bytes %s: %s\n", total, cmd ? "read" : "write",
- ret ? "ERROR" : "OK");
-
- return ret;
- } else if (strcmp(argv[1],"erase") == 0) {
- ulong off = simple_strtoul(argv[2], NULL, 16);
- ulong size = simple_strtoul(argv[3], NULL, 16);
- int ret;
-
- printf ("\nDOC erase: device %d offset %ld, size %ld ... ",
- curr_device, off, size);
-
- ret = doc_erase (doc_dev_desc + curr_device, off, size);
-
- printf("%s\n", ret ? "ERROR" : "OK");
-
- return ret;
- } else {
- cmd_usage(cmdtp);
- rcode = 1;
- }
-
- return rcode;
- }
-}
-U_BOOT_CMD(
- doc, 5, 1, do_doc,
- "Disk-On-Chip sub-system",
- "info - show available DOC devices\n"
- "doc device [dev] - show or set current device\n"
- "doc read addr off size\n"
- "doc write addr off size - read/write `size'"
- " bytes starting at offset `off'\n"
- " to/from memory address `addr'\n"
- "doc erase off size - erase `size' bytes of DOC from offset `off'"
-);
-
-int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- char *boot_device = NULL;
- char *ep;
- int dev;
- ulong cnt;
- ulong addr;
- ulong offset = 0;
- image_header_t *hdr;
- int rcode = 0;
-#if defined(CONFIG_FIT)
- const void *fit_hdr = NULL;
-#endif
-
- show_boot_progress (34);
- switch (argc) {
- case 1:
- addr = CONFIG_SYS_LOAD_ADDR;
- boot_device = getenv ("bootdevice");
- break;
- case 2:
- addr = simple_strtoul(argv[1], NULL, 16);
- boot_device = getenv ("bootdevice");
- break;
- case 3:
- addr = simple_strtoul(argv[1], NULL, 16);
- boot_device = argv[2];
- break;
- case 4:
- addr = simple_strtoul(argv[1], NULL, 16);
- boot_device = argv[2];
- offset = simple_strtoul(argv[3], NULL, 16);
- break;
- default:
- cmd_usage(cmdtp);
- show_boot_progress (-35);
- return 1;
- }
-
- show_boot_progress (35);
- if (!boot_device) {
- puts ("\n** No boot device **\n");
- show_boot_progress (-36);
- return 1;
- }
- show_boot_progress (36);
-
- dev = simple_strtoul(boot_device, &ep, 16);
-
- if ((dev >= CONFIG_SYS_MAX_DOC_DEVICE) ||
- (doc_dev_desc[dev].ChipID == DOC_ChipID_UNKNOWN)) {
- printf ("\n** Device %d not available\n", dev);
- show_boot_progress (-37);
- return 1;
- }
- show_boot_progress (37);
-
- printf ("\nLoading from device %d: %s at 0x%lX (offset 0x%lX)\n",
- dev, doc_dev_desc[dev].name, doc_dev_desc[dev].physadr,
- offset);
-
- if (doc_rw (doc_dev_desc + dev, 1, offset,
- SECTORSIZE, NULL, (u_char *)addr)) {
- printf ("** Read error on %d\n", dev);
- show_boot_progress (-38);
- return 1;
- }
- show_boot_progress (38);
-
- switch (genimg_get_format ((void *)addr)) {
- case IMAGE_FORMAT_LEGACY:
- hdr = (image_header_t *)addr;
-
- image_print_contents (hdr);
-
- cnt = image_get_image_size (hdr);
- break;
-#if defined(CONFIG_FIT)
- case IMAGE_FORMAT_FIT:
- fit_hdr = (const void *)addr;
- puts ("Fit image detected...\n");
-
- cnt = fit_get_size (fit_hdr);
- break;
-#endif
- default:
- show_boot_progress (-39);
- puts ("** Unknown image type\n");
- return 1;
- }
- show_boot_progress (39);
-
- cnt -= SECTORSIZE;
- if (doc_rw (doc_dev_desc + dev, 1, offset + SECTORSIZE, cnt,
- NULL, (u_char *)(addr+SECTORSIZE))) {
- printf ("** Read error on %d\n", dev);
- show_boot_progress (-40);
- return 1;
- }
- show_boot_progress (40);
-
-#if defined(CONFIG_FIT)
- /* This cannot be done earlier, we need complete FIT image in RAM first */
- if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) {
- if (!fit_check_format (fit_hdr)) {
- show_boot_progress (-130);
- puts ("** Bad FIT image format\n");
- return 1;
- }
- show_boot_progress (131);
- fit_print_contents (fit_hdr);
- }
-#endif
-
- /* Loading ok, update default load address */
-
- load_addr = addr;
-
- /* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
- char *local_args[2];
- extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
-
- local_args[0] = argv[0];
- local_args[1] = NULL;
-
- printf ("Automatic boot of image at addr 0x%08lX ...\n", addr);
-
- do_bootm (cmdtp, 0, 1, local_args);
- rcode = 1;
- }
- return rcode;
-}
-
-U_BOOT_CMD(
- docboot, 4, 1, do_docboot,
- "boot from DOC device",
- "loadAddr dev"
-);
-
-int doc_rw (struct DiskOnChip* this, int cmd,
- loff_t from, size_t len,
- size_t * retlen, u_char * buf)
-{
- int noecc, ret = 0, n, total = 0;
- char eccbuf[6];
-
- while(len) {
- /* The ECC will not be calculated correctly if
- less than 512 is written or read */
- noecc = (from != (from | 0x1ff) + 1) || (len < 0x200);
-
- if (cmd)
- ret = doc_read_ecc(this, from, len,
- (size_t *)&n, (u_char*)buf,
- noecc ? (uchar *)NULL : (uchar *)eccbuf);
- else
- ret = doc_write_ecc(this, from, len,
- (size_t *)&n, (u_char*)buf,
- noecc ? (uchar *)NULL : (uchar *)eccbuf);
-
- if (ret)
- break;
-
- from += n;
- buf += n;
- total += n;
- len -= n;
- }
-
- if (retlen)
- *retlen = total;
-
- return ret;
-}
-
-void doc_print(struct DiskOnChip *this) {
- printf("%s at 0x%lX,\n"
- "\t %d chip%s %s, size %d MB, \n"
- "\t total size %ld MB, sector size %ld kB\n",
- this->name, this->physadr, this->numchips,
- this->numchips>1 ? "s" : "", this->chips_name,
- 1 << (this->chipshift - 20),
- this->totlen >> 20, this->erasesize >> 10);
-
- if (this->nftl_found) {
- struct NFTLrecord *nftl = &this->nftl;
- unsigned long bin_size, flash_size;
-
- bin_size = nftl->nb_boot_blocks * this->erasesize;
- flash_size = (nftl->nb_blocks - nftl->nb_boot_blocks) * this->erasesize;
-
- printf("\t NFTL boot record:\n"
- "\t Binary partition: size %ld%s\n"
- "\t Flash disk partition: size %ld%s, offset 0x%lx\n",
- bin_size > (1 << 20) ? bin_size >> 20 : bin_size >> 10,
- bin_size > (1 << 20) ? "MB" : "kB",
- flash_size > (1 << 20) ? flash_size >> 20 : flash_size >> 10,
- flash_size > (1 << 20) ? "MB" : "kB", bin_size);
- } else {
- puts ("\t No NFTL boot record found.\n");
- }
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* This function is needed to avoid calls of the __ashrdi3 function. */
-static int shr(int val, int shift) {
- return val >> shift;
-}
-
-/* Perform the required delay cycles by reading from the appropriate register */
-static void DoC_Delay(struct DiskOnChip *doc, unsigned short cycles)
-{
- volatile char dummy;
- int i;
-
- for (i = 0; i < cycles; i++) {
- if (DoC_is_Millennium(doc))
- dummy = ReadDOC(doc->virtadr, NOP);
- else
- dummy = ReadDOC(doc->virtadr, DOCStatus);
- }
-
-}
-
-/* DOC_WaitReady: Wait for RDY line to be asserted by the flash chip */
-static int _DoC_WaitReady(struct DiskOnChip *doc)
-{
- unsigned long docptr = doc->virtadr;
- unsigned long start = get_timer(0);
-
-#ifdef PSYCHO_DEBUG
- puts ("_DoC_WaitReady called for out-of-line wait\n");
-#endif
-
- /* Out-of-line routine to wait for chip response */
- while (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) {
-#ifdef CONFIG_SYS_DOC_SHORT_TIMEOUT
- /* it seems that after a certain time the DoC deasserts
- * the CDSN_CTRL_FR_B although it is not ready...
- * using a short timout solve this (timer increments every ms) */
- if (get_timer(start) > 10) {
- return DOC_ETIMEOUT;
- }
-#else
- if (get_timer(start) > 10 * 1000) {
- puts ("_DoC_WaitReady timed out.\n");
- return DOC_ETIMEOUT;
- }
-#endif
- udelay(1);
- }
-
- return 0;
-}
-
-static int DoC_WaitReady(struct DiskOnChip *doc)
-{
- unsigned long docptr = doc->virtadr;
- /* This is inline, to optimise the common case, where it's ready instantly */
- int ret = 0;
-
- /* 4 read form NOP register should be issued in prior to the read from CDSNControl
- see Software Requirement 11.4 item 2. */
- DoC_Delay(doc, 4);
-
- if (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B))
- /* Call the out-of-line routine to wait */
- ret = _DoC_WaitReady(doc);
-
- /* issue 2 read from NOP register after reading from CDSNControl register
- see Software Requirement 11.4 item 2. */
- DoC_Delay(doc, 2);
-
- return ret;
-}
-
-/* DoC_Command: Send a flash command to the flash chip through the CDSN Slow IO register to
- bypass the internal pipeline. Each of 4 delay cycles (read from the NOP register) is
- required after writing to CDSN Control register, see Software Requirement 11.4 item 3. */
-
-static inline int DoC_Command(struct DiskOnChip *doc, unsigned char command,
- unsigned char xtraflags)
-{
- unsigned long docptr = doc->virtadr;
-
- if (DoC_is_2000(doc))
- xtraflags |= CDSN_CTRL_FLASH_IO;
-
- /* Assert the CLE (Command Latch Enable) line to the flash chip */
- WriteDOC(xtraflags | CDSN_CTRL_CLE | CDSN_CTRL_CE, docptr, CDSNControl);
- DoC_Delay(doc, 4); /* Software requirement 11.4.3 for Millennium */
-
- if (DoC_is_Millennium(doc))
- WriteDOC(command, docptr, CDSNSlowIO);
-
- /* Send the command */
- WriteDOC_(command, docptr, doc->ioreg);
-
- /* Lower the CLE line */
- WriteDOC(xtraflags | CDSN_CTRL_CE, docptr, CDSNControl);
- DoC_Delay(doc, 4); /* Software requirement 11.4.3 for Millennium */
-
- /* Wait for the chip to respond - Software requirement 11.4.1 (extended for any command) */
- return DoC_WaitReady(doc);
-}
-
-/* DoC_Address: Set the current address for the flash chip through the CDSN Slow IO register to
- bypass the internal pipeline. Each of 4 delay cycles (read from the NOP register) is
- required after writing to CDSN Control register, see Software Requirement 11.4 item 3. */
-
-static int DoC_Address(struct DiskOnChip *doc, int numbytes, unsigned long ofs,
- unsigned char xtraflags1, unsigned char xtraflags2)
-{
- unsigned long docptr;
- int i;
-
- docptr = doc->virtadr;
-
- if (DoC_is_2000(doc))
- xtraflags1 |= CDSN_CTRL_FLASH_IO;
-
- /* Assert the ALE (Address Latch Enable) line to the flash chip */
- WriteDOC(xtraflags1 | CDSN_CTRL_ALE | CDSN_CTRL_CE, docptr, CDSNControl);
-
- DoC_Delay(doc, 4); /* Software requirement 11.4.3 for Millennium */
-
- /* Send the address */
- /* Devices with 256-byte page are addressed as:
- Column (bits 0-7), Page (bits 8-15, 16-23, 24-31)
- * there is no device on the market with page256
- and more than 24 bits.
- Devices with 512-byte page are addressed as:
- Column (bits 0-7), Page (bits 9-16, 17-24, 25-31)
- * 25-31 is sent only if the chip support it.
- * bit 8 changes the read command to be sent
- (NAND_CMD_READ0 or NAND_CMD_READ1).
- */
-
- if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE) {
- if (DoC_is_Millennium(doc))
- WriteDOC(ofs & 0xff, docptr, CDSNSlowIO);
- WriteDOC_(ofs & 0xff, docptr, doc->ioreg);
- }
-
- if (doc->page256) {
- ofs = ofs >> 8;
- } else {
- ofs = ofs >> 9;
- }
-
- if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) {
- for (i = 0; i < doc->pageadrlen; i++, ofs = ofs >> 8) {
- if (DoC_is_Millennium(doc))
- WriteDOC(ofs & 0xff, docptr, CDSNSlowIO);
- WriteDOC_(ofs & 0xff, docptr, doc->ioreg);
- }
- }
-
- DoC_Delay(doc, 2); /* Needed for some slow flash chips. mf. */
-
- /* FIXME: The SlowIO's for millennium could be replaced by
- a single WritePipeTerm here. mf. */
-
- /* Lower the ALE line */
- WriteDOC(xtraflags1 | xtraflags2 | CDSN_CTRL_CE, docptr,
- CDSNControl);
-
- DoC_Delay(doc, 4); /* Software requirement 11.4.3 for Millennium */
-
- /* Wait for the chip to respond - Software requirement 11.4.1 */
- return DoC_WaitReady(doc);
-}
-
-/* Read a buffer from DoC, taking care of Millennium oddities */
-static void DoC_ReadBuf(struct DiskOnChip *doc, u_char * buf, int len)
-{
- volatile int dummy;
- int modulus = 0xffff;
- unsigned long docptr;
- int i;
-
- docptr = doc->virtadr;
-
- if (len <= 0)
- return;
-
- if (DoC_is_Millennium(doc)) {
- /* Read the data via the internal pipeline through CDSN IO register,
- see Pipelined Read Operations 11.3 */
- dummy = ReadDOC(docptr, ReadPipeInit);
-
- /* Millennium should use the LastDataRead register - Pipeline Reads */
- len--;
-
- /* This is needed for correctly ECC calculation */
- modulus = 0xff;
- }
-
- for (i = 0; i < len; i++)
- buf[i] = ReadDOC_(docptr, doc->ioreg + (i & modulus));
-
- if (DoC_is_Millennium(doc)) {
- buf[i] = ReadDOC(docptr, LastDataRead);
- }
-}
-
-/* Write a buffer to DoC, taking care of Millennium oddities */
-static void DoC_WriteBuf(struct DiskOnChip *doc, const u_char * buf, int len)
-{
- unsigned long docptr;
- int i;
-
- docptr = doc->virtadr;
-
- if (len <= 0)
- return;
-
- for (i = 0; i < len; i++)
- WriteDOC_(buf[i], docptr, doc->ioreg + i);
-
- if (DoC_is_Millennium(doc)) {
- WriteDOC(0x00, docptr, WritePipeTerm);
- }
-}
-
-
-/* DoC_SelectChip: Select a given flash chip within the current floor */
-
-static inline int DoC_SelectChip(struct DiskOnChip *doc, int chip)
-{
- unsigned long docptr = doc->virtadr;
-
- /* Software requirement 11.4.4 before writing DeviceSelect */
- /* Deassert the CE line to eliminate glitches on the FCE# outputs */
- WriteDOC(CDSN_CTRL_WP, docptr, CDSNControl);
- DoC_Delay(doc, 4); /* Software requirement 11.4.3 for Millennium */
-
- /* Select the individual flash chip requested */
- WriteDOC(chip, docptr, CDSNDeviceSelect);
- DoC_Delay(doc, 4);
-
- /* Reassert the CE line */
- WriteDOC(CDSN_CTRL_CE | CDSN_CTRL_FLASH_IO | CDSN_CTRL_WP, docptr,
- CDSNControl);
- DoC_Delay(doc, 4); /* Software requirement 11.4.3 for Millennium */
-
- /* Wait for it to be ready */
- return DoC_WaitReady(doc);
-}
-
-/* DoC_SelectFloor: Select a given floor (bank of flash chips) */
-
-static inline int DoC_SelectFloor(struct DiskOnChip *doc, int floor)
-{
- unsigned long docptr = doc->virtadr;
-
- /* Select the floor (bank) of chips required */
- WriteDOC(floor, docptr, FloorSelect);
-
- /* Wait for the chip to be ready */
- return DoC_WaitReady(doc);
-}
-
-/* DoC_IdentChip: Identify a given NAND chip given {floor,chip} */
-
-static int DoC_IdentChip(struct DiskOnChip *doc, int floor, int chip)
-{
- int mfr, id, i;
- volatile char dummy;
-
- /* Page in the required floor/chip */
- DoC_SelectFloor(doc, floor);
- DoC_SelectChip(doc, chip);
-
- /* Reset the chip */
- if (DoC_Command(doc, NAND_CMD_RESET, CDSN_CTRL_WP)) {
-#ifdef DOC_DEBUG
- printf("DoC_Command (reset) for %d,%d returned true\n",
- floor, chip);
-#endif
- return 0;
- }
-
-
- /* Read the NAND chip ID: 1. Send ReadID command */
- if (DoC_Command(doc, NAND_CMD_READID, CDSN_CTRL_WP)) {
-#ifdef DOC_DEBUG
- printf("DoC_Command (ReadID) for %d,%d returned true\n",
- floor, chip);
-#endif
- return 0;
- }
-
- /* Read the NAND chip ID: 2. Send address byte zero */
- DoC_Address(doc, ADDR_COLUMN, 0, CDSN_CTRL_WP, 0);
-
- /* Read the manufacturer and device id codes from the device */
-
- /* CDSN Slow IO register see Software Requirement 11.4 item 5. */
- dummy = ReadDOC(doc->virtadr, CDSNSlowIO);
- DoC_Delay(doc, 2);
- mfr = ReadDOC_(doc->virtadr, doc->ioreg);
-
- /* CDSN Slow IO register see Software Requirement 11.4 item 5. */
- dummy = ReadDOC(doc->virtadr, CDSNSlowIO);
- DoC_Delay(doc, 2);
- id = ReadDOC_(doc->virtadr, doc->ioreg);
-
- /* No response - return failure */
- if (mfr == 0xff || mfr == 0)
- return 0;
-
- /* Check it's the same as the first chip we identified.
- * M-Systems say that any given DiskOnChip device should only
- * contain _one_ type of flash part, although that's not a
- * hardware restriction. */
- if (doc->mfr) {
- if (doc->mfr == mfr && doc->id == id)
- return 1; /* This is another the same the first */
- else
- printf("Flash chip at floor %d, chip %d is different:\n",
- floor, chip);
- }
-
- /* Print and store the manufacturer and ID codes. */
- for (i = 0; nand_flash_ids[i].name != NULL; i++) {
- if (mfr == nand_flash_ids[i].manufacture_id &&
- id == nand_flash_ids[i].model_id) {
-#ifdef DOC_DEBUG
- printf("Flash chip found: Manufacturer ID: %2.2X, "
- "Chip ID: %2.2X (%s)\n", mfr, id,
- nand_flash_ids[i].name);
-#endif
- if (!doc->mfr) {
- doc->mfr = mfr;
- doc->id = id;
- doc->chipshift =
- nand_flash_ids[i].chipshift;
- doc->page256 = nand_flash_ids[i].page256;
- doc->pageadrlen =
- nand_flash_ids[i].pageadrlen;
- doc->erasesize =
- nand_flash_ids[i].erasesize;
- doc->chips_name =
- nand_flash_ids[i].name;
- return 1;
- }
- return 0;
- }
- }
-
-
-#ifdef DOC_DEBUG
- /* We haven't fully identified the chip. Print as much as we know. */
- printf("Unknown flash chip found: %2.2X %2.2X\n",
- id, mfr);
-#endif
-
- return 0;
-}
-
-/* DoC_ScanChips: Find all NAND chips present in a DiskOnChip, and identify them */
-
-static void DoC_ScanChips(struct DiskOnChip *this)
-{
- int floor, chip;
- int numchips[MAX_FLOORS];
- int maxchips = MAX_CHIPS;
- int ret = 1;
-
- this->numchips = 0;
- this->mfr = 0;
- this->id = 0;
-
- if (DoC_is_Millennium(this))
- maxchips = MAX_CHIPS_MIL;
-
- /* For each floor, find the number of valid chips it contains */
- for (floor = 0; floor < MAX_FLOORS; floor++) {
- ret = 1;
- numchips[floor] = 0;
- for (chip = 0; chip < maxchips && ret != 0; chip++) {
-
- ret = DoC_IdentChip(this, floor, chip);
- if (ret) {
- numchips[floor]++;
- this->numchips++;
- }
- }
- }
-
- /* If there are none at all that we recognise, bail */
- if (!this->numchips) {
- puts ("No flash chips recognised.\n");
- return;
- }
-
- /* Allocate an array to hold the information for each chip */
- this->chips = malloc(sizeof(struct Nand) * this->numchips);
- if (!this->chips) {
- puts ("No memory for allocating chip info structures\n");
- return;
- }
-
- ret = 0;
-
- /* Fill out the chip array with {floor, chipno} for each
- * detected chip in the device. */
- for (floor = 0; floor < MAX_FLOORS; floor++) {
- for (chip = 0; chip < numchips[floor]; chip++) {
- this->chips[ret].floor = floor;
- this->chips[ret].chip = chip;
- this->chips[ret].curadr = 0;
- this->chips[ret].curmode = 0x50;
- ret++;
- }
- }
-
- /* Calculate and print the total size of the device */
- this->totlen = this->numchips * (1 << this->chipshift);
-
-#ifdef DOC_DEBUG
- printf("%d flash chips found. Total DiskOnChip size: %ld MB\n",
- this->numchips, this->totlen >> 20);
-#endif
-}
-
-/* find_boot_record: Find the NFTL Media Header and its Spare copy which contains the
- * various device information of the NFTL partition and Bad Unit Table. Update
- * the ReplUnitTable[] table accroding to the Bad Unit Table. ReplUnitTable[]
- * is used for management of Erase Unit in other routines in nftl.c and nftlmount.c
- */
-static int find_boot_record(struct NFTLrecord *nftl)
-{
- struct nftl_uci1 h1;
- struct nftl_oob oob;
- unsigned int block, boot_record_count = 0;
- int retlen;
- u8 buf[SECTORSIZE];
- struct NFTLMediaHeader *mh = &nftl->MediaHdr;
- unsigned int i;
-
- nftl->MediaUnit = BLOCK_NIL;
- nftl->SpareMediaUnit = BLOCK_NIL;
-
- /* search for a valid boot record */
- for (block = 0; block < nftl->nb_blocks; block++) {
- int ret;
-
- /* Check for ANAND header first. Then can whinge if it's found but later
- checks fail */
- if ((ret = doc_read_ecc(nftl->mtd, block * nftl->EraseSize, SECTORSIZE,
- (size_t *)&retlen, buf, NULL))) {
- static int warncount = 5;
-
- if (warncount) {
- printf("Block read at 0x%x failed\n", block * nftl->EraseSize);
- if (!--warncount)
- puts ("Further failures for this block will not be printed\n");
- }
- continue;
- }
-
- if (retlen < 6 || memcmp(buf, "ANAND", 6)) {
- /* ANAND\0 not found. Continue */
-#ifdef PSYCHO_DEBUG
- printf("ANAND header not found at 0x%x\n", block * nftl->EraseSize);
-#endif
- continue;
- }
-
-#ifdef NFTL_DEBUG
- printf("ANAND header found at 0x%x\n", block * nftl->EraseSize);
-#endif
-
- /* To be safer with BIOS, also use erase mark as discriminant */
- if ((ret = doc_read_oob(nftl->mtd, block * nftl->EraseSize + SECTORSIZE + 8,
- 8, (size_t *)&retlen, (uchar *)&h1) < 0)) {
-#ifdef NFTL_DEBUG
- printf("ANAND header found at 0x%x, but OOB data read failed\n",
- block * nftl->EraseSize);
-#endif
- continue;
- }
-
- /* OK, we like it. */
-
- if (boot_record_count) {
- /* We've already processed one. So we just check if
- this one is the same as the first one we found */
- if (memcmp(mh, buf, sizeof(struct NFTLMediaHeader))) {
-#ifdef NFTL_DEBUG
- printf("NFTL Media Headers at 0x%x and 0x%x disagree.\n",
- nftl->MediaUnit * nftl->EraseSize, block * nftl->EraseSize);
-#endif
- /* if (debug) Print both side by side */
- return -1;
- }
- if (boot_record_count == 1)
- nftl->SpareMediaUnit = block;
-
- boot_record_count++;
- continue;
- }
-
- /* This is the first we've seen. Copy the media header structure into place */
- memcpy(mh, buf, sizeof(struct NFTLMediaHeader));
-
- /* Do some sanity checks on it */
- if (mh->UnitSizeFactor == 0) {
-#ifdef NFTL_DEBUG
- puts ("UnitSizeFactor 0x00 detected.\n"
- "This violates the spec but we think we know what it means...\n");
-#endif
- } else if (mh->UnitSizeFactor != 0xff) {
- printf ("Sorry, we don't support UnitSizeFactor "
- "of != 1 yet.\n");
- return -1;
- }
-
- nftl->nb_boot_blocks = le16_to_cpu(mh->FirstPhysicalEUN);
- if ((nftl->nb_boot_blocks + 2) >= nftl->nb_blocks) {
- printf ("NFTL Media Header sanity check failed:\n"
- "nb_boot_blocks (%d) + 2 > nb_blocks (%d)\n",
- nftl->nb_boot_blocks, nftl->nb_blocks);
- return -1;
- }
-
- nftl->numvunits = le32_to_cpu(mh->FormattedSize) / nftl->EraseSize;
- if (nftl->numvunits > (nftl->nb_blocks - nftl->nb_boot_blocks - 2)) {
- printf ("NFTL Media Header sanity check failed:\n"
- "numvunits (%d) > nb_blocks (%d) - nb_boot_blocks(%d) - 2\n",
- nftl->numvunits,
- nftl->nb_blocks,
- nftl->nb_boot_blocks);
- return -1;
- }
-
- nftl->nr_sects = nftl->numvunits * (nftl->EraseSize / SECTORSIZE);
-
- /* If we're not using the last sectors in the device for some reason,
- reduce nb_blocks accordingly so we forget they're there */
- nftl->nb_blocks = le16_to_cpu(mh->NumEraseUnits) + le16_to_cpu(mh->FirstPhysicalEUN);
-
- /* read the Bad Erase Unit Table and modify ReplUnitTable[] accordingly */
- for (i = 0; i < nftl->nb_blocks; i++) {
- if ((i & (SECTORSIZE - 1)) == 0) {
- /* read one sector for every SECTORSIZE of blocks */
- if ((ret = doc_read_ecc(nftl->mtd, block * nftl->EraseSize +
- i + SECTORSIZE, SECTORSIZE,
- (size_t *)&retlen, buf, (uchar *)&oob)) < 0) {
- puts ("Read of bad sector table failed\n");
- return -1;
- }
- }
- /* mark the Bad Erase Unit as RESERVED in ReplUnitTable */
- if (buf[i & (SECTORSIZE - 1)] != 0xff)
- nftl->ReplUnitTable[i] = BLOCK_RESERVED;
- }
-
- nftl->MediaUnit = block;
- boot_record_count++;
-
- } /* foreach (block) */
-
- return boot_record_count?0:-1;
-}
-
-/* This routine is made available to other mtd code via
- * inter_module_register. It must only be accessed through
- * inter_module_get which will bump the use count of this module. The
- * addresses passed back in mtd are valid as long as the use count of
- * this module is non-zero, i.e. between inter_module_get and
- * inter_module_put. Keith Owens <kaos@ocs.com.au> 29 Oct 2000.
- */
-static void DoC2k_init(struct DiskOnChip* this)
-{
- struct NFTLrecord *nftl;
-
- switch (this->ChipID) {
- case DOC_ChipID_Doc2k:
- this->name = "DiskOnChip 2000";
- this->ioreg = DoC_2k_CDSN_IO;
- break;
- case DOC_ChipID_DocMil:
- this->name = "DiskOnChip Millennium";
- this->ioreg = DoC_Mil_CDSN_IO;
- break;
- }
-
-#ifdef DOC_DEBUG
- printf("%s found at address 0x%lX\n", this->name,
- this->physadr);
-#endif
-
- this->totlen = 0;
- this->numchips = 0;
-
- this->curfloor = -1;
- this->curchip = -1;
-
- /* Ident all the chips present. */
- DoC_ScanChips(this);
- if ((!this->numchips) || (!this->chips))
- return;
-
- nftl = &this->nftl;
-
- /* Get physical parameters */
- nftl->EraseSize = this->erasesize;
- nftl->nb_blocks = this->totlen / this->erasesize;
- nftl->mtd = this;
-
- if (find_boot_record(nftl) != 0)
- this->nftl_found = 0;
- else
- this->nftl_found = 1;
-
- printf("%s @ 0x%lX, %ld MB\n", this->name, this->physadr, this->totlen >> 20);
-}
-
-int doc_read_ecc(struct DiskOnChip* this, loff_t from, size_t len,
- size_t * retlen, u_char * buf, u_char * eccbuf)
-{
- unsigned long docptr;
- struct Nand *mychip;
- unsigned char syndrome[6];
- volatile char dummy;
- int i, len256 = 0, ret=0;
-
- docptr = this->virtadr;
-
- /* Don't allow read past end of device */
- if (from >= this->totlen) {
- puts ("Out of flash\n");
- return DOC_EINVAL;
- }
-
- /* Don't allow a single read to cross a 512-byte block boundary */
- if (from + len > ((from | 0x1ff) + 1))
- len = ((from | 0x1ff) + 1) - from;
-
- /* The ECC will not be calculated correctly if less than 512 is read */
- if (len != 0x200 && eccbuf)
- printf("ECC needs a full sector read (adr: %lx size %lx)\n",
- (long) from, (long) len);
-
-#ifdef PSYCHO_DEBUG
- printf("DoC_Read (adr: %lx size %lx)\n", (long) from, (long) len);
-#endif
-
- /* Find the chip which is to be used and select it */
- mychip = &this->chips[shr(from, this->chipshift)];
-
- if (this->curfloor != mychip->floor) {
- DoC_SelectFloor(this, mychip->floor);
- DoC_SelectChip(this, mychip->chip);
- } else if (this->curchip != mychip->chip) {
- DoC_SelectChip(this, mychip->chip);
- }
-
- this->curfloor = mychip->floor;
- this->curchip = mychip->chip;
-
- DoC_Command(this,
- (!this->page256
- && (from & 0x100)) ? NAND_CMD_READ1 : NAND_CMD_READ0,
- CDSN_CTRL_WP);
- DoC_Address(this, ADDR_COLUMN_PAGE, from, CDSN_CTRL_WP,
- CDSN_CTRL_ECC_IO);
-
- if (eccbuf) {
- /* Prime the ECC engine */
- WriteDOC(DOC_ECC_RESET, docptr, ECCConf);
- WriteDOC(DOC_ECC_EN, docptr, ECCConf);
- } else {
- /* disable the ECC engine */
- WriteDOC(DOC_ECC_RESET, docptr, ECCConf);
- WriteDOC(DOC_ECC_DIS, docptr, ECCConf);
- }
-
- /* treat crossing 256-byte sector for 2M x 8bits devices */
- if (this->page256 && from + len > (from | 0xff) + 1) {
- len256 = (from | 0xff) + 1 - from;
- DoC_ReadBuf(this, buf, len256);
-
- DoC_Command(this, NAND_CMD_READ0, CDSN_CTRL_WP);
- DoC_Address(this, ADDR_COLUMN_PAGE, from + len256,
- CDSN_CTRL_WP, CDSN_CTRL_ECC_IO);
- }
-
- DoC_ReadBuf(this, &buf[len256], len - len256);
-
- /* Let the caller know we completed it */
- *retlen = len;
-
- if (eccbuf) {
- /* Read the ECC data through the DiskOnChip ECC logic */
- /* Note: this will work even with 2M x 8bit devices as */
- /* they have 8 bytes of OOB per 256 page. mf. */
- DoC_ReadBuf(this, eccbuf, 6);
-
- /* Flush the pipeline */
- if (DoC_is_Millennium(this)) {
- dummy = ReadDOC(docptr, ECCConf);
- dummy = ReadDOC(docptr, ECCConf);
- i = ReadDOC(docptr, ECCConf);
- } else {
- dummy = ReadDOC(docptr, 2k_ECCStatus);
- dummy = ReadDOC(docptr, 2k_ECCStatus);
- i = ReadDOC(docptr, 2k_ECCStatus);
- }
-
- /* Check the ECC Status */
- if (i & 0x80) {
- int nb_errors;
- /* There was an ECC error */
-#ifdef ECC_DEBUG
- printf("DiskOnChip ECC Error: Read at %lx\n", (long)from);
-#endif
- /* Read the ECC syndrom through the DiskOnChip ECC logic.
- These syndrome will be all ZERO when there is no error */
- for (i = 0; i < 6; i++) {
- syndrome[i] =
- ReadDOC(docptr, ECCSyndrome0 + i);
- }
- nb_errors = doc_decode_ecc(buf, syndrome);
-
-#ifdef ECC_DEBUG
- printf("Errors corrected: %x\n", nb_errors);
-#endif
- if (nb_errors < 0) {
- /* We return error, but have actually done the read. Not that
- this can be told to user-space, via sys_read(), but at least
- MTD-aware stuff can know about it by checking *retlen */
- printf("ECC Errors at %lx\n", (long)from);
- ret = DOC_EECC;
- }
- }
-
-#ifdef PSYCHO_DEBUG
- printf("ECC DATA at %lxB: %2.2X %2.2X %2.2X %2.2X %2.2X %2.2X\n",
- (long)from, eccbuf[0], eccbuf[1], eccbuf[2],
- eccbuf[3], eccbuf[4], eccbuf[5]);
-#endif
-
- /* disable the ECC engine */
- WriteDOC(DOC_ECC_DIS, docptr , ECCConf);
- }
-
- /* according to 11.4.1, we need to wait for the busy line
- * drop if we read to the end of the page. */
- if(0 == ((from + *retlen) & 0x1ff))
- {
- DoC_WaitReady(this);
- }
-
- return ret;
-}
-
-int doc_write_ecc(struct DiskOnChip* this, loff_t to, size_t len,
- size_t * retlen, const u_char * buf,
- u_char * eccbuf)
-{
- int di; /* Yes, DI is a hangover from when I was disassembling the binary driver */
- unsigned long docptr;
- volatile char dummy;
- int len256 = 0;
- struct Nand *mychip;
-
- docptr = this->virtadr;
-
- /* Don't allow write past end of device */
- if (to >= this->totlen) {
- puts ("Out of flash\n");
- return DOC_EINVAL;
- }
-
- /* Don't allow a single write to cross a 512-byte block boundary */
- if (to + len > ((to | 0x1ff) + 1))
- len = ((to | 0x1ff) + 1) - to;
-
- /* The ECC will not be calculated correctly if less than 512 is written */
- if (len != 0x200 && eccbuf)
- printf("ECC needs a full sector write (adr: %lx size %lx)\n",
- (long) to, (long) len);
-
- /* printf("DoC_Write (adr: %lx size %lx)\n", (long) to, (long) len); */
-
- /* Find the chip which is to be used and select it */
- mychip = &this->chips[shr(to, this->chipshift)];
-
- if (this->curfloor != mychip->floor) {
- DoC_SelectFloor(this, mychip->floor);
- DoC_SelectChip(this, mychip->chip);
- } else if (this->curchip != mychip->chip) {
- DoC_SelectChip(this, mychip->chip);
- }
-
- this->curfloor = mychip->floor;
- this->curchip = mychip->chip;
-
- /* Set device to main plane of flash */
- DoC_Command(this, NAND_CMD_RESET, CDSN_CTRL_WP);
- DoC_Command(this,
- (!this->page256
- && (to & 0x100)) ? NAND_CMD_READ1 : NAND_CMD_READ0,
- CDSN_CTRL_WP);
-
- DoC_Command(this, NAND_CMD_SEQIN, 0);
- DoC_Address(this, ADDR_COLUMN_PAGE, to, 0, CDSN_CTRL_ECC_IO);
-
- if (eccbuf) {
- /* Prime the ECC engine */
- WriteDOC(DOC_ECC_RESET, docptr, ECCConf);
- WriteDOC(DOC_ECC_EN | DOC_ECC_RW, docptr, ECCConf);
- } else {
- /* disable the ECC engine */
- WriteDOC(DOC_ECC_RESET, docptr, ECCConf);
- WriteDOC(DOC_ECC_DIS, docptr, ECCConf);
- }
-
- /* treat crossing 256-byte sector for 2M x 8bits devices */
- if (this->page256 && to + len > (to | 0xff) + 1) {
- len256 = (to | 0xff) + 1 - to;
- DoC_WriteBuf(this, buf, len256);
-
- DoC_Command(this, NAND_CMD_PAGEPROG, 0);
-
- DoC_Command(this, NAND_CMD_STATUS, CDSN_CTRL_WP);
- /* There's an implicit DoC_WaitReady() in DoC_Command */
-
- dummy = ReadDOC(docptr, CDSNSlowIO);
- DoC_Delay(this, 2);
-
- if (ReadDOC_(docptr, this->ioreg) & 1) {
- puts ("Error programming flash\n");
- /* Error in programming */
- *retlen = 0;
- return DOC_EIO;
- }
-
- DoC_Command(this, NAND_CMD_SEQIN, 0);
- DoC_Address(this, ADDR_COLUMN_PAGE, to + len256, 0,
- CDSN_CTRL_ECC_IO);
- }
-
- DoC_WriteBuf(this, &buf[len256], len - len256);
-
- if (eccbuf) {
- WriteDOC(CDSN_CTRL_ECC_IO | CDSN_CTRL_CE, docptr,
- CDSNControl);
-
- if (DoC_is_Millennium(this)) {
- WriteDOC(0, docptr, NOP);
- WriteDOC(0, docptr, NOP);
- WriteDOC(0, docptr, NOP);
- } else {
- WriteDOC_(0, docptr, this->ioreg);
- WriteDOC_(0, docptr, this->ioreg);
- WriteDOC_(0, docptr, this->ioreg);
- }
-
- /* Read the ECC data through the DiskOnChip ECC logic */
- for (di = 0; di < 6; di++) {
- eccbuf[di] = ReadDOC(docptr, ECCSyndrome0 + di);
- }
-
- /* Reset the ECC engine */
- WriteDOC(DOC_ECC_DIS, docptr, ECCConf);
-
-#ifdef PSYCHO_DEBUG
- printf
- ("OOB data at %lx is %2.2X %2.2X %2.2X %2.2X %2.2X %2.2X\n",
- (long) to, eccbuf[0], eccbuf[1], eccbuf[2], eccbuf[3],
- eccbuf[4], eccbuf[5]);
-#endif
- }
-
- DoC_Command(this, NAND_CMD_PAGEPROG, 0);
-
- DoC_Command(this, NAND_CMD_STATUS, CDSN_CTRL_WP);
- /* There's an implicit DoC_WaitReady() in DoC_Command */
-
- dummy = ReadDOC(docptr, CDSNSlowIO);
- DoC_Delay(this, 2);
-
- if (ReadDOC_(docptr, this->ioreg) & 1) {
- puts ("Error programming flash\n");
- /* Error in programming */
- *retlen = 0;
- return DOC_EIO;
- }
-
- /* Let the caller know we completed it */
- *retlen = len;
-
- if (eccbuf) {
- unsigned char x[8];
- size_t dummy;
- int ret;
-
- /* Write the ECC data to flash */
- for (di=0; di<6; di++)
- x[di] = eccbuf[di];
-
- x[6]=0x55;
- x[7]=0x55;
-
- ret = doc_write_oob(this, to, 8, &dummy, x);
- return ret;
- }
- return 0;
-}
-
-int doc_read_oob(struct DiskOnChip* this, loff_t ofs, size_t len,
- size_t * retlen, u_char * buf)
-{
- int len256 = 0, ret;
- unsigned long docptr;
- struct Nand *mychip;
-
- docptr = this->virtadr;
-
- mychip = &this->chips[shr(ofs, this->chipshift)];
-
- if (this->curfloor != mychip->floor) {
- DoC_SelectFloor(this, mychip->floor);
- DoC_SelectChip(this, mychip->chip);
- } else if (this->curchip != mychip->chip) {
- DoC_SelectChip(this, mychip->chip);
- }
- this->curfloor = mychip->floor;
- this->curchip = mychip->chip;
-
- /* update address for 2M x 8bit devices. OOB starts on the second */
- /* page to maintain compatibility with doc_read_ecc. */
- if (this->page256) {
- if (!(ofs & 0x8))
- ofs += 0x100;
- else
- ofs -= 0x8;
- }
-
- DoC_Command(this, NAND_CMD_READOOB, CDSN_CTRL_WP);
- DoC_Address(this, ADDR_COLUMN_PAGE, ofs, CDSN_CTRL_WP, 0);
-
- /* treat crossing 8-byte OOB data for 2M x 8bit devices */
- /* Note: datasheet says it should automaticaly wrap to the */
- /* next OOB block, but it didn't work here. mf. */
- if (this->page256 && ofs + len > (ofs | 0x7) + 1) {
- len256 = (ofs | 0x7) + 1 - ofs;
- DoC_ReadBuf(this, buf, len256);
-
- DoC_Command(this, NAND_CMD_READOOB, CDSN_CTRL_WP);
- DoC_Address(this, ADDR_COLUMN_PAGE, ofs & (~0x1ff),
- CDSN_CTRL_WP, 0);
- }
-
- DoC_ReadBuf(this, &buf[len256], len - len256);
-
- *retlen = len;
- /* Reading the full OOB data drops us off of the end of the page,
- * causing the flash device to go into busy mode, so we need
- * to wait until ready 11.4.1 and Toshiba TC58256FT docs */
-
- ret = DoC_WaitReady(this);
-
- return ret;
-
-}
-
-int doc_write_oob(struct DiskOnChip* this, loff_t ofs, size_t len,
- size_t * retlen, const u_char * buf)
-{
- int len256 = 0;
- unsigned long docptr = this->virtadr;
- struct Nand *mychip = &this->chips[shr(ofs, this->chipshift)];
- volatile int dummy;
-
-#ifdef PSYCHO_DEBUG
- printf("doc_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n",
- (long)ofs, len, buf[0], buf[1], buf[2], buf[3],
- buf[8], buf[9], buf[14],buf[15]);
-#endif
-
- /* Find the chip which is to be used and select it */
- if (this->curfloor != mychip->floor) {
- DoC_SelectFloor(this, mychip->floor);
- DoC_SelectChip(this, mychip->chip);
- } else if (this->curchip != mychip->chip) {
- DoC_SelectChip(this, mychip->chip);
- }
- this->curfloor = mychip->floor;
- this->curchip = mychip->chip;
-
- /* disable the ECC engine */
- WriteDOC (DOC_ECC_RESET, docptr, ECCConf);
- WriteDOC (DOC_ECC_DIS, docptr, ECCConf);
-
- /* Reset the chip, see Software Requirement 11.4 item 1. */
- DoC_Command(this, NAND_CMD_RESET, CDSN_CTRL_WP);
-
- /* issue the Read2 command to set the pointer to the Spare Data Area. */
- DoC_Command(this, NAND_CMD_READOOB, CDSN_CTRL_WP);
-
- /* update address for 2M x 8bit devices. OOB starts on the second */
- /* page to maintain compatibility with doc_read_ecc. */
- if (this->page256) {
- if (!(ofs & 0x8))
- ofs += 0x100;
- else
- ofs -= 0x8;
- }
-
- /* issue the Serial Data In command to initial the Page Program process */
- DoC_Command(this, NAND_CMD_SEQIN, 0);
- DoC_Address(this, ADDR_COLUMN_PAGE, ofs, 0, 0);
-
- /* treat crossing 8-byte OOB data for 2M x 8bit devices */
- /* Note: datasheet says it should automaticaly wrap to the */
- /* next OOB block, but it didn't work here. mf. */
- if (this->page256 && ofs + len > (ofs | 0x7) + 1) {
- len256 = (ofs | 0x7) + 1 - ofs;
- DoC_WriteBuf(this, buf, len256);
-
- DoC_Command(this, NAND_CMD_PAGEPROG, 0);
- DoC_Command(this, NAND_CMD_STATUS, 0);
- /* DoC_WaitReady() is implicit in DoC_Command */
-
- dummy = ReadDOC(docptr, CDSNSlowIO);
- DoC_Delay(this, 2);
-
- if (ReadDOC_(docptr, this->ioreg) & 1) {
- puts ("Error programming oob data\n");
- /* There was an error */
- *retlen = 0;
- return DOC_EIO;
- }
- DoC_Command(this, NAND_CMD_SEQIN, 0);
- DoC_Address(this, ADDR_COLUMN_PAGE, ofs & (~0x1ff), 0, 0);
- }
-
- DoC_WriteBuf(this, &buf[len256], len - len256);
-
- DoC_Command(this, NAND_CMD_PAGEPROG, 0);
- DoC_Command(this, NAND_CMD_STATUS, 0);
- /* DoC_WaitReady() is implicit in DoC_Command */
-
- dummy = ReadDOC(docptr, CDSNSlowIO);
- DoC_Delay(this, 2);
-
- if (ReadDOC_(docptr, this->ioreg) & 1) {
- puts ("Error programming oob data\n");
- /* There was an error */
- *retlen = 0;
- return DOC_EIO;
- }
-
- *retlen = len;
- return 0;
-
-}
-
-int doc_erase(struct DiskOnChip* this, loff_t ofs, size_t len)
-{
- volatile int dummy;
- unsigned long docptr;
- struct Nand *mychip;
-
- if (ofs & (this->erasesize-1) || len & (this->erasesize-1)) {
- puts ("Offset and size must be sector aligned\n");
- return DOC_EINVAL;
- }
-
- docptr = this->virtadr;
-
- /* FIXME: Do this in the background. Use timers or schedule_task() */
- while(len) {
- mychip = &this->chips[shr(ofs, this->chipshift)];
-
- if (this->curfloor != mychip->floor) {
- DoC_SelectFloor(this, mychip->floor);
- DoC_SelectChip(this, mychip->chip);
- } else if (this->curchip != mychip->chip) {
- DoC_SelectChip(this, mychip->chip);
- }
- this->curfloor = mychip->floor;
- this->curchip = mychip->chip;
-
- DoC_Command(this, NAND_CMD_ERASE1, 0);
- DoC_Address(this, ADDR_PAGE, ofs, 0, 0);
- DoC_Command(this, NAND_CMD_ERASE2, 0);
-
- DoC_Command(this, NAND_CMD_STATUS, CDSN_CTRL_WP);
-
- dummy = ReadDOC(docptr, CDSNSlowIO);
- DoC_Delay(this, 2);
-
- if (ReadDOC_(docptr, this->ioreg) & 1) {
- printf("Error erasing at 0x%lx\n", (long)ofs);
- /* There was an error */
- goto callback;
- }
- ofs += this->erasesize;
- len -= this->erasesize;
- }
-
- callback:
- return 0;
-}
-
-static inline int doccheck(unsigned long potential, unsigned long physadr)
-{
- unsigned long window=potential;
- unsigned char tmp, ChipID;
-#ifndef DOC_PASSIVE_PROBE
- unsigned char tmp2;
-#endif
-
- /* Routine copied from the Linux DOC driver */
-
-#ifdef CONFIG_SYS_DOCPROBE_55AA
- /* Check for 0x55 0xAA signature at beginning of window,
- this is no longer true once we remove the IPL (for Millennium */
- if (ReadDOC(window, Sig1) != 0x55 || ReadDOC(window, Sig2) != 0xaa)
- return 0;
-#endif /* CONFIG_SYS_DOCPROBE_55AA */
-
-#ifndef DOC_PASSIVE_PROBE
- /* It's not possible to cleanly detect the DiskOnChip - the
- * bootup procedure will put the device into reset mode, and
- * it's not possible to talk to it without actually writing
- * to the DOCControl register. So we store the current contents
- * of the DOCControl register's location, in case we later decide
- * that it's not a DiskOnChip, and want to put it back how we
- * found it.
- */
- tmp2 = ReadDOC(window, DOCControl);
-
- /* Reset the DiskOnChip ASIC */
- WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET,
- window, DOCControl);
- WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET,
- window, DOCControl);
-
- /* Enable the DiskOnChip ASIC */
- WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL,
- window, DOCControl);
- WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL,
- window, DOCControl);
-#endif /* !DOC_PASSIVE_PROBE */
-
- ChipID = ReadDOC(window, ChipID);
-
- switch (ChipID) {
- case DOC_ChipID_Doc2k:
- /* Check the TOGGLE bit in the ECC register */
- tmp = ReadDOC(window, 2k_ECCStatus) & DOC_TOGGLE_BIT;
- if ((ReadDOC(window, 2k_ECCStatus) & DOC_TOGGLE_BIT) != tmp)
- return ChipID;
- break;
-
- case DOC_ChipID_DocMil:
- /* Check the TOGGLE bit in the ECC register */
- tmp = ReadDOC(window, ECCConf) & DOC_TOGGLE_BIT;
- if ((ReadDOC(window, ECCConf) & DOC_TOGGLE_BIT) != tmp)
- return ChipID;
- break;
-
- default:
-#ifndef CONFIG_SYS_DOCPROBE_55AA
-/*
- * if the ID isn't the DoC2000 or DoCMillenium ID, so we can assume
- * the DOC is missing
- */
-# if 0
- printf("Possible DiskOnChip with unknown ChipID %2.2X found at 0x%lx\n",
- ChipID, physadr);
-# endif
-#endif
-#ifndef DOC_PASSIVE_PROBE
- /* Put back the contents of the DOCControl register, in case it's not
- * actually a DiskOnChip.
- */
- WriteDOC(tmp2, window, DOCControl);
-#endif
- return 0;
- }
-
- puts ("DiskOnChip failed TOGGLE test, dropping.\n");
-
-#ifndef DOC_PASSIVE_PROBE
- /* Put back the contents of the DOCControl register: it's not a DiskOnChip */
- WriteDOC(tmp2, window, DOCControl);
-#endif
- return 0;
-}
-
-void doc_probe(unsigned long physadr)
-{
- struct DiskOnChip *this = NULL;
- int i=0, ChipID;
-
- if ((ChipID = doccheck(physadr, physadr))) {
-
- for (i=0; i<CONFIG_SYS_MAX_DOC_DEVICE; i++) {
- if (doc_dev_desc[i].ChipID == DOC_ChipID_UNKNOWN) {
- this = doc_dev_desc + i;
- break;
- }
- }
-
- if (!this) {
- puts ("Cannot allocate memory for data structures.\n");
- return;
- }
-
- if (curr_device == -1)
- curr_device = i;
-
- memset((char *)this, 0, sizeof(struct DiskOnChip));
-
- this->virtadr = physadr;
- this->physadr = physadr;
- this->ChipID = ChipID;
-
- DoC2k_init(this);
- } else {
- puts ("No DiskOnChip found\n");
- }
-}
-#else
-void doc_probe(unsigned long physadr) {}
-#endif
}
if (strtab) {
- printf ("%sing %s @ 0x%08lx (%ld bytes)\n",
+ debug("%sing %s @ 0x%08lx (%ld bytes)\n",
(shdr->sh_type == SHT_NOBITS) ?
"Clear" : "Load",
&strtab[shdr->sh_name],
if (argc < 3) {
cmd_usage(cmdtp);
- return(1);
+ return 1;
}
dev = (int)simple_strtoul (argv[2], &ep, 16);
dev_desc = get_dev(argv[1],dev);
if (dev_desc == NULL) {
printf ("\n** Block device %s %d not supported\n", argv[1], dev);
- return(1);
+ return 1;
}
if (*ep) {
if (*ep != ':') {
puts ("\n** Invalid boot device, use `dev[:part]' **\n");
- return(1);
+ return 1;
}
part = (int)simple_strtoul(++ep, NULL, 16);
}
- if (argc == 4) {
- filename = argv[3];
- }
+ if (argc == 4)
+ filename = argv[3];
PRINTF("Using device %s %d:%d, directory: %s\n", argv[1], dev, part, filename);
if ((part_length = ext2fs_set_blk_dev(dev_desc, part)) == 0) {
printf ("** Bad partition - %s %d:%d **\n", argv[1], dev, part);
ext2fs_close();
- return(1);
+ return 1;
}
if (!ext2fs_mount(part_length)) {
printf ("** Bad ext2 partition or disk - %s %d:%d **\n", argv[1], dev, part);
ext2fs_close();
- return(1);
+ return 1;
}
if (ext2fs_ls (filename)) {
printf ("** Error ext2fs_ls() **\n");
ext2fs_close();
- return(1);
+ return 1;
};
ext2fs_close();
- return(0);
+ return 0;
}
U_BOOT_CMD(
switch (argc) {
case 3:
addr_str = getenv("loadaddr");
- if (addr_str != NULL) {
+ if (addr_str != NULL)
addr = simple_strtoul (addr_str, NULL, 16);
- } else {
+ else
addr = CONFIG_SYS_LOAD_ADDR;
- }
+
filename = getenv ("bootfile");
count = 0;
break;
default:
cmd_usage(cmdtp);
- return(1);
+ return 1;
}
if (!filename) {
- puts ("\n** No boot file defined **\n");
- return(1);
+ puts ("** No boot file defined **\n");
+ return 1;
}
dev = (int)simple_strtoul (argv[2], &ep, 16);
dev_desc = get_dev(argv[1],dev);
if (dev_desc==NULL) {
- printf ("\n** Block device %s %d not supported\n", argv[1], dev);
- return(1);
+ printf ("** Block device %s %d not supported\n", argv[1], dev);
+ return 1;
}
if (*ep) {
if (*ep != ':') {
- puts ("\n** Invalid boot device, use `dev[:part]' **\n");
- return(1);
+ puts ("** Invalid boot device, use `dev[:part]' **\n");
+ return 1;
}
part = (int)simple_strtoul(++ep, NULL, 16);
}
if (part != 0) {
if (get_partition_info (dev_desc, part, &info)) {
printf ("** Bad partition %d **\n", part);
- return(1);
+ return 1;
}
if (strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) {
- printf ("\n** Invalid partition type \"%.32s\""
+ printf ("** Invalid partition type \"%.32s\""
" (expect \"" BOOT_PART_TYPE "\")\n",
info.type);
- return(1);
+ return 1;
}
- PRINTF ("\nLoading from block device %s device %d, partition %d: "
- "Name: %.32s Type: %.32s File:%s\n",
- argv[1], dev, part, info.name, info.type, filename);
+ printf ("Loading file \"%s\" "
+ "from %s device %d:%d (%.32s)\n",
+ filename,
+ argv[1], dev, part, info.name);
} else {
- PRINTF ("\nLoading from block device %s device %d, File:%s\n",
- argv[1], dev, filename);
+ printf ("Loading file \"%s\" from %s device %d\n",
+ filename, argv[1], dev);
}
if ((part_length = ext2fs_set_blk_dev(dev_desc, part)) == 0) {
printf ("** Bad partition - %s %d:%d **\n", argv[1], dev, part);
ext2fs_close();
- return(1);
+ return 1;
}
if (!ext2fs_mount(part_length)) {
- printf ("** Bad ext2 partition or disk - %s %d:%d **\n", argv[1], dev, part);
+ printf ("** Bad ext2 partition or disk - %s %d:%d **\n",
+ argv[1], dev, part);
ext2fs_close();
- return(1);
+ return 1;
}
filelen = ext2fs_open(filename);
if (filelen < 0) {
printf("** File not found %s\n", filename);
ext2fs_close();
- return(1);
+ return 1;
}
if ((count < filelen) && (count != 0)) {
filelen = count;
}
if (ext2fs_read((char *)addr, filelen) != filelen) {
- printf("\n** Unable to read \"%s\" from %s %d:%d **\n", filename, argv[1], dev, part);
+ printf("** Unable to read \"%s\" from %s %d:%d **\n",
+ filename, argv[1], dev, part);
ext2fs_close();
- return(1);
+ return 1;
}
ext2fs_close();
/* Loading ok, update default load address */
load_addr = addr;
- printf ("\n%d bytes read\n", filelen);
+ printf ("%d bytes read\n", filelen);
sprintf(buf, "%X", filelen);
setenv("filesize", buf);
- return(filelen);
+ return 0;
}
U_BOOT_CMD(
ulong bank;
int i, n, sect_first, sect_last;
#endif /* CONFIG_SYS_NO_FLASH */
+#if !defined(CONFIG_SYS_NO_FLASH) || defined(CONFIG_HAS_DATAFLASH)
ulong addr_first, addr_last;
- int p;
+#endif
#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_CMD_MTDPARTS)
struct mtd_device *dev;
struct part_info *part;
u8 dev_type, dev_num, pnum;
#endif
- int rcode = 0;
#ifdef CONFIG_HAS_DATAFLASH
int status;
#endif
+ int p;
+ int rcode = 0;
if (argc < 3) {
cmd_usage(cmdtp);
return do_i2c_crc(cmdtp, flag, argc, argv);
if (!strncmp(argv[0], "pr", 2))
return do_i2c_probe(cmdtp, flag, argc, argv);
- if (!strncmp(argv[0], "re", 2))
+ if (!strncmp(argv[0], "re", 2)) {
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
return 0;
+ }
if (!strncmp(argv[0], "lo", 2))
return do_i2c_loop(cmdtp, flag, argc, argv);
#if defined(CONFIG_CMD_SDRAM)
if (!strncmp(argv[0], "sd", 2))
return do_sdram(cmdtp, flag, argc, argv);
#endif
- else
- cmd_usage(cmdtp);
+ cmd_usage(cmdtp);
return 0;
}
#include <cramfs/cramfs_fs.h>
#if defined(CONFIG_CMD_NAND)
-#ifdef CONFIG_NAND_LEGACY
-#include <linux/mtd/nand_legacy.h>
-#else /* !CONFIG_NAND_LEGACY */
#include <linux/mtd/nand.h>
#include <nand.h>
-#endif /* !CONFIG_NAND_LEGACY */
#endif
#if defined(CONFIG_CMD_ONENAND)
} else if (type == MTD_DEV_TYPE_NAND) {
#if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
if (num < CONFIG_SYS_MAX_NAND_DEVICE) {
-#ifndef CONFIG_NAND_LEGACY
*size = nand_info[num].size;
-#else
- extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
- *size = nand_dev_desc[num].totlen;
-#endif
return 0;
}
static inline u32 get_part_sector_size_nand(struct mtdids *id)
{
#if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
-#if defined(CONFIG_NAND_LEGACY)
- extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
-
- return nand_dev_desc[id->num].erasesize;
-#else
nand_info_t *nand;
nand = &nand_info[id->num];
return nand->erasesize;
-#endif
#else
BUG();
return 0;
#include <common.h>
#include <command.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <post.h>
#include <logbuff.h>
int drv_logbuff_init (void)
{
- device_t logdev;
+ struct stdio_dev logdev;
int rc;
/* Device initialization */
logdev.putc = logbuff_putc; /* 'putc' function */
logdev.puts = logbuff_puts; /* 'puts' function */
- rc = device_register (&logdev);
+ rc = stdio_register (&logdev);
return (rc == 0) ? 1 : rc;
}
#include <mmc.h>
#ifndef CONFIG_GENERIC_MMC
-int curr_device = -1;
+static int curr_device = -1;
int do_mmc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#include <linux/mtd/mtd.h>
#if defined(CONFIG_CMD_NAND)
-#ifdef CONFIG_NAND_LEGACY
-#include <linux/mtd/nand_legacy.h>
-#else /* !CONFIG_NAND_LEGACY */
#include <linux/mtd/nand.h>
#include <nand.h>
-#endif /* !CONFIG_NAND_LEGACY */
#endif
#if defined(CONFIG_CMD_ONENAND)
}
}
-#ifdef CONFIG_NAND_LEGACY
- jffs2_free_cache(part);
-#endif
list_del(&part->link);
free(part);
dev->num_parts--;
list_for_each_safe(entry, n, head) {
part_tmp = list_entry(entry, struct part_info, link);
-#ifdef CONFIG_NAND_LEGACY
- jffs2_free_cache(part_tmp);
-#endif
list_del(entry);
free(part_tmp);
}
#include <common.h>
-#ifndef CONFIG_NAND_LEGACY
/*
*
* New NAND support
"[partition] | [[[loadAddr] dev] offset]"
);
#endif
-
-#else /* CONFIG_NAND_LEGACY */
-/*
- *
- * Legacy NAND support - to be phased out
- *
- */
-#include <command.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <watchdog.h>
-
-#ifdef CONFIG_show_boot_progress
-# include <status_led.h>
-# define show_boot_progress(arg) show_boot_progress(arg)
-#else
-# define show_boot_progress(arg)
-#endif
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-#if 0
-#include <linux/mtd/nand_ids.h>
-#include <jffs2/jffs2.h>
-#endif
-
-#ifdef CONFIG_OMAP1510
-void archflashwp(void *archdata, int wp);
-#endif
-
-#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
-
-#undef NAND_DEBUG
-#undef PSYCHO_DEBUG
-
-/* ****************** WARNING *********************
- * When ALLOW_ERASE_BAD_DEBUG is non-zero the erase command will
- * erase (or at least attempt to erase) blocks that are marked
- * bad. This can be very handy if you are _sure_ that the block
- * is OK, say because you marked a good block bad to test bad
- * block handling and you are done testing, or if you have
- * accidentally marked blocks bad.
- *
- * Erasing factory marked bad blocks is a _bad_ idea. If the
- * erase succeeds there is no reliable way to find them again,
- * and attempting to program or erase bad blocks can affect
- * the data in _other_ (good) blocks.
- */
-#define ALLOW_ERASE_BAD_DEBUG 0
-
-#define CONFIG_MTD_NAND_ECC /* enable ECC */
-#define CONFIG_MTD_NAND_ECC_JFFS2
-
-/* bits for nand_legacy_rw() `cmd'; or together as needed */
-#define NANDRW_READ 0x01
-#define NANDRW_WRITE 0x00
-#define NANDRW_JFFS2 0x02
-#define NANDRW_JFFS2_SKIP 0x04
-
-/*
- * Imports from nand_legacy.c
- */
-extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
-extern int curr_device;
-extern int nand_legacy_erase(struct nand_chip *nand, size_t ofs,
- size_t len, int clean);
-extern int nand_legacy_rw(struct nand_chip *nand, int cmd, size_t start,
- size_t len, size_t *retlen, u_char *buf);
-extern void nand_print(struct nand_chip *nand);
-extern void nand_print_bad(struct nand_chip *nand);
-extern int nand_read_oob(struct nand_chip *nand, size_t ofs,
- size_t len, size_t *retlen, u_char *buf);
-extern int nand_write_oob(struct nand_chip *nand, size_t ofs,
- size_t len, size_t *retlen, const u_char *buf);
-
-
-int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- int rcode = 0;
-
- switch (argc) {
- case 0:
- case 1:
- cmd_usage(cmdtp);
- return 1;
- case 2:
- if (strcmp (argv[1], "info") == 0) {
- int i;
-
- putc ('\n');
-
- for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; ++i) {
- if (nand_dev_desc[i].ChipID ==
- NAND_ChipID_UNKNOWN)
- continue; /* list only known devices */
- printf ("Device %d: ", i);
- nand_print (&nand_dev_desc[i]);
- }
- return 0;
-
- } else if (strcmp (argv[1], "device") == 0) {
- if ((curr_device < 0)
- || (curr_device >= CONFIG_SYS_MAX_NAND_DEVICE)) {
- puts ("\nno devices available\n");
- return 1;
- }
- printf ("\nDevice %d: ", curr_device);
- nand_print (&nand_dev_desc[curr_device]);
- return 0;
-
- } else if (strcmp (argv[1], "bad") == 0) {
- if ((curr_device < 0)
- || (curr_device >= CONFIG_SYS_MAX_NAND_DEVICE)) {
- puts ("\nno devices available\n");
- return 1;
- }
- printf ("\nDevice %d bad blocks:\n", curr_device);
- nand_print_bad (&nand_dev_desc[curr_device]);
- return 0;
-
- }
- cmd_usage(cmdtp);
- return 1;
- case 3:
- if (strcmp (argv[1], "device") == 0) {
- int dev = (int) simple_strtoul (argv[2], NULL, 10);
-
- printf ("\nDevice %d: ", dev);
- if (dev >= CONFIG_SYS_MAX_NAND_DEVICE) {
- puts ("unknown device\n");
- return 1;
- }
- nand_print (&nand_dev_desc[dev]);
- /*nand_print (dev); */
-
- if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) {
- return 1;
- }
-
- curr_device = dev;
-
- puts ("... is now current device\n");
-
- return 0;
- } else if (strcmp (argv[1], "erase") == 0
- && strcmp (argv[2], "clean") == 0) {
- struct nand_chip *nand = &nand_dev_desc[curr_device];
- ulong off = 0;
- ulong size = nand->totlen;
- int ret;
-
- printf ("\nNAND erase: device %d offset %ld, size %ld ... ", curr_device, off, size);
-
- ret = nand_legacy_erase (nand, off, size, 1);
-
- printf ("%s\n", ret ? "ERROR" : "OK");
-
- return ret;
- }
-
- cmd_usage(cmdtp);
- return 1;
- default:
- /* at least 4 args */
-
- if (strncmp (argv[1], "read", 4) == 0 ||
- strncmp (argv[1], "write", 5) == 0) {
- ulong addr = simple_strtoul (argv[2], NULL, 16);
- off_t off = simple_strtoul (argv[3], NULL, 16);
- size_t size = simple_strtoul (argv[4], NULL, 16);
- int cmd = (strncmp (argv[1], "read", 4) == 0) ?
- NANDRW_READ : NANDRW_WRITE;
- size_t total;
- int ret;
- char *cmdtail = strchr (argv[1], '.');
-
- if (cmdtail && !strncmp (cmdtail, ".oob", 2)) {
- /* read out-of-band data */
- if (cmd & NANDRW_READ) {
- ret = nand_read_oob (nand_dev_desc + curr_device,
- off, size, &total,
- (u_char *) addr);
- } else {
- ret = nand_write_oob (nand_dev_desc + curr_device,
- off, size, &total,
- (u_char *) addr);
- }
- return ret;
- } else if (cmdtail && !strncmp (cmdtail, ".jffs2s", 7)) {
- cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */
- if (cmd & NANDRW_READ)
- cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */
- } else if (cmdtail && !strncmp (cmdtail, ".jffs2", 2))
- cmd |= NANDRW_JFFS2; /* skip bad blocks */
-#ifdef SXNI855T
- /* need ".e" same as ".j" for compatibility with older units */
- else if (cmdtail && !strcmp (cmdtail, ".e"))
- cmd |= NANDRW_JFFS2; /* skip bad blocks */
-#endif
-#ifdef CONFIG_SYS_NAND_SKIP_BAD_DOT_I
- /* need ".i" same as ".jffs2s" for compatibility with older units (esd) */
- /* ".i" for image -> read skips bad block (no 0xff) */
- else if (cmdtail && !strcmp (cmdtail, ".i")) {
- cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */
- if (cmd & NANDRW_READ)
- cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */
- }
-#endif /* CONFIG_SYS_NAND_SKIP_BAD_DOT_I */
- else if (cmdtail) {
- cmd_usage(cmdtp);
- return 1;
- }
-
- printf ("\nNAND %s: device %d offset %ld, size %lu ...\n",
- (cmd & NANDRW_READ) ? "read" : "write",
- curr_device, off, (ulong)size);
-
- ret = nand_legacy_rw (nand_dev_desc + curr_device,
- cmd, off, size,
- &total, (u_char *) addr);
-
- printf (" %d bytes %s: %s\n", total,
- (cmd & NANDRW_READ) ? "read" : "written",
- ret ? "ERROR" : "OK");
-
- return ret;
- } else if (strcmp (argv[1], "erase") == 0 &&
- (argc == 4 || strcmp ("clean", argv[2]) == 0)) {
- int clean = argc == 5;
- ulong off =
- simple_strtoul (argv[2 + clean], NULL, 16);
- ulong size =
- simple_strtoul (argv[3 + clean], NULL, 16);
- int ret;
-
- printf ("\nNAND erase: device %d offset %ld, size %ld ...\n",
- curr_device, off, size);
-
- ret = nand_legacy_erase (nand_dev_desc + curr_device,
- off, size, clean);
-
- printf ("%s\n", ret ? "ERROR" : "OK");
-
- return ret;
- } else {
- cmd_usage(cmdtp);
- rcode = 1;
- }
-
- return rcode;
- }
-}
-
-U_BOOT_CMD(
- nand, 5, 1, do_nand,
- "legacy NAND sub-system",
- "info - show available NAND devices\n"
- "nand device [dev] - show or set current device\n"
- "nand read[.jffs2[s]] addr off size\n"
- "nand write[.jffs2] addr off size - read/write `size' bytes starting\n"
- " at offset `off' to/from memory address `addr'\n"
- "nand erase [clean] [off size] - erase `size' bytes from\n"
- " offset `off' (entire device if not specified)\n"
- "nand bad - show bad blocks\n"
- "nand read.oob addr off size - read out-of-band data\n"
- "nand write.oob addr off size - read out-of-band data"
-);
-
-int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- char *boot_device = NULL;
- char *ep;
- int dev;
- ulong cnt;
- ulong addr;
- ulong offset = 0;
- image_header_t *hdr;
- int rcode = 0;
-#if defined(CONFIG_FIT)
- const void *fit_hdr = NULL;
-#endif
-
- show_boot_progress (52);
- switch (argc) {
- case 1:
- addr = CONFIG_SYS_LOAD_ADDR;
- boot_device = getenv ("bootdevice");
- break;
- case 2:
- addr = simple_strtoul(argv[1], NULL, 16);
- boot_device = getenv ("bootdevice");
- break;
- case 3:
- addr = simple_strtoul(argv[1], NULL, 16);
- boot_device = argv[2];
- break;
- case 4:
- addr = simple_strtoul(argv[1], NULL, 16);
- boot_device = argv[2];
- offset = simple_strtoul(argv[3], NULL, 16);
- break;
- default:
- cmd_usage(cmdtp);
- show_boot_progress (-53);
- return 1;
- }
-
- show_boot_progress (53);
- if (!boot_device) {
- puts ("\n** No boot device **\n");
- show_boot_progress (-54);
- return 1;
- }
- show_boot_progress (54);
-
- dev = simple_strtoul(boot_device, &ep, 16);
-
- if ((dev >= CONFIG_SYS_MAX_NAND_DEVICE) ||
- (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) {
- printf ("\n** Device %d not available\n", dev);
- show_boot_progress (-55);
- return 1;
- }
- show_boot_progress (55);
-
- printf ("\nLoading from device %d: %s at 0x%lx (offset 0x%lx)\n",
- dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR,
- offset);
-
- if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset,
- SECTORSIZE, NULL, (u_char *)addr)) {
- printf ("** Read error on %d\n", dev);
- show_boot_progress (-56);
- return 1;
- }
- show_boot_progress (56);
-
- switch (genimg_get_format ((void *)addr)) {
- case IMAGE_FORMAT_LEGACY:
- hdr = (image_header_t *)addr;
- image_print_contents (hdr);
-
- cnt = image_get_image_size (hdr);
- cnt -= SECTORSIZE;
- break;
-#if defined(CONFIG_FIT)
- case IMAGE_FORMAT_FIT:
- fit_hdr = (const void *)addr;
- puts ("Fit image detected...\n");
-
- cnt = fit_get_size (fit_hdr);
- break;
-#endif
- default:
- show_boot_progress (-57);
- puts ("** Unknown image type\n");
- return 1;
- }
- show_boot_progress (57);
-
- if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ,
- offset + SECTORSIZE, cnt, NULL,
- (u_char *)(addr+SECTORSIZE))) {
- printf ("** Read error on %d\n", dev);
- show_boot_progress (-58);
- return 1;
- }
- show_boot_progress (58);
-
-#if defined(CONFIG_FIT)
- /* This cannot be done earlier, we need complete FIT image in RAM first */
- if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) {
- if (!fit_check_format (fit_hdr)) {
- show_boot_progress (-150);
- puts ("** Bad FIT image format\n");
- return 1;
- }
- show_boot_progress (151);
- fit_print_contents (fit_hdr);
- }
-#endif
-
- /* Loading ok, update default load address */
-
- load_addr = addr;
-
- /* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
- char *local_args[2];
- extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
-
- local_args[0] = argv[0];
- local_args[1] = NULL;
-
- printf ("Automatic boot of image at addr 0x%08lx ...\n", addr);
-
- do_bootm (cmdtp, 0, 1, local_args);
- rcode = 1;
- }
- return rcode;
-}
-
-U_BOOT_CMD(
- nboot, 4, 1, do_nandboot,
- "boot from NAND device",
- "loadAddr dev"
-);
-
-#endif
-
-#endif /* CONFIG_NAND_LEGACY */
"[NTP server IP]\n"
);
#endif
+
+#if defined(CONFIG_CMD_DNS)
+int do_dns(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ if (argc == 1) {
+ cmd_usage(cmdtp);
+ return -1;
+ }
+
+ /*
+ * We should check for a valid hostname:
+ * - Each label must be between 1 and 63 characters long
+ * - the entire hostname has a maximum of 255 characters
+ * - only the ASCII letters 'a' through 'z' (case-insensitive),
+ * the digits '0' through '9', and the hyphen
+ * - cannot begin or end with a hyphen
+ * - no other symbols, punctuation characters, or blank spaces are
+ * permitted
+ * but hey - this is a minimalist implmentation, so only check length
+ * and let the name server deal with things.
+ */
+ if (strlen(argv[1]) >= 255) {
+ printf("dns error: hostname too long\n");
+ return 1;
+ }
+
+ NetDNSResolve = argv[1];
+
+ if (argc == 3)
+ NetDNSenvvar = argv[2];
+ else
+ NetDNSenvvar = NULL;
+
+ if (NetLoop(DNS) < 0) {
+ printf("dns lookup of %s failed, check setup\n", argv[1]);
+ return 1;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ dns, 3, 1, do_dns,
+ "lookup the IP of a hostname",
+ "hostname [envvar]"
+);
+
+#endif /* CONFIG_CMD_DNS */
#include <part.h>
#include <sata.h>
-int curr_device = -1;
+int sata_curr_device = -1;
block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
int __sata_initialize(void)
if ((sata_dev_desc[i].lba > 0) && (sata_dev_desc[i].blksz > 0))
init_part(&sata_dev_desc[i]);
}
- curr_device = 0;
+ sata_curr_device = 0;
return rc;
}
int sata_initialize(void) __attribute__((weak,alias("__sata_initialize")));
return sata_initialize();
/* If the user has not yet run `sata init`, do it now */
- if (curr_device == -1)
+ if (sata_curr_device == -1)
if (sata_initialize())
return 1;
}
return 0;
} else if (strncmp(argv[1],"dev", 3) == 0) {
- if ((curr_device < 0) || (curr_device >= CONFIG_SYS_SATA_MAX_DEVICE)) {
+ if ((sata_curr_device < 0) || (sata_curr_device >= CONFIG_SYS_SATA_MAX_DEVICE)) {
puts("\nno SATA devices available\n");
return 1;
}
- printf("\nSATA device %d: ", curr_device);
- dev_print(&sata_dev_desc[curr_device]);
+ printf("\nSATA device %d: ", sata_curr_device);
+ dev_print(&sata_dev_desc[sata_curr_device]);
return 0;
} else if (strncmp(argv[1],"part",4) == 0) {
int dev, ok;
if (sata_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
return 1;
- curr_device = dev;
+ sata_curr_device = dev;
puts("... is now current device\n");
lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
printf("\nSATA read: device %d block # %ld, count %ld ... ",
- curr_device, blk, cnt);
+ sata_curr_device, blk, cnt);
- n = sata_read(curr_device, blk, cnt, (u32 *)addr);
+ n = sata_read(sata_curr_device, blk, cnt, (u32 *)addr);
/* flush cache after read */
- flush_cache(addr, cnt * sata_dev_desc[curr_device].blksz);
+ flush_cache(addr, cnt * sata_dev_desc[sata_curr_device].blksz);
printf("%ld blocks read: %s\n",
n, (n==cnt) ? "OK" : "ERROR");
lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
printf("\nSATA write: device %d block # %ld, count %ld ... ",
- curr_device, blk, cnt);
+ sata_curr_device, blk, cnt);
- n = sata_write(curr_device, blk, cnt, (u32 *)addr);
+ n = sata_write(sata_curr_device, blk, cnt, (u32 *)addr);
printf("%ld blocks written: %s\n",
n, (n == cnt) ? "OK" : "ERROR");
*/
#include <common.h>
#include <command.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <serial.h>
int do_terminal(cmd_tbl_t * cmd, int flag, int argc, char *argv[])
{
int last_tilde = 0;
- device_t *dev = NULL;
+ struct stdio_dev *dev = NULL;
if (argc < 1)
return -1;
/* Scan for selected output/input device */
- dev = device_get_by_name(argv[1]);
+ dev = stdio_get_by_name(argv[1]);
if (!dev)
return -1;
--- /dev/null
+/*
+ * (C) Copyright 2009 Reinhard Arlt, reinhard.arlt@esd-electronics.com
+ *
+ * base on universe.h by
+ *
+ * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#include <tsi148.h>
+
+#define PCI_VENDOR PCI_VENDOR_ID_TUNDRA
+#define PCI_DEVICE PCI_DEVICE_ID_TUNDRA_TSI148
+
+typedef struct _TSI148_DEV TSI148_DEV;
+
+struct _TSI148_DEV {
+ int bus;
+ pci_dev_t busdevfn;
+ TSI148 *uregs;
+ unsigned int pci_bs;
+};
+
+static TSI148_DEV *dev;
+
+/*
+ * Most of the TSI148 register are BIGENDIAN
+ * This is the reason for the __raw_writel(htonl(x), x) usage!
+ */
+
+int tsi148_init(void)
+{
+ int j, result, lastError = 0;
+ pci_dev_t busdevfn;
+ unsigned int val;
+
+ busdevfn = pci_find_device(PCI_VENDOR, PCI_DEVICE, 0);
+ if (busdevfn == -1) {
+ puts("Tsi148: No Tundra Tsi148 found!\n");
+ return -1;
+ }
+
+ /* Lets turn Latency off */
+ pci_write_config_dword(busdevfn, 0x0c, 0);
+
+ dev = malloc(sizeof(*dev));
+ if (NULL == dev) {
+ puts("Tsi148: No memory!\n");
+ result = -1;
+ goto break_20;
+ }
+
+ memset(dev, 0, sizeof(*dev));
+ dev->busdevfn = busdevfn;
+
+ pci_read_config_dword(busdevfn, PCI_BASE_ADDRESS_0, &val);
+ val &= ~0xf;
+ dev->uregs = (TSI148 *)val;
+
+ debug("Tsi148: Base : %p\n", dev->uregs);
+
+ /* check mapping */
+ debug("Tsi148: Read via mapping, PCI_ID = %08X\n",
+ readl(&dev->uregs->pci_id));
+ if (((PCI_DEVICE << 16) | PCI_VENDOR) != readl(&dev->uregs->pci_id)) {
+ printf("Tsi148: Cannot read PCI-ID via Mapping: %08x\n",
+ readl(&dev->uregs->pci_id));
+ result = -1;
+ goto break_30;
+ }
+
+ debug("Tsi148: PCI_BS = %08X\n", readl(&dev->uregs->pci_mbarl));
+
+ dev->pci_bs = readl(&dev->uregs->pci_mbarl);
+
+ /* turn off windows */
+ for (j = 0; j < 8; j++) {
+ __raw_writel(htonl(0x00000000), &dev->uregs->outbound[j].otat);
+ __raw_writel(htonl(0x00000000), &dev->uregs->inbound[j].itat);
+ }
+
+ /* Tsi148 VME timeout etc */
+ __raw_writel(htonl(0x00000084), &dev->uregs->vctrl);
+
+#ifdef DEBUG
+ if ((__raw_readl(&dev->uregs->vstat) & 0x00000100) != 0)
+ printf("Tsi148: System Controller!\n");
+ else
+ printf("Tsi148: Not System Controller!\n");
+#endif
+
+ /*
+ * Lets turn off interrupts
+ */
+ /* Disable interrupts in Tsi148 first */
+ __raw_writel(htonl(0x00000000), &dev->uregs->inten);
+ /* Disable interrupt out */
+ __raw_writel(htonl(0x00000000), &dev->uregs->inteo);
+ eieio();
+ /* Reset all IRQ's */
+ __raw_writel(htonl(0x03ff3f00), &dev->uregs->intc);
+ /* Map all ints to 0 */
+ __raw_writel(htonl(0x00000000), &dev->uregs->intm1);
+ __raw_writel(htonl(0x00000000), &dev->uregs->intm2);
+ eieio();
+
+ val = __raw_readl(&dev->uregs->vstat);
+ val &= ~(0x00004000);
+ __raw_writel(val, &dev->uregs->vstat);
+ eieio();
+
+ debug("Tsi148: register struct size %08x\n", sizeof(TSI148));
+
+ return 0;
+
+ break_30:
+ free(dev);
+ dev = NULL;
+ break_20:
+ lastError = result;
+
+ return result;
+}
+
+/*
+ * Create pci slave window (access: pci -> vme)
+ */
+int tsi148_pci_slave_window(unsigned int pciAddr, unsigned int vmeAddr,
+ int size, int vam, int vdw)
+{
+ int result, i;
+ unsigned int ctl = 0;
+
+ if (NULL == dev) {
+ result = -1;
+ goto exit_10;
+ }
+
+ for (i = 0; i < 8; i++) {
+ if (0x00000000 == readl(&dev->uregs->outbound[i].otat))
+ break;
+ }
+
+ if (i > 7) {
+ printf("Tsi148: No Image available\n");
+ result = -1;
+ goto exit_10;
+ }
+
+ debug("Tsi148: Using image %d\n", i);
+
+ printf("Tsi148: Pci addr %08x\n", pciAddr);
+
+ __raw_writel(htonl(pciAddr), &dev->uregs->outbound[i].otsal);
+ __raw_writel(0x00000000, &dev->uregs->outbound[i].otsau);
+ __raw_writel(htonl(pciAddr + size), &dev->uregs->outbound[i].oteal);
+ __raw_writel(0x00000000, &dev->uregs->outbound[i].oteau);
+ __raw_writel(htonl(vmeAddr - pciAddr), &dev->uregs->outbound[i].otofl);
+ __raw_writel(0x00000000, &dev->uregs->outbound[i].otofu);
+
+ switch (vam & VME_AM_Axx) {
+ case VME_AM_A16:
+ ctl = 0x00000000;
+ break;
+ case VME_AM_A24:
+ ctl = 0x00000001;
+ break;
+ case VME_AM_A32:
+ ctl = 0x00000002;
+ break;
+ }
+
+ switch (vam & VME_AM_Mxx) {
+ case VME_AM_DATA:
+ ctl |= 0x00000000;
+ break;
+ case VME_AM_PROG:
+ ctl |= 0x00000010;
+ break;
+ }
+
+ if (vam & VME_AM_SUP)
+ ctl |= 0x00000020;
+
+ switch (vdw & VME_FLAG_Dxx) {
+ case VME_FLAG_D16:
+ ctl |= 0x00000000;
+ break;
+ case VME_FLAG_D32:
+ ctl |= 0x00000040;
+ break;
+ }
+
+ ctl |= 0x80040000; /* enable, no prefetch */
+
+ __raw_writel(htonl(ctl), &dev->uregs->outbound[i].otat);
+
+ debug("Tsi148: window-addr =%p\n",
+ &dev->uregs->outbound[i].otsau);
+ debug("Tsi148: pci slave window[%d] attr =%08x\n",
+ i, ntohl(__raw_readl(&dev->uregs->outbound[i].otat)));
+ debug("Tsi148: pci slave window[%d] start =%08x\n",
+ i, ntohl(__raw_readl(&dev->uregs->outbound[i].otsal)));
+ debug("Tsi148: pci slave window[%d] end =%08x\n",
+ i, ntohl(__raw_readl(&dev->uregs->outbound[i].oteal)));
+ debug("Tsi148: pci slave window[%d] offset=%08x\n",
+ i, ntohl(__raw_readl(&dev->uregs->outbound[i].otofl)));
+
+ return 0;
+
+ exit_10:
+ return -result;
+}
+
+unsigned int tsi148_eval_vam(int vam)
+{
+ unsigned int ctl = 0;
+
+ switch (vam & VME_AM_Axx) {
+ case VME_AM_A16:
+ ctl = 0x00000000;
+ break;
+ case VME_AM_A24:
+ ctl = 0x00000010;
+ break;
+ case VME_AM_A32:
+ ctl = 0x00000020;
+ break;
+ }
+ switch (vam & VME_AM_Mxx) {
+ case VME_AM_DATA:
+ ctl |= 0x00000001;
+ break;
+ case VME_AM_PROG:
+ ctl |= 0x00000002;
+ break;
+ case (VME_AM_PROG | VME_AM_DATA):
+ ctl |= 0x00000003;
+ break;
+ }
+
+ if (vam & VME_AM_SUP)
+ ctl |= 0x00000008;
+ if (vam & VME_AM_USR)
+ ctl |= 0x00000004;
+
+ return ctl;
+}
+
+/*
+ * Create vme slave window (access: vme -> pci)
+ */
+int tsi148_vme_slave_window(unsigned int vmeAddr, unsigned int pciAddr,
+ int size, int vam)
+{
+ int result, i;
+ unsigned int ctl = 0;
+
+ if (NULL == dev) {
+ result = -1;
+ goto exit_10;
+ }
+
+ for (i = 0; i < 8; i++) {
+ if (0x00000000 == readl(&dev->uregs->inbound[i].itat))
+ break;
+ }
+
+ if (i > 7) {
+ printf("Tsi148: No Image available\n");
+ result = -1;
+ goto exit_10;
+ }
+
+ debug("Tsi148: Using image %d\n", i);
+
+ __raw_writel(htonl(vmeAddr), &dev->uregs->inbound[i].itsal);
+ __raw_writel(0x00000000, &dev->uregs->inbound[i].itsau);
+ __raw_writel(htonl(vmeAddr + size), &dev->uregs->inbound[i].iteal);
+ __raw_writel(0x00000000, &dev->uregs->inbound[i].iteau);
+ __raw_writel(htonl(pciAddr - vmeAddr), &dev->uregs->inbound[i].itofl);
+ if (vmeAddr > pciAddr)
+ __raw_writel(0xffffffff, &dev->uregs->inbound[i].itofu);
+ else
+ __raw_writel(0x00000000, &dev->uregs->inbound[i].itofu);
+
+ ctl = tsi148_eval_vam(vam);
+ ctl |= 0x80000000; /* enable */
+ __raw_writel(htonl(ctl), &dev->uregs->inbound[i].itat);
+
+ debug("Tsi148: window-addr =%p\n",
+ &dev->uregs->inbound[i].itsau);
+ debug("Tsi148: vme slave window[%d] attr =%08x\n",
+ i, ntohl(__raw_readl(&dev->uregs->inbound[i].itat)));
+ debug("Tsi148: vme slave window[%d] start =%08x\n",
+ i, ntohl(__raw_readl(&dev->uregs->inbound[i].itsal)));
+ debug("Tsi148: vme slave window[%d] end =%08x\n",
+ i, ntohl(__raw_readl(&dev->uregs->inbound[i].iteal)));
+ debug("Tsi148: vme slave window[%d] offset=%08x\n",
+ i, ntohl(__raw_readl(&dev->uregs->inbound[i].itofl)));
+
+ return 0;
+
+ exit_10:
+ return -result;
+}
+
+/*
+ * Create vme slave window (access: vme -> gcsr)
+ */
+int tsi148_vme_gcsr_window(unsigned int vmeAddr, int vam)
+{
+ int result;
+ unsigned int ctl;
+
+ result = 0;
+
+ if (NULL == dev) {
+ result = 1;
+ } else {
+ __raw_writel(htonl(vmeAddr), &dev->uregs->gbal);
+ __raw_writel(0x00000000, &dev->uregs->gbau);
+
+ ctl = tsi148_eval_vam(vam);
+ ctl |= 0x00000080; /* enable */
+ __raw_writel(htonl(ctl), &dev->uregs->gcsrat);
+ }
+
+ return result;
+}
+
+/*
+ * Create vme slave window (access: vme -> crcsr)
+ */
+int tsi148_vme_crcsr_window(unsigned int vmeAddr)
+{
+ int result;
+ unsigned int ctl;
+
+ result = 0;
+
+ if (NULL == dev) {
+ result = 1;
+ } else {
+ __raw_writel(htonl(vmeAddr), &dev->uregs->crol);
+ __raw_writel(0x00000000, &dev->uregs->crou);
+
+ ctl = 0x00000080; /* enable */
+ __raw_writel(htonl(ctl), &dev->uregs->crat);
+ }
+
+ return result;
+}
+
+/*
+ * Create vme slave window (access: vme -> crg)
+ */
+int tsi148_vme_crg_window(unsigned int vmeAddr, int vam)
+{
+ int result;
+ unsigned int ctl;
+
+ result = 0;
+
+ if (NULL == dev) {
+ result = 1;
+ } else {
+ __raw_writel(htonl(vmeAddr), &dev->uregs->cbal);
+ __raw_writel(0x00000000, &dev->uregs->cbau);
+
+ ctl = tsi148_eval_vam(vam);
+ ctl |= 0x00000080; /* enable */
+ __raw_writel(htonl(ctl), &dev->uregs->crgat);
+ }
+
+ return result;
+}
+
+/*
+ * Tundra Tsi148 configuration
+ */
+int do_tsi148(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ulong addr1 = 0, addr2 = 0, size = 0, vam = 0, vdw = 0;
+ char cmd = 'x';
+
+ /* get parameter */
+ if (argc > 1)
+ cmd = argv[1][0];
+ if (argc > 2)
+ addr1 = simple_strtoul(argv[2], NULL, 16);
+ if (argc > 3)
+ addr2 = simple_strtoul(argv[3], NULL, 16);
+ if (argc > 4)
+ size = simple_strtoul(argv[4], NULL, 16);
+ if (argc > 5)
+ vam = simple_strtoul(argv[5], NULL, 16);
+ if (argc > 6)
+ vdw = simple_strtoul(argv[7], NULL, 16);
+
+ switch (cmd) {
+ case 'c':
+ if (strcmp(argv[1], "crg") == 0) {
+ vam = addr2;
+ printf("Tsi148: Configuring VME CRG Window "
+ "(VME->CRG):\n");
+ printf(" vme=%08lx vam=%02lx\n", addr1, vam);
+ tsi148_vme_crg_window(addr1, vam);
+ } else {
+ printf("Tsi148: Configuring VME CR/CSR Window "
+ "(VME->CR/CSR):\n");
+ printf(" pci=%08lx\n", addr1);
+ tsi148_vme_crcsr_window(addr1);
+ }
+ break;
+ case 'i': /* init */
+ tsi148_init();
+ break;
+ case 'g':
+ vam = addr2;
+ printf("Tsi148: Configuring VME GCSR Window (VME->GCSR):\n");
+ printf(" vme=%08lx vam=%02lx\n", addr1, vam);
+ tsi148_vme_gcsr_window(addr1, vam);
+ break;
+ case 'v': /* vme */
+ printf("Tsi148: Configuring VME Slave Window (VME->PCI):\n");
+ printf(" vme=%08lx pci=%08lx size=%08lx vam=%02lx\n",
+ addr1, addr2, size, vam);
+ tsi148_vme_slave_window(addr1, addr2, size, vam);
+ break;
+ case 'p': /* pci */
+ printf("Tsi148: Configuring PCI Slave Window (PCI->VME):\n");
+ printf(" pci=%08lx vme=%08lx size=%08lx vam=%02lx vdw=%02lx\n",
+ addr1, addr2, size, vam, vdw);
+ tsi148_pci_slave_window(addr1, addr2, size, vam, vdw);
+ break;
+ default:
+ printf("Tsi148: Command %s not supported!\n", argv[1]);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ tsi148, 8, 1, do_tsi148,
+ "initialize and configure Turndra Tsi148\n",
+ "init\n"
+ " - initialize tsi148\n"
+ "tsi148 vme [vme_addr] [pci_addr] [size] [vam]\n"
+ " - create vme slave window (access: vme->pci)\n"
+ "tsi148 pci [pci_addr] [vme_addr] [size] [vam] [vdw]\n"
+ " - create pci slave window (access: pci->vme)\n"
+ "tsi148 crg [vme_addr] [vam]\n"
+ " - create vme slave window: (access vme->CRG\n"
+ "tsi148 crcsr [pci_addr]\n"
+ " - create vme slave window: (access vme->CR/CSR\n"
+ "tsi148 gcsr [vme_addr] [vam]\n"
+ " - create vme slave window: (access vme->GCSR\n"
+ " [vam] = VMEbus Address-Modifier: 01 -> A16 Address Space\n"
+ " 02 -> A24 Address Space\n"
+ " 03 -> A32 Address Space\n"
+ " 04 -> Usr AM Code\n"
+ " 08 -> Supervisor AM Code\n"
+ " 10 -> Data AM Code\n"
+ " 20 -> Program AM Code\n"
+ " [vdw] = VMEbus Maximum Datawidth: 02 -> D16 Data Width\n"
+ " 03 -> D32 Data Width\n"
+);
"ubi remove[vol] volume"
" - Remove volume\n"
"[Legends]\n"
- " volume: charater name\n"
- " size: KiB, MiB, GiB, and bytes\n"
+ " volume: character name\n"
+ " size: specified in bytes\n"
" type: s[tatic] or d[ynamic] (default=dynamic)"
);
#include <common.h>
#include <stdarg.h>
#include <malloc.h>
-#include <console.h>
+#include <stdio_dev.h>
#include <exports.h>
DECLARE_GLOBAL_DATA_PTR;
#endif /* CONFIG_SYS_CONSOLE_IS_IN_ENV */
-static int console_setfile(int file, device_t * dev)
+static int console_setfile(int file, struct stdio_dev * dev)
{
int error = 0;
#if defined(CONFIG_CONSOLE_MUX)
/** Console I/O multiplexing *******************************************/
-static device_t *tstcdev;
-device_t **console_devices[MAX_FILES];
+static struct stdio_dev *tstcdev;
+struct stdio_dev **console_devices[MAX_FILES];
int cd_count[MAX_FILES];
/*
static int console_tstc(int file)
{
int i, ret;
- device_t *dev;
+ struct stdio_dev *dev;
disable_ctrlc(1);
for (i = 0; i < cd_count[file]; i++) {
static void console_putc(int file, const char c)
{
int i;
- device_t *dev;
+ struct stdio_dev *dev;
for (i = 0; i < cd_count[file]; i++) {
dev = console_devices[file][i];
static void console_puts(int file, const char *s)
{
int i;
- device_t *dev;
+ struct stdio_dev *dev;
for (i = 0; i < cd_count[file]; i++) {
dev = console_devices[file][i];
iomux_printdevs(file);
}
-static inline void console_doenv(int file, device_t *dev)
+static inline void console_doenv(int file, struct stdio_dev *dev)
{
iomux_doenv(file, dev->name);
}
printf("%s\n", stdio_devices[file]->name);
}
-static inline void console_doenv(int file, device_t *dev)
+static inline void console_doenv(int file, struct stdio_dev *dev)
{
console_setfile(file, dev);
}
/** U-Boot INIT FUNCTIONS *************************************************/
-device_t *search_device(int flags, char *name)
+struct stdio_dev *search_device(int flags, char *name)
{
- device_t *dev;
+ struct stdio_dev *dev;
- dev = device_get_by_name(name);
+ dev = stdio_get_by_name(name);
if (dev && (dev->flags & flags))
return dev;
int console_assign(int file, char *devname)
{
int flag;
- device_t *dev;
+ struct stdio_dev *dev;
/* Check for valid file */
switch (file) {
return 0;
}
+void stdio_print_current_devices(void)
+{
+#ifdef CONFIG_SYS_CONSOLE_INFO_QUIET
+ /* Print information */
+ puts("In: ");
+ if (stdio_devices[stdin] == NULL) {
+ puts("No input devices available!\n");
+ } else {
+ printf ("%s\n", stdio_devices[stdin]->name);
+ }
+
+ puts("Out: ");
+ if (stdio_devices[stdout] == NULL) {
+ puts("No output devices available!\n");
+ } else {
+ printf ("%s\n", stdio_devices[stdout]->name);
+ }
+
+ puts("Err: ");
+ if (stdio_devices[stderr] == NULL) {
+ puts("No error devices available!\n");
+ } else {
+ printf ("%s\n", stdio_devices[stderr]->name);
+ }
+#endif /* CONFIG_SYS_CONSOLE_INFO_QUIET */
+}
+
#ifdef CONFIG_SYS_CONSOLE_IS_IN_ENV
/* Called after the relocation - use desired console functions */
int console_init_r(void)
{
char *stdinname, *stdoutname, *stderrname;
- device_t *inputdev = NULL, *outputdev = NULL, *errdev = NULL;
+ struct stdio_dev *inputdev = NULL, *outputdev = NULL, *errdev = NULL;
#ifdef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
int i;
#endif /* CONFIG_SYS_CONSOLE_ENV_OVERWRITE */
gd->flags |= GD_FLG_DEVINIT; /* device initialization completed */
-#ifndef CONFIG_SYS_CONSOLE_INFO_QUIET
- /* Print information */
- puts("In: ");
- if (stdio_devices[stdin] == NULL) {
- puts("No input devices available!\n");
- } else {
- console_printdevs(stdin);
- }
-
- puts("Out: ");
- if (stdio_devices[stdout] == NULL) {
- puts("No output devices available!\n");
- } else {
- console_printdevs(stdout);
- }
-
- puts("Err: ");
- if (stdio_devices[stderr] == NULL) {
- puts("No error devices available!\n");
- } else {
- console_printdevs(stderr);
- }
-#endif /* CONFIG_SYS_CONSOLE_INFO_QUIET */
+ stdio_print_current_devices();
#ifdef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
/* set the environment variables (will overwrite previous env settings) */
/* Called after the relocation - use desired console functions */
int console_init_r(void)
{
- device_t *inputdev = NULL, *outputdev = NULL;
+ struct stdio_dev *inputdev = NULL, *outputdev = NULL;
int i;
- struct list_head *list = device_get_list();
+ struct list_head *list = stdio_get_list();
struct list_head *pos;
- device_t *dev;
+ struct stdio_dev *dev;
#ifdef CONFIG_SPLASH_SCREEN
/*
/* Scan devices looking for input and output devices */
list_for_each(pos, list) {
- dev = list_entry(pos, device_t, list);
+ dev = list_entry(pos, struct stdio_dev, list);
if ((dev->flags & DEV_FLAGS_INPUT) && (inputdev == NULL)) {
inputdev = dev;
gd->flags |= GD_FLG_DEVINIT; /* device initialization completed */
-#ifndef CONFIG_SYS_CONSOLE_INFO_QUIET
- /* Print information */
- puts("In: ");
- if (stdio_devices[stdin] == NULL) {
- puts("No input devices available!\n");
- } else {
- printf("%s\n", stdio_devices[stdin]->name);
- }
-
- puts("Out: ");
- if (stdio_devices[stdout] == NULL) {
- puts("No output devices available!\n");
- } else {
- printf("%s\n", stdio_devices[stdout]->name);
- }
-
- puts("Err: ");
- if (stdio_devices[stderr] == NULL) {
- puts("No error devices available!\n");
- } else {
- printf("%s\n", stdio_devices[stderr]->name);
- }
-#endif /* CONFIG_SYS_CONSOLE_INFO_QUIET */
+ stdio_print_current_devices();
/* Setting environment variables */
for (i = 0; i < 3; i++) {
+++ /dev/null
-/*
- * ECC algorithm for M-systems disk on chip. We use the excellent Reed
- * Solmon code of Phil Karn (karn@ka9q.ampr.org) available under the
- * GNU GPL License. The rest is simply to convert the disk on chip
- * syndrom into a standard syndom.
- *
- * Author: Fabrice Bellard (fabrice.bellard@netgem.com)
- * Copyright (C) 2000 Netgem S.A.
- *
- * $Id: docecc.c,v 1.4 2001/10/02 15:05:13 dwmw2 Exp $
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <malloc.h>
-
-#undef ECC_DEBUG
-#undef PSYCHO_DEBUG
-
-#include <linux/mtd/doc2000.h>
-
-/* need to undef it (from asm/termbits.h) */
-#undef B0
-
-#define MM 10 /* Symbol size in bits */
-#define KK (1023-4) /* Number of data symbols per block */
-#define B0 510 /* First root of generator polynomial, alpha form */
-#define PRIM 1 /* power of alpha used to generate roots of generator poly */
-#define NN ((1 << MM) - 1)
-
-typedef unsigned short dtype;
-
-/* 1+x^3+x^10 */
-static const int Pp[MM+1] = { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1 };
-
-/* This defines the type used to store an element of the Galois Field
- * used by the code. Make sure this is something larger than a char if
- * if anything larger than GF(256) is used.
- *
- * Note: unsigned char will work up to GF(256) but int seems to run
- * faster on the Pentium.
- */
-typedef int gf;
-
-/* No legal value in index form represents zero, so
- * we need a special value for this purpose
- */
-#define A0 (NN)
-
-/* Compute x % NN, where NN is 2**MM - 1,
- * without a slow divide
- */
-static inline gf
-modnn(int x)
-{
- while (x >= NN) {
- x -= NN;
- x = (x >> MM) + (x & NN);
- }
- return x;
-}
-
-#define CLEAR(a,n) {\
-int ci;\
-for(ci=(n)-1;ci >=0;ci--)\
-(a)[ci] = 0;\
-}
-
-#define COPY(a,b,n) {\
-int ci;\
-for(ci=(n)-1;ci >=0;ci--)\
-(a)[ci] = (b)[ci];\
-}
-
-#define COPYDOWN(a,b,n) {\
-int ci;\
-for(ci=(n)-1;ci >=0;ci--)\
-(a)[ci] = (b)[ci];\
-}
-
-#define Ldec 1
-
-/* generate GF(2**m) from the irreducible polynomial p(X) in Pp[0]..Pp[m]
- lookup tables: index->polynomial form alpha_to[] contains j=alpha**i;
- polynomial form -> index form index_of[j=alpha**i] = i
- alpha=2 is the primitive element of GF(2**m)
- HARI's COMMENT: (4/13/94) alpha_to[] can be used as follows:
- Let @ represent the primitive element commonly called "alpha" that
- is the root of the primitive polynomial p(x). Then in GF(2^m), for any
- 0 <= i <= 2^m-2,
- @^i = a(0) + a(1) @ + a(2) @^2 + ... + a(m-1) @^(m-1)
- where the binary vector (a(0),a(1),a(2),...,a(m-1)) is the representation
- of the integer "alpha_to[i]" with a(0) being the LSB and a(m-1) the MSB. Thus for
- example the polynomial representation of @^5 would be given by the binary
- representation of the integer "alpha_to[5]".
- Similarily, index_of[] can be used as follows:
- As above, let @ represent the primitive element of GF(2^m) that is
- the root of the primitive polynomial p(x). In order to find the power
- of @ (alpha) that has the polynomial representation
- a(0) + a(1) @ + a(2) @^2 + ... + a(m-1) @^(m-1)
- we consider the integer "i" whose binary representation with a(0) being LSB
- and a(m-1) MSB is (a(0),a(1),...,a(m-1)) and locate the entry
- "index_of[i]". Now, @^index_of[i] is that element whose polynomial
- representation is (a(0),a(1),a(2),...,a(m-1)).
- NOTE:
- The element alpha_to[2^m-1] = 0 always signifying that the
- representation of "@^infinity" = 0 is (0,0,0,...,0).
- Similarily, the element index_of[0] = A0 always signifying
- that the power of alpha which has the polynomial representation
- (0,0,...,0) is "infinity".
-
-*/
-
-static void
-generate_gf(dtype Alpha_to[NN + 1], dtype Index_of[NN + 1])
-{
- register int i, mask;
-
- mask = 1;
- Alpha_to[MM] = 0;
- for (i = 0; i < MM; i++) {
- Alpha_to[i] = mask;
- Index_of[Alpha_to[i]] = i;
- /* If Pp[i] == 1 then, term @^i occurs in poly-repr of @^MM */
- if (Pp[i] != 0)
- Alpha_to[MM] ^= mask; /* Bit-wise EXOR operation */
- mask <<= 1; /* single left-shift */
- }
- Index_of[Alpha_to[MM]] = MM;
- /*
- * Have obtained poly-repr of @^MM. Poly-repr of @^(i+1) is given by
- * poly-repr of @^i shifted left one-bit and accounting for any @^MM
- * term that may occur when poly-repr of @^i is shifted.
- */
- mask >>= 1;
- for (i = MM + 1; i < NN; i++) {
- if (Alpha_to[i - 1] >= mask)
- Alpha_to[i] = Alpha_to[MM] ^ ((Alpha_to[i - 1] ^ mask) << 1);
- else
- Alpha_to[i] = Alpha_to[i - 1] << 1;
- Index_of[Alpha_to[i]] = i;
- }
- Index_of[0] = A0;
- Alpha_to[NN] = 0;
-}
-
-/*
- * Performs ERRORS+ERASURES decoding of RS codes. bb[] is the content
- * of the feedback shift register after having processed the data and
- * the ECC.
- *
- * Return number of symbols corrected, or -1 if codeword is illegal
- * or uncorrectable. If eras_pos is non-null, the detected error locations
- * are written back. NOTE! This array must be at least NN-KK elements long.
- * The corrected data are written in eras_val[]. They must be xor with the data
- * to retrieve the correct data : data[erase_pos[i]] ^= erase_val[i] .
- *
- * First "no_eras" erasures are declared by the calling program. Then, the
- * maximum # of errors correctable is t_after_eras = floor((NN-KK-no_eras)/2).
- * If the number of channel errors is not greater than "t_after_eras" the
- * transmitted codeword will be recovered. Details of algorithm can be found
- * in R. Blahut's "Theory ... of Error-Correcting Codes".
-
- * Warning: the eras_pos[] array must not contain duplicate entries; decoder failure
- * will result. The decoder *could* check for this condition, but it would involve
- * extra time on every decoding operation.
- * */
-static int
-eras_dec_rs(dtype Alpha_to[NN + 1], dtype Index_of[NN + 1],
- gf bb[NN - KK + 1], gf eras_val[NN-KK], int eras_pos[NN-KK],
- int no_eras)
-{
- int deg_lambda, el, deg_omega;
- int i, j, r,k;
- gf u,q,tmp,num1,num2,den,discr_r;
- gf lambda[NN-KK + 1], s[NN-KK + 1]; /* Err+Eras Locator poly
- * and syndrome poly */
- gf b[NN-KK + 1], t[NN-KK + 1], omega[NN-KK + 1];
- gf root[NN-KK], reg[NN-KK + 1], loc[NN-KK];
- int syn_error, count;
-
- syn_error = 0;
- for(i=0;i<NN-KK;i++)
- syn_error |= bb[i];
-
- if (!syn_error) {
- /* if remainder is zero, data[] is a codeword and there are no
- * errors to correct. So return data[] unmodified
- */
- count = 0;
- goto finish;
- }
-
- for(i=1;i<=NN-KK;i++){
- s[i] = bb[0];
- }
- for(j=1;j<NN-KK;j++){
- if(bb[j] == 0)
- continue;
- tmp = Index_of[bb[j]];
-
- for(i=1;i<=NN-KK;i++)
- s[i] ^= Alpha_to[modnn(tmp + (B0+i-1)*PRIM*j)];
- }
-
- /* undo the feedback register implicit multiplication and convert
- syndromes to index form */
-
- for(i=1;i<=NN-KK;i++) {
- tmp = Index_of[s[i]];
- if (tmp != A0)
- tmp = modnn(tmp + 2 * KK * (B0+i-1)*PRIM);
- s[i] = tmp;
- }
-
- CLEAR(&lambda[1],NN-KK);
- lambda[0] = 1;
-
- if (no_eras > 0) {
- /* Init lambda to be the erasure locator polynomial */
- lambda[1] = Alpha_to[modnn(PRIM * eras_pos[0])];
- for (i = 1; i < no_eras; i++) {
- u = modnn(PRIM*eras_pos[i]);
- for (j = i+1; j > 0; j--) {
- tmp = Index_of[lambda[j - 1]];
- if(tmp != A0)
- lambda[j] ^= Alpha_to[modnn(u + tmp)];
- }
- }
-#ifdef ECC_DEBUG
- /* Test code that verifies the erasure locator polynomial just constructed
- Needed only for decoder debugging. */
-
- /* find roots of the erasure location polynomial */
- for(i=1;i<=no_eras;i++)
- reg[i] = Index_of[lambda[i]];
- count = 0;
- for (i = 1,k=NN-Ldec; i <= NN; i++,k = modnn(NN+k-Ldec)) {
- q = 1;
- for (j = 1; j <= no_eras; j++)
- if (reg[j] != A0) {
- reg[j] = modnn(reg[j] + j);
- q ^= Alpha_to[reg[j]];
- }
- if (q != 0)
- continue;
- /* store root and error location number indices */
- root[count] = i;
- loc[count] = k;
- count++;
- }
- if (count != no_eras) {
- printf("\n lambda(x) is WRONG\n");
- count = -1;
- goto finish;
- }
-#ifdef PSYCHO_DEBUG
- printf("\n Erasure positions as determined by roots of Eras Loc Poly:\n");
- for (i = 0; i < count; i++)
- printf("%d ", loc[i]);
- printf("\n");
-#endif
-#endif
- }
- for(i=0;i<NN-KK+1;i++)
- b[i] = Index_of[lambda[i]];
-
- /*
- * Begin Berlekamp-Massey algorithm to determine error+erasure
- * locator polynomial
- */
- r = no_eras;
- el = no_eras;
- while (++r <= NN-KK) { /* r is the step number */
- /* Compute discrepancy at the r-th step in poly-form */
- discr_r = 0;
- for (i = 0; i < r; i++){
- if ((lambda[i] != 0) && (s[r - i] != A0)) {
- discr_r ^= Alpha_to[modnn(Index_of[lambda[i]] + s[r - i])];
- }
- }
- discr_r = Index_of[discr_r]; /* Index form */
- if (discr_r == A0) {
- /* 2 lines below: B(x) <-- x*B(x) */
- COPYDOWN(&b[1],b,NN-KK);
- b[0] = A0;
- } else {
- /* 7 lines below: T(x) <-- lambda(x) - discr_r*x*b(x) */
- t[0] = lambda[0];
- for (i = 0 ; i < NN-KK; i++) {
- if(b[i] != A0)
- t[i+1] = lambda[i+1] ^ Alpha_to[modnn(discr_r + b[i])];
- else
- t[i+1] = lambda[i+1];
- }
- if (2 * el <= r + no_eras - 1) {
- el = r + no_eras - el;
- /*
- * 2 lines below: B(x) <-- inv(discr_r) *
- * lambda(x)
- */
- for (i = 0; i <= NN-KK; i++)
- b[i] = (lambda[i] == 0) ? A0 : modnn(Index_of[lambda[i]] - discr_r + NN);
- } else {
- /* 2 lines below: B(x) <-- x*B(x) */
- COPYDOWN(&b[1],b,NN-KK);
- b[0] = A0;
- }
- COPY(lambda,t,NN-KK+1);
- }
- }
-
- /* Convert lambda to index form and compute deg(lambda(x)) */
- deg_lambda = 0;
- for(i=0;i<NN-KK+1;i++){
- lambda[i] = Index_of[lambda[i]];
- if(lambda[i] != A0)
- deg_lambda = i;
- }
- /*
- * Find roots of the error+erasure locator polynomial by Chien
- * Search
- */
- COPY(®[1],&lambda[1],NN-KK);
- count = 0; /* Number of roots of lambda(x) */
- for (i = 1,k=NN-Ldec; i <= NN; i++,k = modnn(NN+k-Ldec)) {
- q = 1;
- for (j = deg_lambda; j > 0; j--){
- if (reg[j] != A0) {
- reg[j] = modnn(reg[j] + j);
- q ^= Alpha_to[reg[j]];
- }
- }
- if (q != 0)
- continue;
- /* store root (index-form) and error location number */
- root[count] = i;
- loc[count] = k;
- /* If we've already found max possible roots,
- * abort the search to save time
- */
- if(++count == deg_lambda)
- break;
- }
- if (deg_lambda != count) {
- /*
- * deg(lambda) unequal to number of roots => uncorrectable
- * error detected
- */
- count = -1;
- goto finish;
- }
- /*
- * Compute err+eras evaluator poly omega(x) = s(x)*lambda(x) (modulo
- * x**(NN-KK)). in index form. Also find deg(omega).
- */
- deg_omega = 0;
- for (i = 0; i < NN-KK;i++){
- tmp = 0;
- j = (deg_lambda < i) ? deg_lambda : i;
- for(;j >= 0; j--){
- if ((s[i + 1 - j] != A0) && (lambda[j] != A0))
- tmp ^= Alpha_to[modnn(s[i + 1 - j] + lambda[j])];
- }
- if(tmp != 0)
- deg_omega = i;
- omega[i] = Index_of[tmp];
- }
- omega[NN-KK] = A0;
-
- /*
- * Compute error values in poly-form. num1 = omega(inv(X(l))), num2 =
- * inv(X(l))**(B0-1) and den = lambda_pr(inv(X(l))) all in poly-form
- */
- for (j = count-1; j >=0; j--) {
- num1 = 0;
- for (i = deg_omega; i >= 0; i--) {
- if (omega[i] != A0)
- num1 ^= Alpha_to[modnn(omega[i] + i * root[j])];
- }
- num2 = Alpha_to[modnn(root[j] * (B0 - 1) + NN)];
- den = 0;
-
- /* lambda[i+1] for i even is the formal derivative lambda_pr of lambda[i] */
- for (i = min(deg_lambda,NN-KK-1) & ~1; i >= 0; i -=2) {
- if(lambda[i+1] != A0)
- den ^= Alpha_to[modnn(lambda[i+1] + i * root[j])];
- }
- if (den == 0) {
-#ifdef ECC_DEBUG
- printf("\n ERROR: denominator = 0\n");
-#endif
- /* Convert to dual- basis */
- count = -1;
- goto finish;
- }
- /* Apply error to data */
- if (num1 != 0) {
- eras_val[j] = Alpha_to[modnn(Index_of[num1] + Index_of[num2] + NN - Index_of[den])];
- } else {
- eras_val[j] = 0;
- }
- }
- finish:
- for(i=0;i<count;i++)
- eras_pos[i] = loc[i];
- return count;
-}
-
-/***************************************************************************/
-/* The DOC specific code begins here */
-
-#define SECTOR_SIZE 512
-/* The sector bytes are packed into NB_DATA MM bits words */
-#define NB_DATA (((SECTOR_SIZE + 1) * 8 + 6) / MM)
-
-/*
- * Correct the errors in 'sector[]' by using 'ecc1[]' which is the
- * content of the feedback shift register applyied to the sector and
- * the ECC. Return the number of errors corrected (and correct them in
- * sector), or -1 if error
- */
-int doc_decode_ecc(unsigned char sector[SECTOR_SIZE], unsigned char ecc1[6])
-{
- int parity, i, nb_errors;
- gf bb[NN - KK + 1];
- gf error_val[NN-KK];
- int error_pos[NN-KK], pos, bitpos, index, val;
- dtype *Alpha_to, *Index_of;
-
- /* init log and exp tables here to save memory. However, it is slower */
- Alpha_to = malloc((NN + 1) * sizeof(dtype));
- if (!Alpha_to)
- return -1;
-
- Index_of = malloc((NN + 1) * sizeof(dtype));
- if (!Index_of) {
- free(Alpha_to);
- return -1;
- }
-
- generate_gf(Alpha_to, Index_of);
-
- parity = ecc1[1];
-
- bb[0] = (ecc1[4] & 0xff) | ((ecc1[5] & 0x03) << 8);
- bb[1] = ((ecc1[5] & 0xfc) >> 2) | ((ecc1[2] & 0x0f) << 6);
- bb[2] = ((ecc1[2] & 0xf0) >> 4) | ((ecc1[3] & 0x3f) << 4);
- bb[3] = ((ecc1[3] & 0xc0) >> 6) | ((ecc1[0] & 0xff) << 2);
-
- nb_errors = eras_dec_rs(Alpha_to, Index_of, bb,
- error_val, error_pos, 0);
- if (nb_errors <= 0)
- goto the_end;
-
- /* correct the errors */
- for(i=0;i<nb_errors;i++) {
- pos = error_pos[i];
- if (pos >= NB_DATA && pos < KK) {
- nb_errors = -1;
- goto the_end;
- }
- if (pos < NB_DATA) {
- /* extract bit position (MSB first) */
- pos = 10 * (NB_DATA - 1 - pos) - 6;
- /* now correct the following 10 bits. At most two bytes
- can be modified since pos is even */
- index = (pos >> 3) ^ 1;
- bitpos = pos & 7;
- if ((index >= 0 && index < SECTOR_SIZE) ||
- index == (SECTOR_SIZE + 1)) {
- val = error_val[i] >> (2 + bitpos);
- parity ^= val;
- if (index < SECTOR_SIZE)
- sector[index] ^= val;
- }
- index = ((pos >> 3) + 1) ^ 1;
- bitpos = (bitpos + 10) & 7;
- if (bitpos == 0)
- bitpos = 8;
- if ((index >= 0 && index < SECTOR_SIZE) ||
- index == (SECTOR_SIZE + 1)) {
- val = error_val[i] << (8 - bitpos);
- parity ^= val;
- if (index < SECTOR_SIZE)
- sector[index] ^= val;
- }
- }
- }
-
- /* use parity to test extra errors */
- if ((parity & 0xff) != 0)
- nb_errors = -1;
-
- the_end:
- free(Alpha_to);
- free(Index_of);
- return nb_errors;
-}
#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
#endif
-int nand_legacy_rw (struct nand_chip* nand, int cmd,
- size_t start, size_t len,
- size_t * retlen, u_char * buf);
-
/* references to names in env_common.c */
extern uchar default_environment[];
extern int default_environment_size;
/*
- * (C) Copyright 2005-2007 Samsung Electronics
+ * (C) Copyright 2005-2009 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
/* References to names in env_common.c */
extern uchar default_environment[];
-#define ONENAND_ENV_SIZE(mtd) (mtd.writesize - ENV_HEADER_SIZE)
-
char *env_name_spec = "OneNAND";
+#define ONENAND_MAX_ENV_SIZE 4096
+#define ONENAND_ENV_SIZE(mtd) (ONENAND_MAX_ENV_SIZE - ENV_HEADER_SIZE)
+
#ifdef ENV_IS_EMBEDDED
extern uchar environment[];
env_t *env_ptr = (env_t *) (&environment[0]);
#else /* ! ENV_IS_EMBEDDED */
-static unsigned char onenand_env[MAX_ONENAND_PAGESIZE];
+static unsigned char onenand_env[ONENAND_MAX_ENV_SIZE];
env_t *env_ptr = (env_t *) onenand_env;
#endif /* ENV_IS_EMBEDDED */
void env_relocate_spec(void)
{
+ struct mtd_info *mtd = &onenand_mtd;
loff_t env_addr;
int use_default = 0;
size_t retlen;
env_addr = CONFIG_ENV_ADDR;
/* Check OneNAND exist */
- if (onenand_mtd.writesize)
+ if (mtd->writesize)
/* Ignore read fail */
- onenand_read(&onenand_mtd, env_addr, onenand_mtd.writesize,
+ mtd->read(mtd, env_addr, ONENAND_MAX_ENV_SIZE,
&retlen, (u_char *) env_ptr);
else
- onenand_mtd.writesize = MAX_ONENAND_PAGESIZE;
+ mtd->writesize = MAX_ONENAND_PAGESIZE;
- if (crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd)) !=
- env_ptr->crc)
+ if (crc32(0, env_ptr->data, ONENAND_ENV_SIZE(mtd)) != env_ptr->crc)
use_default = 1;
if (use_default) {
memcpy(env_ptr->data, default_environment,
- ONENAND_ENV_SIZE(onenand_mtd));
+ ONENAND_ENV_SIZE(mtd));
env_ptr->crc =
- crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd));
+ crc32(0, env_ptr->data, ONENAND_ENV_SIZE(mtd));
}
gd->env_addr = (ulong) & env_ptr->data;
int saveenv(void)
{
- unsigned long env_addr = CONFIG_ENV_ADDR;
+ struct mtd_info *mtd = &onenand_mtd;
+ loff_t env_addr = CONFIG_ENV_ADDR;
struct erase_info instr = {
.callback = NULL,
};
instr.len = CONFIG_ENV_SIZE;
instr.addr = env_addr;
- instr.mtd = &onenand_mtd;
- if (onenand_erase(&onenand_mtd, &instr)) {
- printf("OneNAND: erase failed at 0x%08lx\n", env_addr);
+ instr.mtd = mtd;
+ if (mtd->erase(mtd, &instr)) {
+ printf("OneNAND: erase failed at 0x%08llx\n", env_addr);
return 1;
}
/* update crc */
- env_ptr->crc =
- crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd));
+ env_ptr->crc = crc32(0, env_ptr->data, ONENAND_ENV_SIZE(mtd));
- if (onenand_write(&onenand_mtd, env_addr, onenand_mtd.writesize, &retlen,
+ if (mtd->write(mtd, env_addr, ONENAND_MAX_ENV_SIZE, &retlen,
(u_char *) env_ptr)) {
printf("OneNAND: write failed at 0x%llx\n", instr.addr);
return 2;
--- /dev/null
+/*
+ * An inteface for configuring a hardware via u-boot environment.
+ *
+ * Copyright (c) 2009 MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <exports.h>
+#include <hwconfig.h>
+#include <linux/types.h>
+#include <linux/string.h>
+
+static const char *hwconfig_parse(const char *opts, size_t maxlen,
+ const char *opt, char stopch, char eqch,
+ size_t *arglen)
+{
+ size_t optlen = strlen(opt);
+ char *str;
+ const char *start = opts;
+ const char *end;
+
+next:
+ str = strstr(opts, opt);
+ end = str + optlen;
+ if (end - start > maxlen)
+ return NULL;
+
+ if (str && (str == opts || str[-1] == stopch) &&
+ (*end == stopch || *end == eqch || *end == '\0')) {
+ const char *arg_end;
+
+ if (!arglen)
+ return str;
+
+ if (*end != eqch)
+ return NULL;
+
+ arg_end = strchr(str, stopch);
+ if (!arg_end)
+ *arglen = min(maxlen, strlen(str)) - optlen - 1;
+ else
+ *arglen = arg_end - end - 1;
+
+ return end + 1;
+ } else if (str) {
+ opts = end;
+ goto next;
+ }
+ return NULL;
+}
+
+const char *cpu_hwconfig __attribute__((weak));
+const char *board_hwconfig __attribute__((weak));
+
+static const char *__hwconfig(const char *opt, size_t *arglen)
+{
+ const char *env_hwconfig = getenv("hwconfig");
+
+ if (env_hwconfig)
+ return hwconfig_parse(env_hwconfig, strlen(env_hwconfig),
+ opt, ';', ':', arglen);
+
+ if (board_hwconfig)
+ return hwconfig_parse(board_hwconfig, strlen(board_hwconfig),
+ opt, ';', ':', arglen);
+
+ if (cpu_hwconfig)
+ return hwconfig_parse(cpu_hwconfig, strlen(cpu_hwconfig),
+ opt, ';', ':', arglen);
+
+ return NULL;
+}
+
+/*
+ * hwconfig - query if a particular hwconfig option is specified
+ * @opt: a string representing an option
+ *
+ * This call can be used to find out whether U-Boot should configure
+ * a particular hardware option.
+ *
+ * Returns non-zero value if the hardware option can be used and thus
+ * should be configured, 0 otherwise.
+ *
+ * This function also returns non-zero value if CONFIG_HWCONFIG is
+ * undefined.
+ *
+ * Returning non-zero value without CONFIG_HWCONFIG has its crucial
+ * purpose: the hwconfig() call should be a "transparent" interface,
+ * e.g. if a board doesn't need hwconfig facility, then we assume
+ * that the board file only calls things that are actually used, so
+ * hwconfig() will always return true result.
+ */
+int hwconfig(const char *opt)
+{
+ return !!__hwconfig(opt, NULL);
+}
+
+/*
+ * hwconfig_arg - get hwconfig option's argument
+ * @opt: a string representing an option
+ * @arglen: a pointer to an allocated size_t variable
+ *
+ * Unlike hwconfig() function, this function returns a pointer to the
+ * start of the hwconfig arguments, if option is not found or it has
+ * no specified arguments, the function returns NULL pointer.
+ *
+ * If CONFIG_HWCONFIG is undefined, the function returns "", and
+ * arglen is set to 0.
+ */
+const char *hwconfig_arg(const char *opt, size_t *arglen)
+{
+ return __hwconfig(opt, arglen);
+}
+
+/*
+ * hwconfig_arg_cmp - compare hwconfig option's argument
+ * @opt: a string representing an option
+ * @arg: a string for comparing an option's argument
+ *
+ * This call is similar to hwconfig_arg, but instead of returning
+ * hwconfig argument and its length, it is comparing it to @arg.
+ *
+ * Returns non-zero value if @arg matches, 0 otherwise.
+ *
+ * If CONFIG_HWCONFIG is undefined, the function returns a non-zero
+ * value, i.e. the argument matches.
+ */
+int hwconfig_arg_cmp(const char *opt, const char *arg)
+{
+ const char *argstr;
+ size_t arglen;
+
+ argstr = hwconfig_arg(opt, &arglen);
+ if (!argstr || arglen != strlen(arg))
+ return 0;
+
+ return !strncmp(argstr, arg, arglen);
+}
+
+/*
+ * hwconfig_sub - query if a particular hwconfig sub-option is specified
+ * @opt: a string representing an option
+ * @subopt: a string representing a sub-option
+ *
+ * This call is similar to hwconfig(), except that it takes additional
+ * argument @subopt. In this example:
+ * "dr_usb:mode=peripheral"
+ * "dr_usb" is an option, "mode" is a sub-option, and "peripheral" is its
+ * argument.
+ */
+int hwconfig_sub(const char *opt, const char *subopt)
+{
+ size_t arglen;
+ const char *arg;
+
+ arg = __hwconfig(opt, &arglen);
+ if (!arg)
+ return 0;
+ return !!hwconfig_parse(arg, arglen, subopt, ',', '=', NULL);
+}
+
+/*
+ * hwconfig_subarg - get hwconfig sub-option's argument
+ * @opt: a string representing an option
+ * @subopt: a string representing a sub-option
+ * @subarglen: a pointer to an allocated size_t variable
+ *
+ * This call is similar to hwconfig_arg(), except that it takes an additional
+ * argument @subopt, and so works with sub-options.
+ */
+const char *hwconfig_subarg(const char *opt, const char *subopt,
+ size_t *subarglen)
+{
+ size_t arglen;
+ const char *arg;
+
+ arg = __hwconfig(opt, &arglen);
+ if (!arg)
+ return NULL;
+ return hwconfig_parse(arg, arglen, subopt, ',', '=', subarglen);
+}
+
+/*
+ * hwconfig_arg_cmp - compare hwconfig sub-option's argument
+ * @opt: a string representing an option
+ * @subopt: a string representing a sub-option
+ * @subarg: a string for comparing an sub-option's argument
+ *
+ * This call is similar to hwconfig_arg_cmp, except that it takes an additional
+ * argument @subopt, and so works with sub-options.
+ */
+int hwconfig_subarg_cmp(const char *opt, const char *subopt, const char *subarg)
+{
+ const char *argstr;
+ size_t arglen;
+
+ argstr = hwconfig_subarg(opt, subopt, &arglen);
+ if (!argstr || arglen != strlen(subarg))
+ return 0;
+
+ return !strncmp(argstr, subarg, arglen);
+}
void iomux_printdevs(const int console)
{
int i;
- device_t *dev;
+ struct stdio_dev *dev;
for (i = 0; i < cd_count[console]; i++) {
dev = console_devices[console][i];
{
char *console_args, *temp, **start;
int i, j, k, io_flag, cs_idx, repeat;
- device_t *dev;
- device_t **cons_set;
+ struct stdio_dev *dev;
+ struct stdio_dev **cons_set;
console_args = strdup(arg);
if (console_args == NULL)
*temp = '\0';
start[i] = temp + 1;
}
- cons_set = (device_t **)calloc(i, sizeof(device_t *));
+ cons_set = (struct stdio_dev **)calloc(i, sizeof(struct stdio_dev *));
if (cons_set == NULL) {
free(start);
free(console_args);
} else {
/* Works even if console_devices[console] is NULL. */
console_devices[console] =
- (device_t **)realloc(console_devices[console],
- cs_idx * sizeof(device_t *));
+ (struct stdio_dev **)realloc(console_devices[console],
+ cs_idx * sizeof(struct stdio_dev *));
if (console_devices[console] == NULL) {
free(cons_set);
return 1;
}
memcpy(console_devices[console], cons_set, cs_idx *
- sizeof(device_t *));
+ sizeof(struct stdio_dev *));
cd_count[console] = cs_idx;
}
#include <command.h>
#include <stdarg.h>
#include <linux/types.h>
-#include <devices.h>
+#include <stdio_dev.h>
#if defined(CONFIG_POST)
#include <post.h>
#endif
static int lcd_init (void *lcdbase);
static int lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
-extern void lcd_ctrl_init (void *lcdbase);
-extern void lcd_enable (void);
static void *lcd_logo (void);
-
-#if (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16)
-extern void lcd_setcolreg (ushort regno,
- ushort red, ushort green, ushort blue);
-#endif
-#if LCD_BPP == LCD_MONOCHROME
-extern void lcd_initcolregs (void);
-#endif
-
static int lcd_getbgcolor (void);
static void lcd_setfgcolor (int color);
static void lcd_setbgcolor (int color);
char lcd_is_enabled = 0;
-extern vidinfo_t panel_info;
#ifdef NOT_USED_SO_FAR
static void lcd_getcolreg (ushort regno,
int drv_lcd_init (void)
{
- device_t lcddev;
+ struct stdio_dev lcddev;
int rc;
lcd_base = (void *)(gd->fb_base);
lcddev.putc = lcd_putc; /* 'putc' function */
lcddev.puts = lcd_puts; /* 'puts' function */
- rc = device_register (&lcddev);
+ rc = stdio_register (&lcddev);
return (rc == 0) ? 1 : rc;
}
* Display the BMP file located at address bmp_image.
* Only uncompressed.
*/
+
+#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+#define BMP_ALIGN_CENTER 0x7FFF
+#endif
+
int lcd_display_bitmap(ulong bmp_image, int x, int y)
{
#if !defined(CONFIG_MCC200)
#endif
padded_line = (width&0x3) ? ((width&~0x3)+4) : (width);
+
+#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+ if (x == BMP_ALIGN_CENTER)
+ x = max(0, (pwidth - width) / 2);
+ else if (x < 0)
+ x = max(0, pwidth - width + x + 1);
+
+ if (y == BMP_ALIGN_CENTER)
+ y = max(0, (panel_info.vl_row - height) / 2);
+ else if (y < 0)
+ y = max(0, panel_info.vl_row - height + y + 1);
+#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
+
if ((x + width)>pwidth)
width = pwidth - x;
if ((y + height)>panel_info.vl_row)
}
#endif
-#ifdef CONFIG_VIDEO_BMP_GZIP
-extern bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp);
-#endif
-
static void *lcd_logo (void)
{
#ifdef CONFIG_SPLASH_SCREEN
static int do_splash = 1;
if (do_splash && (s = getenv("splashimage")) != NULL) {
- addr = simple_strtoul(s, NULL, 16);
+ int x = 0, y = 0;
do_splash = 0;
+ addr = simple_strtoul (s, NULL, 16);
+#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+ if ((s = getenv ("splashpos")) != NULL) {
+ if (s[0] == 'm')
+ x = BMP_ALIGN_CENTER;
+ else
+ x = simple_strtol (s, NULL, 0);
+
+ if ((s = strchr (s + 1, ',')) != NULL) {
+ if (s[1] == 'm')
+ y = BMP_ALIGN_CENTER;
+ else
+ y = simple_strtol (s + 1, NULL, 0);
+ }
+ }
+#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
+
#ifdef CONFIG_VIDEO_BMP_GZIP
bmp_image_t *bmp = (bmp_image_t *)addr;
unsigned long len;
}
#endif
- if (lcd_display_bitmap (addr, 0, 0) == 0) {
+ if (lcd_display_bitmap (addr, x, y) == 0) {
return ((void *)lcd_base);
}
}
#include <common.h>
#include <serial.h>
-#include <devices.h>
+#include <stdio_dev.h>
DECLARE_GLOBAL_DATA_PTR;
serial_assign (default_serial_console ()->name);
}
-void serial_devices_init (void)
+void serial_stdio_init (void)
{
- device_t dev;
+ struct stdio_dev dev;
struct serial_device *s = serial_devices;
while (s) {
dev.getc = s->getc;
dev.tstc = s->tstc;
- device_register (&dev);
+ stdio_register (&dev);
s = s->next;
}
#include <common.h>
#include <stdarg.h>
#include <malloc.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <serial.h>
#ifdef CONFIG_LOGBUFFER
#include <logbuff.h>
DECLARE_GLOBAL_DATA_PTR;
-static device_t devs;
-device_t *stdio_devices[] = { NULL, NULL, NULL };
+static struct stdio_dev devs;
+struct stdio_dev *stdio_devices[] = { NULL, NULL, NULL };
char *stdio_names[MAX_FILES] = { "stdin", "stdout", "stderr" };
#if defined(CONFIG_SPLASH_SCREEN) && !defined(CONFIG_SYS_DEVICE_NULLDEV)
static void drv_system_init (void)
{
- device_t dev;
+ struct stdio_dev dev;
memset (&dev, 0, sizeof (dev));
dev.tstc = serial_tstc;
#endif
- device_register (&dev);
+ stdio_register (&dev);
#ifdef CONFIG_SYS_DEVICE_NULLDEV
memset (&dev, 0, sizeof (dev));
dev.getc = nulldev_input;
dev.tstc = nulldev_input;
- device_register (&dev);
+ stdio_register (&dev);
#endif
}
* DEVICES
**************************************************************************
*/
-struct list_head* device_get_list(void)
+struct list_head* stdio_get_list(void)
{
return &(devs.list);
}
-device_t* device_get_by_name(char* name)
+struct stdio_dev* stdio_get_by_name(char* name)
{
struct list_head *pos;
- device_t *dev;
+ struct stdio_dev *dev;
if(!name)
return NULL;
list_for_each(pos, &(devs.list)) {
- dev = list_entry(pos, device_t, list);
+ dev = list_entry(pos, struct stdio_dev, list);
if(strcmp(dev->name, name) == 0)
return dev;
}
return NULL;
}
-device_t* device_clone(device_t *dev)
+struct stdio_dev* stdio_clone(struct stdio_dev *dev)
{
- device_t *_dev;
+ struct stdio_dev *_dev;
if(!dev)
return NULL;
- _dev = calloc(1, sizeof(device_t));
+ _dev = calloc(1, sizeof(struct stdio_dev));
if(!_dev)
return NULL;
- memcpy(_dev, dev, sizeof(device_t));
+ memcpy(_dev, dev, sizeof(struct stdio_dev));
strncpy(_dev->name, dev->name, 16);
return _dev;
}
-int device_register (device_t * dev)
+int stdio_register (struct stdio_dev * dev)
{
- device_t *_dev;
+ struct stdio_dev *_dev;
- _dev = device_clone(dev);
+ _dev = stdio_clone(dev);
if(!_dev)
return -1;
list_add_tail(&(_dev->list), &(devs.list));
/* deregister the device "devname".
* returns 0 if success, -1 if device is assigned and 1 if devname not found
*/
-#ifdef CONFIG_SYS_DEVICE_DEREGISTER
-int device_deregister(char *devname)
+#ifdef CONFIG_SYS_STDIO_DEREGISTER
+int stdio_deregister(char *devname)
{
int l;
struct list_head *pos;
- device_t *dev;
+ struct stdio_dev *dev;
char temp_names[3][8];
- dev = device_get_by_name(devname);
+ dev = stdio_get_by_name(devname);
if(!dev) /* device not found */
return -1;
/* reassign Device list */
list_for_each(pos, &(devs.list)) {
- dev = list_entry(pos, device_t, list);
+ dev = list_entry(pos, struct stdio_dev, list);
for (l=0 ; l< MAX_FILES; l++) {
if(strcmp(dev->name, temp_names[l]) == 0)
stdio_devices[l] = dev;
}
return 0;
}
-#endif /* CONFIG_SYS_DEVICE_DEREGISTER */
+#endif /* CONFIG_SYS_STDIO_DEREGISTER */
-int devices_init (void)
+int stdio_init (void)
{
#ifndef CONFIG_ARM /* already relocated for current ARM implementation */
ulong relocation_offset = gd->reloc_off;
#endif
drv_system_init ();
#ifdef CONFIG_SERIAL_MULTI
- serial_devices_init ();
+ serial_stdio_init ();
#endif
#ifdef CONFIG_USB_TTY
drv_usbtty_init ();
*
*/
#include <common.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <asm/byteorder.h>
#include <usb.h>
int drv_usb_kbd_init(void)
{
int error,i;
- device_t usb_kbd_dev,*old_dev;
+ struct stdio_dev usb_kbd_dev,*old_dev;
struct usb_device *dev;
char *stdinname = getenv ("stdin");
if(usb_kbd_probe(dev,0)==1) { /* Ok, we found a keyboard */
/* check, if it is already registered */
USB_KBD_PRINTF("USB KBD found set up device.\n");
- old_dev = device_get_by_name(DEVNAME);
+ old_dev = stdio_get_by_name(DEVNAME);
if(old_dev) {
/* ok, already registered, just return ok */
USB_KBD_PRINTF("USB KBD is already registered.\n");
}
/* register the keyboard */
USB_KBD_PRINTF("USB KBD register.\n");
- memset (&usb_kbd_dev, 0, sizeof(device_t));
+ memset (&usb_kbd_dev, 0, sizeof(struct stdio_dev));
strcpy(usb_kbd_dev.name, DEVNAME);
usb_kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
usb_kbd_dev.putc = NULL;
usb_kbd_dev.getc = usb_kbd_getc;
usb_kbd_dev.tstc = usb_kbd_testc;
usb_kbd_dev.priv = (void *)dev;
- error = device_register (&usb_kbd_dev);
+ error = stdio_register (&usb_kbd_dev);
if(error==0) {
/* check if this is the standard input device */
if(strcmp(stdinname,DEVNAME)==0) {
/* deregistering the keyboard */
int usb_kbd_deregister(void)
{
-#ifdef CONFIG_SYS_DEVICE_DEREGISTER
- return device_deregister(DEVNAME);
+#ifdef CONFIG_SYS_STDIO_DEREGISTER
+ return stdio_deregister(DEVNAME);
#else
return 1;
#endif
xyzModem_CHAR_TIMEOUT);
#else
/* TODO: CHECK ! */
- int dummy;
+ int dummy = 0;
xyz.__chan = &dummy;
#endif
xyz.len = 0;
sinclude $(OBJTREE)/include/autoconf.mk
ifdef ARCH
-sinclude $(TOPDIR)/$(ARCH)_config.mk # include architecture dependend rules
+sinclude $(TOPDIR)/lib_$(ARCH)/config.mk # include architecture dependend rules
endif
ifdef CPU
sinclude $(TOPDIR)/cpu/$(CPU)/config.mk # include CPU specific rules
endif
endif
-ifeq ($(PCI_CLOCK),PCI_66M)
-CFLAGS := $(CFLAGS) -DPCI_66M
-endif
-
#########################################################################
-export HPATH HOSTCC HOSTCFLAGS CROSS_COMPILE \
+export HOSTCC HOSTCFLAGS CROSS_COMPILE \
AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP MAKE
export TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS
#include <at91rm9200_net.h>
#include <net.h>
#include <miiphy.h>
+#include <asm/mach-types.h>
/* ----- Ethernet Buffer definitions ----- */
p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */
- /* Init Ehternet buffers */
+ /* Init Ethernet buffers */
for (i = 0; i < RBF_FRAMEMAX; i++) {
rbfdt[i].addr = (unsigned long)rbf_framebuf[i];
rbfdt[i].size = 0;
rbfp = &rbfdt[0];
eth_getenv_enetaddr("ethaddr", enetaddr);
- p_mac->EMAC_SA2L = (enetaddr[3] << 24) | (enetaddr[2] << 16)
- | (enetaddr[1] << 8) | (enetaddr[0]);
- p_mac->EMAC_SA2H = (enetaddr[5] << 8) | (enetaddr[4]);
+
+ /* The CSB337 originally used a version of the MicroMonitor bootloader
+ * which saved Ethernet addresses in the "wrong" order. Operating
+ * systems (like Linux) know this, and apply a workaround. Replicate
+ * that MicroMonitor behavior so we avoid needing to make such OS code
+ * care about which bootloader was used.
+ */
+ if (machine_is_csb337()) {
+ p_mac->EMAC_SA2H = (enetaddr[0] << 8) | (enetaddr[1]);
+ p_mac->EMAC_SA2L = (enetaddr[2] << 24) | (enetaddr[3] << 16)
+ | (enetaddr[4] << 8) | (enetaddr[5]);
+ } else {
+ p_mac->EMAC_SA2L = (enetaddr[3] << 24) | (enetaddr[2] << 16)
+ | (enetaddr[1] << 8) | (enetaddr[0]);
+ p_mac->EMAC_SA2H = (enetaddr[5] << 8) | (enetaddr[4]);
+ }
p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
bne 0b
/* delay - this is all done by guess */
ldr r0, =0x00010000
+ /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
1:
subs r0, r0, #1
bhi 1b
.ltorg
SMRDATA:
- .word AT91C_MC_PUIA
- .word CONFIG_SYS_MC_PUIA_VAL
- .word AT91C_MC_PUP
- .word CONFIG_SYS_MC_PUP_VAL
- .word AT91C_MC_PUER
- .word CONFIG_SYS_MC_PUER_VAL
- .word AT91C_MC_ASR
- .word CONFIG_SYS_MC_ASR_VAL
- .word AT91C_MC_AASR
- .word CONFIG_SYS_MC_AASR_VAL
.word AT91C_EBI_CFGR
.word CONFIG_SYS_EBI_CFGR_VAL
.word AT91C_SMC_CSR0
.word CONFIG_SYS_PLLBR_VAL
.word AT91C_MCKR
.word CONFIG_SYS_MCKR_VAL
- /* SMRDATA is 80 bytes long */
- /* here there's a delay of 100 */
+ /* here there's a delay */
SMRDATA1:
.word AT91C_PIOC_ASR
.word CONFIG_SYS_PIOC_ASR_VAL
* MA 02111-1307 USA
*/
+#include <common.h>
#include <config.h>
-#include <version.h>
-#include <status_led.h>
/*
*************************************************************************
.word CONFIG_SYS_PIOD_PPUDR_VAL
.word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
.word CONFIG_SYS_PIOD_PPUDR_VAL
-#elif defined(CONFIG_AT91SAM9261)
+#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261)
.word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR)
.word CONFIG_SYS_PIOC_PDR_VAL1
.word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR)
#include <common.h>
#include <div64.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
}
#endif
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FEC_MXC)
+ return fecmxc_initialize(bis);
+#else
+ return 0;
+#endif
+}
+
void imx_gpio_mode(int gpio_mode)
{
struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
LIB = $(obj)lib$(SOC).a
-COBJS = timer.o
+COBJS = timer.o gpio.o
SOBJS = reset.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
--- /dev/null
+/*
+ * (C) Copyright 2009 Alessandro Rubini
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+
+static unsigned long gpio_base[4] = {
+ NOMADIK_GPIO0_BASE,
+ NOMADIK_GPIO1_BASE,
+ NOMADIK_GPIO2_BASE,
+ NOMADIK_GPIO3_BASE
+};
+
+enum gpio_registers {
+ GPIO_DAT = 0x00, /* data register */
+ GPIO_DATS = 0x04, /* data set */
+ GPIO_DATC = 0x08, /* data clear */
+ GPIO_PDIS = 0x0c, /* pull disable */
+ GPIO_DIR = 0x10, /* direction */
+ GPIO_DIRS = 0x14, /* direction set */
+ GPIO_DIRC = 0x18, /* direction clear */
+ GPIO_AFSLA = 0x20, /* alternate function select A */
+ GPIO_AFSLB = 0x24, /* alternate function select B */
+};
+
+static inline unsigned long gpio_to_base(int gpio)
+{
+ return gpio_base[gpio / 32];
+}
+
+static inline u32 gpio_to_bit(int gpio)
+{
+ return 1 << (gpio & 0x1f);
+}
+
+void nmk_gpio_af(int gpio, int alternate_function)
+{
+ unsigned long base = gpio_to_base(gpio);
+ u32 bit = gpio_to_bit(gpio);
+ u32 afunc, bfunc;
+
+ /* alternate function is 0..3, with one bit per register */
+ afunc = readl(base + GPIO_AFSLA) & ~bit;
+ bfunc = readl(base + GPIO_AFSLB) & ~bit;
+ if (alternate_function & 1) afunc |= bit;
+ if (alternate_function & 2) bfunc |= bit;
+ writel(afunc, base + GPIO_AFSLA);
+ writel(bfunc, base + GPIO_AFSLB);
+}
+
+void nmk_gpio_dir(int gpio, int dir)
+{
+ unsigned long base = gpio_to_base(gpio);
+ u32 bit = gpio_to_bit(gpio);
+
+ if (dir)
+ writel(bit, base + GPIO_DIRS);
+ else
+ writel(bit, base + GPIO_DIRC);
+}
+
+void nmk_gpio_set(int gpio, int val)
+{
+ unsigned long base = gpio_to_base(gpio);
+ u32 bit = gpio_to_bit(gpio);
+
+ if (val)
+ writel(bit, base + GPIO_DATS);
+ else
+ writel(bit, base + GPIO_DATC);
+}
+
+int nmk_gpio_get(int gpio)
+{
+ unsigned long base = gpio_to_base(gpio);
+ u32 bit = gpio_to_bit(gpio);
+
+ return readl(base + GPIO_DAT) & bit;
+}
#include <config.h>
+#include <common.h>
#include <version.h>
#if defined(CONFIG_OMAP1610)
#include <command.h>
#include <asm/system.h>
#include <asm/cache.h>
+#ifndef CONFIG_L2_OFF
+#include <asm/arch/sys_proto.h>
+#endif
static void cache_flush(void);
LIB = $(obj)lib$(SOC).a
SOBJS := lowlevel_init.o
+SOBJS += reset.o
COBJS += board.o
COBJS += cache.o
/*
- * (C) Copyright 2000
- * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ * Copyright (c) 2009 Samsung Electronics.
+ * Minkyu Kang <mk7.kang@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* MA 02111-1307 USA
*/
-#ifndef _CONSOLE_H_
-#define _CONSOLE_H_
+#include <config.h>
-#include <devices.h>
-
-/*
-** VARIABLES
-*/
-
-extern device_t *stdio_devices[] ;
-extern char *stdio_names[MAX_FILES] ;
-
-#endif
+.global reset_cpu
+reset_cpu:
+ ldr r1, rstctl @ get addr for global reset
+ @ reg
+ mov r3, #0x2 @ full reset pll + mpu
+ str r3, [r1] @ force reset
+ mov r0, r0
+_loop_forever:
+ b _loop_forever
+rstctl:
+ .word PRM_RSTCTRL
@ but we compile with armv5
ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}
-
-
- .align 5
-.global reset_cpu
-reset_cpu:
- ldr r1, rstctl @ get addr for global reset
- @ reg
- mov r3, #0x2 @ full reset pll + mpu
- str r3, [r1] @ force reset
- mov r0, r0
-_loop_forever:
- b _loop_forever
-rstctl:
- .word PRM_RSTCTRL
#ifdef CONFIG_PLL
/* Use PLL0 as main clock */
sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
+
+#ifdef CONFIG_LCD
+ /* Set up pixel clock for the LCDC */
+ sm_writel(PM_GCCTRL(7), SM_BIT(PLLSEL) | SM_BIT(CEN));
+#endif
#endif
}
PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
}
#endif
+
+#ifdef AT32AP700x_CHIP_HAS_LCDC
+void portmux_enable_lcdc(int pin_config)
+{
+ unsigned long portc_mask = 0;
+ unsigned long portd_mask = 0;
+ unsigned long porte_mask = 0;
+
+ switch (pin_config) {
+ case 0:
+ portc_mask = (1 << 19) /* CC */
+ | (1 << 20) /* HSYNC */
+ | (1 << 21) /* PCLK */
+ | (1 << 22) /* VSYNC */
+ | (1 << 23) /* DVAL */
+ | (1 << 24) /* MODE */
+ | (1 << 25) /* PWR */
+ | (1 << 26) /* DATA0 */
+ | (1 << 27) /* DATA1 */
+ | (1 << 28) /* DATA2 */
+ | (1 << 29) /* DATA3 */
+ | (1 << 30) /* DATA4 */
+ | (1 << 31); /* DATA5 */
+
+ portd_mask = (1 << 0) /* DATA6 */
+ | (1 << 1) /* DATA7 */
+ | (1 << 2) /* DATA8 */
+ | (1 << 3) /* DATA9 */
+ | (1 << 4) /* DATA10 */
+ | (1 << 5) /* DATA11 */
+ | (1 << 6) /* DATA12 */
+ | (1 << 7) /* DATA13 */
+ | (1 << 8) /* DATA14 */
+ | (1 << 9) /* DATA15 */
+ | (1 << 10) /* DATA16 */
+ | (1 << 11) /* DATA17 */
+ | (1 << 12) /* DATA18 */
+ | (1 << 13) /* DATA19 */
+ | (1 << 14) /* DATA20 */
+ | (1 << 15) /* DATA21 */
+ | (1 << 16) /* DATA22 */
+ | (1 << 17); /* DATA23 */
+ break;
+
+ case 1:
+ portc_mask = (1 << 20) /* HSYNC */
+ | (1 << 21) /* PCLK */
+ | (1 << 22) /* VSYNC */
+ | (1 << 25) /* PWR */
+ | (1 << 31); /* DATA5 */
+
+ portd_mask = (1 << 0) /* DATA6 */
+ | (1 << 1) /* DATA7 */
+ | (1 << 7) /* DATA13 */
+ | (1 << 8) /* DATA14 */
+ | (1 << 9) /* DATA15 */
+ | (1 << 16) /* DATA22 */
+ | (1 << 17); /* DATA23 */
+
+ porte_mask = (1 << 0) /* CC */
+ | (1 << 1) /* DVAL */
+ | (1 << 2) /* MODE */
+ | (1 << 3) /* DATA0 */
+ | (1 << 4) /* DATA1 */
+ | (1 << 5) /* DATA2 */
+ | (1 << 6) /* DATA3 */
+ | (1 << 7) /* DATA4 */
+ | (1 << 8) /* DATA8 */
+ | (1 << 9) /* DATA9 */
+ | (1 << 10) /* DATA10 */
+ | (1 << 11) /* DATA11 */
+ | (1 << 12) /* DATA12 */
+ | (1 << 13) /* DATA16 */
+ | (1 << 14) /* DATA17 */
+ | (1 << 15) /* DATA18 */
+ | (1 << 16) /* DATA19 */
+ | (1 << 17) /* DATA20 */
+ | (1 << 18); /* DATA21 */
+ break;
+ }
+
+ /* REVISIT: Some pins are probably pure outputs */
+ portmux_select_peripheral(PORTMUX_PORT_C, portc_mask,
+ PORTMUX_FUNC_A, PORTMUX_BUSKEEPER);
+ portmux_select_peripheral(PORTMUX_PORT_D, portd_mask,
+ PORTMUX_FUNC_A, PORTMUX_BUSKEEPER);
+ portmux_select_peripheral(PORTMUX_PORT_E, porte_mask,
+ PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);
+}
+#endif
CEXTRA := initcode.o
SEXTRA := start.o
SOBJS := interrupt.o cache.o
-COBJS-y := cpu.o traps.o interrupts.o reset.o serial.o watchdog.o
+COBJS-y += cpu.o
+COBJS-y += interrupts.o
COBJS-$(CONFIG_JTAG_CONSOLE) += jtag-console.o
+COBJS-y += os_log.o
+COBJS-y += reset.o
+COBJS-y += serial.o
+COBJS-y += traps.o
+COBJS-y += watchdog.o
ifeq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
COBJS-y += initcode.o
*/
#include <common.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <asm/blackfin.h>
#ifndef CONFIG_JTAG_CONSOLE_TIMEOUT
int drv_jtag_console_init(void)
{
- device_t dev;
+ struct stdio_dev dev;
int ret;
memset(&dev, 0x00, sizeof(dev));
dev.tstc = jtag_tstc;
dev.getc = jtag_getc;
- ret = device_register(&dev);
+ ret = stdio_register(&dev);
return (ret == 0 ? 1 : ret);
}
--- /dev/null
+/*
+ * functions for handling OS log buffer
+ *
+ * Copyright (c) 2009 Analog Devices Inc.
+ *
+ * Licensed under the 2-clause BSD.
+ */
+
+#include <common.h>
+
+#define OS_LOG_MAGIC 0xDEADBEEF
+#define OS_LOG_MAGIC_ADDR ((unsigned long *)0x4f0)
+#define OS_LOG_PTR_ADDR ((char **)0x4f4)
+
+bool bfin_os_log_check(void)
+{
+ if (*OS_LOG_MAGIC_ADDR != OS_LOG_MAGIC)
+ return false;
+ *OS_LOG_MAGIC_ADDR = 0;
+ return true;
+}
+
+void bfin_os_log_dump(void)
+{
+ char *log = *OS_LOG_PTR_ADDR;
+ while (*log) {
+ puts(log);
+ log += strlen(log) + 1;
+ }
+}
LOCAL_CFLAGS += -I$(TOPDIR)/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux
CFLAGS += $(LOCAL_CFLAGS)
-HOST_CFLAGS += $(LOCAL_CFLAGS)
+HOSTCFLAGS += $(LOCAL_CFLAGS)
COBJS-$(CONFIG_IXP4XX_NPE) := npe.o \
miiphy.o \
#include "../../board/freescale/common/fsl_diu_fb.h"
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
-#include <devices.h>
+#include <stdio_dev.h>
#include <video_fb.h>
#endif
/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007. All rights reserved.
+ * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007.
* Copyright (C) 2009 DENX Software Engineering <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
- * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved.
+ * Copyright Freescale Semiconductor, Inc. 2004, 2006.
*
* See file CREDITS for list of people who contributed to this
* project.
COBJS-y += ecc.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_FSL_SERDES) += serdes.o
-COBJS-$(CONFIG_83XX_GENERIC_PCI) += pci.o
-COBJS-$(CONFIG_83XX_GENERIC_PCIE) += pcie.o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS-$(CONFIG_PCIE) += pcie.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS := $(COBJS-y)
im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
#endif
#ifdef CONFIG_USB_EHCI_FSL
+#ifndef CONFIG_MPC834x
uint32_t temp;
struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
udelay(1000);
} while (!(temp & PHY_CLK_VALID));
#endif
+#endif
}
int cpu_init_r (void)
/*
* Freescale SerDes initialization routine
*
- * Copyright (C) 2007 Freescale Semicondutor, Inc. All rights reserved.
+ * Copyright (C) 2007 Freescale Semicondutor, Inc.
* Copyright (C) 2008 MontaVista Software, Inc. All rights reserved.
*
* Author: Li Yang <leoli@freescale.com>
/*
- * Copyright (C) 2008 Freescale Semicondutor, Inc. All rights reserved.
+ * Copyright (C) 2008 Freescale Semicondutor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
- out_be32(&ddr->sdram_mode_1, regs->ddr_sdram_mode);
+ out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
udelay(200);
asm volatile("sync;isync");
- out_be32(&ddr->sdram_cfg_1, regs->ddr_sdram_cfg);
+ out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
/*
* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
#include <stdarg.h>
#include <lcdvideo.h>
#include <linux/types.h>
-#include <devices.h>
+#include <stdio_dev.h>
#if defined(CONFIG_POST)
#include <post.h>
#endif
#include <timestamp.h>
#include <i2c.h>
#include <linux/types.h>
-#include <devices.h>
+#include <stdio_dev.h>
#ifdef CONFIG_VIDEO
{
int error, devices = 1;
- device_t videodev;
+ struct stdio_dev videodev;
video_init ((void *)(gd->fb_base)); /* Video initialization */
videodev.putc = video_putc; /* 'putc' function */
videodev.puts = video_puts; /* 'puts' function */
- error = device_register (&videodev);
+ error = stdio_register (&videodev);
return (error == 0) ? devices : error;
}
j++;
}
}
- if (j == 2) {
+ if (j == 2)
*memctl_interleaving = 1;
- printf("\nMemory controller interleaving enabled: ");
-
- switch (pinfo->memctl_opts[0].memctl_interleaving_mode) {
- case FSL_DDR_CACHE_LINE_INTERLEAVING:
- printf("Cache-line interleaving!\n");
- break;
- case FSL_DDR_PAGE_INTERLEAVING:
- printf("Page interleaving!\n");
- break;
- case FSL_DDR_BANK_INTERLEAVING:
- printf("Bank interleaving!\n");
- break;
- case FSL_DDR_SUPERBANK_INTERLEAVING:
- printf("Super bank interleaving\n");
- default:
- break;
- }
- }
-
/* Check that all controllers are rank interleaving. */
j = 0;
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
j++;
}
}
- if (j == 2) {
+ if (j == 2)
*rank_interleaving = 1;
- printf("Bank(chip-select) interleaving enabled: ");
-
- switch (pinfo->memctl_opts[0].ba_intlv_ctl &
- FSL_DDR_CS0_CS1_CS2_CS3) {
- case FSL_DDR_CS0_CS1_CS2_CS3:
- printf("CS0+CS1+CS2+CS3\n");
- break;
- case FSL_DDR_CS0_CS1:
- printf("CS0+CS1\n");
- break;
- case FSL_DDR_CS2_CS3:
- printf("CS2+CS3\n");
- break;
- case FSL_DDR_CS0_CS1_AND_CS2_CS3:
- printf("CS0+CS1 and CS2+CS3\n");
- default:
- break;
- }
- }
-
if (*memctl_interleaving) {
unsigned long long addr, total_mem_per_ctlr = 0;
/*
fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
unsigned int memctl_interleaved,
unsigned int ctrl_num);
+
+void board_add_ram_info(int use_default)
+{
+#if defined(CONFIG_MPC85xx)
+ volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+#elif defined(CONFIG_MPC86xx)
+ volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
+#endif
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+ uint32_t cs0_config = in_be32(&ddr->cs0_config);
+#endif
+ uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
+ int cas_lat;
+
+ puts(" (DDR");
+ switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
+ SDRAM_CFG_SDRAM_TYPE_SHIFT) {
+ case SDRAM_TYPE_DDR1:
+ puts("1");
+ break;
+ case SDRAM_TYPE_DDR2:
+ puts("2");
+ break;
+ case SDRAM_TYPE_DDR3:
+ puts("3");
+ break;
+ default:
+ puts("?");
+ break;
+ }
+
+ if (sdram_cfg & SDRAM_CFG_32_BE)
+ puts(", 32-bit");
+ else
+ puts(", 64-bit");
+
+ /* Calculate CAS latency based on timing cfg values */
+ cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
+ if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1)
+ cas_lat += (8 << 1);
+ printf(", CL=%d", cas_lat >> 1);
+ if (cas_lat & 0x1)
+ puts(".5");
+
+ if (sdram_cfg & SDRAM_CFG_ECC_EN)
+ puts(", ECC on)");
+ else
+ puts(", ECC off)");
+
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+ if (cs0_config & 0x20000000) {
+ puts("\n");
+ puts(" DDR Controller Interleaving Mode: ");
+
+ switch ((cs0_config >> 24) & 0xf) {
+ case FSL_DDR_CACHE_LINE_INTERLEAVING:
+ puts("cache line");
+ break;
+ case FSL_DDR_PAGE_INTERLEAVING:
+ puts("page");
+ break;
+ case FSL_DDR_BANK_INTERLEAVING:
+ puts("bank");
+ break;
+ case FSL_DDR_SUPERBANK_INTERLEAVING:
+ puts("super-bank");
+ break;
+ default:
+ puts("invalid");
+ break;
+ }
+ }
+#endif
+
+ if ((sdram_cfg >> 8) & 0x7f) {
+ puts("\n");
+ puts(" DDR Chip-Select Interleaving Mode: ");
+ switch(sdram_cfg >> 8 & 0x7f) {
+ case FSL_DDR_CS0_CS1_CS2_CS3:
+ puts("CS0+CS1+CS2+CS3");
+ break;
+ case FSL_DDR_CS0_CS1:
+ puts("CS0+CS1");
+ break;
+ case FSL_DDR_CS2_CS3:
+ puts("CS2+CS3");
+ break;
+ case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+ puts("CS0+CS1 and CS2+CS3");
+ break;
+ default:
+ puts("invalid");
+ break;
+ }
+ }
+}
COBJS += 4xx_pci.o
COBJS += 4xx_pcie.o
COBJS += bedbug_405.o
+ifdef CONFIG_CMD_CHIP_CONFIG
+COBJS += cmd_chip_config.o
+endif
COBJS += commproc.o
COBJS += cpu.o
COBJS += cpu_init.o
COBJS += i2c.o
COBJS += interrupts.o
COBJS += iop480_uart.o
-COBJS += ndfc.o
COBJS += sdram.o
COBJS += speed.o
COBJS += tlb.o
--- /dev/null
+/*
+ * (C) Copyright 2008-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2009
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <asm/ppc4xx_config.h>
+#include <asm/io.h>
+
+static void print_configs(int cur_config_nr)
+{
+ int i;
+
+ for (i = 0; i < ppc4xx_config_count; i++) {
+ printf("%-16s - %s", ppc4xx_config_val[i].label,
+ ppc4xx_config_val[i].description);
+ if (i == cur_config_nr)
+ printf(" ***");
+ printf("\n");
+ }
+
+}
+
+static int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int i;
+ int ret;
+ int cur_config_nr = -1;
+ u8 cur_config[CONFIG_4xx_CONFIG_BLOCKSIZE];
+
+#ifdef CONFIG_CMD_EEPROM
+ ret = eeprom_read(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR,
+ CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET,
+ cur_config, CONFIG_4xx_CONFIG_BLOCKSIZE);
+#else
+ ret = i2c_read(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR,
+ CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET,
+ 1, cur_config, CONFIG_4xx_CONFIG_BLOCKSIZE);
+#endif
+ if (ret) {
+ printf("Error reading EEPROM at addr 0x%x\n",
+ CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR);
+ return -1;
+ }
+
+ /*
+ * Search the current configuration
+ */
+ for (i = 0; i < ppc4xx_config_count; i++) {
+ if (memcmp(cur_config, ppc4xx_config_val[i].val,
+ CONFIG_4xx_CONFIG_BLOCKSIZE) == 0)
+ cur_config_nr = i;
+ }
+
+ if (cur_config_nr == -1) {
+ printf("Warning: The I2C bootstrap values don't match any"
+ " of the available options!\n");
+ printf("I2C bootstrap EEPROM values are (I2C address 0x%02x):\n",
+ CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR);
+ for (i = 0; i < CONFIG_4xx_CONFIG_BLOCKSIZE; i++) {
+ printf("%02x ", cur_config[i]);
+ }
+ printf("\n");
+ }
+
+ if (argc < 2) {
+ printf("Available configurations (I2C address 0x%02x):\n",
+ CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR);
+ print_configs(cur_config_nr);
+ return 0;
+ }
+
+ for (i = 0; i < ppc4xx_config_count; i++) {
+ /*
+ * Search for configuration name/label
+ */
+ if (strcmp(argv[1], ppc4xx_config_val[i].label) == 0) {
+ printf("Using configuration:\n%-16s - %s\n",
+ ppc4xx_config_val[i].label,
+ ppc4xx_config_val[i].description);
+
+#ifdef CONFIG_CMD_EEPROM
+ ret = eeprom_write(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR,
+ CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET,
+ ppc4xx_config_val[i].val,
+ CONFIG_4xx_CONFIG_BLOCKSIZE);
+#else
+ ret = i2c_write(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR,
+ CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET,
+ 1, ppc4xx_config_val[i].val,
+ CONFIG_4xx_CONFIG_BLOCKSIZE);
+#endif
+ udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+ if (ret) {
+ printf("Error updating EEPROM at addr 0x%x\n",
+ CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR);
+ return -1;
+ }
+
+ printf("done (dump via 'i2c md %x 0.1 %x')\n",
+ CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR,
+ CONFIG_4xx_CONFIG_BLOCKSIZE);
+ printf("Reset the board for the changes to"
+ " take effect\n");
+ return 0;
+ }
+ }
+
+ printf("Configuration %s not found!\n", argv[1]);
+ print_configs(cur_config_nr);
+ return -1;
+}
+
+U_BOOT_CMD(
+ chip_config, 2, 0, do_chip_config,
+ "program the I2C bootstrap EEPROM",
+ "[config-label]"
+);
mtdcr (cpc0_sys0, sys0);
mtdcr (cpc0_sys1, sys1);
mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
- mtspr (dbcr0, 0x20000000); /* Reset the chip */
+ mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */
return 1;
}
uint pvr = get_pvr();
ulong clock = gd->cpu_clk;
char buf[32];
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ u32 reg;
+#endif
#if !defined(CONFIG_IOP480)
char addstr[64] = "";
strcpy(addstr, "No RAID 6 support");
break;
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
case PVR_460EX_RA:
puts("EX Rev. A");
strcpy(addstr, "No Security/Kasumi support");
strcpy(addstr, "Security/Kasumi support");
break;
+ case PVR_460EX_RB:
+ puts("EX Rev. B");
+ mfsdr(SDR0_ECID3, reg);
+ if (reg & 0x00100000)
+ strcpy(addstr, "No Security/Kasumi support");
+ else
+ strcpy(addstr, "Security/Kasumi support");
+ break;
+
case PVR_460GT_RA:
puts("GT Rev. A");
strcpy(addstr, "No Security/Kasumi support");
strcpy(addstr, "Security/Kasumi support");
break;
+ case PVR_460GT_RB:
+ puts("GT Rev. B");
+ mfsdr(SDR0_ECID3, reg);
+ if (reg & 0x00100000)
+ strcpy(addstr, "No Security/Kasumi support");
+ else
+ strcpy(addstr, "Security/Kasumi support");
+ break;
+#endif
+
case PVR_460SX_RA:
puts("SX Rev. A");
strcpy(addstr, "Security support");
board_reset();
#else
#if defined(CONFIG_SYS_4xx_RESET_TYPE)
- mtspr(dbcr0, CONFIG_SYS_4xx_RESET_TYPE << 28);
+ mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
#else
/*
* Initiate system reset in debug control register DBCR
*/
- mtspr(dbcr0, 0x30000000);
+ mtspr(SPRN_DBCR0, 0x30000000);
#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
#endif /* defined(CONFIG_BOARD_RESET) */
/*
* Clear TSR(WIS) bit
*/
- mtspr(tsr, 0x40000000);
+ mtspr(SPRN_TSR, 0x40000000);
}
#endif /* CONFIG_WATCHDOG */
/* Reset processor if configuration changed */
if (reset_needed) {
__asm__ __volatile__ ("sync; isync");
- mtspr(dbcr0, 0x20000000);
+ mtspr(SPRN_DBCR0, 0x20000000);
}
#endif
}
* Init PIT
*/
#if defined(CONFIG_440)
- val = mfspr( tcr );
+ val = mfspr( SPRN_TCR );
val &= (~0x04400000); /* clear DIS & ARE */
- mtspr( tcr, val );
- mtspr( dec, 0 ); /* Prevent exception after TSR clear*/
- mtspr( decar, 0 ); /* clear reload */
- mtspr( tsr, 0x08000000 ); /* clear DEC status */
+ mtspr( SPRN_TCR, val );
+ mtspr( SPRN_DEC, 0 ); /* Prevent exception after TSR clear*/
+ mtspr( SPRN_DECAR, 0 ); /* clear reload */
+ mtspr( SPRN_TSR, 0x08000000 ); /* clear DEC status */
val = gd->bd->bi_intfreq/1000; /* 1 msec */
- mtspr( decar, val ); /* Set auto-reload value */
- mtspr( dec, val ); /* Set inital val */
+ mtspr( SPRN_DECAR, val ); /* Set auto-reload value */
+ mtspr( SPRN_DEC, val ); /* Set inital val */
#else
set_pit(gd->bd->bi_intfreq / 1000);
#endif
/*
* Enable PIT
*/
- val = mfspr(tcr);
+ val = mfspr(SPRN_TCR);
val |= 0x04400000;
- mtspr(tcr, val);
+ mtspr(SPRN_TCR, val);
/*
* Set EVPR to 0
sysInfo->freqUART = sysInfo->freqPLB;
/* Figure which timer source to use */
- if (mfspr(ccr1) & 0x0080) { /* External Clock, assume same as SYS_CLK */
+ if (mfspr(SPRN_CCR1) & 0x0080) {
+ /* External Clock, assume same as SYS_CLK */
temp = sysInfo->freqProcessor / 2; /* Max extern clock speed */
if (CONFIG_SYS_CLK_FREQ > temp)
sysInfo->freqTmrClk = temp;
sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv;
+ sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv;
+
sysInfo->freqUART = sysInfo->freqProcessor * pllmr0_ccdv;
}
| Core bug fix. Clear the esr
+-----------------------------------------------------------------*/
li r0,0
- mtspr esr,r0
+ mtspr SPRN_ESR,r0
/*----------------------------------------------------------------*/
/* Clear and set up some registers. */
/*----------------------------------------------------------------*/
dccci r0,r0 /* NOTE: operands not used for 440 */
sync
li r0,0
- mtspr srr0,r0
- mtspr srr1,r0
- mtspr csrr0,r0
- mtspr csrr1,r0
+ mtspr SPRN_SRR0,r0
+ mtspr SPRN_SRR1,r0
+ mtspr SPRN_CSRR0,r0
+ mtspr SPRN_CSRR1,r0
/* NOTE: 440GX adds machine check status regs */
#if defined(CONFIG_440) && !defined(CONFIG_440GP)
- mtspr mcsrr0,r0
- mtspr mcsrr1,r0
- mfspr r1,mcsr
- mtspr mcsr,r1
+ mtspr SPRN_MCSRR0,r0
+ mtspr SPRN_MCSRR1,r0
+ mfspr r1,SPRN_MCSR
+ mtspr SPRN_MCSR,r1
#endif
/*----------------------------------------------------------------*/
*/
lis r1,0x0030 /* store gathering & broadcast disable */
ori r1,r1,0x6000 /* cache touch */
- mtspr ccr0,r1
+ mtspr SPRN_CCR0,r1
/*----------------------------------------------------------------*/
/* Initialize debug */
/*----------------------------------------------------------------*/
- mfspr r1,dbcr0
+ mfspr r1,SPRN_DBCR0
andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
bne skip_debug_init /* if set, don't clear debug register */
- mtspr dbcr0,r0
- mtspr dbcr1,r0
- mtspr dbcr2,r0
- mtspr iac1,r0
- mtspr iac2,r0
- mtspr iac3,r0
- mtspr dac1,r0
- mtspr dac2,r0
- mtspr dvc1,r0
- mtspr dvc2,r0
-
- mfspr r1,dbsr
- mtspr dbsr,r1 /* Clear all valid bits */
+ mtspr SPRN_DBCR0,r0
+ mtspr SPRN_DBCR1,r0
+ mtspr SPRN_DBCR2,r0
+ mtspr SPRN_IAC1,r0
+ mtspr SPRN_IAC2,r0
+ mtspr SPRN_IAC3,r0
+ mtspr SPRN_DAC1,r0
+ mtspr SPRN_DAC2,r0
+ mtspr SPRN_DVC1,r0
+ mtspr SPRN_DVC2,r0
+
+ mfspr r1,SPRN_DBSR
+ mtspr SPRN_DBSR,r1 /* Clear all valid bits */
skip_debug_init:
#if defined (CONFIG_440SPE)
| j. TCS: Timebase increments from CPU clock.
+-----------------------------------------------------------------*/
li r0,0
- mtspr ccr1, r0
+ mtspr SPRN_CCR1, r0
/*----------------------------------------------------------------+
| Reset the timebase.
| The previous write to CCR1 sets the timebase source.
+-----------------------------------------------------------------*/
- mtspr tbl, r0
- mtspr tbu, r0
+ mtspr SPRN_TBWL, r0
+ mtspr SPRN_TBWU, r0
#endif
/*----------------------------------------------------------------*/
/* Setup interrupt vectors */
/*----------------------------------------------------------------*/
- mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
+ mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
li r1,0x0100
- mtspr ivor0,r1 /* Critical input */
+ mtspr SPRN_IVOR0,r1 /* Critical input */
li r1,0x0200
- mtspr ivor1,r1 /* Machine check */
+ mtspr SPRN_IVOR1,r1 /* Machine check */
li r1,0x0300
- mtspr ivor2,r1 /* Data storage */
+ mtspr SPRN_IVOR2,r1 /* Data storage */
li r1,0x0400
- mtspr ivor3,r1 /* Instruction storage */
+ mtspr SPRN_IVOR3,r1 /* Instruction storage */
li r1,0x0500
- mtspr ivor4,r1 /* External interrupt */
+ mtspr SPRN_IVOR4,r1 /* External interrupt */
li r1,0x0600
- mtspr ivor5,r1 /* Alignment */
+ mtspr SPRN_IVOR5,r1 /* Alignment */
li r1,0x0700
- mtspr ivor6,r1 /* Program check */
+ mtspr SPRN_IVOR6,r1 /* Program check */
li r1,0x0800
- mtspr ivor7,r1 /* Floating point unavailable */
+ mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
li r1,0x0c00
- mtspr ivor8,r1 /* System call */
+ mtspr SPRN_IVOR8,r1 /* System call */
li r1,0x0a00
- mtspr ivor9,r1 /* Auxiliary Processor unavailable */
+ mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
li r1,0x0900
- mtspr ivor10,r1 /* Decrementer */
+ mtspr SPRN_IVOR10,r1 /* Decrementer */
li r1,0x1300
- mtspr ivor13,r1 /* Data TLB error */
+ mtspr SPRN_IVOR13,r1 /* Data TLB error */
li r1,0x1400
- mtspr ivor14,r1 /* Instr TLB error */
+ mtspr SPRN_IVOR14,r1 /* Instr TLB error */
li r1,0x2000
- mtspr ivor15,r1 /* Debug */
+ mtspr SPRN_IVOR15,r1 /* Debug */
/*----------------------------------------------------------------*/
/* Configure cache regions */
/*----------------------------------------------------------------*/
- mtspr inv0,r0
- mtspr inv1,r0
- mtspr inv2,r0
- mtspr inv3,r0
- mtspr dnv0,r0
- mtspr dnv1,r0
- mtspr dnv2,r0
- mtspr dnv3,r0
- mtspr itv0,r0
- mtspr itv1,r0
- mtspr itv2,r0
- mtspr itv3,r0
- mtspr dtv0,r0
- mtspr dtv1,r0
- mtspr dtv2,r0
- mtspr dtv3,r0
+ mtspr SPRN_INV0,r0
+ mtspr SPRN_INV1,r0
+ mtspr SPRN_INV2,r0
+ mtspr SPRN_INV3,r0
+ mtspr SPRN_DNV0,r0
+ mtspr SPRN_DNV1,r0
+ mtspr SPRN_DNV2,r0
+ mtspr SPRN_DNV3,r0
+ mtspr SPRN_ITV0,r0
+ mtspr SPRN_ITV1,r0
+ mtspr SPRN_ITV2,r0
+ mtspr SPRN_ITV3,r0
+ mtspr SPRN_DTV0,r0
+ mtspr SPRN_DTV1,r0
+ mtspr SPRN_DTV2,r0
+ mtspr SPRN_DTV3,r0
/*----------------------------------------------------------------*/
/* Cache victim limits */
*/
lis r1,0x0001
ori r1,r1,0xf800
- mtspr ivlim,r1
- mtspr dvlim,r1
+ mtspr SPRN_IVLIM,r1
+ mtspr SPRN_DVLIM,r1
/*----------------------------------------------------------------+
|Initialize MMUCR[STID] = 0.
+-----------------------------------------------------------------*/
- mfspr r0,mmucr
+ mfspr r0,SPRN_MMUCR
addis r1,0,0xFFFF
ori r1,r1,0xFF00
and r0,r0,r1
- mtspr mmucr,r0
+ mtspr SPRN_MMUCR,r0
/*----------------------------------------------------------------*/
/* Clear all TLB entries -- TID = 0, TS = 0 */
/*----------------------------------------------------------------*/
addis r0,0,0x0000
- li r1,0x003f /* 64 TLB entries */
- mtctr r1
+#ifdef CONFIG_SYS_RAMBOOT
li r4,0 /* Start with TLB #0 */
+#else
+ li r4,1 /* Start with TLB #1 */
+#endif
+ li r1,64 /* 64 TLB entries */
+ sub r1,r1,r4 /* calculate last TLB # */
+ mtctr r1
rsttlb:
#ifdef CONFIG_SYS_RAMBOOT
tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
b _start
3: li r0,0
- mtspr srr1,r0 /* Keep things disabled for now */
+ mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
mflr r1
- mtspr srr0,r1
+ mtspr SPRN_SRR0,r1
rfi
#endif /* CONFIG_440 */
/*----------------------------------------------------------------*/
li r0,0x0000
lis r1,0xffff
- mtspr dec,r0 /* prevent dec exceptions */
- mtspr tbl,r0 /* prevent fit & wdt exceptions */
- mtspr tbu,r0
- mtspr tsr,r1 /* clear all timer exception status */
- mtspr tcr,r0 /* disable all */
- mtspr esr,r0 /* clear exception syndrome register */
+ mtspr SPRN_DEC,r0 /* prevent dec exceptions */
+ mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
+ mtspr SPRN_TBWU,r0
+ mtspr SPRN_TSR,r1 /* clear all timer exception status */
+ mtspr SPRN_TCR,r0 /* disable all */
+ mtspr SPRN_ESR,r0 /* clear exception syndrome register */
mtxer r0 /* clear integer exception register */
/*----------------------------------------------------------------*/
#if defined(CONFIG_SYS_INIT_DBCR)
lis r1,0xffff
ori r1,r1,0xffff
- mtspr dbsr,r1 /* Clear all status bits */
+ mtspr SPRN_DBSR,r1 /* Clear all status bits */
lis r0,CONFIG_SYS_INIT_DBCR@h
ori r0,r0,CONFIG_SYS_INIT_DBCR@l
- mtspr dbcr0,r0
+ mtspr SPRN_DBCR0,r0
isync
#endif
/* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
lis r1,0x0201
ori r1,r1,0xf808
- mtspr dvlim,r1
+ mtspr SPRN_DVLIM,r1
lis r1,0x0808
ori r1,r1,0x0808
- mtspr dnv0,r1
- mtspr dnv1,r1
- mtspr dnv2,r1
- mtspr dnv3,r1
- mtspr dtv0,r1
- mtspr dtv1,r1
- mtspr dtv2,r1
- mtspr dtv3,r1
+ mtspr SPRN_DNV0,r1
+ mtspr SPRN_DNV1,r1
+ mtspr SPRN_DNV2,r1
+ mtspr SPRN_DNV3,r1
+ mtspr SPRN_DTV0,r1
+ mtspr SPRN_DTV1,r1
+ mtspr SPRN_DTV2,r1
+ mtspr SPRN_DTV3,r1
msync
isync
#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
/* Set up some machine state registers. */
/*----------------------------------------------------------------------- */
addi r0,r0,0x0000 /* initialize r0 to zero */
- mtspr esr,r0 /* clear Exception Syndrome Reg */
+ mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */
mttcr r0 /* timer control register */
mtexier r0 /* disable all interrupts */
addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
/*----------------------------------------------------------------------- */
addi r4,r0,0x0000
#if !defined(CONFIG_405EX)
- mtspr sgr,r4
+ mtspr SPRN_SGR,r4
#else
/*
* On 405EX, completely clearing the SGR leads to PPC hangup
*/
lis r3,0x0000
ori r3,r3,0x7FFC
- mtspr sgr,r3
+ mtspr SPRN_SGR,r3
#endif
- mtspr dcwr,r4
+ mtspr SPRN_DCWR,r4
mtesr r4 /* clear Exception Syndrome Reg */
mttcr r4 /* clear Timer Control Reg */
mtxer r4 /* clear Fixed-Point Exception Reg */
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
- mtspr csrr0,r2
- mtspr csrr1,r0
+ mtspr SPRN_CSRR0,r2
+ mtspr SPRN_CSRR1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
- mtspr mcsrr0,r2
- mtspr mcsrr1,r0
+ mtspr SPRN_MCSRR0,r2
+ mtspr SPRN_MCSRR1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
/* set TFLOOR/NFLOOR to 0 again */
lis r6,0x0001
ori r6,r6,0xf800
- mtspr dvlim,r6
+ mtspr SPRN_DVLIM,r6
lis r6,0x0000
ori r6,r6,0x0000
- mtspr dnv0,r6
- mtspr dnv1,r6
- mtspr dnv2,r6
- mtspr dnv3,r6
- mtspr dtv0,r6
- mtspr dtv1,r6
- mtspr dtv2,r6
- mtspr dtv3,r6
+ mtspr SPRN_DNV0,r6
+ mtspr SPRN_DNV1,r6
+ mtspr SPRN_DNV2,r6
+ mtspr SPRN_DNV3,r6
+ mtspr SPRN_DTV0,r6
+ mtspr SPRN_DTV1,r6
+ mtspr SPRN_DTV2,r6
+ mtspr SPRN_DTV3,r6
msync
isync
#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
isync
/* Clear all potential pending exceptions */
- mfspr r1,mcsr
- mtspr mcsr,r1
+ mfspr r1,SPRN_MCSR
+ mtspr SPRN_MCSR,r1
#ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH
addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
#else
__440_msr_set:
addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
- mtspr srr1,r7
+ mtspr SPRN_SRR1,r7
mflr r7
- mtspr srr0,r7
+ mtspr SPRN_SRR0,r7
rfi
__440_msr_continue:
#endif
* Not sure if this is needed...
*/
addis r3,0,0x1000
- mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
+ mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
/* execution will continue from the poweron */
/* vector of 0xfffffffc */
#endif /* CONFIG_405EP */
#include <version.h>
#include <stdarg.h>
#include <linux/types.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <lcd.h>
#include <asm/arch/pxa-regs.h>
--- /dev/null
+/*
+ * (C) Copyright 2008-2009
+ * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
+ * Jens Scharsig <esw@bus-elektronik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+U-Boot vcxk video controller driver
+======================================
+
+By defining CONFIG_VIDEO_VCXK this driver can be used with VC2K, VC4K and
+VC8K devices on following boards:
+
+board | ARCH | Vendor
+-----------------------------------------------------------------------
+EB+CPU5282-T1 | MCF5282 | BuS Elektronik GmbH & Co. KG
+EB+MCF-EVB123 | MCF5282 | BuS Elektronik GmbH & Co. KG
+EB+CPUx9K2 | AT91RM9200 | BuS Elektronik GmbH & Co. KG
+ZLSA | AT91RM9200 | Ruf Telematik AG
+
+Driver configuration
+--------------------
+
+The driver needs some defines to describe the target hardware:
+
+CONFIG_SYS_VCXK_BASE
+
+ base address of VCxK hardware memory
+
+CONFIG_SYS_VCXK_DEFAULT_LINEALIGN
+
+ defines the physical alignment of a pixel row
+
+CONFIG_SYS_VCXK_DOUBLEBUFFERED
+
+ some boards that use vcxk prevent read from framebuffer memory.
+ define this option to enable double buffering (needs 16KiB RAM)
+
+CONFIG_SYS_VCXK_<xxxx>_PIN
+
+ defines the number of the I/O line PIN in the port
+ valid values for <xxxx> are:
+
+ ACKNOWLEDGE
+ describes the acknowledge line from vcxk hardware
+
+ ENABLE
+ describes the enable line to vcxk hardware
+
+ INVERT
+ describes the invert line to vcxk hardware
+
+ RESET
+ describes the reset line to vcxk hardware
+
+ REQUEST
+ describes the request line to vcxk hardware
+
+CONFIG_SYS_VCXK_<xxxx>_PORT
+
+ defines the I/O port which is connected with the line
+ for valid values for <xxxx> see CONFIG_SYS_VCXK_<xxxx>_PIN
+
+CONFIG_SYS_VCXK_<xxxx>_DDR
+
+ defines the register which configures the direction
+ for valid values for <xxxx> see CONFIG_SYS_VCXK_<xxxx>_PIN
--- /dev/null
+Domain Name System
+-------------------------------------------
+
+The Domain Name System (DNS) is a hierarchical naming system for computers,
+services, or any resource participating in the Internet. It associates various
+information with domain names assigned to each of the participants. Most
+importantly, it translates domain names meaningful to humans into the numerical
+(binary) identifiers associated with networking equipment for the purpose of
+locating and addressing these devices world-wide. An often used analogy to
+explain the Domain Name System is that it serves as the "phone book" for the
+Internet by translating human-friendly computer hostnames into IP addresses.
+For example, www.example.com translates to 208.77.188.166.
+
+For more information on DNS - http://en.wikipedia.org/wiki/Domain_Name_System
+
+U-Boot and DNS
+------------------------------------------
+
+CONFIG_CMD_DNS - controls if the 'dns' command is compiled in. If it is, it
+ will send name lookups to the dns server (env var 'dnsip')
+ Turning this option on will about abou 1k to U-Boot's size.
+
+ Example:
+
+bfin> print dnsip
+dnsip=192.168.0.1
+
+bfin> dns www.google.com
+66.102.1.104
+
+ By default, dns does nothing except print the IP number on
+ the default console - which by itself, would be pretty
+ useless. Adding a third argument to the dns command will
+ use that as the environment variable to be set.
+
+ Example:
+
+bfin> print googleip
+## Error: "googleip" not defined
+bfin> dns www.google.com googleip
+64.233.161.104
+bfin> print googleip
+googleip=64.233.161.104
+bfin> ping ${googleip}
+Using Blackfin EMAC device
+host 64.233.161.104 is alive
+
+ In this way, you can lookup, and set many more meaningful
+ things.
+
+bfin> sntp
+ntpserverip not set
+bfin> dns pool.ntp.org ntpserverip
+72.18.205.156
+bfin> sntp
+Date: 2009-07-18 Time: 4:06:57
+
+ For some helpful things that can be related to DNS in U-Boot,
+ look at the top level README for these config options:
+ CONFIG_CMD_DHCP
+ CONFIG_BOOTP_DNS
+ CONFIG_BOOTP_DNS2
=====
The current NAND implementation is based on what is in recent
-Linux kernels. The old legacy implementation has been disabled,
-and will be removed soon.
+Linux kernels. The old legacy implementation has been removed.
If you have board code which used CONFIG_NAND_LEGACY, you'll need
to convert to the current NAND interface for it to continue to work.
@$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec
@ echo "remember to set pcm030_REV to 0 for rev 1245.0 rev or to 1 for rev 1245.1"
-
Alternative SDRAM settings:
#define SDRAM_MODE 0x018D0000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xfe0000)
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000
-
-
-
The flash type is intel 28F640Jx (4096x16) [one device]. Base address
is 0xFF80_0000 which is also where the Hardware Reset Configuration
-Word (HRCW) is stored. Caution should be used to not overwrite the
-HRCW, or "CF RCW" with a Wind River ICE will be required to restore
-the HRCW and allow the board to enter background mode for further
-steps in the flash process.
+Word (HRCW) is stored. Caution should be used to not reset the
+board without having a valid HRCW in place (i.e. erased flash) as
+then a Wind River ICE will be required to restore the HRCW and flash
+image.
Restoring a corrupted or missing flash image:
=============================================
+Note that U-boot versions up to and including 2009.06 had essentially
+two copies of u-boot in flash; one at the very beginning, which set
+the HRCW, and one at the very end, which was the image that was run.
+As of this point in time, the two have been combined into just one
+at the beginning of flash, which provides both the HRCW, and the image
+that is executed. This frees up the remainder of flash for other uses.
+Use of the u-boot command "fli" will indicate what parts are in use.
Details for storing U-boot to flash using a Wind River ICE can be found
on page 19 of the board manual (request ERG-00328-001). The following
is a summary of that information:
- Select the appropriate flash type (listed above)
- Prepare a u-boot image by using the Wind River Convert utility;
by using "Convert and Add file" on the ELF file from your build.
- Convert from FFF0_0000 to FFFF_FFFF (or to FFF3_FFFF if you are
- trying to preserve your old environment settings).
- - Set the start address of the erase/flash process to FFF0_0000
+ Convert from FF80_0000 to FFFF_FFFF (or to FF83_FFFF if you are
+ trying to preserve your old environment settings and user flash).
+ - Set the start address of the erase/flash process to FF80_0000
- Set the target RAM required to 64kB.
- Select sectors for erasing (see note on enviroment below)
- Select Erase and Reprogram.
use all the remaining register file content.
If you wish to preserve your prior U-Boot environment settings,
-then convert (and erase to) 0xFFF3FFFF instead of 0xFFFFFFFF.
+then convert (and erase to) 0xFF83FFFF instead of 0xFFFFFFFF.
The size for converting (and erasing) must be at least as large
as u-boot.bin.
tftp 200000 u-boot.bin
protect off all
- erase fff00000 fff3ffff
- cp.b 200000 fff00000 3ffff
+ erase ff800000 ff83ffff
+ cp.b 200000 ff800000 40000
protect on all
+You may wish to do a "md ff800000 20" operation as a prefix and postfix
+to the above steps to inspect/compare the HRCW before/after as an extra
+safety check before resetting the board upon completion of the reflash.
PCI:
====
for an old and probably incomplete list of such files.
Who: Wolfgang Denk <wd@denx.de> and board maintainers
-
----------------------------
-
-What: Legacy NAND code
-When: April 2009
-Why: Legacy NAND code is deprecated. Similar functionality exists in
- more recent NAND code ported from the Linux kernel.
-Who: Scott Wood <scottwood@freescale.com>
-D__PPC__ -D__BIG_ENDIAN__
CFLAGS += $(EXTRA_CFLAGS)
-HOST_CFLAGS += $(EXTRA_CFLAGS)
+HOSTCFLAGS += $(EXTRA_CFLAGS)
all: $(LIB)
* Video BOOT Graphics Card POST Module
*
* ========================================================================
-* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+* Copyright (C) 2007 Freescale Semiconductor, Inc.
* Jason Jin <Jason.jin@freescale.com>
*
* Copyright (C) 1991-2004 SciTech Software, Inc. All rights reserved.
*
* ========================================================================
*
-* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+* Copyright (C) 2007 Freescale Semiconductor, Inc.
* Jason Jin<Jason.jin@freescale.com>
*
* Copyright (C) 1991-2004 SciTech Software, Inc. All rights reserved.
* BIOS emulator and interface
* to Realmode X86 Emulator Library
*
-* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+* Copyright (C) 2007 Freescale Semiconductor, Inc.
* Jason Jin <Jason.jin@freescale.com>
*
* Copyright (C) 1996-1999 SciTech Software, Inc.
* BIOS emulator and interface
* to Realmode X86 Emulator Library
*
-* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+* Copyright (C) 2007 Freescale Semiconductor, Inc.
* Jason Jin <Jason.jin@freescale.com>
*
* Copyright (C) 1996-1999 SciTech Software, Inc.
_BE_env.biosmem_base = _BE_env.busmem_base + 0x20000;
_BE_env.biosmem_limit = 0xC7FFF;
}
- if (*((u32 *) info->LowMem) == 0)
+ if ((info->LowMem[0] == 0) && (info->LowMem[1] == 0) &&
+ (info->LowMem[2] == 0) && (info->LowMem[3] == 0))
_BE_bios_init((u32 *) info->LowMem);
memcpy((u8 *) M.mem_base, info->LowMem, sizeof(info->LowMem));
}
* BIOS emulator and interface
* to Realmode X86 Emulator Library
*
-* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+* Copyright (C) 2007 Freescale Semiconductor, Inc.
* Jason Jin <Jason.jin@freescale.com>
*
* Copyright (C) 1996-1999 SciTech Software, Inc.
/****************************************************************************
* Realmode X86 Emulator Library
*
-* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+* Copyright (C) 2007 Freescale Semiconductor, Inc.
* Jason Jin <Jason.jin@freescale.com>
*
* Copyright (C) 1991-2004 SciTech Software, Inc.
*
* Realmode X86 Emulator Library
*
-* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+* Copyright (C) 2007 Freescale Semiconductor, Inc.
* Jason Jin <Jason.jin@freescale.com>
*
* Copyright (C) 1991-2004 SciTech Software, Inc.
COBJS-$(CONFIG_IDE_SIL680) += sil680.o
COBJS-$(CONFIG_LIBATA) += libata.o
COBJS-$(CONFIG_PATA_BFIN) += pata_bfin.o
+COBJS-$(CONFIG_SATA_DWC) += sata_dwc.o
COBJS-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
COBJS-$(CONFIG_SCSI_AHCI) += ahci.o
COBJS-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
* Author: Jason Jin<Jason.jin@freescale.com>
* Zhang Wei<wei.zhang@freescale.com>
*
*/
static int ata_scsiop_read_capacity10(ccb *pccb)
{
- u8 buf[8];
+ u32 cap;
if (!ataid[pccb->target]) {
printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
return -EPERM;
}
- memset(buf, 0, 8);
+ cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
+ memcpy(pccb->pdata, &cap, sizeof(cap));
- *(u32 *) buf = le32_to_cpu(ataid[pccb->target]->lba_capacity);
-
- buf[6] = 512 >> 8;
- buf[7] = 512 & 0xff;
-
- memcpy(pccb->pdata, buf, 8);
+ pccb->pdata[4] = pccb->pdata[5] = 0;
+ pccb->pdata[6] = 512 >> 8;
+ pccb->pdata[7] = 512 & 0xff;
return 0;
}
#include <ata.h>
extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-extern int curr_device;
+extern int sata_curr_device;
#define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */
dev_print (&sata_dev_desc[devno]);
/* initialize partition type */
init_part (&sata_dev_desc[devno]);
- if (curr_device < 0)
- curr_device =
+ if (sata_curr_device < 0)
+ sata_curr_device =
i * CONFIG_SYS_SATA_DEVS_PER_BUS + j;
}
}
printf("\n\r");
}
-static void fsl_sata_dump_sfis(struct sfis *s)
+static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
{
printf("Status FIS dump:\n\r");
printf("fis_type: %02x\n\r", s->fis_type);
printf("SYSPR: %08x\n\r", in_be32(®->syspr));
}
-static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct cfis *cfis,
+static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
int is_ncq, int tag, u8 *buffer, u32 len)
{
cmd_hdr_entry_t *cmd_hdr;
if (val32) {
u32 der;
- fsl_sata_dump_sfis((struct sfis *)cmd_desc->sfis);
+ fsl_sata_dump_sfis((struct sata_fis_d2h *)cmd_desc->sfis);
printf("CE at device\n\r");
fsl_sata_dump_regs(reg);
der = in_le32(®->der);
return len;
}
-static int fsl_ata_exec_reset_cmd(struct fsl_sata *sata, struct cfis *cfis,
+static int fsl_ata_exec_reset_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
int tag, u8 *buffer, u32 len)
{
return 0;
}
-static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct cfis *cfis,
+static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
enum cmd_type command_type, int tag, u8 *buffer, u32 len)
{
int rc;
static void fsl_sata_identify(int dev, u16 *id)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
- struct sata_fis_h2d h2d;
- struct cfis *cfis;
+ struct sata_fis_h2d h2d, *cfis = &h2d;
- cfis = (struct cfis *)&h2d;
- memset((void *)cfis, 0, sizeof(struct cfis));
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
cfis->pm_port_c = 0x80; /* is command */
static void fsl_sata_set_features(int dev)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
- struct sata_fis_h2d h2d;
- struct cfis *cfis;
+ struct sata_fis_h2d h2d, *cfis = &h2d;
u8 udma_cap;
- cfis = (struct cfis *)&h2d;
- memset((void *)cfis, 0, sizeof(struct cfis));
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
cfis->pm_port_c = 0x80; /* is command */
static u32 fsl_sata_rw_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
- struct sata_fis_h2d h2d;
- struct cfis *cfis;
+ struct sata_fis_h2d h2d, *cfis = &h2d;
u32 block;
block = start;
- cfis = (struct cfis *)&h2d;
- memset((void *)cfis, 0, sizeof(struct cfis));
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
cfis->pm_port_c = 0x80; /* is command */
void fsl_sata_flush_cache(int dev)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
- struct sata_fis_h2d h2d;
- struct cfis *cfis;
+ struct sata_fis_h2d h2d, *cfis = &h2d;
- cfis = (struct cfis *)&h2d;
-
- memset((void *)cfis, 0, sizeof(struct cfis));
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
cfis->pm_port_c = 0x80; /* is command */
static u32 fsl_sata_rw_cmd_ext(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
- struct sata_fis_h2d h2d;
- struct cfis *cfis;
+ struct sata_fis_h2d h2d, *cfis = &h2d;
u64 block;
block = (u64)start;
- cfis = (struct cfis *)&h2d;
- memset((void *)cfis, 0, sizeof(struct cfis));
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
cfis->pm_port_c = 0x80; /* is command */
u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
- struct sata_fis_h2d h2d;
- struct cfis *cfis;
+ struct sata_fis_h2d h2d, *cfis = &h2d;
int ncq_channel;
u64 block;
}
block = (u64)start;
- cfis = (struct cfis *)&h2d;
- memset((void *)cfis, 0, sizeof(struct cfis));
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
cfis->pm_port_c = 0x80; /* is command */
void fsl_sata_flush_cache_ext(int dev)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
- struct sata_fis_h2d h2d;
- struct cfis *cfis;
-
- cfis = (struct cfis *)&h2d;
+ struct sata_fis_h2d h2d, *cfis = &h2d;
- memset((void *)cfis, 0, sizeof(struct cfis));
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
cfis->pm_port_c = 0x80; /* is command */
#define SATA_HC_CMD_DESC_SIZE sizeof(struct cmd_desc)
#define SATA_HC_CMD_DESC_ALIGN 4
-/*
-* CFIS - Command FIS, which is H2D register FIS, the struct defination
-* of Non-Queued command is different than NCQ command. see them is sata2.h
-*/
-typedef struct cfis {
- u8 fis_type;
- u8 pm_port_c;
- u8 command;
- u8 features;
- u8 lba_low;
- u8 lba_mid;
- u8 lba_high;
- u8 device;
- u8 lba_low_exp;
- u8 lba_mid_exp;
- u8 lba_high_exp;
- u8 features_exp;
- u8 sector_count;
- u8 sector_count_exp;
- u8 res1;
- u8 control;
- u8 res2[4];
-} __attribute__ ((packed)) cfis_t;
-
-/*
-* SFIS - Status FIS, which is D2H register FIS.
-*/
-typedef struct sfis {
- u8 fis_type;
- u8 pm_port_i;
- u8 status;
- u8 error;
- u8 lba_low;
- u8 lba_mid;
- u8 lba_high;
- u8 device;
- u8 lba_low_exp;
- u8 lba_mid_exp;
- u8 lba_high_exp;
- u8 res1;
- u8 sector_count;
- u8 sector_count_exp;
- u8 res2[2];
- u8 res3[4];
-} __attribute__ ((packed)) sfis_t;
-
/*
* SATA device driver info
*/
--- /dev/null
+/*
+ * sata_dwc.c
+ *
+ * Synopsys DesignWare Cores (DWC) SATA host driver
+ *
+ * Author: Mark Miesfeld <mmiesfeld@amcc.com>
+ *
+ * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
+ * Copyright 2008 DENX Software Engineering
+ *
+ * Based on versions provided by AMCC and Synopsys which are:
+ * Copyright 2006 Applied Micro Circuits Corporation
+ * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
+ *
+ * This program is free software; you can redistribute
+ * it and/or modify it under the terms of the GNU
+ * General Public License as published by the
+ * Free Software Foundation; either version 2 of the License,
+ * or (at your option) any later version.
+ *
+ */
+/*
+ * SATA support based on the chip canyonlands.
+ *
+ * 04-17-2009
+ * The local version of this driver for the canyonlands board
+ * does not use interrupts but polls the chip instead.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <ata.h>
+#include <linux/ctype.h>
+
+#include "sata_dwc.h"
+
+#define DMA_NUM_CHANS 1
+#define DMA_NUM_CHAN_REGS 8
+
+#define AHB_DMA_BRST_DFLT 16
+
+struct dmareg {
+ u32 low;
+ u32 high;
+};
+
+struct dma_chan_regs {
+ struct dmareg sar;
+ struct dmareg dar;
+ struct dmareg llp;
+ struct dmareg ctl;
+ struct dmareg sstat;
+ struct dmareg dstat;
+ struct dmareg sstatar;
+ struct dmareg dstatar;
+ struct dmareg cfg;
+ struct dmareg sgr;
+ struct dmareg dsr;
+};
+
+struct dma_interrupt_regs {
+ struct dmareg tfr;
+ struct dmareg block;
+ struct dmareg srctran;
+ struct dmareg dsttran;
+ struct dmareg error;
+};
+
+struct ahb_dma_regs {
+ struct dma_chan_regs chan_regs[DMA_NUM_CHAN_REGS];
+ struct dma_interrupt_regs interrupt_raw;
+ struct dma_interrupt_regs interrupt_status;
+ struct dma_interrupt_regs interrupt_mask;
+ struct dma_interrupt_regs interrupt_clear;
+ struct dmareg statusInt;
+ struct dmareg rq_srcreg;
+ struct dmareg rq_dstreg;
+ struct dmareg rq_sgl_srcreg;
+ struct dmareg rq_sgl_dstreg;
+ struct dmareg rq_lst_srcreg;
+ struct dmareg rq_lst_dstreg;
+ struct dmareg dma_cfg;
+ struct dmareg dma_chan_en;
+ struct dmareg dma_id;
+ struct dmareg dma_test;
+ struct dmareg res1;
+ struct dmareg res2;
+ /* DMA Comp Params
+ * Param 6 = dma_param[0], Param 5 = dma_param[1],
+ * Param 4 = dma_param[2] ...
+ */
+ struct dmareg dma_params[6];
+};
+
+#define DMA_EN 0x00000001
+#define DMA_DI 0x00000000
+#define DMA_CHANNEL(ch) (0x00000001 << (ch))
+#define DMA_ENABLE_CHAN(ch) ((0x00000001 << (ch)) | \
+ ((0x000000001 << (ch)) << 8))
+#define DMA_DISABLE_CHAN(ch) (0x00000000 | \
+ ((0x000000001 << (ch)) << 8))
+
+#define SATA_DWC_MAX_PORTS 1
+#define SATA_DWC_SCR_OFFSET 0x24
+#define SATA_DWC_REG_OFFSET 0x64
+
+struct sata_dwc_regs {
+ u32 fptagr;
+ u32 fpbor;
+ u32 fptcr;
+ u32 dmacr;
+ u32 dbtsr;
+ u32 intpr;
+ u32 intmr;
+ u32 errmr;
+ u32 llcr;
+ u32 phycr;
+ u32 physr;
+ u32 rxbistpd;
+ u32 rxbistpd1;
+ u32 rxbistpd2;
+ u32 txbistpd;
+ u32 txbistpd1;
+ u32 txbistpd2;
+ u32 bistcr;
+ u32 bistfctr;
+ u32 bistsr;
+ u32 bistdecr;
+ u32 res[15];
+ u32 testr;
+ u32 versionr;
+ u32 idr;
+ u32 unimpl[192];
+ u32 dmadr[256];
+};
+
+#define SATA_DWC_TXFIFO_DEPTH 0x01FF
+#define SATA_DWC_RXFIFO_DEPTH 0x01FF
+
+#define SATA_DWC_DBTSR_MWR(size) ((size / 4) & SATA_DWC_TXFIFO_DEPTH)
+#define SATA_DWC_DBTSR_MRD(size) (((size / 4) & \
+ SATA_DWC_RXFIFO_DEPTH) << 16)
+#define SATA_DWC_INTPR_DMAT 0x00000001
+#define SATA_DWC_INTPR_NEWFP 0x00000002
+#define SATA_DWC_INTPR_PMABRT 0x00000004
+#define SATA_DWC_INTPR_ERR 0x00000008
+#define SATA_DWC_INTPR_NEWBIST 0x00000010
+#define SATA_DWC_INTPR_IPF 0x10000000
+#define SATA_DWC_INTMR_DMATM 0x00000001
+#define SATA_DWC_INTMR_NEWFPM 0x00000002
+#define SATA_DWC_INTMR_PMABRTM 0x00000004
+#define SATA_DWC_INTMR_ERRM 0x00000008
+#define SATA_DWC_INTMR_NEWBISTM 0x00000010
+
+#define SATA_DWC_DMACR_TMOD_TXCHEN 0x00000004
+#define SATA_DWC_DMACR_TXRXCH_CLEAR SATA_DWC_DMACR_TMOD_TXCHEN
+
+#define SATA_DWC_QCMD_MAX 32
+
+#define SATA_DWC_SERROR_ERR_BITS 0x0FFF0F03
+
+#define HSDEVP_FROM_AP(ap) (struct sata_dwc_device_port*) \
+ (ap)->private_data
+
+struct sata_dwc_device {
+ struct device *dev;
+ struct ata_probe_ent *pe;
+ struct ata_host *host;
+ u8 *reg_base;
+ struct sata_dwc_regs *sata_dwc_regs;
+ int irq_dma;
+};
+
+struct sata_dwc_device_port {
+ struct sata_dwc_device *hsdev;
+ int cmd_issued[SATA_DWC_QCMD_MAX];
+ u32 dma_chan[SATA_DWC_QCMD_MAX];
+ int dma_pending[SATA_DWC_QCMD_MAX];
+};
+
+enum {
+ SATA_DWC_CMD_ISSUED_NOT = 0,
+ SATA_DWC_CMD_ISSUED_PEND = 1,
+ SATA_DWC_CMD_ISSUED_EXEC = 2,
+ SATA_DWC_CMD_ISSUED_NODATA = 3,
+
+ SATA_DWC_DMA_PENDING_NONE = 0,
+ SATA_DWC_DMA_PENDING_TX = 1,
+ SATA_DWC_DMA_PENDING_RX = 2,
+};
+
+#define msleep(a) udelay(a * 1000)
+#define ssleep(a) msleep(a * 1000)
+
+static int ata_probe_timeout = (ATA_TMOUT_INTERNAL / 100);
+
+enum sata_dev_state {
+ SATA_INIT = 0,
+ SATA_READY = 1,
+ SATA_NODEVICE = 2,
+ SATA_ERROR = 3,
+};
+enum sata_dev_state dev_state = SATA_INIT;
+
+static struct ahb_dma_regs *sata_dma_regs = 0;
+static struct ata_host *phost;
+static struct ata_port ap;
+static struct ata_port *pap = ≈
+static struct ata_device ata_device;
+static struct sata_dwc_device_port dwc_devp;
+
+static void *scr_addr_sstatus;
+static u32 temp_n_block = 0;
+
+static unsigned ata_exec_internal(struct ata_device *dev,
+ struct ata_taskfile *tf, const u8 *cdb,
+ int dma_dir, unsigned int buflen,
+ unsigned long timeout);
+static unsigned int ata_dev_set_feature(struct ata_device *dev,
+ u8 enable,u8 feature);
+static unsigned int ata_dev_init_params(struct ata_device *dev,
+ u16 heads, u16 sectors);
+static u8 ata_irq_on(struct ata_port *ap);
+static struct ata_queued_cmd *__ata_qc_from_tag(struct ata_port *ap,
+ unsigned int tag);
+static int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
+ u8 status, int in_wq);
+static void ata_tf_to_host(struct ata_port *ap,
+ const struct ata_taskfile *tf);
+static void ata_exec_command(struct ata_port *ap,
+ const struct ata_taskfile *tf);
+static unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc);
+static u8 ata_check_altstatus(struct ata_port *ap);
+static u8 ata_check_status(struct ata_port *ap);
+static void ata_dev_select(struct ata_port *ap, unsigned int device,
+ unsigned int wait, unsigned int can_sleep);
+static void ata_qc_issue(struct ata_queued_cmd *qc);
+static void ata_tf_load(struct ata_port *ap,
+ const struct ata_taskfile *tf);
+static int ata_dev_read_sectors(unsigned char* pdata,
+ unsigned long datalen, u32 block, u32 n_block);
+static int ata_dev_write_sectors(unsigned char* pdata,
+ unsigned long datalen , u32 block, u32 n_block);
+static void ata_std_dev_select(struct ata_port *ap, unsigned int device);
+static void ata_qc_complete(struct ata_queued_cmd *qc);
+static void __ata_qc_complete(struct ata_queued_cmd *qc);
+static void fill_result_tf(struct ata_queued_cmd *qc);
+static void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
+static void ata_mmio_data_xfer(struct ata_device *dev,
+ unsigned char *buf,
+ unsigned int buflen,int do_write);
+static void ata_pio_task(struct ata_port *arg_ap);
+static void __ata_port_freeze(struct ata_port *ap);
+static int ata_port_freeze(struct ata_port *ap);
+static void ata_qc_free(struct ata_queued_cmd *qc);
+static void ata_pio_sectors(struct ata_queued_cmd *qc);
+static void ata_pio_sector(struct ata_queued_cmd *qc);
+static void ata_pio_queue_task(struct ata_port *ap,
+ void *data,unsigned long delay);
+static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq);
+static int sata_dwc_softreset(struct ata_port *ap);
+static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
+ unsigned int flags, u16 *id);
+static int check_sata_dev_state(void);
+
+extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
+
+static const struct ata_port_info sata_dwc_port_info[] = {
+ {
+ .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
+ ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING |
+ ATA_FLAG_SRST | ATA_FLAG_NCQ,
+ .pio_mask = 0x1f,
+ .mwdma_mask = 0x07,
+ .udma_mask = 0x7f,
+ },
+};
+
+int init_sata(int dev)
+{
+ struct sata_dwc_device hsdev;
+ struct ata_host host;
+ struct ata_port_info pi = sata_dwc_port_info[0];
+ struct ata_link *link;
+ struct sata_dwc_device_port hsdevp = dwc_devp;
+ u8 *base = 0;
+ u8 *sata_dma_regs_addr = 0;
+ u8 status;
+ unsigned long base_addr = 0;
+ int chan = 0;
+ int rc;
+ int i;
+
+ phost = &host;
+
+ base = (u8*)SATA_BASE_ADDR;
+
+ hsdev.sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
+
+ host.n_ports = SATA_DWC_MAX_PORTS;
+
+ for (i = 0; i < SATA_DWC_MAX_PORTS; i++) {
+ ap.pflags |= ATA_PFLAG_INITIALIZING;
+ ap.flags = ATA_FLAG_DISABLED;
+ ap.print_id = -1;
+ ap.ctl = ATA_DEVCTL_OBS;
+ ap.host = &host;
+ ap.last_ctl = 0xFF;
+
+ link = &ap.link;
+ link->ap = ≈
+ link->pmp = 0;
+ link->active_tag = ATA_TAG_POISON;
+ link->hw_sata_spd_limit = 0;
+
+ ap.port_no = i;
+ host.ports[i] = ≈
+ }
+
+ ap.pio_mask = pi.pio_mask;
+ ap.mwdma_mask = pi.mwdma_mask;
+ ap.udma_mask = pi.udma_mask;
+ ap.flags |= pi.flags;
+ ap.link.flags |= pi.link_flags;
+
+ host.ports[0]->ioaddr.cmd_addr = base;
+ host.ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
+ scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
+
+ base_addr = (unsigned long)base;
+
+ host.ports[0]->ioaddr.cmd_addr = (void *)base_addr + 0x00;
+ host.ports[0]->ioaddr.data_addr = (void *)base_addr + 0x00;
+
+ host.ports[0]->ioaddr.error_addr = (void *)base_addr + 0x04;
+ host.ports[0]->ioaddr.feature_addr = (void *)base_addr + 0x04;
+
+ host.ports[0]->ioaddr.nsect_addr = (void *)base_addr + 0x08;
+
+ host.ports[0]->ioaddr.lbal_addr = (void *)base_addr + 0x0c;
+ host.ports[0]->ioaddr.lbam_addr = (void *)base_addr + 0x10;
+ host.ports[0]->ioaddr.lbah_addr = (void *)base_addr + 0x14;
+
+ host.ports[0]->ioaddr.device_addr = (void *)base_addr + 0x18;
+ host.ports[0]->ioaddr.command_addr = (void *)base_addr + 0x1c;
+ host.ports[0]->ioaddr.status_addr = (void *)base_addr + 0x1c;
+
+ host.ports[0]->ioaddr.altstatus_addr = (void *)base_addr + 0x20;
+ host.ports[0]->ioaddr.ctl_addr = (void *)base_addr + 0x20;
+
+ sata_dma_regs_addr = (u8*)SATA_DMA_REG_ADDR;
+ sata_dma_regs = (void *__iomem)sata_dma_regs_addr;
+
+ status = ata_check_altstatus(&ap);
+
+ if (status == 0x7f) {
+ printf("Hard Disk not found.\n");
+ dev_state = SATA_NODEVICE;
+ rc = FALSE;
+ return rc;
+ }
+
+ printf("Waiting for device...");
+ i = 0;
+ while (1) {
+ udelay(10000);
+
+ status = ata_check_altstatus(&ap);
+
+ if ((status & ATA_BUSY) == 0) {
+ printf("\n");
+ break;
+ }
+
+ i++;
+ if (i > (ATA_RESET_TIME * 100)) {
+ printf("** TimeOUT **\n");
+
+ dev_state = SATA_NODEVICE;
+ rc = FALSE;
+ return rc;
+ }
+ if ((i >= 100) && ((i % 100) == 0))
+ printf(".");
+ }
+
+ rc = sata_dwc_softreset(&ap);
+
+ if (rc) {
+ printf("sata_dwc : error. soft reset failed\n");
+ return rc;
+ }
+
+ for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
+ out_le32(&(sata_dma_regs->interrupt_mask.error.low),
+ DMA_DISABLE_CHAN(chan));
+
+ out_le32(&(sata_dma_regs->interrupt_mask.tfr.low),
+ DMA_DISABLE_CHAN(chan));
+ }
+
+ out_le32(&(sata_dma_regs->dma_cfg.low), DMA_DI);
+
+ out_le32(&hsdev.sata_dwc_regs->intmr,
+ SATA_DWC_INTMR_ERRM |
+ SATA_DWC_INTMR_PMABRTM);
+
+ /* Unmask the error bits that should trigger
+ * an error interrupt by setting the error mask register.
+ */
+ out_le32(&hsdev.sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
+
+ hsdev.host = ap.host;
+ memset(&hsdevp, 0, sizeof(hsdevp));
+ hsdevp.hsdev = &hsdev;
+
+ for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
+ hsdevp.cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
+
+ out_le32((void __iomem *)scr_addr_sstatus + 4,
+ in_le32((void __iomem *)scr_addr_sstatus + 4));
+
+ rc = 0;
+ return rc;
+}
+
+static u8 ata_check_altstatus(struct ata_port *ap)
+{
+ u8 val = 0;
+ val = readb(ap->ioaddr.altstatus_addr);
+ return val;
+}
+
+static int sata_dwc_softreset(struct ata_port *ap)
+{
+ u8 nsect,lbal = 0;
+ u8 tmp = 0;
+ u32 serror = 0;
+ u8 status = 0;
+ struct ata_ioports *ioaddr = &ap->ioaddr;
+
+ serror = in_le32((void *)ap->ioaddr.scr_addr + (SCR_ERROR * 4));
+
+ writeb(0x55, ioaddr->nsect_addr);
+ writeb(0xaa, ioaddr->lbal_addr);
+ writeb(0xaa, ioaddr->nsect_addr);
+ writeb(0x55, ioaddr->lbal_addr);
+ writeb(0x55, ioaddr->nsect_addr);
+ writeb(0xaa, ioaddr->lbal_addr);
+
+ nsect = readb(ioaddr->nsect_addr);
+ lbal = readb(ioaddr->lbal_addr);
+
+ if ((nsect == 0x55) && (lbal == 0xaa)) {
+ printf("Device found\n");
+ } else {
+ printf("No device found\n");
+ dev_state = SATA_NODEVICE;
+ return FALSE;
+ }
+
+ tmp = ATA_DEVICE_OBS;
+ writeb(tmp, ioaddr->device_addr);
+ writeb(ap->ctl, ioaddr->ctl_addr);
+
+ udelay(200);
+
+ writeb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
+
+ udelay(200);
+ writeb(ap->ctl, ioaddr->ctl_addr);
+
+ msleep(150);
+ status = ata_check_status(ap);
+
+ msleep(50);
+ ata_check_status(ap);
+
+ while (1) {
+ u8 status = ata_check_status(ap);
+
+ if (!(status & ATA_BUSY))
+ break;
+
+ printf("Hard Disk status is BUSY.\n");
+ msleep(50);
+ }
+
+ tmp = ATA_DEVICE_OBS;
+ writeb(tmp, ioaddr->device_addr);
+
+ nsect = readb(ioaddr->nsect_addr);
+ lbal = readb(ioaddr->lbal_addr);
+
+ return 0;
+}
+
+static u8 ata_check_status(struct ata_port *ap)
+{
+ u8 val = 0;
+ val = readb(ap->ioaddr.status_addr);
+ return val;
+}
+
+static int ata_id_has_hipm(const u16 *id)
+{
+ u16 val = id[76];
+
+ if (val == 0 || val == 0xffff)
+ return -1;
+
+ return val & (1 << 9);
+}
+
+static int ata_id_has_dipm(const u16 *id)
+{
+ u16 val = id[78];
+
+ if (val == 0 || val == 0xffff)
+ return -1;
+
+ return val & (1 << 3);
+}
+
+int scan_sata(int dev)
+{
+ int i;
+ int rc;
+ u8 status;
+ const u16 *id;
+ struct ata_device *ata_dev = &ata_device;
+ unsigned long pio_mask, mwdma_mask, udma_mask;
+ unsigned long xfer_mask;
+ char revbuf[7];
+ u16 iobuf[ATA_SECTOR_WORDS];
+
+ memset(iobuf, 0, sizeof(iobuf));
+
+ if (dev_state == SATA_NODEVICE)
+ return 1;
+
+ printf("Waiting for device...");
+ i = 0;
+ while (1) {
+ udelay(10000);
+
+ status = ata_check_altstatus(&ap);
+
+ if ((status & ATA_BUSY) == 0) {
+ printf("\n");
+ break;
+ }
+
+ i++;
+ if (i > (ATA_RESET_TIME * 100)) {
+ printf("** TimeOUT **\n");
+
+ dev_state = SATA_NODEVICE;
+ return 1;
+ }
+ if ((i >= 100) && ((i % 100) == 0))
+ printf(".");
+ }
+
+ udelay(1000);
+
+ rc = ata_dev_read_id(ata_dev, &ata_dev->class,
+ ATA_READID_POSTRESET,ata_dev->id);
+ if (rc) {
+ printf("sata_dwc : error. failed sata scan\n");
+ return 1;
+ }
+
+ /* SATA drives indicate we have a bridge. We don't know which
+ * end of the link the bridge is which is a problem
+ */
+ if (ata_id_is_sata(ata_dev->id))
+ ap.cbl = ATA_CBL_SATA;
+
+ id = ata_dev->id;
+
+ ata_dev->flags &= ~ATA_DFLAG_CFG_MASK;
+ ata_dev->max_sectors = 0;
+ ata_dev->cdb_len = 0;
+ ata_dev->n_sectors = 0;
+ ata_dev->cylinders = 0;
+ ata_dev->heads = 0;
+ ata_dev->sectors = 0;
+
+ if (id[ATA_ID_FIELD_VALID] & (1 << 1)) {
+ pio_mask = id[ATA_ID_PIO_MODES] & 0x03;
+ pio_mask <<= 3;
+ pio_mask |= 0x7;
+ } else {
+ /* If word 64 isn't valid then Word 51 high byte holds
+ * the PIO timing number for the maximum. Turn it into
+ * a mask.
+ */
+ u8 mode = (id[ATA_ID_OLD_PIO_MODES] >> 8) & 0xFF;
+ if (mode < 5) {
+ pio_mask = (2 << mode) - 1;
+ } else {
+ pio_mask = 1;
+ }
+ }
+
+ mwdma_mask = id[ATA_ID_MWDMA_MODES] & 0x07;
+
+ if (ata_id_is_cfa(id)) {
+ int pio = id[163] & 0x7;
+ int dma = (id[163] >> 3) & 7;
+
+ if (pio)
+ pio_mask |= (1 << 5);
+ if (pio > 1)
+ pio_mask |= (1 << 6);
+ if (dma)
+ mwdma_mask |= (1 << 3);
+ if (dma > 1)
+ mwdma_mask |= (1 << 4);
+ }
+
+ udma_mask = 0;
+ if (id[ATA_ID_FIELD_VALID] & (1 << 2))
+ udma_mask = id[ATA_ID_UDMA_MODES] & 0xff;
+
+ xfer_mask = ((pio_mask << ATA_SHIFT_PIO) & ATA_MASK_PIO) |
+ ((mwdma_mask << ATA_SHIFT_MWDMA) & ATA_MASK_MWDMA) |
+ ((udma_mask << ATA_SHIFT_UDMA) & ATA_MASK_UDMA);
+
+ if (ata_dev->class == ATA_DEV_ATA) {
+ if (ata_id_is_cfa(id)) {
+ if (id[162] & 1)
+ printf("supports DRM functions and may "
+ "not be fully accessable.\n");
+ sprintf(revbuf, "%s", "CFA");
+ } else {
+ if (ata_id_has_tpm(id))
+ printf("supports DRM functions and may "
+ "not be fully accessable.\n");
+ }
+
+ ata_dev->n_sectors = ata_id_n_sectors((u16*)id);
+
+ if (ata_dev->id[59] & 0x100)
+ ata_dev->multi_count = ata_dev->id[59] & 0xff;
+
+ if (ata_id_has_lba(id)) {
+ const char *lba_desc;
+ char ncq_desc[20];
+
+ lba_desc = "LBA";
+ ata_dev->flags |= ATA_DFLAG_LBA;
+ if (ata_id_has_lba48(id)) {
+ ata_dev->flags |= ATA_DFLAG_LBA48;
+ lba_desc = "LBA48";
+
+ if (ata_dev->n_sectors >= (1UL << 28) &&
+ ata_id_has_flush_ext(id))
+ ata_dev->flags |= ATA_DFLAG_FLUSH_EXT;
+ }
+ if (!ata_id_has_ncq(ata_dev->id))
+ ncq_desc[0] = '\0';
+
+ if (ata_dev->horkage & ATA_HORKAGE_NONCQ)
+ sprintf(ncq_desc, "%s", "NCQ (not used)");
+
+ if (ap.flags & ATA_FLAG_NCQ)
+ ata_dev->flags |= ATA_DFLAG_NCQ;
+ }
+ ata_dev->cdb_len = 16;
+ }
+ ata_dev->max_sectors = ATA_MAX_SECTORS;
+ if (ata_dev->flags & ATA_DFLAG_LBA48)
+ ata_dev->max_sectors = ATA_MAX_SECTORS_LBA48;
+
+ if (!(ata_dev->horkage & ATA_HORKAGE_IPM)) {
+ if (ata_id_has_hipm(ata_dev->id))
+ ata_dev->flags |= ATA_DFLAG_HIPM;
+ if (ata_id_has_dipm(ata_dev->id))
+ ata_dev->flags |= ATA_DFLAG_DIPM;
+ }
+
+ if ((ap.cbl == ATA_CBL_SATA) && (!ata_id_is_sata(ata_dev->id))) {
+ ata_dev->udma_mask &= ATA_UDMA5;
+ ata_dev->max_sectors = ATA_MAX_SECTORS;
+ }
+
+ if (ata_dev->horkage & ATA_HORKAGE_DIAGNOSTIC) {
+ printf("Drive reports diagnostics failure."
+ "This may indicate a drive\n");
+ printf("fault or invalid emulation."
+ "Contact drive vendor for information.\n");
+ }
+
+ rc = check_sata_dev_state();
+
+ ata_id_c_string(ata_dev->id,
+ (unsigned char *)sata_dev_desc[dev].revision,
+ ATA_ID_FW_REV, sizeof(sata_dev_desc[dev].revision));
+ ata_id_c_string(ata_dev->id,
+ (unsigned char *)sata_dev_desc[dev].vendor,
+ ATA_ID_PROD, sizeof(sata_dev_desc[dev].vendor));
+ ata_id_c_string(ata_dev->id,
+ (unsigned char *)sata_dev_desc[dev].product,
+ ATA_ID_SERNO, sizeof(sata_dev_desc[dev].product));
+
+ sata_dev_desc[dev].lba = (u32) ata_dev->n_sectors;
+
+#ifdef CONFIG_LBA48
+ if (ata_dev->id[83] & (1 << 10)) {
+ sata_dev_desc[dev].lba48 = 1;
+ } else {
+ sata_dev_desc[dev].lba48 = 0;
+ }
+#endif
+
+ return 0;
+}
+
+static u8 ata_busy_wait(struct ata_port *ap,
+ unsigned int bits,unsigned int max)
+{
+ u8 status;
+
+ do {
+ udelay(10);
+ status = ata_check_status(ap);
+ max--;
+ } while (status != 0xff && (status & bits) && (max > 0));
+
+ return status;
+}
+
+static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
+ unsigned int flags, u16 *id)
+{
+ struct ata_port *ap = pap;
+ unsigned int class = *p_class;
+ struct ata_taskfile tf;
+ unsigned int err_mask = 0;
+ const char *reason;
+ int may_fallback = 1, tried_spinup = 0;
+ u8 status;
+ int rc;
+
+ status = ata_busy_wait(ap, ATA_BUSY, 30000);
+ if (status & ATA_BUSY) {
+ printf("BSY = 0 check. timeout.\n");
+ rc = FALSE;
+ return rc;
+ }
+
+ ata_dev_select(ap, dev->devno, 1, 1);
+
+retry:
+ memset(&tf, 0, sizeof(tf));
+ ap->print_id = 1;
+ ap->flags &= ~ATA_FLAG_DISABLED;
+ tf.ctl = ap->ctl;
+ tf.device = ATA_DEVICE_OBS;
+ tf.command = ATA_CMD_ID_ATA;
+ tf.protocol = ATA_PROT_PIO;
+
+ /* Some devices choke if TF registers contain garbage. Make
+ * sure those are properly initialized.
+ */
+ tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
+
+ /* Device presence detection is unreliable on some
+ * controllers. Always poll IDENTIFY if available.
+ */
+ tf.flags |= ATA_TFLAG_POLLING;
+
+ temp_n_block = 1;
+
+ err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE,
+ sizeof(id[0]) * ATA_ID_WORDS, 0);
+
+ if (err_mask) {
+ if (err_mask & AC_ERR_NODEV_HINT) {
+ printf("NODEV after polling detection\n");
+ return -ENOENT;
+ }
+
+ if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
+ /* Device or controller might have reported
+ * the wrong device class. Give a shot at the
+ * other IDENTIFY if the current one is
+ * aborted by the device.
+ */
+ if (may_fallback) {
+ may_fallback = 0;
+
+ if (class == ATA_DEV_ATA) {
+ class = ATA_DEV_ATAPI;
+ } else {
+ class = ATA_DEV_ATA;
+ }
+ goto retry;
+ }
+ /* Control reaches here iff the device aborted
+ * both flavors of IDENTIFYs which happens
+ * sometimes with phantom devices.
+ */
+ printf("both IDENTIFYs aborted, assuming NODEV\n");
+ return -ENOENT;
+ }
+ rc = -EIO;
+ reason = "I/O error";
+ goto err_out;
+ }
+
+ /* Falling back doesn't make sense if ID data was read
+ * successfully at least once.
+ */
+ may_fallback = 0;
+
+ unsigned int id_cnt;
+
+ for (id_cnt = 0; id_cnt < ATA_ID_WORDS; id_cnt++)
+ id[id_cnt] = le16_to_cpu(id[id_cnt]);
+
+
+ rc = -EINVAL;
+ reason = "device reports invalid type";
+
+ if (class == ATA_DEV_ATA) {
+ if (!ata_id_is_ata(id) && !ata_id_is_cfa(id))
+ goto err_out;
+ } else {
+ if (ata_id_is_ata(id))
+ goto err_out;
+ }
+ if (!tried_spinup && (id[2] == 0x37c8 || id[2] == 0x738c)) {
+ tried_spinup = 1;
+ /*
+ * Drive powered-up in standby mode, and requires a specific
+ * SET_FEATURES spin-up subcommand before it will accept
+ * anything other than the original IDENTIFY command.
+ */
+ err_mask = ata_dev_set_feature(dev, SETFEATURES_SPINUP, 0);
+ if (err_mask && id[2] != 0x738c) {
+ rc = -EIO;
+ reason = "SPINUP failed";
+ goto err_out;
+ }
+ /*
+ * If the drive initially returned incomplete IDENTIFY info,
+ * we now must reissue the IDENTIFY command.
+ */
+ if (id[2] == 0x37c8)
+ goto retry;
+ }
+
+ if ((flags & ATA_READID_POSTRESET) && class == ATA_DEV_ATA) {
+ /*
+ * The exact sequence expected by certain pre-ATA4 drives is:
+ * SRST RESET
+ * IDENTIFY (optional in early ATA)
+ * INITIALIZE DEVICE PARAMETERS (later IDE and ATA)
+ * anything else..
+ * Some drives were very specific about that exact sequence.
+ *
+ * Note that ATA4 says lba is mandatory so the second check
+ * shoud never trigger.
+ */
+ if (ata_id_major_version(id) < 4 || !ata_id_has_lba(id)) {
+ err_mask = ata_dev_init_params(dev, id[3], id[6]);
+ if (err_mask) {
+ rc = -EIO;
+ reason = "INIT_DEV_PARAMS failed";
+ goto err_out;
+ }
+
+ /* current CHS translation info (id[53-58]) might be
+ * changed. reread the identify device info.
+ */
+ flags &= ~ATA_READID_POSTRESET;
+ goto retry;
+ }
+ }
+
+ *p_class = class;
+ return 0;
+
+err_out:
+ return rc;
+}
+
+static u8 ata_wait_idle(struct ata_port *ap)
+{
+ u8 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
+ return status;
+}
+
+static void ata_dev_select(struct ata_port *ap, unsigned int device,
+ unsigned int wait, unsigned int can_sleep)
+{
+ if (wait)
+ ata_wait_idle(ap);
+
+ ata_std_dev_select(ap, device);
+
+ if (wait)
+ ata_wait_idle(ap);
+}
+
+static void ata_std_dev_select(struct ata_port *ap, unsigned int device)
+{
+ u8 tmp;
+
+ if (device == 0) {
+ tmp = ATA_DEVICE_OBS;
+ } else {
+ tmp = ATA_DEVICE_OBS | ATA_DEV1;
+ }
+
+ writeb(tmp, ap->ioaddr.device_addr);
+
+ readb(ap->ioaddr.altstatus_addr);
+
+ udelay(1);
+}
+
+static int waiting_for_reg_state(volatile u8 *offset,
+ int timeout_msec,
+ u32 sign)
+{
+ int i;
+ u32 status;
+
+ for (i = 0; i < timeout_msec; i++) {
+ status = readl(offset);
+ if ((status & sign) != 0)
+ break;
+ msleep(1);
+ }
+
+ return (i < timeout_msec) ? 0 : -1;
+}
+
+static void ata_qc_reinit(struct ata_queued_cmd *qc)
+{
+ qc->dma_dir = DMA_NONE;
+ qc->flags = 0;
+ qc->nbytes = qc->extrabytes = qc->curbytes = 0;
+ qc->n_elem = 0;
+ qc->err_mask = 0;
+ qc->sect_size = ATA_SECT_SIZE;
+ qc->nbytes = ATA_SECT_SIZE * temp_n_block;
+
+ memset(&qc->tf, 0, sizeof(qc->tf));
+ qc->tf.ctl = 0;
+ qc->tf.device = ATA_DEVICE_OBS;
+
+ qc->result_tf.command = ATA_DRDY;
+ qc->result_tf.feature = 0;
+}
+
+struct ata_queued_cmd *__ata_qc_from_tag(struct ata_port *ap,
+ unsigned int tag)
+{
+ if (tag < ATA_MAX_QUEUE)
+ return &ap->qcmd[tag];
+ return NULL;
+}
+
+static void __ata_port_freeze(struct ata_port *ap)
+{
+ printf("set port freeze.\n");
+ ap->pflags |= ATA_PFLAG_FROZEN;
+}
+
+static int ata_port_freeze(struct ata_port *ap)
+{
+ __ata_port_freeze(ap);
+ return 0;
+}
+
+unsigned ata_exec_internal(struct ata_device *dev,
+ struct ata_taskfile *tf, const u8 *cdb,
+ int dma_dir, unsigned int buflen,
+ unsigned long timeout)
+{
+ struct ata_link *link = dev->link;
+ struct ata_port *ap = pap;
+ struct ata_queued_cmd *qc;
+ unsigned int tag, preempted_tag;
+ u32 preempted_sactive, preempted_qc_active;
+ int preempted_nr_active_links;
+ unsigned int err_mask;
+ int rc = 0;
+ u8 status;
+
+ status = ata_busy_wait(ap, ATA_BUSY, 300000);
+ if (status & ATA_BUSY) {
+ printf("BSY = 0 check. timeout.\n");
+ rc = FALSE;
+ return rc;
+ }
+
+ if (ap->pflags & ATA_PFLAG_FROZEN)
+ return AC_ERR_SYSTEM;
+
+ tag = ATA_TAG_INTERNAL;
+
+ if (test_and_set_bit(tag, &ap->qc_allocated)) {
+ rc = FALSE;
+ return rc;
+ }
+
+ qc = __ata_qc_from_tag(ap, tag);
+ qc->tag = tag;
+ qc->ap = ap;
+ qc->dev = dev;
+
+ ata_qc_reinit(qc);
+
+ preempted_tag = link->active_tag;
+ preempted_sactive = link->sactive;
+ preempted_qc_active = ap->qc_active;
+ preempted_nr_active_links = ap->nr_active_links;
+ link->active_tag = ATA_TAG_POISON;
+ link->sactive = 0;
+ ap->qc_active = 0;
+ ap->nr_active_links = 0;
+
+ qc->tf = *tf;
+ if (cdb)
+ memcpy(qc->cdb, cdb, ATAPI_CDB_LEN);
+ qc->flags |= ATA_QCFLAG_RESULT_TF;
+ qc->dma_dir = dma_dir;
+ qc->private_data = 0;
+
+ ata_qc_issue(qc);
+
+ if (!timeout)
+ timeout = ata_probe_timeout * 1000 / HZ;
+
+ status = ata_busy_wait(ap, ATA_BUSY, 30000);
+ if (status & ATA_BUSY) {
+ printf("BSY = 0 check. timeout.\n");
+ printf("altstatus = 0x%x.\n", status);
+ qc->err_mask |= AC_ERR_OTHER;
+ return qc->err_mask;
+ }
+
+ if (waiting_for_reg_state(ap->ioaddr.altstatus_addr, 1000, 0x8)) {
+ u8 status = 0;
+ u8 errorStatus = 0;
+
+ status = readb(ap->ioaddr.altstatus_addr);
+ if ((status & 0x01) != 0) {
+ errorStatus = readb(ap->ioaddr.feature_addr);
+ if (errorStatus == 0x04 &&
+ qc->tf.command == ATA_CMD_PIO_READ_EXT){
+ printf("Hard Disk doesn't support LBA48\n");
+ dev_state = SATA_ERROR;
+ qc->err_mask |= AC_ERR_OTHER;
+ return qc->err_mask;
+ }
+ }
+ qc->err_mask |= AC_ERR_OTHER;
+ return qc->err_mask;
+ }
+
+ status = ata_busy_wait(ap, ATA_BUSY, 10);
+ if (status & ATA_BUSY) {
+ printf("BSY = 0 check. timeout.\n");
+ qc->err_mask |= AC_ERR_OTHER;
+ return qc->err_mask;
+ }
+
+ ata_pio_task(ap);
+
+ if (!rc) {
+ if (qc->flags & ATA_QCFLAG_ACTIVE) {
+ qc->err_mask |= AC_ERR_TIMEOUT;
+ ata_port_freeze(ap);
+ }
+ }
+
+ if (qc->flags & ATA_QCFLAG_FAILED) {
+ if (qc->result_tf.command & (ATA_ERR | ATA_DF))
+ qc->err_mask |= AC_ERR_DEV;
+
+ if (!qc->err_mask)
+ qc->err_mask |= AC_ERR_OTHER;
+
+ if (qc->err_mask & ~AC_ERR_OTHER)
+ qc->err_mask &= ~AC_ERR_OTHER;
+ }
+
+ *tf = qc->result_tf;
+ err_mask = qc->err_mask;
+ ata_qc_free(qc);
+ link->active_tag = preempted_tag;
+ link->sactive = preempted_sactive;
+ ap->qc_active = preempted_qc_active;
+ ap->nr_active_links = preempted_nr_active_links;
+
+ if (ap->flags & ATA_FLAG_DISABLED) {
+ err_mask |= AC_ERR_SYSTEM;
+ ap->flags &= ~ATA_FLAG_DISABLED;
+ }
+
+ return err_mask;
+}
+
+static void ata_qc_issue(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+ struct ata_link *link = qc->dev->link;
+ u8 prot = qc->tf.protocol;
+
+ if (ata_is_ncq(prot)) {
+ if (!link->sactive)
+ ap->nr_active_links++;
+ link->sactive |= 1 << qc->tag;
+ } else {
+ ap->nr_active_links++;
+ link->active_tag = qc->tag;
+ }
+
+ qc->flags |= ATA_QCFLAG_ACTIVE;
+ ap->qc_active |= 1 << qc->tag;
+
+ if (qc->dev->flags & ATA_DFLAG_SLEEPING) {
+ msleep(1);
+ return;
+ }
+
+ qc->err_mask |= ata_qc_issue_prot(qc);
+ if (qc->err_mask)
+ goto err;
+
+ return;
+err:
+ ata_qc_complete(qc);
+}
+
+static unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+
+ if (ap->flags & ATA_FLAG_PIO_POLLING) {
+ switch (qc->tf.protocol) {
+ case ATA_PROT_PIO:
+ case ATA_PROT_NODATA:
+ case ATAPI_PROT_PIO:
+ case ATAPI_PROT_NODATA:
+ qc->tf.flags |= ATA_TFLAG_POLLING;
+ break;
+ default:
+ break;
+ }
+ }
+
+ ata_dev_select(ap, qc->dev->devno, 1, 0);
+
+ switch (qc->tf.protocol) {
+ case ATA_PROT_PIO:
+ if (qc->tf.flags & ATA_TFLAG_POLLING)
+ qc->tf.ctl |= ATA_NIEN;
+
+ ata_tf_to_host(ap, &qc->tf);
+
+ ap->hsm_task_state = HSM_ST;
+
+ if (qc->tf.flags & ATA_TFLAG_POLLING)
+ ata_pio_queue_task(ap, qc, 0);
+
+ break;
+
+ default:
+ return AC_ERR_SYSTEM;
+ }
+
+ return 0;
+}
+
+static void ata_tf_to_host(struct ata_port *ap,
+ const struct ata_taskfile *tf)
+{
+ ata_tf_load(ap, tf);
+ ata_exec_command(ap, tf);
+}
+
+static void ata_tf_load(struct ata_port *ap,
+ const struct ata_taskfile *tf)
+{
+ struct ata_ioports *ioaddr = &ap->ioaddr;
+ unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
+
+ if (tf->ctl != ap->last_ctl) {
+ if (ioaddr->ctl_addr)
+ writeb(tf->ctl, ioaddr->ctl_addr);
+ ap->last_ctl = tf->ctl;
+ ata_wait_idle(ap);
+ }
+
+ if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
+ writeb(tf->hob_feature, ioaddr->feature_addr);
+ writeb(tf->hob_nsect, ioaddr->nsect_addr);
+ writeb(tf->hob_lbal, ioaddr->lbal_addr);
+ writeb(tf->hob_lbam, ioaddr->lbam_addr);
+ writeb(tf->hob_lbah, ioaddr->lbah_addr);
+ }
+
+ if (is_addr) {
+ writeb(tf->feature, ioaddr->feature_addr);
+ writeb(tf->nsect, ioaddr->nsect_addr);
+ writeb(tf->lbal, ioaddr->lbal_addr);
+ writeb(tf->lbam, ioaddr->lbam_addr);
+ writeb(tf->lbah, ioaddr->lbah_addr);
+ }
+
+ if (tf->flags & ATA_TFLAG_DEVICE)
+ writeb(tf->device, ioaddr->device_addr);
+
+ ata_wait_idle(ap);
+}
+
+static void ata_exec_command(struct ata_port *ap,
+ const struct ata_taskfile *tf)
+{
+ writeb(tf->command, ap->ioaddr.command_addr);
+
+ readb(ap->ioaddr.altstatus_addr);
+
+ udelay(1);
+}
+
+static void ata_pio_queue_task(struct ata_port *ap,
+ void *data,unsigned long delay)
+{
+ ap->port_task_data = data;
+}
+
+static unsigned int ac_err_mask(u8 status)
+{
+ if (status & (ATA_BUSY | ATA_DRQ))
+ return AC_ERR_HSM;
+ if (status & (ATA_ERR | ATA_DF))
+ return AC_ERR_DEV;
+ return 0;
+}
+
+static unsigned int __ac_err_mask(u8 status)
+{
+ unsigned int mask = ac_err_mask(status);
+ if (mask == 0)
+ return AC_ERR_OTHER;
+ return mask;
+}
+
+static void ata_pio_task(struct ata_port *arg_ap)
+{
+ struct ata_port *ap = arg_ap;
+ struct ata_queued_cmd *qc = ap->port_task_data;
+ u8 status;
+ int poll_next;
+
+fsm_start:
+ /*
+ * This is purely heuristic. This is a fast path.
+ * Sometimes when we enter, BSY will be cleared in
+ * a chk-status or two. If not, the drive is probably seeking
+ * or something. Snooze for a couple msecs, then
+ * chk-status again. If still busy, queue delayed work.
+ */
+ status = ata_busy_wait(ap, ATA_BUSY, 5);
+ if (status & ATA_BUSY) {
+ msleep(2);
+ status = ata_busy_wait(ap, ATA_BUSY, 10);
+ if (status & ATA_BUSY) {
+ ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
+ return;
+ }
+ }
+
+ poll_next = ata_hsm_move(ap, qc, status, 1);
+
+ /* another command or interrupt handler
+ * may be running at this point.
+ */
+ if (poll_next)
+ goto fsm_start;
+}
+
+static int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
+ u8 status, int in_wq)
+{
+ int poll_next;
+
+fsm_start:
+ switch (ap->hsm_task_state) {
+ case HSM_ST_FIRST:
+ poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
+
+ if ((status & ATA_DRQ) == 0) {
+ if (status & (ATA_ERR | ATA_DF)) {
+ qc->err_mask |= AC_ERR_DEV;
+ } else {
+ qc->err_mask |= AC_ERR_HSM;
+ }
+ ap->hsm_task_state = HSM_ST_ERR;
+ goto fsm_start;
+ }
+
+ /* Device should not ask for data transfer (DRQ=1)
+ * when it finds something wrong.
+ * We ignore DRQ here and stop the HSM by
+ * changing hsm_task_state to HSM_ST_ERR and
+ * let the EH abort the command or reset the device.
+ */
+ if (status & (ATA_ERR | ATA_DF)) {
+ if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
+ printf("DRQ=1 with device error, "
+ "dev_stat 0x%X\n", status);
+ qc->err_mask |= AC_ERR_HSM;
+ ap->hsm_task_state = HSM_ST_ERR;
+ goto fsm_start;
+ }
+ }
+
+ if (qc->tf.protocol == ATA_PROT_PIO) {
+ /* PIO data out protocol.
+ * send first data block.
+ */
+ /* ata_pio_sectors() might change the state
+ * to HSM_ST_LAST. so, the state is changed here
+ * before ata_pio_sectors().
+ */
+ ap->hsm_task_state = HSM_ST;
+ ata_pio_sectors(qc);
+ } else {
+ printf("protocol is not ATA_PROT_PIO \n");
+ }
+ break;
+
+ case HSM_ST:
+ if ((status & ATA_DRQ) == 0) {
+ if (status & (ATA_ERR | ATA_DF)) {
+ qc->err_mask |= AC_ERR_DEV;
+ } else {
+ /* HSM violation. Let EH handle this.
+ * Phantom devices also trigger this
+ * condition. Mark hint.
+ */
+ qc->err_mask |= AC_ERR_HSM | AC_ERR_NODEV_HINT;
+ }
+
+ ap->hsm_task_state = HSM_ST_ERR;
+ goto fsm_start;
+ }
+ /* For PIO reads, some devices may ask for
+ * data transfer (DRQ=1) alone with ERR=1.
+ * We respect DRQ here and transfer one
+ * block of junk data before changing the
+ * hsm_task_state to HSM_ST_ERR.
+ *
+ * For PIO writes, ERR=1 DRQ=1 doesn't make
+ * sense since the data block has been
+ * transferred to the device.
+ */
+ if (status & (ATA_ERR | ATA_DF)) {
+ qc->err_mask |= AC_ERR_DEV;
+
+ if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
+ ata_pio_sectors(qc);
+ status = ata_wait_idle(ap);
+ }
+
+ if (status & (ATA_BUSY | ATA_DRQ))
+ qc->err_mask |= AC_ERR_HSM;
+
+ /* ata_pio_sectors() might change the
+ * state to HSM_ST_LAST. so, the state
+ * is changed after ata_pio_sectors().
+ */
+ ap->hsm_task_state = HSM_ST_ERR;
+ goto fsm_start;
+ }
+
+ ata_pio_sectors(qc);
+ if (ap->hsm_task_state == HSM_ST_LAST &&
+ (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
+ status = ata_wait_idle(ap);
+ goto fsm_start;
+ }
+
+ poll_next = 1;
+ break;
+
+ case HSM_ST_LAST:
+ if (!ata_ok(status)) {
+ qc->err_mask |= __ac_err_mask(status);
+ ap->hsm_task_state = HSM_ST_ERR;
+ goto fsm_start;
+ }
+
+ ap->hsm_task_state = HSM_ST_IDLE;
+
+ ata_hsm_qc_complete(qc, in_wq);
+
+ poll_next = 0;
+ break;
+
+ case HSM_ST_ERR:
+ /* make sure qc->err_mask is available to
+ * know what's wrong and recover
+ */
+ ap->hsm_task_state = HSM_ST_IDLE;
+
+ ata_hsm_qc_complete(qc, in_wq);
+
+ poll_next = 0;
+ break;
+ default:
+ poll_next = 0;
+ }
+
+ return poll_next;
+}
+
+static void ata_pio_sectors(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap;
+ ap = pap;
+ qc->pdata = ap->pdata;
+
+ ata_pio_sector(qc);
+
+ readb(qc->ap->ioaddr.altstatus_addr);
+ udelay(1);
+}
+
+static void ata_pio_sector(struct ata_queued_cmd *qc)
+{
+ int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
+ struct ata_port *ap = qc->ap;
+ unsigned int offset;
+ unsigned char *buf;
+ char temp_data_buf[512];
+
+ if (qc->curbytes == qc->nbytes - qc->sect_size)
+ ap->hsm_task_state = HSM_ST_LAST;
+
+ offset = qc->curbytes;
+
+ switch (qc->tf.command) {
+ case ATA_CMD_ID_ATA:
+ buf = (unsigned char *)&ata_device.id[0];
+ break;
+ case ATA_CMD_PIO_READ_EXT:
+ case ATA_CMD_PIO_READ:
+ case ATA_CMD_PIO_WRITE_EXT:
+ case ATA_CMD_PIO_WRITE:
+ buf = qc->pdata + offset;
+ break;
+ default:
+ buf = (unsigned char *)&temp_data_buf[0];
+ }
+
+ ata_mmio_data_xfer(qc->dev, buf, qc->sect_size, do_write);
+
+ qc->curbytes += qc->sect_size;
+
+}
+
+static void ata_mmio_data_xfer(struct ata_device *dev, unsigned char *buf,
+ unsigned int buflen, int do_write)
+{
+ struct ata_port *ap = pap;
+ void __iomem *data_addr = ap->ioaddr.data_addr;
+ unsigned int words = buflen >> 1;
+ u16 *buf16 = (u16 *)buf;
+ unsigned int i = 0;
+
+ udelay(100);
+ if (do_write) {
+ for (i = 0; i < words; i++)
+ writew(le16_to_cpu(buf16[i]), data_addr);
+ } else {
+ for (i = 0; i < words; i++)
+ buf16[i] = cpu_to_le16(readw(data_addr));
+ }
+
+ if (buflen & 0x01) {
+ __le16 align_buf[1] = { 0 };
+ unsigned char *trailing_buf = buf + buflen - 1;
+
+ if (do_write) {
+ memcpy(align_buf, trailing_buf, 1);
+ writew(le16_to_cpu(align_buf[0]), data_addr);
+ } else {
+ align_buf[0] = cpu_to_le16(readw(data_addr));
+ memcpy(trailing_buf, align_buf, 1);
+ }
+ }
+}
+
+static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
+{
+ struct ata_port *ap = qc->ap;
+
+ if (in_wq) {
+ /* EH might have kicked in while host lock is
+ * released.
+ */
+ qc = &ap->qcmd[qc->tag];
+ if (qc) {
+ if (!(qc->err_mask & AC_ERR_HSM)) {
+ ata_irq_on(ap);
+ ata_qc_complete(qc);
+ } else {
+ ata_port_freeze(ap);
+ }
+ }
+ } else {
+ if (!(qc->err_mask & AC_ERR_HSM)) {
+ ata_qc_complete(qc);
+ } else {
+ ata_port_freeze(ap);
+ }
+ }
+}
+
+static u8 ata_irq_on(struct ata_port *ap)
+{
+ struct ata_ioports *ioaddr = &ap->ioaddr;
+ u8 tmp;
+
+ ap->ctl &= ~ATA_NIEN;
+ ap->last_ctl = ap->ctl;
+
+ if (ioaddr->ctl_addr)
+ writeb(ap->ctl, ioaddr->ctl_addr);
+
+ tmp = ata_wait_idle(ap);
+
+ return tmp;
+}
+
+static unsigned int ata_tag_internal(unsigned int tag)
+{
+ return tag == ATA_MAX_QUEUE - 1;
+}
+
+static void ata_qc_complete(struct ata_queued_cmd *qc)
+{
+ struct ata_device *dev = qc->dev;
+ if (qc->err_mask)
+ qc->flags |= ATA_QCFLAG_FAILED;
+
+ if (qc->flags & ATA_QCFLAG_FAILED) {
+ if (!ata_tag_internal(qc->tag)) {
+ fill_result_tf(qc);
+ return;
+ }
+ }
+ if (qc->flags & ATA_QCFLAG_RESULT_TF)
+ fill_result_tf(qc);
+
+ /* Some commands need post-processing after successful
+ * completion.
+ */
+ switch (qc->tf.command) {
+ case ATA_CMD_SET_FEATURES:
+ if (qc->tf.feature != SETFEATURES_WC_ON &&
+ qc->tf.feature != SETFEATURES_WC_OFF)
+ break;
+ case ATA_CMD_INIT_DEV_PARAMS:
+ case ATA_CMD_SET_MULTI:
+ break;
+
+ case ATA_CMD_SLEEP:
+ dev->flags |= ATA_DFLAG_SLEEPING;
+ break;
+ }
+
+ __ata_qc_complete(qc);
+}
+
+static void fill_result_tf(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+
+ qc->result_tf.flags = qc->tf.flags;
+ ata_tf_read(ap, &qc->result_tf);
+}
+
+static void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
+{
+ struct ata_ioports *ioaddr = &ap->ioaddr;
+
+ tf->command = ata_check_status(ap);
+ tf->feature = readb(ioaddr->error_addr);
+ tf->nsect = readb(ioaddr->nsect_addr);
+ tf->lbal = readb(ioaddr->lbal_addr);
+ tf->lbam = readb(ioaddr->lbam_addr);
+ tf->lbah = readb(ioaddr->lbah_addr);
+ tf->device = readb(ioaddr->device_addr);
+
+ if (tf->flags & ATA_TFLAG_LBA48) {
+ if (ioaddr->ctl_addr) {
+ writeb(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
+
+ tf->hob_feature = readb(ioaddr->error_addr);
+ tf->hob_nsect = readb(ioaddr->nsect_addr);
+ tf->hob_lbal = readb(ioaddr->lbal_addr);
+ tf->hob_lbam = readb(ioaddr->lbam_addr);
+ tf->hob_lbah = readb(ioaddr->lbah_addr);
+
+ writeb(tf->ctl, ioaddr->ctl_addr);
+ ap->last_ctl = tf->ctl;
+ } else {
+ printf("sata_dwc warnning register read.\n");
+ }
+ }
+}
+
+static void __ata_qc_complete(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+ struct ata_link *link = qc->dev->link;
+
+ link->active_tag = ATA_TAG_POISON;
+ ap->nr_active_links--;
+
+ if (qc->flags & ATA_QCFLAG_CLEAR_EXCL && ap->excl_link == link)
+ ap->excl_link = NULL;
+
+ qc->flags &= ~ATA_QCFLAG_ACTIVE;
+ ap->qc_active &= ~(1 << qc->tag);
+}
+
+static void ata_qc_free(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+ unsigned int tag;
+ qc->flags = 0;
+ tag = qc->tag;
+ if (tag < ATA_MAX_QUEUE) {
+ qc->tag = ATA_TAG_POISON;
+ clear_bit(tag, &ap->qc_allocated);
+ }
+}
+
+static int check_sata_dev_state(void)
+{
+ unsigned long datalen;
+ unsigned char *pdata;
+ int ret = 0;
+ int i = 0;
+ char temp_data_buf[512];
+
+ while (1) {
+ udelay(10000);
+
+ pdata = (unsigned char*)&temp_data_buf[0];
+ datalen = 512;
+
+ ret = ata_dev_read_sectors(pdata, datalen, 0, 1);
+
+ if (ret == TRUE)
+ break;
+
+ i++;
+ if (i > (ATA_RESET_TIME * 100)) {
+ printf("** TimeOUT **\n");
+ dev_state = SATA_NODEVICE;
+ return FALSE;
+ }
+
+ if ((i >= 100) && ((i % 100) == 0))
+ printf(".");
+ }
+
+ dev_state = SATA_READY;
+
+ return TRUE;
+}
+
+static unsigned int ata_dev_set_feature(struct ata_device *dev,
+ u8 enable, u8 feature)
+{
+ struct ata_taskfile tf;
+ struct ata_port *ap;
+ ap = pap;
+ unsigned int err_mask;
+
+ memset(&tf, 0, sizeof(tf));
+ tf.ctl = ap->ctl;
+
+ tf.device = ATA_DEVICE_OBS;
+ tf.command = ATA_CMD_SET_FEATURES;
+ tf.feature = enable;
+ tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
+ tf.protocol = ATA_PROT_NODATA;
+ tf.nsect = feature;
+
+ err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, 0, 0);
+
+ return err_mask;
+}
+
+static unsigned int ata_dev_init_params(struct ata_device *dev,
+ u16 heads, u16 sectors)
+{
+ struct ata_taskfile tf;
+ struct ata_port *ap;
+ ap = pap;
+ unsigned int err_mask;
+
+ if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
+ return AC_ERR_INVALID;
+
+ memset(&tf, 0, sizeof(tf));
+ tf.ctl = ap->ctl;
+ tf.device = ATA_DEVICE_OBS;
+ tf.command = ATA_CMD_INIT_DEV_PARAMS;
+ tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
+ tf.protocol = ATA_PROT_NODATA;
+ tf.nsect = sectors;
+ tf.device |= (heads - 1) & 0x0f;
+
+ err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, 0, 0);
+
+ if (err_mask == AC_ERR_DEV && (tf.feature & ATA_ABORTED))
+ err_mask = 0;
+
+ return err_mask;
+}
+
+#if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48)
+#define SATA_MAX_READ_BLK 0xFF
+#else
+#define SATA_MAX_READ_BLK 0xFFFF
+#endif
+
+ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
+{
+ ulong start,blks, buf_addr;
+ unsigned short smallblks;
+ unsigned long datalen;
+ unsigned char *pdata;
+ device &= 0xff;
+
+ u32 block = 0;
+ u32 n_block = 0;
+
+ if (dev_state != SATA_READY)
+ return 0;
+
+ buf_addr = (unsigned long)buffer;
+ start = blknr;
+ blks = blkcnt;
+ do {
+ pdata = (unsigned char *)buf_addr;
+ if (blks > SATA_MAX_READ_BLK) {
+ datalen = sata_dev_desc[device].blksz * SATA_MAX_READ_BLK;
+ smallblks = SATA_MAX_READ_BLK;
+
+ block = (u32)start;
+ n_block = (u32)smallblks;
+
+ start += SATA_MAX_READ_BLK;
+ blks -= SATA_MAX_READ_BLK;
+ } else {
+ datalen = sata_dev_desc[device].blksz * SATA_MAX_READ_BLK;
+ datalen = sata_dev_desc[device].blksz * blks;
+ smallblks = (unsigned short)blks;
+
+ block = (u32)start;
+ n_block = (u32)smallblks;
+
+ start += blks;
+ blks = 0;
+ }
+
+ if (ata_dev_read_sectors(pdata, datalen, block, n_block) != TRUE) {
+ printf("sata_dwc : Hard disk read error.\n");
+ blkcnt -= blks;
+ break;
+ }
+ buf_addr += datalen;
+ } while (blks != 0);
+
+ return (blkcnt);
+}
+
+static int ata_dev_read_sectors(unsigned char *pdata, unsigned long datalen,
+ u32 block, u32 n_block)
+{
+ struct ata_port *ap = pap;
+ struct ata_device *dev = &ata_device;
+ struct ata_taskfile tf;
+ unsigned int class = ATA_DEV_ATA;
+ unsigned int err_mask = 0;
+ const char *reason;
+ int may_fallback = 1;
+ int rc;
+
+ if (dev_state == SATA_ERROR)
+ return FALSE;
+
+ ata_dev_select(ap, dev->devno, 1, 1);
+
+retry:
+ memset(&tf, 0, sizeof(tf));
+ tf.ctl = ap->ctl;
+ ap->print_id = 1;
+ ap->flags &= ~ATA_FLAG_DISABLED;
+
+ ap->pdata = pdata;
+
+ tf.device = ATA_DEVICE_OBS;
+
+ temp_n_block = n_block;
+
+#ifdef CONFIG_LBA48
+ tf.command = ATA_CMD_PIO_READ_EXT;
+ tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_LBA48;
+
+ tf.hob_feature = 31;
+ tf.feature = 31;
+ tf.hob_nsect = (n_block >> 8) & 0xff;
+ tf.nsect = n_block & 0xff;
+
+ tf.hob_lbah = 0x0;
+ tf.hob_lbam = 0x0;
+ tf.hob_lbal = (block >> 24) & 0xff;
+ tf.lbah = (block >> 16) & 0xff;
+ tf.lbam = (block >> 8) & 0xff;
+ tf.lbal = block & 0xff;
+
+ tf.device = 1 << 6;
+ if (tf.flags & ATA_TFLAG_FUA)
+ tf.device |= 1 << 7;
+#else
+ tf.command = ATA_CMD_PIO_READ;
+ tf.flags |= ATA_TFLAG_LBA ;
+
+ tf.feature = 31;
+ tf.nsect = n_block & 0xff;
+
+ tf.lbah = (block >> 16) & 0xff;
+ tf.lbam = (block >> 8) & 0xff;
+ tf.lbal = block & 0xff;
+
+ tf.device = (block >> 24) & 0xf;
+
+ tf.device |= 1 << 6;
+ if (tf.flags & ATA_TFLAG_FUA)
+ tf.device |= 1 << 7;
+
+#endif
+
+ tf.protocol = ATA_PROT_PIO;
+
+ /* Some devices choke if TF registers contain garbage. Make
+ * sure those are properly initialized.
+ */
+ tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
+ tf.flags |= ATA_TFLAG_POLLING;
+
+ err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE, 0, 0);
+
+ if (err_mask) {
+ if (err_mask & AC_ERR_NODEV_HINT) {
+ printf("READ_SECTORS NODEV after polling detection\n");
+ return -ENOENT;
+ }
+
+ if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
+ /* Device or controller might have reported
+ * the wrong device class. Give a shot at the
+ * other IDENTIFY if the current one is
+ * aborted by the device.
+ */
+ if (may_fallback) {
+ may_fallback = 0;
+
+ if (class == ATA_DEV_ATA) {
+ class = ATA_DEV_ATAPI;
+ } else {
+ class = ATA_DEV_ATA;
+ }
+ goto retry;
+ }
+ /* Control reaches here iff the device aborted
+ * both flavors of IDENTIFYs which happens
+ * sometimes with phantom devices.
+ */
+ printf("both IDENTIFYs aborted, assuming NODEV\n");
+ return -ENOENT;
+ }
+
+ rc = -EIO;
+ reason = "I/O error";
+ goto err_out;
+ }
+
+ /* Falling back doesn't make sense if ID data was read
+ * successfully at least once.
+ */
+ may_fallback = 0;
+
+ rc = -EINVAL;
+ reason = "device reports invalid type";
+
+ return TRUE;
+
+err_out:
+ printf("failed to READ SECTORS (%s, err_mask=0x%x)\n", reason, err_mask);
+ return FALSE;
+}
+
+#if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48)
+#define SATA_MAX_WRITE_BLK 0xFF
+#else
+#define SATA_MAX_WRITE_BLK 0xFFFF
+#endif
+
+ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
+{
+ ulong start,blks, buf_addr;
+ unsigned short smallblks;
+ unsigned long datalen;
+ unsigned char *pdata;
+ device &= 0xff;
+
+
+ u32 block = 0;
+ u32 n_block = 0;
+
+ if (dev_state != SATA_READY)
+ return 0;
+
+ buf_addr = (unsigned long)buffer;
+ start = blknr;
+ blks = blkcnt;
+ do {
+ pdata = (unsigned char *)buf_addr;
+ if (blks > SATA_MAX_WRITE_BLK) {
+ datalen = sata_dev_desc[device].blksz * SATA_MAX_WRITE_BLK;
+ smallblks = SATA_MAX_WRITE_BLK;
+
+ block = (u32)start;
+ n_block = (u32)smallblks;
+
+ start += SATA_MAX_WRITE_BLK;
+ blks -= SATA_MAX_WRITE_BLK;
+ } else {
+ datalen = sata_dev_desc[device].blksz * blks;
+ smallblks = (unsigned short)blks;
+
+ block = (u32)start;
+ n_block = (u32)smallblks;
+
+ start += blks;
+ blks = 0;
+ }
+
+ if (ata_dev_write_sectors(pdata, datalen, block, n_block) != TRUE) {
+ printf("sata_dwc : Hard disk read error.\n");
+ blkcnt -= blks;
+ break;
+ }
+ buf_addr += datalen;
+ } while (blks != 0);
+
+ return (blkcnt);
+}
+
+static int ata_dev_write_sectors(unsigned char* pdata, unsigned long datalen,
+ u32 block, u32 n_block)
+{
+ struct ata_port *ap = pap;
+ struct ata_device *dev = &ata_device;
+ struct ata_taskfile tf;
+ unsigned int class = ATA_DEV_ATA;
+ unsigned int err_mask = 0;
+ const char *reason;
+ int may_fallback = 1;
+ int rc;
+
+ if (dev_state == SATA_ERROR)
+ return FALSE;
+
+ ata_dev_select(ap, dev->devno, 1, 1);
+
+retry:
+ memset(&tf, 0, sizeof(tf));
+ tf.ctl = ap->ctl;
+ ap->print_id = 1;
+ ap->flags &= ~ATA_FLAG_DISABLED;
+
+ ap->pdata = pdata;
+
+ tf.device = ATA_DEVICE_OBS;
+
+ temp_n_block = n_block;
+
+
+#ifdef CONFIG_LBA48
+ tf.command = ATA_CMD_PIO_WRITE_EXT;
+ tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_LBA48 | ATA_TFLAG_WRITE;
+
+ tf.hob_feature = 31;
+ tf.feature = 31;
+ tf.hob_nsect = (n_block >> 8) & 0xff;
+ tf.nsect = n_block & 0xff;
+
+ tf.hob_lbah = 0x0;
+ tf.hob_lbam = 0x0;
+ tf.hob_lbal = (block >> 24) & 0xff;
+ tf.lbah = (block >> 16) & 0xff;
+ tf.lbam = (block >> 8) & 0xff;
+ tf.lbal = block & 0xff;
+
+ tf.device = 1 << 6;
+ if (tf.flags & ATA_TFLAG_FUA)
+ tf.device |= 1 << 7;
+#else
+ tf.command = ATA_CMD_PIO_WRITE;
+ tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_WRITE;
+
+ tf.feature = 31;
+ tf.nsect = n_block & 0xff;
+
+ tf.lbah = (block >> 16) & 0xff;
+ tf.lbam = (block >> 8) & 0xff;
+ tf.lbal = block & 0xff;
+
+ tf.device = (block >> 24) & 0xf;
+
+ tf.device |= 1 << 6;
+ if (tf.flags & ATA_TFLAG_FUA)
+ tf.device |= 1 << 7;
+
+#endif
+
+ tf.protocol = ATA_PROT_PIO;
+
+ /* Some devices choke if TF registers contain garbage. Make
+ * sure those are properly initialized.
+ */
+ tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
+ tf.flags |= ATA_TFLAG_POLLING;
+
+ err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE, 0, 0);
+
+ if (err_mask) {
+ if (err_mask & AC_ERR_NODEV_HINT) {
+ printf("READ_SECTORS NODEV after polling detection\n");
+ return -ENOENT;
+ }
+
+ if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
+ /* Device or controller might have reported
+ * the wrong device class. Give a shot at the
+ * other IDENTIFY if the current one is
+ * aborted by the device.
+ */
+ if (may_fallback) {
+ may_fallback = 0;
+
+ if (class == ATA_DEV_ATA) {
+ class = ATA_DEV_ATAPI;
+ } else {
+ class = ATA_DEV_ATA;
+ }
+ goto retry;
+ }
+ /* Control reaches here iff the device aborted
+ * both flavors of IDENTIFYs which happens
+ * sometimes with phantom devices.
+ */
+ printf("both IDENTIFYs aborted, assuming NODEV\n");
+ return -ENOENT;
+ }
+
+ rc = -EIO;
+ reason = "I/O error";
+ goto err_out;
+ }
+
+ /* Falling back doesn't make sense if ID data was read
+ * successfully at least once.
+ */
+ may_fallback = 0;
+
+ rc = -EINVAL;
+ reason = "device reports invalid type";
+
+ return TRUE;
+
+err_out:
+ printf("failed to WRITE SECTORS (%s, err_mask=0x%x)\n", reason, err_mask);
+ return FALSE;
+}
--- /dev/null
+/*
+ * sata_dwc.h
+ *
+ * Synopsys DesignWare Cores (DWC) SATA host driver
+ *
+ * Author: Mark Miesfeld <mmiesfeld@amcc.com>
+ *
+ * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
+ * Copyright 2008 DENX Software Engineering
+ *
+ * Based on versions provided by AMCC and Synopsys which are:
+ * Copyright 2006 Applied Micro Circuits Corporation
+ * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
+ *
+ * This program is free software; you can redistribute
+ * it and/or modify it under the terms of the GNU
+ * General Public License as published by the
+ * Free Software Foundation; either version 2 of the License,
+ * or (at your option) any later version.
+ *
+ */
+/*
+ * SATA support based on the chip canyonlands.
+ *
+ * 04-17-2009
+ * The local version of this driver for the canyonlands board
+ * does not use interrupts but polls the chip instead.
+ */
+
+
+#ifndef _SATA_DWC_H_
+#define _SATA_DWC_H_
+
+#define __U_BOOT__
+
+#define HZ 100
+#define READ 0
+#define WRITE 1
+
+enum {
+ ATA_READID_POSTRESET = (1 << 0),
+
+ ATA_DNXFER_PIO = 0,
+ ATA_DNXFER_DMA = 1,
+ ATA_DNXFER_40C = 2,
+ ATA_DNXFER_FORCE_PIO = 3,
+ ATA_DNXFER_FORCE_PIO0 = 4,
+
+ ATA_DNXFER_QUIET = (1 << 31),
+};
+
+enum hsm_task_states {
+ HSM_ST_IDLE,
+ HSM_ST_FIRST,
+ HSM_ST,
+ HSM_ST_LAST,
+ HSM_ST_ERR,
+};
+
+#define ATA_SHORT_PAUSE ((HZ >> 6) + 1)
+
+struct ata_queued_cmd {
+ struct ata_port *ap;
+ struct ata_device *dev;
+
+ struct ata_taskfile tf;
+ u8 cdb[ATAPI_CDB_LEN];
+ unsigned long flags;
+ unsigned int tag;
+ unsigned int n_elem;
+
+ int dma_dir;
+ unsigned int sect_size;
+
+ unsigned int nbytes;
+ unsigned int extrabytes;
+ unsigned int curbytes;
+
+ unsigned int err_mask;
+ struct ata_taskfile result_tf;
+
+ void *private_data;
+#ifndef __U_BOOT__
+ void *lldd_task;
+#endif
+ unsigned char *pdata;
+};
+
+typedef void (*ata_qc_cb_t) (struct ata_queued_cmd *qc);
+
+#define ATA_TAG_POISON 0xfafbfcfdU
+
+enum {
+ LIBATA_MAX_PRD = ATA_MAX_PRD / 2,
+ LIBATA_DUMB_MAX_PRD = ATA_MAX_PRD / 4,
+ ATA_MAX_PORTS = 8,
+ ATA_DEF_QUEUE = 1,
+ ATA_MAX_QUEUE = 32,
+ ATA_TAG_INTERNAL = ATA_MAX_QUEUE - 1,
+ ATA_MAX_BUS = 2,
+ ATA_DEF_BUSY_WAIT = 10000,
+
+ ATAPI_MAX_DRAIN = 16 << 10,
+
+ ATA_SHT_EMULATED = 1,
+ ATA_SHT_CMD_PER_LUN = 1,
+ ATA_SHT_THIS_ID = -1,
+ ATA_SHT_USE_CLUSTERING = 1,
+
+ ATA_DFLAG_LBA = (1 << 0),
+ ATA_DFLAG_LBA48 = (1 << 1),
+ ATA_DFLAG_CDB_INTR = (1 << 2),
+ ATA_DFLAG_NCQ = (1 << 3),
+ ATA_DFLAG_FLUSH_EXT = (1 << 4),
+ ATA_DFLAG_ACPI_PENDING = (1 << 5),
+ ATA_DFLAG_ACPI_FAILED = (1 << 6),
+ ATA_DFLAG_AN = (1 << 7),
+ ATA_DFLAG_HIPM = (1 << 8),
+ ATA_DFLAG_DIPM = (1 << 9),
+ ATA_DFLAG_DMADIR = (1 << 10),
+ ATA_DFLAG_CFG_MASK = (1 << 12) - 1,
+
+ ATA_DFLAG_PIO = (1 << 12),
+ ATA_DFLAG_NCQ_OFF = (1 << 13),
+ ATA_DFLAG_SPUNDOWN = (1 << 14),
+ ATA_DFLAG_SLEEPING = (1 << 15),
+ ATA_DFLAG_DUBIOUS_XFER = (1 << 16),
+ ATA_DFLAG_INIT_MASK = (1 << 24) - 1,
+
+ ATA_DFLAG_DETACH = (1 << 24),
+ ATA_DFLAG_DETACHED = (1 << 25),
+
+ ATA_LFLAG_HRST_TO_RESUME = (1 << 0),
+ ATA_LFLAG_SKIP_D2H_BSY = (1 << 1),
+ ATA_LFLAG_NO_SRST = (1 << 2),
+ ATA_LFLAG_ASSUME_ATA = (1 << 3),
+ ATA_LFLAG_ASSUME_SEMB = (1 << 4),
+ ATA_LFLAG_ASSUME_CLASS = ATA_LFLAG_ASSUME_ATA | ATA_LFLAG_ASSUME_SEMB,
+ ATA_LFLAG_NO_RETRY = (1 << 5),
+ ATA_LFLAG_DISABLED = (1 << 6),
+
+ ATA_FLAG_SLAVE_POSS = (1 << 0),
+ ATA_FLAG_SATA = (1 << 1),
+ ATA_FLAG_NO_LEGACY = (1 << 2),
+ ATA_FLAG_MMIO = (1 << 3),
+ ATA_FLAG_SRST = (1 << 4),
+ ATA_FLAG_SATA_RESET = (1 << 5),
+ ATA_FLAG_NO_ATAPI = (1 << 6),
+ ATA_FLAG_PIO_DMA = (1 << 7),
+ ATA_FLAG_PIO_LBA48 = (1 << 8),
+ ATA_FLAG_PIO_POLLING = (1 << 9),
+ ATA_FLAG_NCQ = (1 << 10),
+ ATA_FLAG_DEBUGMSG = (1 << 13),
+ ATA_FLAG_IGN_SIMPLEX = (1 << 15),
+ ATA_FLAG_NO_IORDY = (1 << 16),
+ ATA_FLAG_ACPI_SATA = (1 << 17),
+ ATA_FLAG_AN = (1 << 18),
+ ATA_FLAG_PMP = (1 << 19),
+ ATA_FLAG_IPM = (1 << 20),
+
+ ATA_FLAG_DISABLED = (1 << 23),
+
+ ATA_PFLAG_EH_PENDING = (1 << 0),
+ ATA_PFLAG_EH_IN_PROGRESS = (1 << 1),
+ ATA_PFLAG_FROZEN = (1 << 2),
+ ATA_PFLAG_RECOVERED = (1 << 3),
+ ATA_PFLAG_LOADING = (1 << 4),
+ ATA_PFLAG_UNLOADING = (1 << 5),
+ ATA_PFLAG_SCSI_HOTPLUG = (1 << 6),
+ ATA_PFLAG_INITIALIZING = (1 << 7),
+ ATA_PFLAG_RESETTING = (1 << 8),
+ ATA_PFLAG_SUSPENDED = (1 << 17),
+ ATA_PFLAG_PM_PENDING = (1 << 18),
+
+ ATA_QCFLAG_ACTIVE = (1 << 0),
+ ATA_QCFLAG_DMAMAP = (1 << 1),
+ ATA_QCFLAG_IO = (1 << 3),
+ ATA_QCFLAG_RESULT_TF = (1 << 4),
+ ATA_QCFLAG_CLEAR_EXCL = (1 << 5),
+ ATA_QCFLAG_QUIET = (1 << 6),
+
+ ATA_QCFLAG_FAILED = (1 << 16),
+ ATA_QCFLAG_SENSE_VALID = (1 << 17),
+ ATA_QCFLAG_EH_SCHEDULED = (1 << 18),
+
+ ATA_HOST_SIMPLEX = (1 << 0),
+ ATA_HOST_STARTED = (1 << 1),
+
+ ATA_TMOUT_BOOT = 30 * 100,
+ ATA_TMOUT_BOOT_QUICK = 7 * 100,
+ ATA_TMOUT_INTERNAL = 30 * 100,
+ ATA_TMOUT_INTERNAL_QUICK = 5 * 100,
+
+ /* FIXME: GoVault needs 2s but we can't afford that without
+ * parallel probing. 800ms is enough for iVDR disk
+ * HHD424020F7SV00. Increase to 2secs when parallel probing
+ * is in place.
+ */
+ ATA_TMOUT_FF_WAIT = 4 * 100 / 5,
+
+ BUS_UNKNOWN = 0,
+ BUS_DMA = 1,
+ BUS_IDLE = 2,
+ BUS_NOINTR = 3,
+ BUS_NODATA = 4,
+ BUS_TIMER = 5,
+ BUS_PIO = 6,
+ BUS_EDD = 7,
+ BUS_IDENTIFY = 8,
+ BUS_PACKET = 9,
+
+ PORT_UNKNOWN = 0,
+ PORT_ENABLED = 1,
+ PORT_DISABLED = 2,
+
+ /* encoding various smaller bitmaps into a single
+ * unsigned long bitmap
+ */
+ ATA_NR_PIO_MODES = 7,
+ ATA_NR_MWDMA_MODES = 5,
+ ATA_NR_UDMA_MODES = 8,
+
+ ATA_SHIFT_PIO = 0,
+ ATA_SHIFT_MWDMA = ATA_SHIFT_PIO + ATA_NR_PIO_MODES,
+ ATA_SHIFT_UDMA = ATA_SHIFT_MWDMA + ATA_NR_MWDMA_MODES,
+
+ ATA_DMA_PAD_SZ = 4,
+
+ ATA_ERING_SIZE = 32,
+
+ ATA_DEFER_LINK = 1,
+ ATA_DEFER_PORT = 2,
+
+ ATA_EH_DESC_LEN = 80,
+
+ ATA_EH_REVALIDATE = (1 << 0),
+ ATA_EH_SOFTRESET = (1 << 1),
+ ATA_EH_HARDRESET = (1 << 2),
+ ATA_EH_ENABLE_LINK = (1 << 3),
+ ATA_EH_LPM = (1 << 4),
+
+ ATA_EH_RESET_MASK = ATA_EH_SOFTRESET | ATA_EH_HARDRESET,
+ ATA_EH_PERDEV_MASK = ATA_EH_REVALIDATE,
+
+ ATA_EHI_HOTPLUGGED = (1 << 0),
+ ATA_EHI_RESUME_LINK = (1 << 1),
+ ATA_EHI_NO_AUTOPSY = (1 << 2),
+ ATA_EHI_QUIET = (1 << 3),
+
+ ATA_EHI_DID_SOFTRESET = (1 << 16),
+ ATA_EHI_DID_HARDRESET = (1 << 17),
+ ATA_EHI_PRINTINFO = (1 << 18),
+ ATA_EHI_SETMODE = (1 << 19),
+ ATA_EHI_POST_SETMODE = (1 << 20),
+
+ ATA_EHI_DID_RESET = ATA_EHI_DID_SOFTRESET | ATA_EHI_DID_HARDRESET,
+ ATA_EHI_RESET_MODIFIER_MASK = ATA_EHI_RESUME_LINK,
+
+ ATA_EH_MAX_TRIES = 5,
+
+ ATA_PROBE_MAX_TRIES = 3,
+ ATA_EH_DEV_TRIES = 3,
+ ATA_EH_PMP_TRIES = 5,
+ ATA_EH_PMP_LINK_TRIES = 3,
+
+ SATA_PMP_SCR_TIMEOUT = 250,
+
+ /* Horkage types. May be set by libata or controller on drives
+ (some horkage may be drive/controller pair dependant */
+
+ ATA_HORKAGE_DIAGNOSTIC = (1 << 0),
+ ATA_HORKAGE_NODMA = (1 << 1),
+ ATA_HORKAGE_NONCQ = (1 << 2),
+ ATA_HORKAGE_MAX_SEC_128 = (1 << 3),
+ ATA_HORKAGE_BROKEN_HPA = (1 << 4),
+ ATA_HORKAGE_SKIP_PM = (1 << 5),
+ ATA_HORKAGE_HPA_SIZE = (1 << 6),
+ ATA_HORKAGE_IPM = (1 << 7),
+ ATA_HORKAGE_IVB = (1 << 8),
+ ATA_HORKAGE_STUCK_ERR = (1 << 9),
+
+ ATA_DMA_MASK_ATA = (1 << 0),
+ ATA_DMA_MASK_ATAPI = (1 << 1),
+ ATA_DMA_MASK_CFA = (1 << 2),
+
+ ATAPI_READ = 0,
+ ATAPI_WRITE = 1,
+ ATAPI_READ_CD = 2,
+ ATAPI_PASS_THRU = 3,
+ ATAPI_MISC = 4,
+};
+
+enum ata_completion_errors {
+ AC_ERR_DEV = (1 << 0),
+ AC_ERR_HSM = (1 << 1),
+ AC_ERR_TIMEOUT = (1 << 2),
+ AC_ERR_MEDIA = (1 << 3),
+ AC_ERR_ATA_BUS = (1 << 4),
+ AC_ERR_HOST_BUS = (1 << 5),
+ AC_ERR_SYSTEM = (1 << 6),
+ AC_ERR_INVALID = (1 << 7),
+ AC_ERR_OTHER = (1 << 8),
+ AC_ERR_NODEV_HINT = (1 << 9),
+ AC_ERR_NCQ = (1 << 10),
+};
+
+enum ata_xfer_mask {
+ ATA_MASK_PIO = ((1LU << ATA_NR_PIO_MODES) - 1) << ATA_SHIFT_PIO,
+ ATA_MASK_MWDMA = ((1LU << ATA_NR_MWDMA_MODES) - 1) << ATA_SHIFT_MWDMA,
+ ATA_MASK_UDMA = ((1LU << ATA_NR_UDMA_MODES) - 1) << ATA_SHIFT_UDMA,
+};
+
+struct ata_port_info {
+#ifndef __U_BOOT__
+ struct scsi_host_template *sht;
+#endif
+ unsigned long flags;
+ unsigned long link_flags;
+ unsigned long pio_mask;
+ unsigned long mwdma_mask;
+ unsigned long udma_mask;
+#ifndef __U_BOOT__
+ const struct ata_port_operations *port_ops;
+ void *private_data;
+#endif
+};
+
+struct ata_ioports {
+ void __iomem *cmd_addr;
+ void __iomem *data_addr;
+ void __iomem *error_addr;
+ void __iomem *feature_addr;
+ void __iomem *nsect_addr;
+ void __iomem *lbal_addr;
+ void __iomem *lbam_addr;
+ void __iomem *lbah_addr;
+ void __iomem *device_addr;
+ void __iomem *status_addr;
+ void __iomem *command_addr;
+ void __iomem *altstatus_addr;
+ void __iomem *ctl_addr;
+#ifndef __U_BOOT__
+ void __iomem *bmdma_addr;
+#endif
+ void __iomem *scr_addr;
+};
+
+struct ata_host {
+#ifndef __U_BOOT__
+ void __iomem * const *iomap;
+ void *private_data;
+ const struct ata_port_operations *ops;
+ unsigned long flags;
+ struct ata_port *simplex_claimed;
+#endif
+ unsigned int n_ports;
+ struct ata_port *ports[0];
+};
+
+#ifndef __U_BOOT__
+struct ata_port_stats {
+ unsigned long unhandled_irq;
+ unsigned long idle_irq;
+ unsigned long rw_reqbuf;
+};
+#endif
+
+struct ata_device {
+ struct ata_link *link;
+ unsigned int devno;
+ unsigned long flags;
+ unsigned int horkage;
+#ifndef __U_BOOT__
+ struct scsi_device *sdev;
+#ifdef CONFIG_ATA_ACPI
+ acpi_handle acpi_handle;
+ union acpi_object *gtf_cache;
+#endif
+#endif
+ u64 n_sectors;
+ unsigned int class;
+
+ union {
+ u16 id[ATA_ID_WORDS];
+ u32 gscr[SATA_PMP_GSCR_DWORDS];
+ };
+#ifndef __U_BOOT__
+ u8 pio_mode;
+ u8 dma_mode;
+ u8 xfer_mode;
+ unsigned int xfer_shift;
+#endif
+ unsigned int multi_count;
+ unsigned int max_sectors;
+ unsigned int cdb_len;
+#ifndef __U_BOOT__
+ unsigned long pio_mask;
+ unsigned long mwdma_mask;
+#endif
+ unsigned long udma_mask;
+ u16 cylinders;
+ u16 heads;
+ u16 sectors;
+#ifndef __U_BOOT__
+ int spdn_cnt;
+#endif
+};
+
+enum dma_data_direction {
+ DMA_BIDIRECTIONAL = 0,
+ DMA_TO_DEVICE = 1,
+ DMA_FROM_DEVICE = 2,
+ DMA_NONE = 3,
+};
+
+struct ata_link {
+ struct ata_port *ap;
+ int pmp;
+ unsigned int active_tag;
+ u32 sactive;
+ unsigned int flags;
+ unsigned int hw_sata_spd_limit;
+#ifndef __U_BOOT__
+ unsigned int sata_spd_limit;
+ unsigned int sata_spd;
+ struct ata_device device[2];
+#endif
+};
+
+struct ata_port {
+ unsigned long flags;
+ unsigned int pflags;
+ unsigned int print_id;
+ unsigned int port_no;
+
+ struct ata_ioports ioaddr;
+
+ u8 ctl;
+ u8 last_ctl;
+ unsigned int pio_mask;
+ unsigned int mwdma_mask;
+ unsigned int udma_mask;
+ unsigned int cbl;
+
+ struct ata_queued_cmd qcmd[ATA_MAX_QUEUE];
+ unsigned long qc_allocated;
+ unsigned int qc_active;
+ int nr_active_links;
+
+ struct ata_link link;
+#ifndef __U_BOOT__
+ int nr_pmp_links;
+ struct ata_link *pmp_link;
+#endif
+ struct ata_link *excl_link;
+ int nr_pmp_links;
+#ifndef __U_BOOT__
+ struct ata_port_stats stats;
+ struct device *dev;
+ u32 msg_enable;
+#endif
+ struct ata_host *host;
+ void *port_task_data;
+
+ unsigned int hsm_task_state;
+ void *private_data;
+ unsigned char *pdata;
+};
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#endif
LIB := $(obj)libgpio.a
+COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
COBJS-$(CONFIG_MX31_GPIO) += mx31_gpio.o
COBJS-$(CONFIG_PCA953X) += pca953x.o
--- /dev/null
+/*
+ * arch/arm/plat-orion/gpio.c
+ *
+ * Marvell Orion SoC GPIO handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/*
+ * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
+ * Removed orion_gpiochip struct and kernel level irq handling.
+ *
+ * Dieter Kiermaier dk-arm-linux@gmx.de
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/gpio.h>
+
+static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)];
+static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)];
+
+void __set_direction(unsigned pin, int input)
+{
+ u32 u;
+
+ u = readl(GPIO_IO_CONF(pin));
+ if (input)
+ u |= 1 << (pin & 31);
+ else
+ u &= ~(1 << (pin & 31));
+ writel(u, GPIO_IO_CONF(pin));
+
+ u = readl(GPIO_IO_CONF(pin));
+}
+
+void __set_level(unsigned pin, int high)
+{
+ u32 u;
+
+ u = readl(GPIO_OUT(pin));
+ if (high)
+ u |= 1 << (pin & 31);
+ else
+ u &= ~(1 << (pin & 31));
+ writel(u, GPIO_OUT(pin));
+}
+
+void __set_blinking(unsigned pin, int blink)
+{
+ u32 u;
+
+ u = readl(GPIO_BLINK_EN(pin));
+ if (blink)
+ u |= 1 << (pin & 31);
+ else
+ u &= ~(1 << (pin & 31));
+ writel(u, GPIO_BLINK_EN(pin));
+}
+
+int kw_gpio_is_valid(unsigned pin, int mode)
+{
+ if (pin < GPIO_MAX) {
+ if ((mode & GPIO_INPUT_OK) && !test_bit(pin, gpio_valid_input))
+ goto err_out;
+
+ if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, gpio_valid_output))
+ goto err_out;
+ return 0;
+ }
+
+err_out:
+ printf("%s: invalid GPIO %d\n", __func__, pin);
+ return 1;
+}
+
+void kw_gpio_set_valid(unsigned pin, int mode)
+{
+ if (mode == 1)
+ mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
+ if (mode & GPIO_INPUT_OK)
+ __set_bit(pin, gpio_valid_input);
+ else
+ __clear_bit(pin, gpio_valid_input);
+ if (mode & GPIO_OUTPUT_OK)
+ __set_bit(pin, gpio_valid_output);
+ else
+ __clear_bit(pin, gpio_valid_output);
+}
+/*
+ * GENERIC_GPIO primitives.
+ */
+int kw_gpio_direction_input(unsigned pin)
+{
+ if (!kw_gpio_is_valid(pin, GPIO_INPUT_OK))
+ return 1;
+
+ /* Configure GPIO direction. */
+ __set_direction(pin, 1);
+
+ return 0;
+}
+
+int kw_gpio_direction_output(unsigned pin, int value)
+{
+ if (kw_gpio_is_valid(pin, GPIO_OUTPUT_OK) != 0)
+ {
+ printf("%s: invalid GPIO %d\n", __func__, pin);
+ return 1;
+ }
+
+ __set_blinking(pin, 0);
+
+ /* Configure GPIO output value. */
+ __set_level(pin, value);
+
+ /* Configure GPIO direction. */
+ __set_direction(pin, 0);
+
+ return 0;
+}
+
+int kw_gpio_get_value(unsigned pin)
+{
+ int val;
+
+ if (readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)))
+ val = readl(GPIO_DATA_IN(pin)) ^ readl(GPIO_IN_POL(pin));
+ else
+ val = readl(GPIO_OUT(pin));
+
+ return (val >> (pin & 31)) & 1;
+}
+
+void kw_gpio_set_value(unsigned pin, int value)
+{
+ /* Configure GPIO output value. */
+ __set_level(pin, value);
+}
+
+void kw_gpio_set_blink(unsigned pin, int blink)
+{
+ /* Set output value to zero. */
+ __set_level(pin, 0);
+
+ /* Set blinking. */
+ __set_blinking(pin, blink);
+}
COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o
+COBJS-$(CONFIG_I2C_KIRKWOOD) += kirkwood_i2c.o
COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
struct fsl_i2c *dev;
unsigned int temp;
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+ /* call board specific i2c bus reset routine before accessing the */
+ /* environment, which might be in a chip on that bus. For details */
+ /* about this problem see doc/I2C_Edge_Conditions. */
+ i2c_init_board();
+#endif
dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
writeb(0, &dev->cr); /* stop I2C controller */
--- /dev/null
+/*
+ * Driver for the i2c controller on the Marvell line of host bridges
+ * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, Orion SoC family),
+ * and Kirkwood family.
+ *
+ * Based on:
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2005 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * ported from Linux to u-boot
+ * (C) Copyright 2009
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ */
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0;
+#if defined(CONFIG_I2C_MUX)
+static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0;
+#endif
+
+/* Register defines */
+#define KW_I2C_REG_SLAVE_ADDR 0x00
+#define KW_I2C_REG_DATA 0x04
+#define KW_I2C_REG_CONTROL 0x08
+#define KW_I2C_REG_STATUS 0x0c
+#define KW_I2C_REG_BAUD 0x0c
+#define KW_I2C_REG_EXT_SLAVE_ADDR 0x10
+#define KW_I2C_REG_SOFT_RESET 0x1c
+
+#define KW_I2C_REG_CONTROL_ACK 0x00000004
+#define KW_I2C_REG_CONTROL_IFLG 0x00000008
+#define KW_I2C_REG_CONTROL_STOP 0x00000010
+#define KW_I2C_REG_CONTROL_START 0x00000020
+#define KW_I2C_REG_CONTROL_TWSIEN 0x00000040
+#define KW_I2C_REG_CONTROL_INTEN 0x00000080
+
+/* Ctlr status values */
+#define KW_I2C_STATUS_BUS_ERR 0x00
+#define KW_I2C_STATUS_MAST_START 0x08
+#define KW_I2C_STATUS_MAST_REPEAT_START 0x10
+#define KW_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
+#define KW_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
+#define KW_I2C_STATUS_MAST_WR_ACK 0x28
+#define KW_I2C_STATUS_MAST_WR_NO_ACK 0x30
+#define KW_I2C_STATUS_MAST_LOST_ARB 0x38
+#define KW_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
+#define KW_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
+#define KW_I2C_STATUS_MAST_RD_DATA_ACK 0x50
+#define KW_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
+#define KW_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
+#define KW_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
+#define KW_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
+#define KW_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
+#define KW_I2C_STATUS_NO_STATUS 0xf8
+
+/* Driver states */
+enum {
+ KW_I2C_STATE_INVALID,
+ KW_I2C_STATE_IDLE,
+ KW_I2C_STATE_WAITING_FOR_START_COND,
+ KW_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
+ KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
+ KW_I2C_STATE_WAITING_FOR_SLAVE_ACK,
+ KW_I2C_STATE_WAITING_FOR_SLAVE_DATA,
+};
+
+/* Driver actions */
+enum {
+ KW_I2C_ACTION_INVALID,
+ KW_I2C_ACTION_CONTINUE,
+ KW_I2C_ACTION_SEND_START,
+ KW_I2C_ACTION_SEND_ADDR_1,
+ KW_I2C_ACTION_SEND_ADDR_2,
+ KW_I2C_ACTION_SEND_DATA,
+ KW_I2C_ACTION_RCV_DATA,
+ KW_I2C_ACTION_RCV_DATA_STOP,
+ KW_I2C_ACTION_SEND_STOP,
+};
+
+/* defines to get compatible with Linux driver */
+#define IRQ_NONE 0x0
+#define IRQ_HANDLED 0x01
+
+#define I2C_M_TEN 0x01
+#define I2C_M_RD 0x02
+#define I2C_M_REV_DIR_ADDR 0x04;
+
+struct i2c_msg {
+ u32 addr;
+ u32 flags;
+ u8 *buf;
+ u32 len;
+};
+
+struct kirkwood_i2c_data {
+ int irq;
+ u32 state;
+ u32 action;
+ u32 aborting;
+ u32 cntl_bits;
+ void *reg_base;
+ u32 reg_base_p;
+ u32 reg_size;
+ u32 addr1;
+ u32 addr2;
+ u32 bytes_left;
+ u32 byte_posn;
+ u32 block;
+ int rc;
+ u32 freq_m;
+ u32 freq_n;
+ struct i2c_msg *msg;
+};
+
+static struct kirkwood_i2c_data __drv_data __attribute__ ((section (".data")));
+static struct kirkwood_i2c_data *drv_data = &__drv_data;
+static struct i2c_msg __i2c_msg __attribute__ ((section (".data")));
+static struct i2c_msg *kirkwood_i2c_msg = &__i2c_msg;
+
+/*
+ *****************************************************************************
+ *
+ * Finite State Machine & Interrupt Routines
+ *
+ *****************************************************************************
+ */
+
+static inline int abs(int n)
+{
+ if(n >= 0)
+ return n;
+ else
+ return n * -1;
+}
+
+static void kirkwood_calculate_speed(int speed)
+{
+ int calcspeed;
+ int diff;
+ int best_diff = CONFIG_SYS_TCLK;
+ int best_speed = 0;
+ int m, n;
+ int tmp[8] = {2, 4, 8, 16, 32, 64, 128, 256};
+
+ for (n = 0; n < 8; n++) {
+ for (m = 0; m < 16; m++) {
+ calcspeed = CONFIG_SYS_TCLK / (10 * (m + 1) * tmp[n]);
+ diff = abs((speed - calcspeed));
+ if ( diff < best_diff) {
+ best_diff = diff;
+ best_speed = calcspeed;
+ drv_data->freq_m = m;
+ drv_data->freq_n = n;
+ }
+ }
+ }
+}
+
+/* Reset hardware and initialize FSM */
+static void
+kirkwood_i2c_hw_init(int speed, int slaveadd)
+{
+ drv_data->state = KW_I2C_STATE_IDLE;
+
+ kirkwood_calculate_speed(speed);
+ writel(0, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_SOFT_RESET);
+ writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)),
+ CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_BAUD);
+ writel(slaveadd, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_SLAVE_ADDR);
+ writel(0, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_EXT_SLAVE_ADDR);
+ writel(KW_I2C_REG_CONTROL_TWSIEN | KW_I2C_REG_CONTROL_STOP,
+ CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
+}
+
+static void
+kirkwood_i2c_fsm(u32 status)
+{
+ /*
+ * If state is idle, then this is likely the remnants of an old
+ * operation that driver has given up on or the user has killed.
+ * If so, issue the stop condition and go to idle.
+ */
+ if (drv_data->state == KW_I2C_STATE_IDLE) {
+ drv_data->action = KW_I2C_ACTION_SEND_STOP;
+ return;
+ }
+
+ /* The status from the ctlr [mostly] tells us what to do next */
+ switch (status) {
+ /* Start condition interrupt */
+ case KW_I2C_STATUS_MAST_START: /* 0x08 */
+ case KW_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
+ drv_data->action = KW_I2C_ACTION_SEND_ADDR_1;
+ drv_data->state = KW_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
+ break;
+
+ /* Performing a write */
+ case KW_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
+ if (drv_data->msg->flags & I2C_M_TEN) {
+ drv_data->action = KW_I2C_ACTION_SEND_ADDR_2;
+ drv_data->state =
+ KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
+ break;
+ }
+ /* FALLTHRU */
+ case KW_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
+ case KW_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
+ if ((drv_data->bytes_left == 0)
+ || (drv_data->aborting
+ && (drv_data->byte_posn != 0))) {
+ drv_data->action = KW_I2C_ACTION_SEND_STOP;
+ drv_data->state = KW_I2C_STATE_IDLE;
+ } else {
+ drv_data->action = KW_I2C_ACTION_SEND_DATA;
+ drv_data->state =
+ KW_I2C_STATE_WAITING_FOR_SLAVE_ACK;
+ drv_data->bytes_left--;
+ }
+ break;
+
+ /* Performing a read */
+ case KW_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
+ if (drv_data->msg->flags & I2C_M_TEN) {
+ drv_data->action = KW_I2C_ACTION_SEND_ADDR_2;
+ drv_data->state =
+ KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
+ break;
+ }
+ /* FALLTHRU */
+ case KW_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
+ if (drv_data->bytes_left == 0) {
+ drv_data->action = KW_I2C_ACTION_SEND_STOP;
+ drv_data->state = KW_I2C_STATE_IDLE;
+ break;
+ }
+ /* FALLTHRU */
+ case KW_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
+ if (status != KW_I2C_STATUS_MAST_RD_DATA_ACK)
+ drv_data->action = KW_I2C_ACTION_CONTINUE;
+ else {
+ drv_data->action = KW_I2C_ACTION_RCV_DATA;
+ drv_data->bytes_left--;
+ }
+ drv_data->state = KW_I2C_STATE_WAITING_FOR_SLAVE_DATA;
+
+ if ((drv_data->bytes_left == 1) || drv_data->aborting)
+ drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_ACK;
+ break;
+
+ case KW_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
+ drv_data->action = KW_I2C_ACTION_RCV_DATA_STOP;
+ drv_data->state = KW_I2C_STATE_IDLE;
+ break;
+
+ case KW_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
+ case KW_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
+ case KW_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
+ /* Doesn't seem to be a device at other end */
+ drv_data->action = KW_I2C_ACTION_SEND_STOP;
+ drv_data->state = KW_I2C_STATE_IDLE;
+ drv_data->rc = -ENODEV;
+ break;
+
+ default:
+ printf("kirkwood_i2c_fsm: Ctlr Error -- state: 0x%x, "
+ "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
+ drv_data->state, status, drv_data->msg->addr,
+ drv_data->msg->flags);
+ drv_data->action = KW_I2C_ACTION_SEND_STOP;
+ kirkwood_i2c_hw_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ drv_data->rc = -EIO;
+ }
+}
+
+static void
+kirkwood_i2c_do_action(void)
+{
+ switch(drv_data->action) {
+ case KW_I2C_ACTION_CONTINUE:
+ writel(drv_data->cntl_bits,
+ CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
+ break;
+
+ case KW_I2C_ACTION_SEND_START:
+ writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_START,
+ CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
+ break;
+
+ case KW_I2C_ACTION_SEND_ADDR_1:
+ writel(drv_data->addr1,
+ CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
+ writel(drv_data->cntl_bits,
+ CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
+ break;
+
+ case KW_I2C_ACTION_SEND_ADDR_2:
+ writel(drv_data->addr2,
+ CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
+ writel(drv_data->cntl_bits,
+ CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
+ break;
+
+ case KW_I2C_ACTION_SEND_DATA:
+ writel(drv_data->msg->buf[drv_data->byte_posn++],
+ CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
+ writel(drv_data->cntl_bits,
+ CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
+ break;
+
+ case KW_I2C_ACTION_RCV_DATA:
+ drv_data->msg->buf[drv_data->byte_posn++] =
+ readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
+ writel(drv_data->cntl_bits,
+ CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
+ break;
+
+ case KW_I2C_ACTION_RCV_DATA_STOP:
+ drv_data->msg->buf[drv_data->byte_posn++] =
+ readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
+ drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_INTEN;
+ writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_STOP,
+ CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
+ drv_data->block = 0;
+ break;
+
+ case KW_I2C_ACTION_INVALID:
+ default:
+ printf("kirkwood_i2c_do_action: Invalid action: %d\n",
+ drv_data->action);
+ drv_data->rc = -EIO;
+ /* FALLTHRU */
+ case KW_I2C_ACTION_SEND_STOP:
+ drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_INTEN;
+ writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_STOP,
+ CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
+ drv_data->block = 0;
+ break;
+ }
+}
+
+static int
+kirkwood_i2c_intr(void)
+{
+ u32 status;
+ u32 ctrl;
+ int rc = IRQ_NONE;
+
+ ctrl = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
+ while ((ctrl & KW_I2C_REG_CONTROL_IFLG) &&
+ (drv_data->rc == 0)) {
+ status = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_STATUS);
+ kirkwood_i2c_fsm(status);
+ kirkwood_i2c_do_action();
+ rc = IRQ_HANDLED;
+ ctrl = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
+ udelay(1000);
+ }
+ return rc;
+}
+
+static void
+kirkwood_i2c_doio(struct i2c_msg *msg)
+{
+ int ret;
+
+ while ((drv_data->rc == 0) && (drv_data->state != KW_I2C_STATE_IDLE)) {
+ /* poll Status register */
+ ret = kirkwood_i2c_intr();
+ if (ret == IRQ_NONE)
+ udelay(10);
+ }
+}
+
+static void
+kirkwood_i2c_prepare_for_io(struct i2c_msg *msg)
+{
+ u32 dir = 0;
+
+ drv_data->msg = msg;
+ drv_data->byte_posn = 0;
+ drv_data->bytes_left = msg->len;
+ drv_data->aborting = 0;
+ drv_data->rc = 0;
+ /* in u-boot we use no IRQs */
+ drv_data->cntl_bits = KW_I2C_REG_CONTROL_ACK | KW_I2C_REG_CONTROL_TWSIEN;
+
+ if (msg->flags & I2C_M_RD)
+ dir = 1;
+ if (msg->flags & I2C_M_TEN) {
+ drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
+ drv_data->addr2 = (u32)msg->addr & 0xff;
+ } else {
+ drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir;
+ drv_data->addr2 = 0;
+ }
+ /* OK, no start it (from kirkwood_i2c_execute_msg())*/
+ drv_data->action = KW_I2C_ACTION_SEND_START;
+ drv_data->state = KW_I2C_STATE_WAITING_FOR_START_COND;
+ drv_data->block = 1;
+ kirkwood_i2c_do_action();
+}
+
+void
+i2c_init(int speed, int slaveadd)
+{
+ kirkwood_i2c_hw_init(speed, slaveadd);
+}
+
+int
+i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
+{
+ kirkwood_i2c_msg->buf = data;
+ kirkwood_i2c_msg->len = length;
+ kirkwood_i2c_msg->addr = dev;
+ kirkwood_i2c_msg->flags = I2C_M_RD;
+
+ kirkwood_i2c_prepare_for_io(kirkwood_i2c_msg);
+ kirkwood_i2c_doio(kirkwood_i2c_msg);
+ return drv_data->rc;
+}
+
+int
+i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
+{
+ kirkwood_i2c_msg->buf = data;
+ kirkwood_i2c_msg->len = length;
+ kirkwood_i2c_msg->addr = dev;
+ kirkwood_i2c_msg->flags = 0;
+
+ kirkwood_i2c_prepare_for_io(kirkwood_i2c_msg);
+ kirkwood_i2c_doio(kirkwood_i2c_msg);
+ return drv_data->rc;
+}
+
+int
+i2c_probe(uchar chip)
+{
+ return i2c_read(chip, 0, 0, NULL, 0);
+}
+
+int i2c_set_bus_num(unsigned int bus)
+{
+#if defined(CONFIG_I2C_MUX)
+ if (bus < CONFIG_SYS_MAX_I2C_BUS) {
+ i2c_bus_num = bus;
+ } else {
+ int ret;
+
+ ret = i2x_mux_select_mux(bus);
+ if (ret)
+ return ret;
+ i2c_bus_num = 0;
+ }
+ i2c_bus_num_mux = bus;
+#else
+ if (bus > 0) {
+ return -1;
+ }
+
+ i2c_bus_num = bus;
+#endif
+ return 0;
+}
+
+unsigned int i2c_get_bus_num(void)
+{
+#if defined(CONFIG_I2C_MUX)
+ return i2c_bus_num_mux;
+#else
+ return i2c_bus_num;
+#endif
+}
+
void i2c_init (int speed, int slaveadd)
{
- u16 scl;
+ int psc, fsscll, fssclh;
+ int hsscll = 0, hssclh = 0;
+ u32 scll, sclh;
+
+ /* Only handle standard, fast and high speeds */
+ if ((speed != OMAP_I2C_STANDARD) &&
+ (speed != OMAP_I2C_FAST_MODE) &&
+ (speed != OMAP_I2C_HIGH_SPEED)) {
+ printf("Error : I2C unsupported speed %d\n", speed);
+ return;
+ }
+
+ psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
+ psc -= 1;
+ if (psc < I2C_PSC_MIN) {
+ printf("Error : I2C unsupported prescalar %d\n", psc);
+ return;
+ }
+
+ if (speed == OMAP_I2C_HIGH_SPEED) {
+ /* High speed */
+
+ /* For first phase of HS mode */
+ fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
+ (2 * OMAP_I2C_FAST_MODE);
+
+ fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
+ fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
+ if (((fsscll < 0) || (fssclh < 0)) ||
+ ((fsscll > 255) || (fssclh > 255))) {
+ printf("Error : I2C initializing first phase clock\n");
+ return;
+ }
+
+ /* For second phase of HS mode */
+ hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
+
+ hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
+ hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
+ if (((fsscll < 0) || (fssclh < 0)) ||
+ ((fsscll > 255) || (fssclh > 255))) {
+ printf("Error : I2C initializing second phase clock\n");
+ return;
+ }
+
+ scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
+ sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
+
+ } else {
+ /* Standard and fast speed */
+ fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
+
+ fsscll -= I2C_FASTSPEED_SCLL_TRIM;
+ fssclh -= I2C_FASTSPEED_SCLH_TRIM;
+ if (((fsscll < 0) || (fssclh < 0)) ||
+ ((fsscll > 255) || (fssclh > 255))) {
+ printf("Error : I2C initializing clock\n");
+ return;
+ }
+
+ scll = (unsigned int)fsscll;
+ sclh = (unsigned int)fssclh;
+ }
writew(0x2, I2C_SYSC); /* for ES2 after soft reset */
udelay(1000);
udelay (50000);
}
- /* 12MHz I2C module clock */
- writew (0, I2C_PSC);
- speed = speed/1000; /* 100 or 400 */
- scl = ((12000/(speed*2)) - 7); /* use 7 when PSC = 0 */
- writew (scl, I2C_SCLL);
- writew (scl, I2C_SCLH);
+ writew(psc, I2C_PSC);
+ writew(scll, I2C_SCLL);
+ writew(sclh, I2C_SCLH);
+
/* own address */
writew (slaveadd, I2C_OA);
writew (I2C_CON_EN, I2C_CON);
#include <common.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <keyboard.h>
#undef KBG_DEBUG
int kbd_init (void)
{
int error;
- device_t kbddev ;
+ struct stdio_dev kbddev ;
char *stdinname = getenv ("stdin");
if(kbd_init_hw()==-1)
kbddev.getc = kbd_getc ;
kbddev.tstc = kbd_testc ;
- error = device_register (&kbddev);
+ error = stdio_register (&kbddev);
if(error==0) {
/* check if this is the standard input device */
if(strcmp(stdinname,DEVNAME)==0) {
COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
COBJS-$(CONFIG_NS87308) += ns87308.o
COBJS-$(CONFIG_STATUS_LED) += status_led.o
+COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix at windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * twl4030_led_init is from cpu/omap3/common.c, power_init_r
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05 at gmail.com>
+ * Shashi Ranjan <shashiranjanmca05 at gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2 at ti.com>
+ * Syed Mohammed Khasim <khasim at ti.com>
+ *
+ */
+
+#include <twl4030.h>
+
+#define LEDAON (0x1 << 0)
+#define LEDBON (0x1 << 1)
+#define LEDAPWM (0x1 << 4)
+#define LEDBPWM (0x1 << 5)
+
+void twl4030_led_init(void)
+{
+ unsigned char byte;
+
+ /* enable LED */
+ byte = LEDBPWM | LEDAPWM | LEDBON | LEDAON;
+
+ twl4030_i2c_write_u8(TWL4030_CHIP_LED, byte,
+ TWL4030_LED_LEDEN);
+
+}
#include <config.h>
#include <common.h>
#include <command.h>
+#include <hwconfig.h>
#include <mmc.h>
#include <part.h>
#include <malloc.h>
#include <mmc.h>
#include <fsl_esdhc.h>
+#include <fdt_support.h>
#include <asm/io.h>
{
return esdhc_initialize(bis);
}
+
+void fdt_fixup_esdhc(void *blob, bd_t *bd)
+{
+ const char *compat = "fsl,esdhc";
+ const char *status = "okay";
+
+ if (!hwconfig("esdhc")) {
+ status = "disabled";
+ goto out;
+ }
+
+ do_fixup_by_compat_u32(blob, compat, "clock-frequency",
+ gd->sdhc_clk, 1);
+out:
+ do_fixup_by_compat(blob, compat, "status", status,
+ strlen(status) + 1, 1);
+}
if (err)
return err;
+ mmc_set_bus_width(mmc, 1);
+ mmc_set_clock(mmc, 1);
+
/* Reset the Card */
err = mmc_go_idle(mmc);
#include <mmc.h>
#include <part.h>
#include <i2c.h>
+#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/mmc.h>
return (block_dev_desc_t *) &mmc_blk_dev;
}
-void twl4030_mmc_config(void)
-{
- unsigned char data;
-
- data = DEV_GRP_P1;
- i2c_write(PWRMGT_ADDR_ID4, VMMC1_DEV_GRP, 1, &data, 1);
- data = VMMC1_VSEL_30;
- i2c_write(PWRMGT_ADDR_ID4, VMMC1_DEDICATED, 1, &data, 1);
-}
-
unsigned char mmc_board_init(void)
{
t2_t *t2_base = (t2_t *)T2_BASE;
- twl4030_mmc_config();
+ twl4030_power_mmc_init();
writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
#include <linux/mtd/mtd.h>
#include <linux/mtd/concat.h>
+/* use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined */
+#ifdef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
+# define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS_DETECT
+#else
+# define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS
+#endif
+
extern flash_info_t flash_info[];
-static struct mtd_info cfi_mtd_info[CONFIG_SYS_MAX_FLASH_BANKS];
-static char cfi_mtd_names[CONFIG_SYS_MAX_FLASH_BANKS][16];
+static struct mtd_info cfi_mtd_info[CFI_MAX_FLASH_BANKS];
+static char cfi_mtd_names[CFI_MAX_FLASH_BANKS][16];
#ifdef CONFIG_MTD_CONCAT
static char c_mtd_name[16];
#endif
LIB := $(obj)libnand.a
ifdef CONFIG_CMD_NAND
-ifndef CONFIG_NAND_LEGACY
COBJS-y += nand.o
COBJS-y += nand_base.o
COBJS-y += nand_bbt.o
COBJS-y += nand_ecc.o
COBJS-y += nand_ids.o
COBJS-y += nand_util.o
-endif
COBJS-$(CONFIG_NAND_ATMEL) += atmel_nand.o
COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
COBJS-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
+COBJS-$(CONFIG_NAND_NDFC) += ndfc.o
COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
* knowledge of the clocks and what devices are hooked up ... and
* don't even do that unless no UBL handled it.
*/
-#ifdef CONFIG_SOC_DM6446
+#ifdef CONFIG_SOC_DM644X
u_int32_t acfg1 = 0x3ffffffc;
/*------------------------------------------------------------------*
#include <common.h>
-#if !defined(CONFIG_NAND_LEGACY)
-
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sched.h>
MODULE_LICENSE("GPL");
MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
MODULE_DESCRIPTION("M-Systems DiskOnChip 2000, Millennium and Millennium Plus device driver\n");
-#endif
if (len_incl_bad == *length) {
rval = nand_read (nand, offset, length, buffer);
- if (rval != 0)
- printf ("NAND read from offset %llx failed %d\n",
- offset, rval);
-
+ if (!rval || rval == -EUCLEAN)
+ return 0;
+ printf ("NAND read from offset %llx failed %d\n",
+ offset, rval);
return rval;
}
read_length = nand->erasesize - block_offset;
rval = nand_read (nand, offset, &read_length, p_buffer);
- if (rval != 0) {
+ if (rval && rval != -EUCLEAN) {
printf ("NAND read from offset %llx failed %d\n",
offset, rval);
*length -= left_to_read;
*/
#include <common.h>
-
-#if defined(CONFIG_CMD_NAND) && !defined(CONFIG_NAND_LEGACY) && \
- defined(CONFIG_NAND_NDFC)
-
#include <nand.h>
#include <linux/mtd/ndfc.h>
#include <linux/mtd/nand_ecc.h>
return 0;
}
-
-#endif
+++ /dev/null
-/*
- * (C) 2006 Denx
- * Driver for NAND support, Rick Bronson
- * borrowed heavily from:
- * (c) 1999 Machine Vision Holdings, Inc.
- * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org>
- *
- * Added 16-bit nand support
- * (C) 2004 Texas Instruments
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <watchdog.h>
-#include <linux/mtd/nand_legacy.h>
-#include <linux/mtd/nand_ids.h>
-#include <jffs2/jffs2.h>
-
-#error Legacy NAND is deprecated. Please convert to the current NAND interface.
-#error This code will be removed outright in the next release.
-
-#ifdef CONFIG_OMAP1510
-void archflashwp(void *archdata, int wp);
-#endif
-
-#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
-
-#undef PSYCHO_DEBUG
-#undef NAND_DEBUG
-
-/* ****************** WARNING *********************
- * When ALLOW_ERASE_BAD_DEBUG is non-zero the erase command will
- * erase (or at least attempt to erase) blocks that are marked
- * bad. This can be very handy if you are _sure_ that the block
- * is OK, say because you marked a good block bad to test bad
- * block handling and you are done testing, or if you have
- * accidentally marked blocks bad.
- *
- * Erasing factory marked bad blocks is a _bad_ idea. If the
- * erase succeeds there is no reliable way to find them again,
- * and attempting to program or erase bad blocks can affect
- * the data in _other_ (good) blocks.
- */
-#define ALLOW_ERASE_BAD_DEBUG 0
-
-#define CONFIG_MTD_NAND_ECC /* enable ECC */
-#define CONFIG_MTD_NAND_ECC_JFFS2
-
-/* bits for nand_legacy_rw() `cmd'; or together as needed */
-#define NANDRW_READ 0x01
-#define NANDRW_WRITE 0x00
-#define NANDRW_JFFS2 0x02
-#define NANDRW_JFFS2_SKIP 0x04
-
-
-/*
- * Exported variables etc.
- */
-
-/* Definition of the out of band configuration structure */
-struct nand_oob_config {
- /* position of ECC bytes inside oob */
- int ecc_pos[6];
- /* position of bad blk flag inside oob -1 = inactive */
- int badblock_pos;
- /* position of ECC valid flag inside oob -1 = inactive */
- int eccvalid_pos;
-} oob_config = { {0}, 0, 0};
-
-struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE] = {{0}};
-
-int curr_device = -1; /* Current NAND Device */
-
-
-/*
- * Exported functionss
- */
-int nand_legacy_erase(struct nand_chip* nand, size_t ofs,
- size_t len, int clean);
-int nand_legacy_rw(struct nand_chip* nand, int cmd,
- size_t start, size_t len,
- size_t * retlen, u_char * buf);
-void nand_print(struct nand_chip *nand);
-void nand_print_bad(struct nand_chip *nand);
-int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
- size_t * retlen, u_char * buf);
-int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
- size_t * retlen, const u_char * buf);
-
-/*
- * Internals
- */
-static int NanD_WaitReady(struct nand_chip *nand, int ale_wait);
-static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
- size_t * retlen, u_char *buf, u_char *ecc_code);
-static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
- size_t * retlen, const u_char * buf,
- u_char * ecc_code);
-#ifdef CONFIG_MTD_NAND_ECC
-static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc);
-static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code);
-#endif
-
-
-/*
- *
- * Function definitions
- *
- */
-
-/* returns 0 if block containing pos is OK:
- * valid erase block and
- * not marked bad, or no bad mark position is specified
- * returns 1 if marked bad or otherwise invalid
- */
-static int check_block (struct nand_chip *nand, unsigned long pos)
-{
- size_t retlen;
- uint8_t oob_data;
- uint16_t oob_data16[6];
- int page0 = pos & (-nand->erasesize);
- int page1 = page0 + nand->oobblock;
- int badpos = oob_config.badblock_pos;
-
- if (pos >= nand->totlen)
- return 1;
-
- if (badpos < 0)
- return 0; /* no way to check, assume OK */
-
- if (nand->bus16) {
- if (nand_read_oob(nand, (page0 + 0), 12, &retlen, (uint8_t *)oob_data16)
- || (oob_data16[2] & 0xff00) != 0xff00)
- return 1;
- if (nand_read_oob(nand, (page1 + 0), 12, &retlen, (uint8_t *)oob_data16)
- || (oob_data16[2] & 0xff00) != 0xff00)
- return 1;
- } else {
- /* Note - bad block marker can be on first or second page */
- if (nand_read_oob(nand, page0 + badpos, 1, &retlen, (unsigned char *)&oob_data)
- || oob_data != 0xff
- || nand_read_oob (nand, page1 + badpos, 1, &retlen, (unsigned char *)&oob_data)
- || oob_data != 0xff)
- return 1;
- }
-
- return 0;
-}
-
-/* print bad blocks in NAND flash */
-void nand_print_bad(struct nand_chip* nand)
-{
- unsigned long pos;
-
- for (pos = 0; pos < nand->totlen; pos += nand->erasesize) {
- if (check_block(nand, pos))
- printf(" 0x%8.8lx\n", pos);
- }
- puts("\n");
-}
-
-/* cmd: 0: NANDRW_WRITE write, fail on bad block
- * 1: NANDRW_READ read, fail on bad block
- * 2: NANDRW_WRITE | NANDRW_JFFS2 write, skip bad blocks
- * 3: NANDRW_READ | NANDRW_JFFS2 read, data all 0xff for bad blocks
- * 7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks
- */
-int nand_legacy_rw (struct nand_chip* nand, int cmd,
- size_t start, size_t len,
- size_t * retlen, u_char * buf)
-{
- int ret = 0, n, total = 0;
- char eccbuf[6];
- /* eblk (once set) is the start of the erase block containing the
- * data being processed.
- */
- unsigned long eblk = ~0; /* force mismatch on first pass */
- unsigned long erasesize = nand->erasesize;
-
- while (len) {
- if ((start & (-erasesize)) != eblk) {
- /* have crossed into new erase block, deal with
- * it if it is sure marked bad.
- */
- eblk = start & (-erasesize); /* start of block */
- if (check_block(nand, eblk)) {
- if (cmd == (NANDRW_READ | NANDRW_JFFS2)) {
- while (len > 0 &&
- start - eblk < erasesize) {
- *(buf++) = 0xff;
- ++start;
- ++total;
- --len;
- }
- continue;
- } else if (cmd == (NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP)) {
- start += erasesize;
- continue;
- } else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) {
- /* skip bad block */
- start += erasesize;
- continue;
- } else {
- ret = 1;
- break;
- }
- }
- }
- /* The ECC will not be calculated correctly if
- less than 512 is written or read */
- /* Is request at least 512 bytes AND it starts on a proper boundry */
- if((start != ROUND_DOWN(start, 0x200)) || (len < 0x200))
- printf("Warning block writes should be at least 512 bytes and start on a 512 byte boundry\n");
-
- if (cmd & NANDRW_READ) {
- ret = nand_read_ecc(nand, start,
- min(len, eblk + erasesize - start),
- (size_t *)&n, (u_char*)buf, (u_char *)eccbuf);
- } else {
- ret = nand_write_ecc(nand, start,
- min(len, eblk + erasesize - start),
- (size_t *)&n, (u_char*)buf, (u_char *)eccbuf);
- }
-
- if (ret)
- break;
-
- start += n;
- buf += n;
- total += n;
- len -= n;
- }
- if (retlen)
- *retlen = total;
-
- return ret;
-}
-
-void nand_print(struct nand_chip *nand)
-{
- if (nand->numchips > 1) {
- printf("%s at 0x%lx,\n"
- "\t %d chips %s, size %d MB, \n"
- "\t total size %ld MB, sector size %ld kB\n",
- nand->name, nand->IO_ADDR, nand->numchips,
- nand->chips_name, 1 << (nand->chipshift - 20),
- nand->totlen >> 20, nand->erasesize >> 10);
- }
- else {
- printf("%s at 0x%lx (", nand->chips_name, nand->IO_ADDR);
- print_size(nand->totlen, ", ");
- print_size(nand->erasesize, " sector)\n");
- }
-}
-
-/* ------------------------------------------------------------------------- */
-
-static int NanD_WaitReady(struct nand_chip *nand, int ale_wait)
-{
- /* This is inline, to optimise the common case, where it's ready instantly */
- int ret = 0;
-
-#ifdef NAND_NO_RB /* in config file, shorter delays currently wrap accesses */
- if(ale_wait)
- NAND_WAIT_READY(nand); /* do the worst case 25us wait */
- else
- udelay(10);
-#else /* has functional r/b signal */
- NAND_WAIT_READY(nand);
-#endif
- return ret;
-}
-
-/* NanD_Command: Send a flash command to the flash chip */
-
-static inline int NanD_Command(struct nand_chip *nand, unsigned char command)
-{
- unsigned long nandptr = nand->IO_ADDR;
-
- /* Assert the CLE (Command Latch Enable) line to the flash chip */
- NAND_CTL_SETCLE(nandptr);
-
- /* Send the command */
- WRITE_NAND_COMMAND(command, nandptr);
-
- /* Lower the CLE line */
- NAND_CTL_CLRCLE(nandptr);
-
-#ifdef NAND_NO_RB
- if(command == NAND_CMD_RESET){
- u_char ret_val;
- NanD_Command(nand, NAND_CMD_STATUS);
- do {
- ret_val = READ_NAND(nandptr);/* wait till ready */
- } while((ret_val & 0x40) != 0x40);
- }
-#endif
- return NanD_WaitReady(nand, 0);
-}
-
-/* NanD_Address: Set the current address for the flash chip */
-
-static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs)
-{
- unsigned long nandptr;
- int i;
-
- nandptr = nand->IO_ADDR;
-
- /* Assert the ALE (Address Latch Enable) line to the flash chip */
- NAND_CTL_SETALE(nandptr);
-
- /* Send the address */
- /* Devices with 256-byte page are addressed as:
- * Column (bits 0-7), Page (bits 8-15, 16-23, 24-31)
- * there is no device on the market with page256
- * and more than 24 bits.
- * Devices with 512-byte page are addressed as:
- * Column (bits 0-7), Page (bits 9-16, 17-24, 25-31)
- * 25-31 is sent only if the chip support it.
- * bit 8 changes the read command to be sent
- * (NAND_CMD_READ0 or NAND_CMD_READ1).
- */
-
- if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE)
- WRITE_NAND_ADDRESS(ofs, nandptr);
-
- ofs = ofs >> nand->page_shift;
-
- if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) {
- for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8) {
- WRITE_NAND_ADDRESS(ofs, nandptr);
- }
- }
-
- /* Lower the ALE line */
- NAND_CTL_CLRALE(nandptr);
-
- /* Wait for the chip to respond */
- return NanD_WaitReady(nand, 1);
-}
-
-/* NanD_SelectChip: Select a given flash chip within the current floor */
-
-static inline int NanD_SelectChip(struct nand_chip *nand, int chip)
-{
- /* Wait for it to be ready */
- return NanD_WaitReady(nand, 0);
-}
-
-/* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */
-
-static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip)
-{
- int mfr, id, i;
-
- NAND_ENABLE_CE(nand); /* set pin low */
- /* Reset the chip */
- if (NanD_Command(nand, NAND_CMD_RESET)) {
-#ifdef NAND_DEBUG
- printf("NanD_Command (reset) for %d,%d returned true\n",
- floor, chip);
-#endif
- NAND_DISABLE_CE(nand); /* set pin high */
- return 0;
- }
-
- /* Read the NAND chip ID: 1. Send ReadID command */
- if (NanD_Command(nand, NAND_CMD_READID)) {
-#ifdef NAND_DEBUG
- printf("NanD_Command (ReadID) for %d,%d returned true\n",
- floor, chip);
-#endif
- NAND_DISABLE_CE(nand); /* set pin high */
- return 0;
- }
-
- /* Read the NAND chip ID: 2. Send address byte zero */
- NanD_Address(nand, ADDR_COLUMN, 0);
-
- /* Read the manufacturer and device id codes from the device */
-
- mfr = READ_NAND(nand->IO_ADDR);
-
- id = READ_NAND(nand->IO_ADDR);
-
- NAND_DISABLE_CE(nand); /* set pin high */
-
-#ifdef NAND_DEBUG
- printf("NanD_Command (ReadID) got %x %x\n", mfr, id);
-#endif
- if (mfr == 0xff || mfr == 0) {
- /* No response - return failure */
- return 0;
- }
-
- /* Check it's the same as the first chip we identified.
- * M-Systems say that any given nand_chip device should only
- * contain _one_ type of flash part, although that's not a
- * hardware restriction. */
- if (nand->mfr) {
- if (nand->mfr == mfr && nand->id == id) {
- return 1; /* This is another the same the first */
- } else {
- printf("Flash chip at floor %d, chip %d is different:\n",
- floor, chip);
- }
- }
-
- /* Print and store the manufacturer and ID codes. */
- for (i = 0; nand_flash_ids[i].name != NULL; i++) {
- if (mfr == nand_flash_ids[i].manufacture_id &&
- id == nand_flash_ids[i].model_id) {
-#ifdef NAND_DEBUG
- printf("Flash chip found:\n\t Manufacturer ID: 0x%2.2X, "
- "Chip ID: 0x%2.2X (%s)\n", mfr, id,
- nand_flash_ids[i].name);
-#endif
- if (!nand->mfr) {
- nand->mfr = mfr;
- nand->id = id;
- nand->chipshift =
- nand_flash_ids[i].chipshift;
- nand->page256 = nand_flash_ids[i].page256;
- nand->eccsize = 256;
- if (nand->page256) {
- nand->oobblock = 256;
- nand->oobsize = 8;
- nand->page_shift = 8;
- } else {
- nand->oobblock = 512;
- nand->oobsize = 16;
- nand->page_shift = 9;
- }
- nand->pageadrlen = nand_flash_ids[i].pageadrlen;
- nand->erasesize = nand_flash_ids[i].erasesize;
- nand->chips_name = nand_flash_ids[i].name;
- nand->bus16 = nand_flash_ids[i].bus16;
- return 1;
- }
- return 0;
- }
- }
-
-
-#ifdef NAND_DEBUG
- /* We haven't fully identified the chip. Print as much as we know. */
- printf("Unknown flash chip found: %2.2X %2.2X\n",
- id, mfr);
-#endif
-
- return 0;
-}
-
-/* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */
-
-static void NanD_ScanChips(struct nand_chip *nand)
-{
- int floor, chip;
- int numchips[NAND_MAX_FLOORS];
- int maxchips = CONFIG_SYS_NAND_MAX_CHIPS;
- int ret = 1;
-
- nand->numchips = 0;
- nand->mfr = 0;
- nand->id = 0;
-
-
- /* For each floor, find the number of valid chips it contains */
- for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
- ret = 1;
- numchips[floor] = 0;
- for (chip = 0; chip < maxchips && ret != 0; chip++) {
-
- ret = NanD_IdentChip(nand, floor, chip);
- if (ret) {
- numchips[floor]++;
- nand->numchips++;
- }
- }
- }
-
- /* If there are none at all that we recognise, bail */
- if (!nand->numchips) {
-#ifdef NAND_DEBUG
- puts ("No NAND flash chips recognised.\n");
-#endif
- return;
- }
-
- /* Allocate an array to hold the information for each chip */
- nand->chips = malloc(sizeof(struct Nand) * nand->numchips);
- if (!nand->chips) {
- puts ("No memory for allocating chip info structures\n");
- return;
- }
-
- ret = 0;
-
- /* Fill out the chip array with {floor, chipno} for each
- * detected chip in the device. */
- for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
- for (chip = 0; chip < numchips[floor]; chip++) {
- nand->chips[ret].floor = floor;
- nand->chips[ret].chip = chip;
- nand->chips[ret].curadr = 0;
- nand->chips[ret].curmode = 0x50;
- ret++;
- }
- }
-
- /* Calculate and print the total size of the device */
- nand->totlen = nand->numchips * (1 << nand->chipshift);
-
-#ifdef NAND_DEBUG
- printf("%d flash chips found. Total nand_chip size: %ld MB\n",
- nand->numchips, nand->totlen >> 20);
-#endif
-}
-
-/* we need to be fast here, 1 us per read translates to 1 second per meg */
-static void NanD_ReadBuf (struct nand_chip *nand, u_char * data_buf, int cntr)
-{
- unsigned long nandptr = nand->IO_ADDR;
-
- NanD_Command (nand, NAND_CMD_READ0);
-
- if (nand->bus16) {
- u16 val;
-
- while (cntr >= 16) {
- val = READ_NAND (nandptr);
- *data_buf++ = val & 0xff;
- *data_buf++ = val >> 8;
- val = READ_NAND (nandptr);
- *data_buf++ = val & 0xff;
- *data_buf++ = val >> 8;
- val = READ_NAND (nandptr);
- *data_buf++ = val & 0xff;
- *data_buf++ = val >> 8;
- val = READ_NAND (nandptr);
- *data_buf++ = val & 0xff;
- *data_buf++ = val >> 8;
- val = READ_NAND (nandptr);
- *data_buf++ = val & 0xff;
- *data_buf++ = val >> 8;
- val = READ_NAND (nandptr);
- *data_buf++ = val & 0xff;
- *data_buf++ = val >> 8;
- val = READ_NAND (nandptr);
- *data_buf++ = val & 0xff;
- *data_buf++ = val >> 8;
- val = READ_NAND (nandptr);
- *data_buf++ = val & 0xff;
- *data_buf++ = val >> 8;
- cntr -= 16;
- }
-
- while (cntr > 0) {
- val = READ_NAND (nandptr);
- *data_buf++ = val & 0xff;
- *data_buf++ = val >> 8;
- cntr -= 2;
- }
- } else {
- while (cntr >= 16) {
- *data_buf++ = READ_NAND (nandptr);
- *data_buf++ = READ_NAND (nandptr);
- *data_buf++ = READ_NAND (nandptr);
- *data_buf++ = READ_NAND (nandptr);
- *data_buf++ = READ_NAND (nandptr);
- *data_buf++ = READ_NAND (nandptr);
- *data_buf++ = READ_NAND (nandptr);
- *data_buf++ = READ_NAND (nandptr);
- *data_buf++ = READ_NAND (nandptr);
- *data_buf++ = READ_NAND (nandptr);
- *data_buf++ = READ_NAND (nandptr);
- *data_buf++ = READ_NAND (nandptr);
- *data_buf++ = READ_NAND (nandptr);
- *data_buf++ = READ_NAND (nandptr);
- *data_buf++ = READ_NAND (nandptr);
- *data_buf++ = READ_NAND (nandptr);
- cntr -= 16;
- }
-
- while (cntr > 0) {
- *data_buf++ = READ_NAND (nandptr);
- cntr--;
- }
- }
-}
-
-/*
- * NAND read with ECC
- */
-static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
- size_t * retlen, u_char *buf, u_char *ecc_code)
-{
- int col, page;
- int ecc_status = 0;
-#ifdef CONFIG_MTD_NAND_ECC
- int j;
- int ecc_failed = 0;
- u_char *data_poi;
- u_char ecc_calc[6];
-#endif
-
- /* Do not allow reads past end of device */
- if ((start + len) > nand->totlen) {
- printf ("%s: Attempt read beyond end of device %x %x %x\n",
- __FUNCTION__, (uint) start, (uint) len, (uint) nand->totlen);
- *retlen = 0;
- return -1;
- }
-
- /* First we calculate the starting page */
- /*page = shr(start, nand->page_shift);*/
- page = start >> nand->page_shift;
-
- /* Get raw starting column */
- col = start & (nand->oobblock - 1);
-
- /* Initialize return value */
- *retlen = 0;
-
- /* Select the NAND device */
- NAND_ENABLE_CE(nand); /* set pin low */
-
- /* Loop until all data read */
- while (*retlen < len) {
-
-#ifdef CONFIG_MTD_NAND_ECC
- /* Do we have this page in cache ? */
- if (nand->cache_page == page)
- goto readdata;
- /* Send the read command */
- NanD_Command(nand, NAND_CMD_READ0);
- if (nand->bus16) {
- NanD_Address(nand, ADDR_COLUMN_PAGE,
- (page << nand->page_shift) + (col >> 1));
- } else {
- NanD_Address(nand, ADDR_COLUMN_PAGE,
- (page << nand->page_shift) + col);
- }
-
- /* Read in a page + oob data */
- NanD_ReadBuf(nand, nand->data_buf, nand->oobblock + nand->oobsize);
-
- /* copy data into cache, for read out of cache and if ecc fails */
- if (nand->data_cache) {
- memcpy (nand->data_cache, nand->data_buf,
- nand->oobblock + nand->oobsize);
- }
-
- /* Pick the ECC bytes out of the oob data */
- for (j = 0; j < 6; j++) {
- ecc_code[j] = nand->data_buf[(nand->oobblock + oob_config.ecc_pos[j])];
- }
-
- /* Calculate the ECC and verify it */
- /* If block was not written with ECC, skip ECC */
- if (oob_config.eccvalid_pos != -1 &&
- (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0x0f) != 0x0f) {
-
- nand_calculate_ecc (&nand->data_buf[0], &ecc_calc[0]);
- switch (nand_correct_data (&nand->data_buf[0], &ecc_code[0], &ecc_calc[0])) {
- case -1:
- printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page);
- ecc_failed++;
- break;
- case 1:
- case 2: /* transfer ECC corrected data to cache */
- if (nand->data_cache)
- memcpy (nand->data_cache, nand->data_buf, 256);
- break;
- }
- }
-
- if (oob_config.eccvalid_pos != -1 &&
- nand->oobblock == 512 && (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0xf0) != 0xf0) {
-
- nand_calculate_ecc (&nand->data_buf[256], &ecc_calc[3]);
- switch (nand_correct_data (&nand->data_buf[256], &ecc_code[3], &ecc_calc[3])) {
- case -1:
- printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page);
- ecc_failed++;
- break;
- case 1:
- case 2: /* transfer ECC corrected data to cache */
- if (nand->data_cache)
- memcpy (&nand->data_cache[256], &nand->data_buf[256], 256);
- break;
- }
- }
-readdata:
- /* Read the data from ECC data buffer into return buffer */
- data_poi = (nand->data_cache) ? nand->data_cache : nand->data_buf;
- data_poi += col;
- if ((*retlen + (nand->oobblock - col)) >= len) {
- memcpy (buf + *retlen, data_poi, len - *retlen);
- *retlen = len;
- } else {
- memcpy (buf + *retlen, data_poi, nand->oobblock - col);
- *retlen += nand->oobblock - col;
- }
- /* Set cache page address, invalidate, if ecc_failed */
- nand->cache_page = (nand->data_cache && !ecc_failed) ? page : -1;
-
- ecc_status += ecc_failed;
- ecc_failed = 0;
-
-#else
- /* Send the read command */
- NanD_Command(nand, NAND_CMD_READ0);
- if (nand->bus16) {
- NanD_Address(nand, ADDR_COLUMN_PAGE,
- (page << nand->page_shift) + (col >> 1));
- } else {
- NanD_Address(nand, ADDR_COLUMN_PAGE,
- (page << nand->page_shift) + col);
- }
-
- /* Read the data directly into the return buffer */
- if ((*retlen + (nand->oobblock - col)) >= len) {
- NanD_ReadBuf(nand, buf + *retlen, len - *retlen);
- *retlen = len;
- /* We're done */
- continue;
- } else {
- NanD_ReadBuf(nand, buf + *retlen, nand->oobblock - col);
- *retlen += nand->oobblock - col;
- }
-#endif
- /* For subsequent reads align to page boundary. */
- col = 0;
- /* Increment page address */
- page++;
- }
-
- /* De-select the NAND device */
- NAND_DISABLE_CE(nand); /* set pin high */
-
- /*
- * Return success, if no ECC failures, else -EIO
- * fs driver will take care of that, because
- * retlen == desired len and result == -EIO
- */
- return ecc_status ? -1 : 0;
-}
-
-/*
- * Nand_page_program function is used for write and writev !
- */
-static int nand_write_page (struct nand_chip *nand,
- int page, int col, int last, u_char * ecc_code)
-{
-
- int i;
- unsigned long nandptr = nand->IO_ADDR;
-
-#ifdef CONFIG_MTD_NAND_ECC
-#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
- int ecc_bytes = (nand->oobblock == 512) ? 6 : 3;
-#endif
-#endif
- /* pad oob area */
- for (i = nand->oobblock; i < nand->oobblock + nand->oobsize; i++)
- nand->data_buf[i] = 0xff;
-
-#ifdef CONFIG_MTD_NAND_ECC
- /* Zero out the ECC array */
- for (i = 0; i < 6; i++)
- ecc_code[i] = 0x00;
-
- /* Read back previous written data, if col > 0 */
- if (col) {
- NanD_Command (nand, NAND_CMD_READ0);
- if (nand->bus16) {
- NanD_Address (nand, ADDR_COLUMN_PAGE,
- (page << nand->page_shift) + (col >> 1));
- } else {
- NanD_Address (nand, ADDR_COLUMN_PAGE,
- (page << nand->page_shift) + col);
- }
-
- if (nand->bus16) {
- u16 val;
-
- for (i = 0; i < col; i += 2) {
- val = READ_NAND (nandptr);
- nand->data_buf[i] = val & 0xff;
- nand->data_buf[i + 1] = val >> 8;
- }
- } else {
- for (i = 0; i < col; i++)
- nand->data_buf[i] = READ_NAND (nandptr);
- }
- }
-
- /* Calculate and write the ECC if we have enough data */
- if ((col < nand->eccsize) && (last >= nand->eccsize)) {
- nand_calculate_ecc (&nand->data_buf[0], &(ecc_code[0]));
- for (i = 0; i < 3; i++) {
- nand->data_buf[(nand->oobblock +
- oob_config.ecc_pos[i])] = ecc_code[i];
- }
- if (oob_config.eccvalid_pos != -1) {
- nand->data_buf[nand->oobblock +
- oob_config.eccvalid_pos] = 0xf0;
- }
- }
-
- /* Calculate and write the second ECC if we have enough data */
- if ((nand->oobblock == 512) && (last == nand->oobblock)) {
- nand_calculate_ecc (&nand->data_buf[256], &(ecc_code[3]));
- for (i = 3; i < 6; i++) {
- nand->data_buf[(nand->oobblock +
- oob_config.ecc_pos[i])] = ecc_code[i];
- }
- if (oob_config.eccvalid_pos != -1) {
- nand->data_buf[nand->oobblock +
- oob_config.eccvalid_pos] &= 0x0f;
- }
- }
-#endif
- /* Prepad for partial page programming !!! */
- for (i = 0; i < col; i++)
- nand->data_buf[i] = 0xff;
-
- /* Postpad for partial page programming !!! oob is already padded */
- for (i = last; i < nand->oobblock; i++)
- nand->data_buf[i] = 0xff;
-
- /* Send command to begin auto page programming */
- NanD_Command (nand, NAND_CMD_READ0);
- NanD_Command (nand, NAND_CMD_SEQIN);
- if (nand->bus16) {
- NanD_Address (nand, ADDR_COLUMN_PAGE,
- (page << nand->page_shift) + (col >> 1));
- } else {
- NanD_Address (nand, ADDR_COLUMN_PAGE,
- (page << nand->page_shift) + col);
- }
-
- /* Write out complete page of data */
- if (nand->bus16) {
- for (i = 0; i < (nand->oobblock + nand->oobsize); i += 2) {
- WRITE_NAND (nand->data_buf[i] +
- (nand->data_buf[i + 1] << 8),
- nand->IO_ADDR);
- }
- } else {
- for (i = 0; i < (nand->oobblock + nand->oobsize); i++)
- WRITE_NAND (nand->data_buf[i], nand->IO_ADDR);
- }
-
- /* Send command to actually program the data */
- NanD_Command (nand, NAND_CMD_PAGEPROG);
- NanD_Command (nand, NAND_CMD_STATUS);
-#ifdef NAND_NO_RB
- {
- u_char ret_val;
-
- do {
- ret_val = READ_NAND (nandptr); /* wait till ready */
- } while ((ret_val & 0x40) != 0x40);
- }
-#endif
- /* See if device thinks it succeeded */
- if (READ_NAND (nand->IO_ADDR) & 0x01) {
- printf ("%s: Failed write, page 0x%08x, ", __FUNCTION__,
- page);
- return -1;
- }
-#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
- /*
- * The NAND device assumes that it is always writing to
- * a cleanly erased page. Hence, it performs its internal
- * write verification only on bits that transitioned from
- * 1 to 0. The device does NOT verify the whole page on a
- * byte by byte basis. It is possible that the page was
- * not completely erased or the page is becoming unusable
- * due to wear. The read with ECC would catch the error
- * later when the ECC page check fails, but we would rather
- * catch it early in the page write stage. Better to write
- * no data than invalid data.
- */
-
- /* Send command to read back the page */
- if (col < nand->eccsize)
- NanD_Command (nand, NAND_CMD_READ0);
- else
- NanD_Command (nand, NAND_CMD_READ1);
- if (nand->bus16) {
- NanD_Address (nand, ADDR_COLUMN_PAGE,
- (page << nand->page_shift) + (col >> 1));
- } else {
- NanD_Address (nand, ADDR_COLUMN_PAGE,
- (page << nand->page_shift) + col);
- }
-
- /* Loop through and verify the data */
- if (nand->bus16) {
- for (i = col; i < last; i = +2) {
- if ((nand->data_buf[i] +
- (nand->data_buf[i + 1] << 8)) != READ_NAND (nand->IO_ADDR)) {
- printf ("%s: Failed write verify, page 0x%08x ",
- __FUNCTION__, page);
- return -1;
- }
- }
- } else {
- for (i = col; i < last; i++) {
- if (nand->data_buf[i] != READ_NAND (nand->IO_ADDR)) {
- printf ("%s: Failed write verify, page 0x%08x ",
- __FUNCTION__, page);
- return -1;
- }
- }
- }
-
-#ifdef CONFIG_MTD_NAND_ECC
- /*
- * We also want to check that the ECC bytes wrote
- * correctly for the same reasons stated above.
- */
- NanD_Command (nand, NAND_CMD_READOOB);
- if (nand->bus16) {
- NanD_Address (nand, ADDR_COLUMN_PAGE,
- (page << nand->page_shift) + (col >> 1));
- } else {
- NanD_Address (nand, ADDR_COLUMN_PAGE,
- (page << nand->page_shift) + col);
- }
- if (nand->bus16) {
- for (i = 0; i < nand->oobsize; i += 2) {
- u16 val;
-
- val = READ_NAND (nand->IO_ADDR);
- nand->data_buf[i] = val & 0xff;
- nand->data_buf[i + 1] = val >> 8;
- }
- } else {
- for (i = 0; i < nand->oobsize; i++) {
- nand->data_buf[i] = READ_NAND (nand->IO_ADDR);
- }
- }
- for (i = 0; i < ecc_bytes; i++) {
- if ((nand->data_buf[(oob_config.ecc_pos[i])] != ecc_code[i]) && ecc_code[i]) {
- printf ("%s: Failed ECC write "
- "verify, page 0x%08x, "
- "%6i bytes were succesful\n",
- __FUNCTION__, page, i);
- return -1;
- }
- }
-#endif /* CONFIG_MTD_NAND_ECC */
-#endif /* CONFIG_MTD_NAND_VERIFY_WRITE */
- return 0;
-}
-
-static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
- size_t * retlen, const u_char * buf, u_char * ecc_code)
-{
- int i, page, col, cnt, ret = 0;
-
- /* Do not allow write past end of device */
- if ((to + len) > nand->totlen) {
- printf ("%s: Attempt to write past end of page\n", __FUNCTION__);
- return -1;
- }
-
- /* Shift to get page */
- page = ((int) to) >> nand->page_shift;
-
- /* Get the starting column */
- col = to & (nand->oobblock - 1);
-
- /* Initialize return length value */
- *retlen = 0;
-
- /* Select the NAND device */
-#ifdef CONFIG_OMAP1510
- archflashwp(0,0);
-#endif
-#ifdef CONFIG_SYS_NAND_WP
- NAND_WP_OFF();
-#endif
-
- NAND_ENABLE_CE(nand); /* set pin low */
-
- /* Check the WP bit */
- NanD_Command(nand, NAND_CMD_STATUS);
- if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
- printf ("%s: Device is write protected!!!\n", __FUNCTION__);
- ret = -1;
- goto out;
- }
-
- /* Loop until all data is written */
- while (*retlen < len) {
- /* Invalidate cache, if we write to this page */
- if (nand->cache_page == page)
- nand->cache_page = -1;
-
- /* Write data into buffer */
- if ((col + len) >= nand->oobblock) {
- for (i = col, cnt = 0; i < nand->oobblock; i++, cnt++) {
- nand->data_buf[i] = buf[(*retlen + cnt)];
- }
- } else {
- for (i = col, cnt = 0; cnt < (len - *retlen); i++, cnt++) {
- nand->data_buf[i] = buf[(*retlen + cnt)];
- }
- }
- /* We use the same function for write and writev !) */
- ret = nand_write_page (nand, page, col, i, ecc_code);
- if (ret)
- goto out;
-
- /* Next data start at page boundary */
- col = 0;
-
- /* Update written bytes count */
- *retlen += cnt;
-
- /* Increment page address */
- page++;
- }
-
- /* Return happy */
- *retlen = len;
-
-out:
- /* De-select the NAND device */
- NAND_DISABLE_CE(nand); /* set pin high */
-#ifdef CONFIG_OMAP1510
- archflashwp(0,1);
-#endif
-#ifdef CONFIG_SYS_NAND_WP
- NAND_WP_ON();
-#endif
-
- return ret;
-}
-
-/* read from the 16 bytes of oob data that correspond to a 512 byte
- * page or 2 256-byte pages.
- */
-int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
- size_t * retlen, u_char * buf)
-{
- int len256 = 0;
- struct Nand *mychip;
- int ret = 0;
-
- mychip = &nand->chips[ofs >> nand->chipshift];
-
- /* update address for 2M x 8bit devices. OOB starts on the second */
- /* page to maintain compatibility with nand_read_ecc. */
- if (nand->page256) {
- if (!(ofs & 0x8))
- ofs += 0x100;
- else
- ofs -= 0x8;
- }
-
- NAND_ENABLE_CE(nand); /* set pin low */
- NanD_Command(nand, NAND_CMD_READOOB);
- if (nand->bus16) {
- NanD_Address(nand, ADDR_COLUMN_PAGE,
- ((ofs >> nand->page_shift) << nand->page_shift) +
- ((ofs & (nand->oobblock - 1)) >> 1));
- } else {
- NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
- }
-
- /* treat crossing 8-byte OOB data for 2M x 8bit devices */
- /* Note: datasheet says it should automaticaly wrap to the */
- /* next OOB block, but it didn't work here. mf. */
- if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
- len256 = (ofs | 0x7) + 1 - ofs;
- NanD_ReadBuf(nand, buf, len256);
-
- NanD_Command(nand, NAND_CMD_READOOB);
- NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
- }
-
- NanD_ReadBuf(nand, &buf[len256], len - len256);
-
- *retlen = len;
- /* Reading the full OOB data drops us off of the end of the page,
- * causing the flash device to go into busy mode, so we need
- * to wait until ready 11.4.1 and Toshiba TC58256FT nands */
-
- ret = NanD_WaitReady(nand, 1);
- NAND_DISABLE_CE(nand); /* set pin high */
-
- return ret;
-
-}
-
-/* write to the 16 bytes of oob data that correspond to a 512 byte
- * page or 2 256-byte pages.
- */
-int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
- size_t * retlen, const u_char * buf)
-{
- int len256 = 0;
- int i;
- unsigned long nandptr = nand->IO_ADDR;
-
-#ifdef PSYCHO_DEBUG
- printf("nand_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n",
- (long)ofs, len, buf[0], buf[1], buf[2], buf[3],
- buf[8], buf[9], buf[14],buf[15]);
-#endif
-
- NAND_ENABLE_CE(nand); /* set pin low to enable chip */
-
- /* Reset the chip */
- NanD_Command(nand, NAND_CMD_RESET);
-
- /* issue the Read2 command to set the pointer to the Spare Data Area. */
- NanD_Command(nand, NAND_CMD_READOOB);
- if (nand->bus16) {
- NanD_Address(nand, ADDR_COLUMN_PAGE,
- ((ofs >> nand->page_shift) << nand->page_shift) +
- ((ofs & (nand->oobblock - 1)) >> 1));
- } else {
- NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
- }
-
- /* update address for 2M x 8bit devices. OOB starts on the second */
- /* page to maintain compatibility with nand_read_ecc. */
- if (nand->page256) {
- if (!(ofs & 0x8))
- ofs += 0x100;
- else
- ofs -= 0x8;
- }
-
- /* issue the Serial Data In command to initial the Page Program process */
- NanD_Command(nand, NAND_CMD_SEQIN);
- if (nand->bus16) {
- NanD_Address(nand, ADDR_COLUMN_PAGE,
- ((ofs >> nand->page_shift) << nand->page_shift) +
- ((ofs & (nand->oobblock - 1)) >> 1));
- } else {
- NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
- }
-
- /* treat crossing 8-byte OOB data for 2M x 8bit devices */
- /* Note: datasheet says it should automaticaly wrap to the */
- /* next OOB block, but it didn't work here. mf. */
- if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
- len256 = (ofs | 0x7) + 1 - ofs;
- for (i = 0; i < len256; i++)
- WRITE_NAND(buf[i], nandptr);
-
- NanD_Command(nand, NAND_CMD_PAGEPROG);
- NanD_Command(nand, NAND_CMD_STATUS);
-#ifdef NAND_NO_RB
- { u_char ret_val;
- do {
- ret_val = READ_NAND(nandptr); /* wait till ready */
- } while ((ret_val & 0x40) != 0x40);
- }
-#endif
- if (READ_NAND(nandptr) & 1) {
- puts ("Error programming oob data\n");
- /* There was an error */
- NAND_DISABLE_CE(nand); /* set pin high */
- *retlen = 0;
- return -1;
- }
- NanD_Command(nand, NAND_CMD_SEQIN);
- NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
- }
-
- if (nand->bus16) {
- for (i = len256; i < len; i += 2) {
- WRITE_NAND(buf[i] + (buf[i+1] << 8), nandptr);
- }
- } else {
- for (i = len256; i < len; i++)
- WRITE_NAND(buf[i], nandptr);
- }
-
- NanD_Command(nand, NAND_CMD_PAGEPROG);
- NanD_Command(nand, NAND_CMD_STATUS);
-#ifdef NAND_NO_RB
- { u_char ret_val;
- do {
- ret_val = READ_NAND(nandptr); /* wait till ready */
- } while ((ret_val & 0x40) != 0x40);
- }
-#endif
- if (READ_NAND(nandptr) & 1) {
- puts ("Error programming oob data\n");
- /* There was an error */
- NAND_DISABLE_CE(nand); /* set pin high */
- *retlen = 0;
- return -1;
- }
-
- NAND_DISABLE_CE(nand); /* set pin high */
- *retlen = len;
- return 0;
-
-}
-
-int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean)
-{
- /* This is defined as a structure so it will work on any system
- * using native endian jffs2 (the default).
- */
- static struct jffs2_unknown_node clean_marker = {
- JFFS2_MAGIC_BITMASK,
- JFFS2_NODETYPE_CLEANMARKER,
- 8 /* 8 bytes in this node */
- };
- unsigned long nandptr;
- struct Nand *mychip;
- int ret = 0;
-
- if (ofs & (nand->erasesize-1) || len & (nand->erasesize-1)) {
- printf ("Offset and size must be sector aligned, erasesize = %d\n",
- (int) nand->erasesize);
- return -1;
- }
-
- nandptr = nand->IO_ADDR;
-
- /* Select the NAND device */
-#ifdef CONFIG_OMAP1510
- archflashwp(0,0);
-#endif
-#ifdef CONFIG_SYS_NAND_WP
- NAND_WP_OFF();
-#endif
- NAND_ENABLE_CE(nand); /* set pin low */
-
- /* Check the WP bit */
- NanD_Command(nand, NAND_CMD_STATUS);
- if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
- printf ("nand_write_ecc: Device is write protected!!!\n");
- ret = -1;
- goto out;
- }
-
- /* Check the WP bit */
- NanD_Command(nand, NAND_CMD_STATUS);
- if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
- printf ("%s: Device is write protected!!!\n", __FUNCTION__);
- ret = -1;
- goto out;
- }
-
- /* FIXME: Do nand in the background. Use timers or schedule_task() */
- while(len) {
- /*mychip = &nand->chips[shr(ofs, nand->chipshift)];*/
- mychip = &nand->chips[ofs >> nand->chipshift];
-
- /* always check for bad block first, genuine bad blocks
- * should _never_ be erased.
- */
- if (ALLOW_ERASE_BAD_DEBUG || !check_block(nand, ofs)) {
- /* Select the NAND device */
- NAND_ENABLE_CE(nand); /* set pin low */
-
- NanD_Command(nand, NAND_CMD_ERASE1);
- NanD_Address(nand, ADDR_PAGE, ofs);
- NanD_Command(nand, NAND_CMD_ERASE2);
-
- NanD_Command(nand, NAND_CMD_STATUS);
-
-#ifdef NAND_NO_RB
- { u_char ret_val;
- do {
- ret_val = READ_NAND(nandptr); /* wait till ready */
- } while ((ret_val & 0x40) != 0x40);
- }
-#endif
- if (READ_NAND(nandptr) & 1) {
- printf ("%s: Error erasing at 0x%lx\n",
- __FUNCTION__, (long)ofs);
- /* There was an error */
- ret = -1;
- goto out;
- }
- if (clean) {
- int n; /* return value not used */
- int p, l;
-
- /* clean marker position and size depend
- * on the page size, since 256 byte pages
- * only have 8 bytes of oob data
- */
- if (nand->page256) {
- p = NAND_JFFS2_OOB8_FSDAPOS;
- l = NAND_JFFS2_OOB8_FSDALEN;
- } else {
- p = NAND_JFFS2_OOB16_FSDAPOS;
- l = NAND_JFFS2_OOB16_FSDALEN;
- }
-
- ret = nand_write_oob(nand, ofs + p, l, (size_t *)&n,
- (u_char *)&clean_marker);
- /* quit here if write failed */
- if (ret)
- goto out;
- }
- }
- ofs += nand->erasesize;
- len -= nand->erasesize;
- }
-
-out:
- /* De-select the NAND device */
- NAND_DISABLE_CE(nand); /* set pin high */
-#ifdef CONFIG_OMAP1510
- archflashwp(0,1);
-#endif
-#ifdef CONFIG_SYS_NAND_WP
- NAND_WP_ON();
-#endif
-
- return ret;
-}
-
-
-static inline int nandcheck(unsigned long potential, unsigned long physadr)
-{
- return 0;
-}
-
-unsigned long nand_probe(unsigned long physadr)
-{
- struct nand_chip *nand = NULL;
- int i = 0, ChipID = 1;
-
-#ifdef CONFIG_MTD_NAND_ECC_JFFS2
- oob_config.ecc_pos[0] = NAND_JFFS2_OOB_ECCPOS0;
- oob_config.ecc_pos[1] = NAND_JFFS2_OOB_ECCPOS1;
- oob_config.ecc_pos[2] = NAND_JFFS2_OOB_ECCPOS2;
- oob_config.ecc_pos[3] = NAND_JFFS2_OOB_ECCPOS3;
- oob_config.ecc_pos[4] = NAND_JFFS2_OOB_ECCPOS4;
- oob_config.ecc_pos[5] = NAND_JFFS2_OOB_ECCPOS5;
- oob_config.eccvalid_pos = 4;
-#else
- oob_config.ecc_pos[0] = NAND_NOOB_ECCPOS0;
- oob_config.ecc_pos[1] = NAND_NOOB_ECCPOS1;
- oob_config.ecc_pos[2] = NAND_NOOB_ECCPOS2;
- oob_config.ecc_pos[3] = NAND_NOOB_ECCPOS3;
- oob_config.ecc_pos[4] = NAND_NOOB_ECCPOS4;
- oob_config.ecc_pos[5] = NAND_NOOB_ECCPOS5;
- oob_config.eccvalid_pos = NAND_NOOB_ECCVPOS;
-#endif
- oob_config.badblock_pos = 5;
-
- for (i=0; i<CONFIG_SYS_MAX_NAND_DEVICE; i++) {
- if (nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN) {
- nand = &nand_dev_desc[i];
- break;
- }
- }
- if (!nand)
- return (0);
-
- memset((char *)nand, 0, sizeof(struct nand_chip));
-
- nand->IO_ADDR = physadr;
- nand->cache_page = -1; /* init the cache page */
- NanD_ScanChips(nand);
-
- if (nand->totlen == 0) {
- /* no chips found, clean up and quit */
- memset((char *)nand, 0, sizeof(struct nand_chip));
- nand->ChipID = NAND_ChipID_UNKNOWN;
- return (0);
- }
-
- nand->ChipID = ChipID;
- if (curr_device == -1)
- curr_device = i;
-
- nand->data_buf = malloc (nand->oobblock + nand->oobsize);
- if (!nand->data_buf) {
- puts ("Cannot allocate memory for data structures.\n");
- return (0);
- }
-
- return (nand->totlen);
-}
-
-#ifdef CONFIG_MTD_NAND_ECC
-/*
- * Pre-calculated 256-way 1 byte column parity
- */
-static const u_char nand_ecc_precalc_table[] = {
- 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a,
- 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,
- 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f,
- 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
- 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c,
- 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
- 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59,
- 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
- 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33,
- 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
- 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56,
- 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
- 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55,
- 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
- 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30,
- 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
- 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30,
- 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
- 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55,
- 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
- 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56,
- 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
- 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33,
- 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
- 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59,
- 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
- 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c,
- 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
- 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f,
- 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
- 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a,
- 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00
-};
-
-
-/*
- * Creates non-inverted ECC code from line parity
- */
-static void nand_trans_result(u_char reg2, u_char reg3,
- u_char *ecc_code)
-{
- u_char a, b, i, tmp1, tmp2;
-
- /* Initialize variables */
- a = b = 0x80;
- tmp1 = tmp2 = 0;
-
- /* Calculate first ECC byte */
- for (i = 0; i < 4; i++) {
- if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */
- tmp1 |= b;
- b >>= 1;
- if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */
- tmp1 |= b;
- b >>= 1;
- a >>= 1;
- }
-
- /* Calculate second ECC byte */
- b = 0x80;
- for (i = 0; i < 4; i++) {
- if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */
- tmp2 |= b;
- b >>= 1;
- if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */
- tmp2 |= b;
- b >>= 1;
- a >>= 1;
- }
-
- /* Store two of the ECC bytes */
- ecc_code[0] = tmp1;
- ecc_code[1] = tmp2;
-}
-
-/*
- * Calculate 3 byte ECC code for 256 byte block
- */
-static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code)
-{
- u_char idx, reg1, reg3;
- int j;
-
- /* Initialize variables */
- reg1 = reg3 = 0;
- ecc_code[0] = ecc_code[1] = ecc_code[2] = 0;
-
- /* Build up column parity */
- for(j = 0; j < 256; j++) {
-
- /* Get CP0 - CP5 from table */
- idx = nand_ecc_precalc_table[dat[j]];
- reg1 ^= idx;
-
- /* All bit XOR = 1 ? */
- if (idx & 0x40) {
- reg3 ^= (u_char) j;
- }
- }
-
- /* Create non-inverted ECC code from line parity */
- nand_trans_result((reg1 & 0x40) ? ~reg3 : reg3, reg3, ecc_code);
-
- /* Calculate final ECC code */
- ecc_code[0] = ~ecc_code[0];
- ecc_code[1] = ~ecc_code[1];
- ecc_code[2] = ((~reg1) << 2) | 0x03;
-}
-
-/*
- * Detect and correct a 1 bit error for 256 byte block
- */
-static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc)
-{
- u_char a, b, c, d1, d2, d3, add, bit, i;
-
- /* Do error detection */
- d1 = calc_ecc[0] ^ read_ecc[0];
- d2 = calc_ecc[1] ^ read_ecc[1];
- d3 = calc_ecc[2] ^ read_ecc[2];
-
- if ((d1 | d2 | d3) == 0) {
- /* No errors */
- return 0;
- } else {
- a = (d1 ^ (d1 >> 1)) & 0x55;
- b = (d2 ^ (d2 >> 1)) & 0x55;
- c = (d3 ^ (d3 >> 1)) & 0x54;
-
- /* Found and will correct single bit error in the data */
- if ((a == 0x55) && (b == 0x55) && (c == 0x54)) {
- c = 0x80;
- add = 0;
- a = 0x80;
- for (i=0; i<4; i++) {
- if (d1 & c)
- add |= a;
- c >>= 2;
- a >>= 1;
- }
- c = 0x80;
- for (i=0; i<4; i++) {
- if (d2 & c)
- add |= a;
- c >>= 2;
- a >>= 1;
- }
- bit = 0;
- b = 0x04;
- c = 0x80;
- for (i=0; i<3; i++) {
- if (d3 & c)
- bit |= b;
- c >>= 2;
- b >>= 1;
- }
- b = 0x01;
- a = dat[add];
- a ^= (b << bit);
- dat[add] = a;
- return 1;
- }
- else {
- i = 0;
- while (d1) {
- if (d1 & 0x01)
- ++i;
- d1 >>= 1;
- }
- while (d2) {
- if (d2 & 0x01)
- ++i;
- d2 >>= 1;
- }
- while (d3) {
- if (d3 & 0x01)
- ++i;
- d3 >>= 1;
- }
- if (i == 1) {
- /* ECC Code Error Correction */
- read_ecc[0] = calc_ecc[0];
- read_ecc[1] = calc_ecc[1];
- read_ecc[2] = calc_ecc[2];
- return 2;
- }
- else {
- /* Uncorrectable Error */
- return -1;
- }
- }
- }
-
- /* Should never happen */
- return -1;
-}
-
-#endif
-
-#ifdef CONFIG_JFFS2_NAND
-int read_jffs2_nand(size_t start, size_t len,
- size_t * retlen, u_char * buf, int nanddev)
-{
- return nand_legacy_rw(nand_dev_desc + nanddev, NANDRW_READ | NANDRW_JFFS2,
- start, len, retlen, buf);
-}
-#endif /* CONFIG_JFFS2_NAND */
defined(CONFIG_405EX)
u32 opbfreq;
sys_info_t sysinfo;
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
COBJS-$(CONFIG_E1000) += e1000.o
COBJS-$(CONFIG_EEPRO100) += eepro100.o
COBJS-$(CONFIG_ENC28J60) += enc28j60.o
+COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
COBJS-$(CONFIG_GRETH) += greth.o
COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
COBJS-$(CONFIG_DRIVER_S3C4510_ETH) += s3c4510b_eth.o
COBJS-$(CONFIG_SH_ETHER) += sh_eth.o
COBJS-$(CONFIG_DRIVER_SMC91111) += smc91111.o
-COBJS-$(CONFIG_DRIVER_SMC911X) += smc911x.o
+COBJS-$(CONFIG_SMC911X) += smc911x.o
COBJS-$(CONFIG_TIGON3) += tigon3.o bcm570x_autoneg.o 5701rls.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
COBJS-$(CONFIG_TSEC_ENET) += tsec.o
--- /dev/null
+/*
+ * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
+ * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
+ * (C) Copyright 2008 Armadeus Systems nc
+ * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <miiphy.h>
+#include "fec_mxc.h"
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_MII
+#error "CONFIG_MII has to be defined!"
+#endif
+
+#undef DEBUG
+
+struct nbuf {
+ uint8_t data[1500]; /**< actual data */
+ int length; /**< actual length */
+ int used; /**< buffer in use or not */
+ uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
+};
+
+struct fec_priv gfec = {
+ .eth = (struct ethernet_regs *)IMX_FEC_BASE,
+ .xcv_type = MII100,
+ .rbd_base = NULL,
+ .rbd_index = 0,
+ .tbd_base = NULL,
+ .tbd_index = 0,
+ .bd = NULL,
+};
+
+/*
+ * MII-interface related functions
+ */
+static int fec_miiphy_read(char *dev, uint8_t phyAddr, uint8_t regAddr,
+ uint16_t *retVal)
+{
+ struct eth_device *edev = eth_get_dev_by_name(dev);
+ struct fec_priv *fec = (struct fec_priv *)edev->priv;
+
+ uint32_t reg; /* convenient holder for the PHY register */
+ uint32_t phy; /* convenient holder for the PHY */
+ uint32_t start;
+
+ /*
+ * reading from any PHY's register is done by properly
+ * programming the FEC's MII data register.
+ */
+ writel(FEC_IEVENT_MII, &fec->eth->ievent);
+ reg = regAddr << FEC_MII_DATA_RA_SHIFT;
+ phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
+
+ writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
+ phy | reg, &fec->eth->mii_data);
+
+ /*
+ * wait for the related interrupt
+ */
+ start = get_timer_masked();
+ while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
+ if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
+ printf("Read MDIO failed...\n");
+ return -1;
+ }
+ }
+
+ /*
+ * clear mii interrupt bit
+ */
+ writel(FEC_IEVENT_MII, &fec->eth->ievent);
+
+ /*
+ * it's now safe to read the PHY's register
+ */
+ *retVal = readl(&fec->eth->mii_data);
+ debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
+ regAddr, *retVal);
+ return 0;
+}
+
+static int fec_miiphy_write(char *dev, uint8_t phyAddr, uint8_t regAddr,
+ uint16_t data)
+{
+ struct eth_device *edev = eth_get_dev_by_name(dev);
+ struct fec_priv *fec = (struct fec_priv *)edev->priv;
+
+ uint32_t reg; /* convenient holder for the PHY register */
+ uint32_t phy; /* convenient holder for the PHY */
+ uint32_t start;
+
+ reg = regAddr << FEC_MII_DATA_RA_SHIFT;
+ phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
+
+ writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
+ FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data);
+
+ /*
+ * wait for the MII interrupt
+ */
+ start = get_timer_masked();
+ while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
+ if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
+ printf("Write MDIO failed...\n");
+ return -1;
+ }
+ }
+
+ /*
+ * clear MII interrupt bit
+ */
+ writel(FEC_IEVENT_MII, &fec->eth->ievent);
+ debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
+ regAddr, data);
+
+ return 0;
+}
+
+static int miiphy_restart_aneg(struct eth_device *dev)
+{
+ /*
+ * Wake up from sleep if necessary
+ * Reset PHY, then delay 300ns
+ */
+ miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF);
+ miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
+ PHY_BMCR_RESET);
+ udelay(1000);
+
+ /*
+ * Set the auto-negotiation advertisement register bits
+ */
+ miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR, 0x1e0);
+ miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
+ PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+
+ return 0;
+}
+
+static int miiphy_wait_aneg(struct eth_device *dev)
+{
+ uint32_t start;
+ uint16_t status;
+
+ /*
+ * Wait for AN completion
+ */
+ start = get_timer_masked();
+ do {
+ if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
+ printf("%s: Autonegotiation timeout\n", dev->name);
+ return -1;
+ }
+
+ if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR,
+ PHY_BMSR, &status)) {
+ printf("%s: Autonegotiation failed. status: 0x%04x\n",
+ dev->name, status);
+ return -1;
+ }
+ } while (!(status & PHY_BMSR_LS));
+
+ return 0;
+}
+static int fec_rx_task_enable(struct fec_priv *fec)
+{
+ writel(1 << 24, &fec->eth->r_des_active);
+ return 0;
+}
+
+static int fec_rx_task_disable(struct fec_priv *fec)
+{
+ return 0;
+}
+
+static int fec_tx_task_enable(struct fec_priv *fec)
+{
+ writel(1 << 24, &fec->eth->x_des_active);
+ return 0;
+}
+
+static int fec_tx_task_disable(struct fec_priv *fec)
+{
+ return 0;
+}
+
+/**
+ * Initialize receive task's buffer descriptors
+ * @param[in] fec all we know about the device yet
+ * @param[in] count receive buffer count to be allocated
+ * @param[in] size size of each receive buffer
+ * @return 0 on success
+ *
+ * For this task we need additional memory for the data buffers. And each
+ * data buffer requires some alignment. Thy must be aligned to a specific
+ * boundary each (DB_DATA_ALIGNMENT).
+ */
+static int fec_rbd_init(struct fec_priv *fec, int count, int size)
+{
+ int ix;
+ uint32_t p = 0;
+
+ /* reserve data memory and consider alignment */
+ fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
+ p = (uint32_t)fec->rdb_ptr;
+ if (!p) {
+ puts("fec_imx27: not enough malloc memory!\n");
+ return -ENOMEM;
+ }
+ memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
+ p += DB_DATA_ALIGNMENT-1;
+ p &= ~(DB_DATA_ALIGNMENT-1);
+
+ for (ix = 0; ix < count; ix++) {
+ writel(p, &fec->rbd_base[ix].data_pointer);
+ p += size;
+ writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
+ writew(0, &fec->rbd_base[ix].data_length);
+ }
+ /*
+ * mark the last RBD to close the ring
+ */
+ writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
+ fec->rbd_index = 0;
+
+ return 0;
+}
+
+/**
+ * Initialize transmit task's buffer descriptors
+ * @param[in] fec all we know about the device yet
+ *
+ * Transmit buffers are created externally. We only have to init the BDs here.\n
+ * Note: There is a race condition in the hardware. When only one BD is in
+ * use it must be marked with the WRAP bit to use it for every transmitt.
+ * This bit in combination with the READY bit results into double transmit
+ * of each data buffer. It seems the state machine checks READY earlier then
+ * resetting it after the first transfer.
+ * Using two BDs solves this issue.
+ */
+static void fec_tbd_init(struct fec_priv *fec)
+{
+ writew(0x0000, &fec->tbd_base[0].status);
+ writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
+ fec->tbd_index = 0;
+}
+
+/**
+ * Mark the given read buffer descriptor as free
+ * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
+ * @param[in] pRbd buffer descriptor to mark free again
+ */
+static void fec_rbd_clean(int last, struct fec_bd *pRbd)
+{
+ /*
+ * Reset buffer descriptor as empty
+ */
+ if (last)
+ writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
+ else
+ writew(FEC_RBD_EMPTY, &pRbd->status);
+ /*
+ * no data in it
+ */
+ writew(0, &pRbd->data_length);
+}
+
+static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
+{
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ int i;
+
+ for (i = 0; i < 6; i++)
+ mac[6-1-i] = readl(&iim->iim_bank_area0[IIM0_MAC + i]);
+
+ return is_valid_ether_addr(mac);
+}
+
+static int fec_set_hwaddr(struct eth_device *dev, unsigned char *mac)
+{
+ struct fec_priv *fec = (struct fec_priv *)dev->priv;
+
+ writel(0, &fec->eth->iaddr1);
+ writel(0, &fec->eth->iaddr2);
+ writel(0, &fec->eth->gaddr1);
+ writel(0, &fec->eth->gaddr2);
+
+ /*
+ * Set physical address
+ */
+ writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
+ &fec->eth->paddr1);
+ writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
+
+ return 0;
+}
+
+/**
+ * Start the FEC engine
+ * @param[in] dev Our device to handle
+ */
+static int fec_open(struct eth_device *edev)
+{
+ struct fec_priv *fec = (struct fec_priv *)edev->priv;
+
+ debug("fec_open: fec_open(dev)\n");
+ /* full-duplex, heartbeat disabled */
+ writel(1 << 2, &fec->eth->x_cntrl);
+ fec->rbd_index = 0;
+
+ /*
+ * Enable FEC-Lite controller
+ */
+ writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
+
+ miiphy_wait_aneg(edev);
+ miiphy_speed(edev->name, 0);
+ miiphy_duplex(edev->name, 0);
+
+ /*
+ * Enable SmartDMA receive task
+ */
+ fec_rx_task_enable(fec);
+
+ udelay(100000);
+ return 0;
+}
+
+static int fec_init(struct eth_device *dev, bd_t* bd)
+{
+ uint32_t base;
+ struct fec_priv *fec = (struct fec_priv *)dev->priv;
+
+ /*
+ * reserve memory for both buffer descriptor chains at once
+ * Datasheet forces the startaddress of each chain is 16 byte
+ * aligned
+ */
+ fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
+ sizeof(struct fec_bd) + DB_ALIGNMENT);
+ base = (uint32_t)fec->base_ptr;
+ if (!base) {
+ puts("fec_imx27: not enough malloc memory!\n");
+ return -ENOMEM;
+ }
+ memset((void *)base, 0, (2 + FEC_RBD_NUM) *
+ sizeof(struct fec_bd) + DB_ALIGNMENT);
+ base += (DB_ALIGNMENT-1);
+ base &= ~(DB_ALIGNMENT-1);
+
+ fec->rbd_base = (struct fec_bd *)base;
+
+ base += FEC_RBD_NUM * sizeof(struct fec_bd);
+
+ fec->tbd_base = (struct fec_bd *)base;
+
+ /*
+ * Set interrupt mask register
+ */
+ writel(0x00000000, &fec->eth->imask);
+
+ /*
+ * Clear FEC-Lite interrupt event register(IEVENT)
+ */
+ writel(0xffffffff, &fec->eth->ievent);
+
+
+ /*
+ * Set FEC-Lite receive control register(R_CNTRL):
+ */
+ if (fec->xcv_type == SEVENWIRE) {
+ /*
+ * Frame length=1518; 7-wire mode
+ */
+ writel(0x05ee0020, &fec->eth->r_cntrl); /* FIXME 0x05ee0000 */
+ } else {
+ /*
+ * Frame length=1518; MII mode;
+ */
+ writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */
+ /*
+ * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
+ * and do not drop the Preamble.
+ */
+ writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1,
+ &fec->eth->mii_speed);
+ debug("fec_init: mii_speed %#lx\n",
+ (((imx_get_ahbclk() / 1000000) + 2) / 5) << 1);
+ }
+ /*
+ * Set Opcode/Pause Duration Register
+ */
+ writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
+ writel(0x2, &fec->eth->x_wmrk);
+ /*
+ * Set multicast address filter
+ */
+ writel(0x00000000, &fec->eth->gaddr1);
+ writel(0x00000000, &fec->eth->gaddr2);
+
+
+ /* clear MIB RAM */
+ long *mib_ptr = (long *)(IMX_FEC_BASE + 0x200);
+ while (mib_ptr <= (long *)(IMX_FEC_BASE + 0x2FC))
+ *mib_ptr++ = 0;
+
+ /* FIFO receive start register */
+ writel(0x520, &fec->eth->r_fstart);
+
+ /* size and address of each buffer */
+ writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
+ writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
+ writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
+
+ /*
+ * Initialize RxBD/TxBD rings
+ */
+ if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
+ free(fec->base_ptr);
+ return -ENOMEM;
+ }
+ fec_tbd_init(fec);
+
+
+ if (fec->xcv_type != SEVENWIRE)
+ miiphy_restart_aneg(dev);
+
+ fec_open(dev);
+ return 0;
+}
+
+/**
+ * Halt the FEC engine
+ * @param[in] dev Our device to handle
+ */
+static void fec_halt(struct eth_device *dev)
+{
+ struct fec_priv *fec = &gfec;
+ int counter = 0xffff;
+
+ /*
+ * issue graceful stop command to the FEC transmitter if necessary
+ */
+ writel(FEC_ECNTRL_RESET | readl(&fec->eth->x_cntrl),
+ &fec->eth->x_cntrl);
+
+ debug("eth_halt: wait for stop regs\n");
+ /*
+ * wait for graceful stop to register
+ */
+ while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
+ ; /* FIXME ensure time */
+
+ /*
+ * Disable SmartDMA tasks
+ */
+ fec_tx_task_disable(fec);
+ fec_rx_task_disable(fec);
+
+ /*
+ * Disable the Ethernet Controller
+ * Note: this will also reset the BD index counter!
+ */
+ writel(0, &fec->eth->ecntrl);
+ fec->rbd_index = 0;
+ fec->tbd_index = 0;
+ free(fec->rdb_ptr);
+ free(fec->base_ptr);
+ debug("eth_halt: done\n");
+}
+
+/**
+ * Transmit one frame
+ * @param[in] dev Our ethernet device to handle
+ * @param[in] packet Pointer to the data to be transmitted
+ * @param[in] length Data count in bytes
+ * @return 0 on success
+ */
+static int fec_send(struct eth_device *dev, volatile void* packet, int length)
+{
+ unsigned int status;
+
+ /*
+ * This routine transmits one frame. This routine only accepts
+ * 6-byte Ethernet addresses.
+ */
+ struct fec_priv *fec = (struct fec_priv *)dev->priv;
+
+ /*
+ * Check for valid length of data.
+ */
+ if ((length > 1500) || (length <= 0)) {
+ printf("Payload (%d) to large!\n", length);
+ return -1;
+ }
+
+ /*
+ * Setup the transmit buffer
+ * Note: We are always using the first buffer for transmission,
+ * the second will be empty and only used to stop the DMA engine
+ */
+ writew(length, &fec->tbd_base[fec->tbd_index].data_length);
+ writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
+ /*
+ * update BD's status now
+ * This block:
+ * - is always the last in a chain (means no chain)
+ * - should transmitt the CRC
+ * - might be the last BD in the list, so the address counter should
+ * wrap (-> keep the WRAP flag)
+ */
+ status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
+ status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
+ writew(status, &fec->tbd_base[fec->tbd_index].status);
+
+ /*
+ * Enable SmartDMA transmit task
+ */
+ fec_tx_task_enable(fec);
+
+ /*
+ * wait until frame is sent .
+ */
+ while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
+ /* FIXME: Timeout */
+ }
+ debug("fec_send: status 0x%x index %d\n",
+ readw(&fec->tbd_base[fec->tbd_index].status),
+ fec->tbd_index);
+ /* for next transmission use the other buffer */
+ if (fec->tbd_index)
+ fec->tbd_index = 0;
+ else
+ fec->tbd_index = 1;
+
+ return 0;
+}
+
+/**
+ * Pull one frame from the card
+ * @param[in] dev Our ethernet device to handle
+ * @return Length of packet read
+ */
+static int fec_recv(struct eth_device *dev)
+{
+ struct fec_priv *fec = (struct fec_priv *)dev->priv;
+ struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
+ unsigned long ievent;
+ int frame_length, len = 0;
+ struct nbuf *frame;
+ uint16_t bd_status;
+ uchar buff[FEC_MAX_PKT_SIZE];
+
+ /*
+ * Check if any critical events have happened
+ */
+ ievent = readl(&fec->eth->ievent);
+ writel(ievent, &fec->eth->ievent);
+ debug("fec_recv: ievent 0x%x\n", ievent);
+ if (ievent & FEC_IEVENT_BABR) {
+ fec_halt(dev);
+ fec_init(dev, fec->bd);
+ printf("some error: 0x%08lx\n", ievent);
+ return 0;
+ }
+ if (ievent & FEC_IEVENT_HBERR) {
+ /* Heartbeat error */
+ writel(0x00000001 | readl(&fec->eth->x_cntrl),
+ &fec->eth->x_cntrl);
+ }
+ if (ievent & FEC_IEVENT_GRA) {
+ /* Graceful stop complete */
+ if (readl(&fec->eth->x_cntrl) & 0x00000001) {
+ fec_halt(dev);
+ writel(~0x00000001 & readl(&fec->eth->x_cntrl),
+ &fec->eth->x_cntrl);
+ fec_init(dev, fec->bd);
+ }
+ }
+
+ /*
+ * ensure reading the right buffer status
+ */
+ bd_status = readw(&rbd->status);
+ debug("fec_recv: status 0x%x\n", bd_status);
+
+ if (!(bd_status & FEC_RBD_EMPTY)) {
+ if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
+ ((readw(&rbd->data_length) - 4) > 14)) {
+ /*
+ * Get buffer address and size
+ */
+ frame = (struct nbuf *)readl(&rbd->data_pointer);
+ frame_length = readw(&rbd->data_length) - 4;
+ /*
+ * Fill the buffer and pass it to upper layers
+ */
+ memcpy(buff, frame->data, frame_length);
+ NetReceive(buff, frame_length);
+ len = frame_length;
+ } else {
+ if (bd_status & FEC_RBD_ERR)
+ printf("error frame: 0x%08lx 0x%08x\n",
+ (ulong)rbd->data_pointer,
+ bd_status);
+ }
+ /*
+ * free the current buffer, restart the engine
+ * and move forward to the next buffer
+ */
+ fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
+ fec_rx_task_enable(fec);
+ fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
+ }
+ debug("fec_recv: stop\n");
+
+ return len;
+}
+
+static int fec_probe(bd_t *bd)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+ struct eth_device *edev;
+ struct fec_priv *fec = &gfec;
+ unsigned char ethaddr_str[20];
+ unsigned char ethaddr[6];
+ char *tmp = getenv("ethaddr");
+ char *end;
+
+ /* enable FEC clock */
+ writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
+ writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
+
+ /* create and fill edev struct */
+ edev = (struct eth_device *)malloc(sizeof(struct eth_device));
+ if (!edev) {
+ puts("fec_imx27: not enough malloc memory!\n");
+ return -ENOMEM;
+ }
+ edev->priv = fec;
+ edev->init = fec_init;
+ edev->send = fec_send;
+ edev->recv = fec_recv;
+ edev->halt = fec_halt;
+
+ fec->eth = (struct ethernet_regs *)IMX_FEC_BASE;
+ fec->bd = bd;
+
+ fec->xcv_type = MII100;
+
+ /* Reset chip. */
+ writel(FEC_ECNTRL_RESET, &fec->eth->ecntrl);
+ while (readl(&fec->eth->ecntrl) & 1)
+ udelay(10);
+
+ /*
+ * Set interrupt mask register
+ */
+ writel(0x00000000, &fec->eth->imask);
+
+ /*
+ * Clear FEC-Lite interrupt event register(IEVENT)
+ */
+ writel(0xffffffff, &fec->eth->ievent);
+
+ /*
+ * Set FEC-Lite receive control register(R_CNTRL):
+ */
+ /*
+ * Frame length=1518; MII mode;
+ */
+ writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */
+ /*
+ * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
+ * and do not drop the Preamble.
+ */
+ writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1,
+ &fec->eth->mii_speed);
+ debug("fec_init: mii_speed %#lx\n",
+ (((imx_get_ahbclk() / 1000000) + 2) / 5) << 1);
+
+ sprintf(edev->name, "FEC_MXC");
+
+ miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
+
+ eth_register(edev);
+
+ if ((NULL != tmp) && (12 <= strlen(tmp))) {
+ int i;
+ /* convert MAC from string to int */
+ for (i = 0; i < 6; i++) {
+ ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
+ if (tmp)
+ tmp = (*end) ? end + 1 : end;
+ }
+ } else if (fec_get_hwaddr(edev, ethaddr) == 0) {
+ printf("got MAC address from EEPROM: %pM\n", ethaddr);
+ setenv("ethaddr", (char *)ethaddr_str);
+ }
+ memcpy(edev->enetaddr, ethaddr, 6);
+ fec_set_hwaddr(edev, ethaddr);
+
+ return 0;
+}
+
+int fecmxc_initialize(bd_t *bd)
+{
+ int lout = 1;
+
+ debug("eth_init: fec_probe(bd)\n");
+ lout = fec_probe(bd);
+
+ return lout;
+}
--- /dev/null
+/*
+ * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
+ * (C) Copyright 2008 Armadeus Systems, nc
+ * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
+ * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This file is based on mpc4200fec.h
+ * (C) Copyright Motorola, Inc., 2000
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+
+#ifndef __FEC_MXC_H
+#define __FEC_MXC_H
+
+/**
+ * Layout description of the FEC
+ */
+struct ethernet_regs {
+
+/* [10:2]addr = 00 */
+
+/* Control and status Registers (offset 000-1FF) */
+
+ uint32_t res0[1]; /* MBAR_ETH + 0x000 */
+ uint32_t ievent; /* MBAR_ETH + 0x004 */
+ uint32_t imask; /* MBAR_ETH + 0x008 */
+
+ uint32_t res1[1]; /* MBAR_ETH + 0x00C */
+ uint32_t r_des_active; /* MBAR_ETH + 0x010 */
+ uint32_t x_des_active; /* MBAR_ETH + 0x014 */
+ uint32_t res2[3]; /* MBAR_ETH + 0x018-20 */
+ uint32_t ecntrl; /* MBAR_ETH + 0x024 */
+
+ uint32_t res3[6]; /* MBAR_ETH + 0x028-03C */
+ uint32_t mii_data; /* MBAR_ETH + 0x040 */
+ uint32_t mii_speed; /* MBAR_ETH + 0x044 */
+ uint32_t res4[7]; /* MBAR_ETH + 0x048-60 */
+ uint32_t mib_control; /* MBAR_ETH + 0x064 */
+
+ uint32_t res5[7]; /* MBAR_ETH + 0x068-80 */
+ uint32_t r_cntrl; /* MBAR_ETH + 0x084 */
+ uint32_t res6[15]; /* MBAR_ETH + 0x088-C0 */
+ uint32_t x_cntrl; /* MBAR_ETH + 0x0C4 */
+ uint32_t res7[7]; /* MBAR_ETH + 0x0C8-E0 */
+ uint32_t paddr1; /* MBAR_ETH + 0x0E4 */
+ uint32_t paddr2; /* MBAR_ETH + 0x0E8 */
+ uint32_t op_pause; /* MBAR_ETH + 0x0EC */
+
+ uint32_t res8[10]; /* MBAR_ETH + 0x0F0-114 */
+ uint32_t iaddr1; /* MBAR_ETH + 0x118 */
+ uint32_t iaddr2; /* MBAR_ETH + 0x11C */
+ uint32_t gaddr1; /* MBAR_ETH + 0x120 */
+ uint32_t gaddr2; /* MBAR_ETH + 0x124 */
+ uint32_t res9[7]; /* MBAR_ETH + 0x128-140 */
+
+ uint32_t x_wmrk; /* MBAR_ETH + 0x144 */
+ uint32_t res10[1]; /* MBAR_ETH + 0x148 */
+ uint32_t r_bound; /* MBAR_ETH + 0x14C */
+ uint32_t r_fstart; /* MBAR_ETH + 0x150 */
+ uint32_t res11[11]; /* MBAR_ETH + 0x154-17C */
+ uint32_t erdsr; /* MBAR_ETH + 0x180 */
+ uint32_t etdsr; /* MBAR_ETH + 0x184 */
+ uint32_t emrbr; /* MBAR_ETH + 0x188 */
+ uint32_t res12[29]; /* MBAR_ETH + 0x18C-1FC */
+
+/* MIB COUNTERS (Offset 200-2FF) */
+
+ uint32_t rmon_t_drop; /* MBAR_ETH + 0x200 */
+ uint32_t rmon_t_packets; /* MBAR_ETH + 0x204 */
+ uint32_t rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */
+ uint32_t rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */
+ uint32_t rmon_t_crc_align; /* MBAR_ETH + 0x210 */
+ uint32_t rmon_t_undersize; /* MBAR_ETH + 0x214 */
+ uint32_t rmon_t_oversize; /* MBAR_ETH + 0x218 */
+ uint32_t rmon_t_frag; /* MBAR_ETH + 0x21C */
+ uint32_t rmon_t_jab; /* MBAR_ETH + 0x220 */
+ uint32_t rmon_t_col; /* MBAR_ETH + 0x224 */
+ uint32_t rmon_t_p64; /* MBAR_ETH + 0x228 */
+ uint32_t rmon_t_p65to127; /* MBAR_ETH + 0x22C */
+ uint32_t rmon_t_p128to255; /* MBAR_ETH + 0x230 */
+ uint32_t rmon_t_p256to511; /* MBAR_ETH + 0x234 */
+ uint32_t rmon_t_p512to1023; /* MBAR_ETH + 0x238 */
+ uint32_t rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */
+ uint32_t rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */
+ uint32_t rmon_t_octets; /* MBAR_ETH + 0x244 */
+ uint32_t ieee_t_drop; /* MBAR_ETH + 0x248 */
+ uint32_t ieee_t_frame_ok; /* MBAR_ETH + 0x24C */
+ uint32_t ieee_t_1col; /* MBAR_ETH + 0x250 */
+ uint32_t ieee_t_mcol; /* MBAR_ETH + 0x254 */
+ uint32_t ieee_t_def; /* MBAR_ETH + 0x258 */
+ uint32_t ieee_t_lcol; /* MBAR_ETH + 0x25C */
+ uint32_t ieee_t_excol; /* MBAR_ETH + 0x260 */
+ uint32_t ieee_t_macerr; /* MBAR_ETH + 0x264 */
+ uint32_t ieee_t_cserr; /* MBAR_ETH + 0x268 */
+ uint32_t ieee_t_sqe; /* MBAR_ETH + 0x26C */
+ uint32_t t_fdxfc; /* MBAR_ETH + 0x270 */
+ uint32_t ieee_t_octets_ok; /* MBAR_ETH + 0x274 */
+
+ uint32_t res13[2]; /* MBAR_ETH + 0x278-27C */
+ uint32_t rmon_r_drop; /* MBAR_ETH + 0x280 */
+ uint32_t rmon_r_packets; /* MBAR_ETH + 0x284 */
+ uint32_t rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */
+ uint32_t rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */
+ uint32_t rmon_r_crc_align; /* MBAR_ETH + 0x290 */
+ uint32_t rmon_r_undersize; /* MBAR_ETH + 0x294 */
+ uint32_t rmon_r_oversize; /* MBAR_ETH + 0x298 */
+ uint32_t rmon_r_frag; /* MBAR_ETH + 0x29C */
+ uint32_t rmon_r_jab; /* MBAR_ETH + 0x2A0 */
+
+ uint32_t rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */
+
+ uint32_t rmon_r_p64; /* MBAR_ETH + 0x2A8 */
+ uint32_t rmon_r_p65to127; /* MBAR_ETH + 0x2AC */
+ uint32_t rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */
+ uint32_t rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */
+ uint32_t rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */
+ uint32_t rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */
+ uint32_t rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */
+ uint32_t rmon_r_octets; /* MBAR_ETH + 0x2C4 */
+ uint32_t ieee_r_drop; /* MBAR_ETH + 0x2C8 */
+ uint32_t ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */
+ uint32_t ieee_r_crc; /* MBAR_ETH + 0x2D0 */
+ uint32_t ieee_r_align; /* MBAR_ETH + 0x2D4 */
+ uint32_t r_macerr; /* MBAR_ETH + 0x2D8 */
+ uint32_t r_fdxfc; /* MBAR_ETH + 0x2DC */
+ uint32_t ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */
+
+ uint32_t res14[6]; /* MBAR_ETH + 0x2E4-2FC */
+
+ uint32_t res15[64]; /* MBAR_ETH + 0x300-3FF */
+};
+
+#define FEC_IEVENT_HBERR 0x80000000
+#define FEC_IEVENT_BABR 0x40000000
+#define FEC_IEVENT_BABT 0x20000000
+#define FEC_IEVENT_GRA 0x10000000
+#define FEC_IEVENT_TXF 0x08000000
+#define FEC_IEVENT_TXB 0x04000000
+#define FEC_IEVENT_RXF 0x02000000
+#define FEC_IEVENT_RXB 0x01000000
+#define FEC_IEVENT_MII 0x00800000
+#define FEC_IEVENT_EBERR 0x00400000
+#define FEC_IEVENT_LC 0x00200000
+#define FEC_IEVENT_RL 0x00100000
+#define FEC_IEVENT_UN 0x00080000
+
+#define FEC_IMASK_HBERR 0x80000000
+#define FEC_IMASK_BABR 0x40000000
+#define FEC_IMASKT_BABT 0x20000000
+#define FEC_IMASK_GRA 0x10000000
+#define FEC_IMASKT_TXF 0x08000000
+#define FEC_IMASK_TXB 0x04000000
+#define FEC_IMASKT_RXF 0x02000000
+#define FEC_IMASK_RXB 0x01000000
+#define FEC_IMASK_MII 0x00800000
+#define FEC_IMASK_EBERR 0x00400000
+#define FEC_IMASK_LC 0x00200000
+#define FEC_IMASKT_RL 0x00100000
+#define FEC_IMASK_UN 0x00080000
+
+
+#define FEC_RCNTRL_MAX_FL_SHIFT 16
+#define FEC_RCNTRL_LOOP 0x00000001
+#define FEC_RCNTRL_DRT 0x00000002
+#define FEC_RCNTRL_MII_MODE 0x00000004
+#define FEC_RCNTRL_PROM 0x00000008
+#define FEC_RCNTRL_BC_REJ 0x00000010
+#define FEC_RCNTRL_FCE 0x00000020
+
+#define FEC_TCNTRL_GTS 0x00000001
+#define FEC_TCNTRL_HBC 0x00000002
+#define FEC_TCNTRL_FDEN 0x00000004
+#define FEC_TCNTRL_TFC_PAUSE 0x00000008
+#define FEC_TCNTRL_RFC_PAUSE 0x00000010
+
+#define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */
+#define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */
+
+/**
+ * @brief Descriptor buffer alignment
+ *
+ * i.MX27 requires a 16 byte alignment (but for the first element only)
+ */
+#define DB_ALIGNMENT 16
+
+/**
+ * @brief Data buffer alignment
+ *
+ * i.MX27 requires a four byte alignment for transmit and 16 bits
+ * alignment for receive so take 16
+ * Note: Valid for member data_pointer in struct buffer_descriptor
+ */
+#define DB_DATA_ALIGNMENT 16
+
+/**
+ * @brief Receive & Transmit Buffer Descriptor definitions
+ *
+ * Note: The first BD must be aligned (see DB_ALIGNMENT)
+ */
+struct fec_bd {
+ uint16_t data_length; /* payload's length in bytes */
+ uint16_t status; /* BD's staus (see datasheet) */
+ uint32_t data_pointer; /* payload's buffer address */
+};
+
+/**
+ * Supported phy types on this platform
+ */
+enum xceiver_type {
+ SEVENWIRE, /* 7-wire */
+ MII10, /* MII 10Mbps */
+ MII100 /* MII 100Mbps */
+};
+
+/**
+ * @brief i.MX27-FEC private structure
+ */
+struct fec_priv {
+ struct ethernet_regs *eth; /* pointer to register'S base */
+ enum xceiver_type xcv_type; /* transceiver type */
+ struct fec_bd *rbd_base; /* RBD ring */
+ int rbd_index; /* next receive BD to read */
+ struct fec_bd *tbd_base; /* TBD ring */
+ int tbd_index; /* next transmit BD to write */
+ bd_t *bd;
+ void *rdb_ptr;
+ void *base_ptr;
+};
+
+/**
+ * @brief Numbers of buffer descriptors for receiving
+ *
+ * The number defines the stocked memory buffers for the receiving task.
+ * Larger values makes no sense in this limited environment.
+ */
+#define FEC_RBD_NUM 64
+
+/**
+ * @brief Define the ethernet packet size limit in memory
+ *
+ * Note: Do not shrink this number. This will force the FEC to spread larger
+ * frames in more than one BD. This is nothing to worry about, but the current
+ * driver can't handle it.
+ */
+#define FEC_MAX_PKT_SIZE 1536
+
+/* Receive BD status bits */
+#define FEC_RBD_EMPTY 0x8000 /* Receive BD status: Buffer is empty */
+#define FEC_RBD_WRAP 0x2000 /* Receive BD status: Last BD in ring */
+/* Receive BD status: Buffer is last in frame (useless here!) */
+#define FEC_RBD_LAST 0x0800
+#define FEC_RBD_MISS 0x0100 /* Receive BD status: Miss bit for prom mode */
+/* Receive BD status: The received frame is broadcast frame */
+#define FEC_RBD_BC 0x0080
+/* Receive BD status: The received frame is multicast frame */
+#define FEC_RBD_MC 0x0040
+#define FEC_RBD_LG 0x0020 /* Receive BD status: Frame length violation */
+#define FEC_RBD_NO 0x0010 /* Receive BD status: Nonoctet align frame */
+#define FEC_RBD_CR 0x0004 /* Receive BD status: CRC error */
+#define FEC_RBD_OV 0x0002 /* Receive BD status: Receive FIFO overrun */
+#define FEC_RBD_TR 0x0001 /* Receive BD status: Frame is truncated */
+#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
+ FEC_RBD_OV | FEC_RBD_TR)
+
+/* Transmit BD status bits */
+#define FEC_TBD_READY 0x8000 /* Tansmit BD status: Buffer is ready */
+#define FEC_TBD_WRAP 0x2000 /* Tansmit BD status: Mark as last BD in ring */
+#define FEC_TBD_LAST 0x0800 /* Tansmit BD status: Buffer is last in frame */
+#define FEC_TBD_TC 0x0400 /* Tansmit BD status: Transmit the CRC */
+#define FEC_TBD_ABC 0x0200 /* Tansmit BD status: Append bad CRC */
+
+/* MII-related definitios */
+#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
+#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
+#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
+#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
+#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
+#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */
+#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
+
+#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
+#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
+
+#endif /* __FEC_MXC_H */
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
u32 smi_reg;
- volatile u32 timeout;
+ u32 timeout;
/* Phyadr read request */
if (phy_adr == 0xEE && reg_ofs == 0xEE) {
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
u32 smi_reg;
- volatile u32 timeout;
+ u32 timeout;
/* Phyadr write request*/
if (phy_adr == 0xEE && reg_ofs == 0xEE) {
*/
static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe)
{
- volatile struct kwgbe_rxdesc *p_rx_desc;
+ struct kwgbe_rxdesc *p_rx_desc;
int i;
/* initialize the Rx descriptors ring */
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc;
+ u32 cmd_sts;
if ((u32) dataptr & 0x07) {
printf("Err..(%s) xmit dataptr not 64bit aligned\n",
/*
* wait for packet xmit completion
*/
- while (p_txdesc->cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) {
+ cmd_sts = readl(&p_txdesc->cmd_sts);
+ while (cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) {
/* return fail if error is detected */
- if (p_txdesc->cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) {
+ if ((cmd_sts & (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME)) ==
+ (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME) &&
+ cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) {
printf("Err..(%s) in xmit packet\n", __FUNCTION__);
return -1;
}
+ cmd_sts = readl(&p_txdesc->cmd_sts);
};
return 0;
}
static int kwgbe_recv(struct eth_device *dev)
{
- volatile struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- volatile struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr;
- volatile u32 timeout = 0;
+ struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
+ struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr;
+ u32 cmd_sts;
+ u32 timeout = 0;
/* wait untill rx packet available or timeout */
do {
debug("%s time out...\n", __FUNCTION__);
return -1;
}
- } while (p_rxdesc_curr->cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA);
+ } while (readl(&p_rxdesc_curr->cmd_sts) & KWGBE_BUFFER_OWNED_BY_DMA);
if (p_rxdesc_curr->byte_cnt != 0) {
debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
* OR the error summary bit is on,
* the packets needs to be dropeed.
*/
- if ((p_rxdesc_curr->cmd_sts &
+ cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
+
+ if ((cmd_sts &
(KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC))
!= (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) {
printf("Err..(%s) Dropping packet spread on"
" multiple descriptors\n", __FUNCTION__);
- } else if (p_rxdesc_curr->cmd_sts & KWGBE_ERROR_SUMMARY) {
+ } else if (cmd_sts & KWGBE_ERROR_SUMMARY) {
printf("Err..(%s) Dropping packet with errors\n",
__FUNCTION__);
p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
p_rxdesc_curr->byte_cnt = 0;
- dkwgbe->p_rxdesc_curr = p_rxdesc_curr->nxtdesc_p;
+ writel((unsigned)p_rxdesc_curr->nxtdesc_p, &dkwgbe->p_rxdesc_curr);
+
return 0;
}
#define KWGBE_UR_ERROR (1 << 1)
#define KWGBE_RL_ERROR (1 << 2)
#define KWGBE_LLC_SNAP_FORMAT (1 << 9)
+#define KWGBE_TX_LAST_FRAME (1 << 20)
/* Rx descriptors status */
#define KWGBE_CRC_ERROR 0
#include <common.h>
#include <command.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
int drv_nc_init (void)
{
- device_t dev;
+ struct stdio_dev dev;
int rc;
memset (&dev, 0, sizeof (dev));
dev.getc = nc_getc;
dev.tstc = nc_tstc;
- rc = device_register (&dev);
+ rc = stdio_register (&dev);
return (rc == 0) ? 1 : rc;
}
volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT);
#endif
+ if (value == NULL) {
+ puts("NULL value pointer\n");
+ return (-1);
+ }
+
miiphy_pre (1, addr, reg);
/* tri-state our MDIO I/O pin so we can read */
MDC (1);
MIIDELAY;
}
+ /* There is no PHY, set value to 0xFFFF and return */
+ *value = 0xFFFF;
return (-1);
}
* By default single chip mode is configured
* multichip mode operation can be configured in board header
*/
-static int mv88e61xx_busychk_multic(u32 devaddr)
+static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
{
u32 reg = 0;
u32 timeout = MV88E61XX_PHY_TIMEOUT;
u32 mii_dev_addr;
/* command to read PHY dev address */
- if (!miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
+ if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
printf("Error..could not read PHY dev address\n");
return;
}
- mv88e61xx_busychk_multic(mii_dev_addr);
+ mv88e61xx_busychk_multic(name, mii_dev_addr);
/* Write data to Switch indirect data register */
miiphy_write(name, mii_dev_addr, 0x1, data);
/* Write command to Switch indirect command register (write) */
u32 mii_dev_addr;
/* command to read PHY dev address */
- if (!miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
+ if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
printf("Error..could not read PHY dev address\n");
return;
}
- mv88e61xx_busychk_multic(mii_dev_addr);
+ mv88e61xx_busychk_multic(name, mii_dev_addr);
/* Write command to Switch indirect command register (read) */
miiphy_write(name, mii_dev_addr, 0x0,
- reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 <<
+ reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 <<
15));
- mv88e61xx_busychk_multic(mii_dev_addr);
+ mv88e61xx_busychk_multic(name, mii_dev_addr);
/* Read data from Switch indirect data register */
- miiphy_read(name, mii_dev_addr, 0x1, (u16 *) & data);
+ miiphy_read(name, mii_dev_addr, 0x1, data);
}
#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
printf("SMI busy timeout\n");
return -1;
}
- } while (reg & 1 << 28); /* busy mask */
+ } while (reg & 1 << 15); /* busy mask */
return 0;
}
#define MV88E61XX_ADDR_OFST 5
#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
-static int mv88e61xx_busychk_multic(u32 devaddr);
+static int mv88e61xx_busychk_multic(char *name, u32 devaddr);
static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data);
static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data);
#define WR_PHY mv88e61xx_wr_phy
/* Configure phy */
ret = sh_eth_phy_config(eth);
if (ret) {
- printf(SHETHER_NAME ":i phy config timeout\n");
+ printf(SHETHER_NAME ": phy config timeout\n");
goto err_phy_cfg;
}
/* Read phy status to finish configuring the e-mac */
EXTRA_CFLAGS += -I. -DSK_USE_CSUM $(DBGDEF)
CFLAGS += $(EXTRA_CFLAGS)
-HOST_CFLAGS += $(EXTRA_CFLAGS)
+HOSTCFLAGS += $(EXTRA_CFLAGS)
all: $(LIB)
#include <common.h>
#include <command.h>
+#include <malloc.h>
#include <net.h>
#include <miiphy.h>
#include "smc911x.h"
-u32 pkt_data_pull(u32 addr) \
+u32 pkt_data_pull(struct eth_device *dev, u32 addr) \
__attribute__ ((weak, alias ("smc911x_reg_read")));
-void pkt_data_push(u32 addr, u32 val) \
+void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) \
__attribute__ ((weak, alias ("smc911x_reg_write")));
#define mdelay(n) udelay((n)*1000)
-static int smx911x_handle_mac_address(bd_t *bd)
+static void smx911x_handle_mac_address(struct eth_device *dev)
{
unsigned long addrh, addrl;
- uchar m[6];
-
- if (eth_getenv_enetaddr("ethaddr", m)) {
- /* if the environment has a valid mac address then use it */
- addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
- addrh = m[4] | (m[5] << 8);
- smc911x_set_mac_csr(ADDRL, addrl);
- smc911x_set_mac_csr(ADDRH, addrh);
- } else {
- /* if not, try to get one from the eeprom */
- addrh = smc911x_get_mac_csr(ADDRH);
- addrl = smc911x_get_mac_csr(ADDRL);
-
- m[0] = (addrl ) & 0xff;
- m[1] = (addrl >> 8 ) & 0xff;
- m[2] = (addrl >> 16 ) & 0xff;
- m[3] = (addrl >> 24 ) & 0xff;
- m[4] = (addrh ) & 0xff;
- m[5] = (addrh >> 8 ) & 0xff;
-
- /* we get 0xff when there is no eeprom connected */
- if ((m[0] & m[1] & m[2] & m[3] & m[4] & m[5]) == 0xff) {
- printf(DRIVERNAME ": no valid mac address in environment "
- "and no eeprom found\n");
- return -1;
- }
-
- eth_setenv_enetaddr("ethaddr", m);
- }
+ uchar *m = dev->enetaddr;
- printf(DRIVERNAME ": MAC %pM\n", m);
+ addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
+ addrh = m[4] | (m[5] << 8);
+ smc911x_set_mac_csr(dev, ADDRL, addrl);
+ smc911x_set_mac_csr(dev, ADDRH, addrh);
- return 0;
+ printf(DRIVERNAME ": MAC %pM\n", m);
}
-static int smc911x_miiphy_read(u8 phy, u8 reg, u16 *val)
+static int smc911x_miiphy_read(struct eth_device *dev,
+ u8 phy, u8 reg, u16 *val)
{
- while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY)
+ while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
;
- smc911x_set_mac_csr(MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY);
+ smc911x_set_mac_csr(dev, MII_ACC, phy << 11 | reg << 6 |
+ MII_ACC_MII_BUSY);
- while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY)
+ while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
;
- *val = smc911x_get_mac_csr(MII_DATA);
+ *val = smc911x_get_mac_csr(dev, MII_DATA);
return 0;
}
-static int smc911x_miiphy_write(u8 phy, u8 reg, u16 val)
+static int smc911x_miiphy_write(struct eth_device *dev,
+ u8 phy, u8 reg, u16 val)
{
- while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY)
+ while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
;
- smc911x_set_mac_csr(MII_DATA, val);
- smc911x_set_mac_csr(MII_ACC,
+ smc911x_set_mac_csr(dev, MII_DATA, val);
+ smc911x_set_mac_csr(dev, MII_ACC,
phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE);
- while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY)
+ while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
;
return 0;
}
-static int smc911x_phy_reset(void)
+static int smc911x_phy_reset(struct eth_device *dev)
{
u32 reg;
- reg = smc911x_reg_read(PMT_CTRL);
+ reg = smc911x_reg_read(dev, PMT_CTRL);
reg &= ~0xfffff030;
reg |= PMT_CTRL_PHY_RST;
- smc911x_reg_write(PMT_CTRL, reg);
+ smc911x_reg_write(dev, PMT_CTRL, reg);
mdelay(100);
return 0;
}
-static void smc911x_phy_configure(void)
+static void smc911x_phy_configure(struct eth_device *dev)
{
int timeout;
u16 status;
- smc911x_phy_reset();
+ smc911x_phy_reset(dev);
- smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_RESET);
+ smc911x_miiphy_write(dev, 1, PHY_BMCR, PHY_BMCR_RESET);
mdelay(1);
- smc911x_miiphy_write(1, PHY_ANAR, 0x01e1);
- smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+ smc911x_miiphy_write(dev, 1, PHY_ANAR, 0x01e1);
+ smc911x_miiphy_write(dev, 1, PHY_BMCR, PHY_BMCR_AUTON |
+ PHY_BMCR_RST_NEG);
timeout = 5000;
do {
if ((timeout--) == 0)
goto err_out;
- if (smc911x_miiphy_read(1, PHY_BMSR, &status) != 0)
+ if (smc911x_miiphy_read(dev, 1, PHY_BMSR, &status) != 0)
goto err_out;
} while (!(status & PHY_BMSR_LS));
printf(DRIVERNAME ": autonegotiation timed out\n");
}
-static void smc911x_enable(void)
+static void smc911x_enable(struct eth_device *dev)
{
/* Enable TX */
- smc911x_reg_write(HW_CFG, 8 << 16 | HW_CFG_SF);
+ smc911x_reg_write(dev, HW_CFG, 8 << 16 | HW_CFG_SF);
- smc911x_reg_write(GPT_CFG, GPT_CFG_TIMER_EN | 10000);
+ smc911x_reg_write(dev, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
- smc911x_reg_write(TX_CFG, TX_CFG_TX_ON);
+ smc911x_reg_write(dev, TX_CFG, TX_CFG_TX_ON);
/* no padding to start of packets */
- smc911x_reg_write(RX_CFG, 0);
+ smc911x_reg_write(dev, RX_CFG, 0);
- smc911x_set_mac_csr(MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS);
+ smc911x_set_mac_csr(dev, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN |
+ MAC_CR_HBDIS);
}
-int eth_init(bd_t *bd)
+static int smc911x_init(struct eth_device *dev, bd_t * bd)
{
printf(DRIVERNAME ": initializing\n");
- if (smc911x_detect_chip())
+ if (smc911x_detect_chip(dev))
goto err_out;
- smc911x_reset();
+ smc911x_reset(dev);
/* Configure the PHY, initialize the link state */
- smc911x_phy_configure();
+ smc911x_phy_configure(dev);
- if (smx911x_handle_mac_address(bd))
- goto err_out;
+ smx911x_handle_mac_address(dev);
/* Turn on Tx + Rx */
- smc911x_enable();
+ smc911x_enable(dev);
return 0;
return -1;
}
-int eth_send(volatile void *packet, int length)
+static int smc911x_send(struct eth_device *dev,
+ volatile void *packet, int length)
{
u32 *data = (u32*)packet;
u32 tmplen;
u32 status;
- smc911x_reg_write(TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length);
- smc911x_reg_write(TX_DATA_FIFO, length);
+ smc911x_reg_write(dev, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG |
+ TX_CMD_A_INT_LAST_SEG | length);
+ smc911x_reg_write(dev, TX_DATA_FIFO, length);
tmplen = (length + 3) / 4;
while (tmplen--)
- pkt_data_push(TX_DATA_FIFO, *data++);
+ pkt_data_push(dev, TX_DATA_FIFO, *data++);
/* wait for transmission */
- while (!((smc911x_reg_read(TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16));
+ while (!((smc911x_reg_read(dev, TX_FIFO_INF) &
+ TX_FIFO_INF_TSUSED) >> 16));
/* get status. Ignore 'no carrier' error, it has no meaning for
* full duplex operation
*/
- status = smc911x_reg_read(TX_STATUS_FIFO) & (TX_STS_LOC | TX_STS_LATE_COLL |
- TX_STS_MANY_COLL | TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
+ status = smc911x_reg_read(dev, TX_STATUS_FIFO) &
+ (TX_STS_LOC | TX_STS_LATE_COLL | TX_STS_MANY_COLL |
+ TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
if (!status)
return 0;
return -1;
}
-void eth_halt(void)
+static void smc911x_halt(struct eth_device *dev)
{
- smc911x_reset();
+ smc911x_reset(dev);
}
-int eth_rx(void)
+static int smc911x_rx(struct eth_device *dev)
{
u32 *data = (u32 *)NetRxPackets[0];
u32 pktlen, tmplen;
u32 status;
- if ((smc911x_reg_read(RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) {
- status = smc911x_reg_read(RX_STATUS_FIFO);
+ if ((smc911x_reg_read(dev, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) {
+ status = smc911x_reg_read(dev, RX_STATUS_FIFO);
pktlen = (status & RX_STS_PKT_LEN) >> 16;
- smc911x_reg_write(RX_CFG, 0);
+ smc911x_reg_write(dev, RX_CFG, 0);
tmplen = (pktlen + 2+ 3) / 4;
while (tmplen--)
- *data++ = pkt_data_pull(RX_DATA_FIFO);
+ *data++ = pkt_data_pull(dev, RX_DATA_FIFO);
if (status & RX_STS_ES)
printf(DRIVERNAME
return 0;
}
+
+int smc911x_initialize(u8 dev_num, int base_addr)
+{
+ unsigned long addrl, addrh;
+ struct eth_device *dev;
+
+ dev = malloc(sizeof(*dev));
+ if (!dev) {
+ free(dev);
+ return 0;
+ }
+ memset(dev, 0, sizeof(*dev));
+
+ dev->iobase = base_addr;
+
+ addrh = smc911x_get_mac_csr(dev, ADDRH);
+ addrl = smc911x_get_mac_csr(dev, ADDRL);
+ dev->enetaddr[0] = addrl;
+ dev->enetaddr[1] = addrl >> 8;
+ dev->enetaddr[2] = addrl >> 16;
+ dev->enetaddr[3] = addrl >> 24;
+ dev->enetaddr[4] = addrh;
+ dev->enetaddr[5] = addrh >> 8;
+
+ dev->init = smc911x_init;
+ dev->halt = smc911x_halt;
+ dev->send = smc911x_send;
+ dev->recv = smc911x_rx;
+ sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num);
+
+ eth_register(dev);
+ return 0;
+}
#include <linux/types.h>
-#if defined (CONFIG_DRIVER_SMC911X_32_BIT) && \
- defined (CONFIG_DRIVER_SMC911X_16_BIT)
-#error "SMC911X: Only one of CONFIG_DRIVER_SMC911X_32_BIT and \
- CONFIG_DRIVER_SMC911X_16_BIT shall be set"
+#define DRIVERNAME "smc911x"
+
+#if defined (CONFIG_SMC911X_32_BIT) && \
+ defined (CONFIG_SMC911X_16_BIT)
+#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
+ CONFIG_SMC911X_16_BIT shall be set"
#endif
-#if defined (CONFIG_DRIVER_SMC911X_32_BIT)
-static inline u32 __smc911x_reg_read(u32 addr)
+#if defined (CONFIG_SMC911X_32_BIT)
+static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
{
- return *(volatile u32*)addr;
+ return *(volatile u32*)(dev->iobase + offset);
}
-u32 smc911x_reg_read(u32 addr) __attribute__((weak, alias("__smc911x_reg_read")));
+u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+ __attribute__((weak, alias("__smc911x_reg_read")));
-static inline void __smc911x_reg_write(u32 addr, u32 val)
+static inline void __smc911x_reg_write(struct eth_device *dev,
+ u32 offset, u32 val)
{
- *(volatile u32*)addr = val;
+ *(volatile u32*)(dev->iobase + offset) = val;
}
-void smc911x_reg_write(u32 addr, u32 val) __attribute__((weak, alias("__smc911x_reg_write")));
-#elif defined (CONFIG_DRIVER_SMC911X_16_BIT)
-static inline u32 smc911x_reg_read(u32 addr)
+void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
+ __attribute__((weak, alias("__smc911x_reg_write")));
+#elif defined (CONFIG_SMC911X_16_BIT)
+static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
{
- volatile u16 *addr_16 = (u16 *)addr;
+ volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
}
-static inline void smc911x_reg_write(u32 addr, u32 val)
+static inline void smc911x_reg_write(struct eth_device *dev,
+ u32 offset, u32 val)
{
- *(volatile u16*)addr = (u16)val;
- *(volatile u16*)(addr + 2) = (u16)(val >> 16);
+ *(volatile u16 *)(dev->iobase + offset) = (u16)val;
+ *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
}
#else
#error "SMC911X: undefined bus width"
-#endif /* CONFIG_DRIVER_SMC911X_16_BIT */
+#endif /* CONFIG_SMC911X_16_BIT */
/* Below are the register offsets and bit definitions
* of the Lan911x memory space
*/
-#define RX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x00)
+#define RX_DATA_FIFO 0x00
-#define TX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x20)
+#define TX_DATA_FIFO 0x20
#define TX_CMD_A_INT_ON_COMP 0x80000000
#define TX_CMD_A_INT_BUF_END_ALGN 0x03000000
#define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000
#define TX_CMD_B_DISABLE_PADDING 0x00001000
#define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF
-#define RX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x40)
+#define RX_STATUS_FIFO 0x40
#define RX_STS_PKT_LEN 0x3FFF0000
#define RX_STS_ES 0x00008000
#define RX_STS_BCST 0x00002000
#define RX_STS_MII_ERR 0x00000008
#define RX_STS_DRIBBLING 0x00000004
#define RX_STS_CRC_ERR 0x00000002
-#define RX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x44)
-#define TX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x48)
+#define RX_STATUS_FIFO_PEEK 0x44
+#define TX_STATUS_FIFO 0x48
#define TX_STS_TAG 0xFFFF0000
#define TX_STS_ES 0x00008000
#define TX_STS_LOC 0x00000800
#define TX_STS_MANY_DEFER 0x00000004
#define TX_STS_UNDERRUN 0x00000002
#define TX_STS_DEFERRED 0x00000001
-#define TX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x4C)
-#define ID_REV (CONFIG_DRIVER_SMC911X_BASE + 0x50)
+#define TX_STATUS_FIFO_PEEK 0x4C
+#define ID_REV 0x50
#define ID_REV_CHIP_ID 0xFFFF0000 /* RO */
#define ID_REV_REV_ID 0x0000FFFF /* RO */
-#define INT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x54)
+#define INT_CFG 0x54
#define INT_CFG_INT_DEAS 0xFF000000 /* R/W */
#define INT_CFG_INT_DEAS_CLR 0x00004000
#define INT_CFG_INT_DEAS_STS 0x00002000
#define INT_CFG_IRQ_INT 0x00001000 /* RO */
#define INT_CFG_IRQ_EN 0x00000100 /* R/W */
-#define INT_CFG_IRQ_POL 0x00000010 /* R/W Not Affected by SW Reset */
-#define INT_CFG_IRQ_TYPE 0x00000001 /* R/W Not Affected by SW Reset */
+ /* R/W Not Affected by SW Reset */
+#define INT_CFG_IRQ_POL 0x00000010
+ /* R/W Not Affected by SW Reset */
+#define INT_CFG_IRQ_TYPE 0x00000001
-#define INT_STS (CONFIG_DRIVER_SMC911X_BASE + 0x58)
+#define INT_STS 0x58
#define INT_STS_SW_INT 0x80000000 /* R/WC */
#define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */
#define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */
#define INT_STS_GPIO2_INT 0x00000004 /* R/WC */
#define INT_STS_GPIO1_INT 0x00000002 /* R/WC */
#define INT_STS_GPIO0_INT 0x00000001 /* R/WC */
-#define INT_EN (CONFIG_DRIVER_SMC911X_BASE + 0x5C)
+#define INT_EN 0x5C
#define INT_EN_SW_INT_EN 0x80000000 /* R/W */
#define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */
#define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */
#define INT_EN_GPIO1_INT 0x00000002 /* R/W */
#define INT_EN_GPIO0_INT 0x00000001 /* R/W */
-#define BYTE_TEST (CONFIG_DRIVER_SMC911X_BASE + 0x64)
-#define FIFO_INT (CONFIG_DRIVER_SMC911X_BASE + 0x68)
+#define BYTE_TEST 0x64
+#define FIFO_INT 0x68
#define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */
#define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */
#define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */
#define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */
-#define RX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x6C)
+#define RX_CFG 0x6C
#define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */
#define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */
#define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */
#define RX_CFG_RXDOFF 0x00001F00 /* R/W */
/*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */
-#define TX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x70)
+#define TX_CFG 0x70
/*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */
-/*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/ /* R/W Self Clearing */
+ /* R/W Self Clearing */
+/*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/
#define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */
#define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */
#define TX_CFG_TXSAO 0x00000004 /* R/W */
#define TX_CFG_TX_ON 0x00000002 /* R/W */
#define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */
-#define HW_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x74)
+#define HW_CFG 0x74
#define HW_CFG_TTM 0x00200000 /* R/W */
#define HW_CFG_SF 0x00100000 /* R/W */
#define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */
#define HW_CFG_SRST_TO 0x00000002 /* RO */
#define HW_CFG_SRST 0x00000001 /* Self Clearing */
-#define RX_DP_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x78)
+#define RX_DP_CTRL 0x78
#define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */
#define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */
-#define RX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x7C)
+#define RX_FIFO_INF 0x7C
#define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */
#define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */
-#define TX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x80)
+#define TX_FIFO_INF 0x80
#define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */
#define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */
-#define PMT_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x84)
+#define PMT_CTRL 0x84
#define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */
#define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */
#define PMT_CTRL_WOL_EN 0x00000200 /* R/W */
#define PMT_CTRL_ED_EN 0x00000100 /* R/W */
-#define PMT_CTRL_PME_TYPE 0x00000040 /* R/W Not Affected by SW Reset */
+ /* R/W Not Affected by SW Reset */
+#define PMT_CTRL_PME_TYPE 0x00000040
#define PMT_CTRL_WUPS 0x00000030 /* R/WC */
#define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */
#define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */
#define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */
#define PMT_CTRL_PME_IND 0x00000008 /* R/W */
#define PMT_CTRL_PME_POL 0x00000004 /* R/W */
-#define PMT_CTRL_PME_EN 0x00000002 /* R/W Not Affected by SW Reset */
+ /* R/W Not Affected by SW Reset */
+#define PMT_CTRL_PME_EN 0x00000002
#define PMT_CTRL_READY 0x00000001 /* RO */
-#define GPIO_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x88)
+#define GPIO_CFG 0x88
#define GPIO_CFG_LED3_EN 0x40000000 /* R/W */
#define GPIO_CFG_LED2_EN 0x20000000 /* R/W */
#define GPIO_CFG_LED1_EN 0x10000000 /* R/W */
#define GPIO_CFG_GPIOD1 0x00000002 /* R/W */
#define GPIO_CFG_GPIOD0 0x00000001 /* R/W */
-#define GPT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x8C)
+#define GPT_CFG 0x8C
#define GPT_CFG_TIMER_EN 0x20000000 /* R/W */
#define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */
-#define GPT_CNT (CONFIG_DRIVER_SMC911X_BASE + 0x90)
+#define GPT_CNT 0x90
#define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */
-#define ENDIAN (CONFIG_DRIVER_SMC911X_BASE + 0x98)
-#define FREE_RUN (CONFIG_DRIVER_SMC911X_BASE + 0x9C)
-#define RX_DROP (CONFIG_DRIVER_SMC911X_BASE + 0xA0)
-#define MAC_CSR_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xA4)
+#define ENDIAN 0x98
+#define FREE_RUN 0x9C
+#define RX_DROP 0xA0
+#define MAC_CSR_CMD 0xA4
#define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */
#define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */
#define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */
-#define MAC_CSR_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xA8)
-#define AFC_CFG (CONFIG_DRIVER_SMC911X_BASE + 0xAC)
+#define MAC_CSR_DATA 0xA8
+#define AFC_CFG 0xAC
#define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */
#define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */
#define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */
#define AFC_CFG_FCADD 0x00000002 /* R/W */
#define AFC_CFG_FCANY 0x00000001 /* R/W */
-#define E2P_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xB0)
+#define E2P_CMD 0xB0
#define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */
#define E2P_CMD_EPC_CMD 0x70000000 /* R/W */
#define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */
#define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */
#define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */
-#define E2P_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xB4)
+#define E2P_DATA 0xB4
#define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */
/* end of LAN register offsets and bit definitions */
#define CHIP_9216 0x116a
#define CHIP_9217 0x117a
#define CHIP_9218 0x118a
+#define CHIP_9221 0x9221
struct chip_id {
u16 id;
{ CHIP_9216, "LAN9216" },
{ CHIP_9217, "LAN9217" },
{ CHIP_9218, "LAN9218" },
+ { CHIP_9221, "LAN9221" },
{ 0, NULL },
};
-
-#define DRIVERNAME "smc911x"
-
-static u32 smc911x_get_mac_csr(u8 reg)
+static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
{
- while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+ while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
- smc911x_reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
- while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+ smc911x_reg_write(dev, MAC_CSR_CMD,
+ MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
+ while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
- return smc911x_reg_read(MAC_CSR_DATA);
+ return smc911x_reg_read(dev, MAC_CSR_DATA);
}
-static void smc911x_set_mac_csr(u8 reg, u32 data)
+static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
{
- while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+ while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
- smc911x_reg_write(MAC_CSR_DATA, data);
- smc911x_reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
- while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+ smc911x_reg_write(dev, MAC_CSR_DATA, data);
+ smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
+ while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
}
-static int smc911x_detect_chip(void)
+static int smc911x_detect_chip(struct eth_device *dev)
{
unsigned long val, i;
- val = smc911x_reg_read(BYTE_TEST);
+ val = smc911x_reg_read(dev, BYTE_TEST);
if (val != 0x87654321) {
printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
return -1;
}
- val = smc911x_reg_read(ID_REV) >> 16;
+ val = smc911x_reg_read(dev, ID_REV) >> 16;
for (i = 0; chip_ids[i].id != 0; i++) {
if (chip_ids[i].id == val) break;
}
return 0;
}
-static void smc911x_reset(void)
+static void smc911x_reset(struct eth_device *dev)
{
int timeout;
/* Take out of PM setting first */
- if (smc911x_reg_read(PMT_CTRL) & PMT_CTRL_READY) {
+ if (smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) {
/* Write to the bytetest will take out of powerdown */
- smc911x_reg_write(BYTE_TEST, 0x0);
+ smc911x_reg_write(dev, BYTE_TEST, 0x0);
timeout = 10;
- while (timeout-- && !(smc911x_reg_read(PMT_CTRL) & PMT_CTRL_READY))
+ while (timeout-- &&
+ !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
udelay(10);
if (!timeout) {
printf(DRIVERNAME
}
/* Disable interrupts */
- smc911x_reg_write(INT_EN, 0);
+ smc911x_reg_write(dev, INT_EN, 0);
- smc911x_reg_write(HW_CFG, HW_CFG_SRST);
+ smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
timeout = 1000;
- while (timeout-- && smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY)
+ while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
udelay(10);
if (!timeout) {
}
/* Reset the FIFO level and flow control settings */
- smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN);
- smc911x_reg_write(AFC_CFG, 0x0050287F);
+ smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
+ smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
/* Set to LED outputs */
- smc911x_reg_write(GPIO_CFG, 0x70070000);
+ smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
}
#endif
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
- * Copyright 2004, 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc.
* author Andy Fleming
*
for (i = 0; i < MAC_ADDR_LEN; i++) {
tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
}
- regs->macstnaddr1 = *((uint *) (tmpbuf));
+ tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
+ tmpbuf[3];
+
+ regs->macstnaddr1 = tempval;
tempval = *((uint *) (tmpbuf + 4));
},
};
+struct phy_info phy_info_VSC8641 = {
+ 0x7043,
+ "Vitesse VSC8641",
+ 4,
+ (struct phy_cmd[]){ /* config */
+ /* Configure some basic stuff */
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Read the Status (2x to make sure link is right) */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_VSC8244_AUX_CONSTAT, miim_read,
+ &mii_parse_vsc8244},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
+};
+
+struct phy_info phy_info_VSC8221 = {
+ 0xfc55,
+ "Vitesse VSC8221",
+ 4,
+ (struct phy_cmd[]){ /* config */
+ /* Configure some basic stuff */
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Read the Status (2x to make sure link is right) */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_VSC8244_AUX_CONSTAT, miim_read,
+ &mii_parse_vsc8244},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
+};
+
struct phy_info phy_info_VSC8601 = {
0x00007042,
"Vitesse VSC8601",
&phy_info_VSC8211,
&phy_info_VSC8244,
&phy_info_VSC8601,
+ &phy_info_VSC8641,
+ &phy_info_VSC8221,
&phy_info_dp83865,
&phy_info_rtl8211b,
&phy_info_generic, /* must be last; has ID 0 and 32 bit mask */
/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
*
* Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007
*
PCI_DEV(dev));
break;
#endif
-#ifdef CONFIG_MPC834x
+#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
case PCI_CLASS_BRIDGE_OTHER:
/*
* The host/PCI bridge 1 seems broken in 8349 - it presents
#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright (c) 2009 Wind River Systems, Inc.
+# Tom Rix <Tom.Rix at windriver.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
include $(TOPDIR)/config.mk
-LIB := $(obj)libnand_legacy.a
+LIB := $(obj)libpower.a
-ifdef CONFIG_CMD_NAND
-COBJS-$(CONFIG_NAND_LEGACY) := nand_legacy.o
-endif
+COBJS-$(CONFIG_TWL4030_POWER) += twl4030.o
COBJS := $(COBJS-y)
-SRCS := $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
+
#########################################################################
# defines $(obj).depend target
sinclude $(obj).depend
-#########################################################################
+########################################################################
--- /dev/null
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix at windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * twl4030_power_reset_init is derived from code on omapzoom,
+ * git://git.omapzoom.com/repo/u-boot.git
+ *
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ *
+ * twl4030_power_init is from cpu/omap3/common.c, power_init_r
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05 at gmail.com>
+ * Shashi Ranjan <shashiranjanmca05 at gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2 at ti.com>
+ * Syed Mohammed Khasim <khasim at ti.com>
+ *
+ */
+
+#include <twl4030.h>
+
+/*
+ * Power Reset
+ */
+void twl4030_power_reset_init(void)
+{
+ u8 val = 0;
+ if (twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &val,
+ TWL4030_PM_MASTER_P1_SW_EVENTS)) {
+ printf("Error:TWL4030: failed to read the power register\n");
+ printf("Could not initialize hardware reset\n");
+ } else {
+ val |= TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON;
+ if (twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, val,
+ TWL4030_PM_MASTER_P1_SW_EVENTS)) {
+ printf("Error:TWL4030: failed to write the power register\n");
+ printf("Could not initialize hardware reset\n");
+ }
+ }
+}
+
+
+/*
+ * Power Init
+ */
+#define DEV_GRP_P1 0x20
+#define VAUX3_VSEL_28 0x03
+#define DEV_GRP_ALL 0xE0
+#define VPLL2_VSEL_18 0x05
+#define VDAC_VSEL_18 0x03
+
+void twl4030_power_init(void)
+{
+ unsigned char byte;
+
+ /* set VAUX3 to 2.8V */
+ byte = DEV_GRP_P1;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
+ TWL4030_PM_RECEIVER_VAUX3_DEV_GRP);
+ byte = VAUX3_VSEL_28;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
+ TWL4030_PM_RECEIVER_VAUX3_DEDICATED);
+
+ /* set VPLL2 to 1.8V */
+ byte = DEV_GRP_ALL;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
+ TWL4030_PM_RECEIVER_VPLL2_DEV_GRP);
+ byte = VPLL2_VSEL_18;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
+ TWL4030_PM_RECEIVER_VPLL2_DEDICATED);
+
+ /* set VDAC to 1.8V */
+ byte = DEV_GRP_P1;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
+ TWL4030_PM_RECEIVER_VDAC_DEV_GRP);
+ byte = VDAC_VSEL_18;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
+ TWL4030_PM_RECEIVER_VDAC_DEDICATED);
+}
+
+#define VMMC1_VSEL_30 0x02
+
+void twl4030_power_mmc_init(void)
+{
+ unsigned char byte;
+
+ byte = DEV_GRP_P1;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
+ TWL4030_PM_RECEIVER_VMMC1_DEV_GRP);
+
+ /* 3 Volts */
+ byte = VMMC1_VSEL_30;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
+ TWL4030_PM_RECEIVER_VMMC1_DEDICATED);
+}
*/
#include <common.h>
-#include <devices.h>
+#include <stdio_dev.h>
#if defined(CONFIG_CPU_V6)
/*
}
#ifdef CONFIG_ARM_DCC_MULTI
-static device_t arm_dcc_dev;
+static struct stdio_dev arm_dcc_dev;
int drv_arm_dcc_init(void)
{
arm_dcc_dev.putc = arm_dcc_putc; /* 'putc' function */
arm_dcc_dev.puts = arm_dcc_puts; /* 'puts' function */
- return device_register(&arm_dcc_dev);
+ return stdio_register(&arm_dcc_dev);
}
#endif
#include <common.h>
#include <config.h>
#include <circbuf.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include "usbtty.h"
#include "usb_cdc_acm.h"
#include "usbdescriptors.h"
/*
* Instance variables
*/
-static device_t usbttydev;
+static struct stdio_dev usbttydev;
static struct usb_device_instance device_instance[1];
static struct usb_bus_instance bus_instance[1];
static struct usb_configuration_instance config_instance[NUM_CONFIGS];
usbttydev.putc = usbtty_putc; /* 'putc' function */
usbttydev.puts = usbtty_puts; /* 'puts' function */
- rc = device_register (&usbttydev);
+ rc = stdio_register (&usbttydev);
return (rc == 0) ? 1 : rc;
}
req->requesttype, req->requesttype,
le16_to_cpu(req->value), le16_to_cpu(req->index));
- typeReq = req->request << 8 | req->requesttype;
+ typeReq = req->request | req->requesttype << 8;
- switch (le16_to_cpu(typeReq)) {
+ switch (typeReq) {
case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
switch (le16_to_cpu(req->value) >> 8) {
case USB_DT_DEVICE:
*/
void usb_event_poll()
{
- device_t *dev;
+ struct stdio_dev *dev;
struct usb_device *usb_kbd_dev;
struct usb_interface_descriptor *iface;
struct usb_endpoint_descriptor *ep;
int maxp;
/* Get the pointer to USB Keyboard device pointer */
- dev = device_get_by_name("usbkbd");
+ dev = stdio_get_by_name("usbkbd");
usb_kbd_dev = (struct usb_device *)dev->priv;
iface = &usb_kbd_dev->config.if_desc[0];
ep = &iface->ep_desc[0];
#include "musb_core.h"
#ifdef CONFIG_USB_KEYBOARD
-#include <devices.h>
+#include <stdio_dev.h>
extern unsigned char new[];
#endif
COBJS-$(CONFIG_SED156X) += sed156x.o
COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o
+COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
COBJS-y += videomodes.o
COBJS := $(COBJS-y)
--- /dev/null
+/*
+ * (C) Copyright 2005-2009
+ * Jens Scharsig @ BuS Elektronik GmbH & Co. KG, <esw@bus-elektronik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <bmp_layout.h>
+#include <asm/io.h>
+
+vu_char *vcxk_bws = ((vu_char *) (CONFIG_SYS_VCXK_BASE));
+vu_short *vcxk_bws_word = ((vu_short *)(CONFIG_SYS_VCXK_BASE));
+vu_long *vcxk_bws_long = ((vu_long *) (CONFIG_SYS_VCXK_BASE));
+
+#ifdef CONFIG_AT91RM9200
+ #include <asm/arch/hardware.h>
+ #ifndef VCBITMASK
+ #define VCBITMASK(bitno) (0x0001 << (bitno % 16))
+ #endif
+ #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \
+ ((AT91PS_PIO) PORT)->PIO_PER = PIN; \
+ ((AT91PS_PIO) PORT)->DDR = PIN; \
+ ((AT91PS_PIO) PORT)->PIO_MDDR = PIN; \
+ if (!I0O1) ((AT91PS_PIO) PORT)->PIO_PPUER = PIN;
+
+ #define VCXK_SET_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_SODR = PIN;
+ #define VCXK_CLR_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_CODR = PIN;
+
+ #define VCXK_ACKNOWLEDGE \
+ (!(((AT91PS_PIO) CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT)->\
+ PIO_PDSR & CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN))
+
+#elif defined(CONFIG_MCF52x2)
+ #include <asm/m5282.h>
+ #ifndef VCBITMASK
+ #define VCBITMASK(bitno) (0x8000 >> (bitno % 16))
+ #endif
+
+ #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \
+ if (I0O1) DDR |= PIN; else DDR &= ~PIN;
+
+ #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN;
+ #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN;
+
+ #define VCXK_ACKNOWLEDGE \
+ (!(CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT & \
+ CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN))
+
+#else
+ #error no vcxk support for selected ARCH
+#endif
+
+#define VCXK_DISABLE\
+ VCXK_SET_PIN(CONFIG_SYS_VCXK_ENABLE_PORT, CONFIG_SYS_VCXK_ENABLE_PIN)
+#define VCXK_ENABLE\
+ VCXK_CLR_PIN(CONFIG_SYS_VCXK_ENABLE_PORT, CONFIG_SYS_VCXK_ENABLE_PIN)
+
+#ifndef CONFIG_SYS_VCXK_DOUBLEBUFFERED
+ #define VCXK_BWS(x, data) vcxk_bws[x] = data;
+ #define VCXK_BWS_WORD_SET(x, mask) vcxk_bws_word[x] |= mask;
+ #define VCXK_BWS_WORD_CLEAR(x, mask) vcxk_bws_word[x] &= ~mask;
+ #define VCXK_BWS_LONG(x, data) vcxk_bws_long[x] = data;
+#else
+ u_char double_bws[16384];
+ u_short *double_bws_word;
+ u_long *double_bws_long;
+ #define VCXK_BWS(x,data) \
+ double_bws[x] = data; vcxk_bws[x] = data;
+ #define VCXK_BWS_WORD_SET(x,mask) \
+ double_bws_word[x] |= mask; \
+ vcxk_bws_word[x] = double_bws_word[x];
+ #define VCXK_BWS_WORD_CLEAR(x,mask) \
+ double_bws_word[x] &= ~mask; \
+ vcxk_bws_word[x] = double_bws_word[x];
+ #define VCXK_BWS_LONG(x,data) \
+ double_bws_long[x] = data; vcxk_bws_long[x] = data;
+#endif
+
+#define VC4K16_Bright1 vcxk_bws_word[0x20004 / 2]
+#define VC4K16_Bright2 vcxk_bws_word[0x20006 / 2]
+#define VC2K_Bright vcxk_bws[0x8000]
+#define VC8K_BrightH vcxk_bws[0xC000]
+#define VC8K_BrightL vcxk_bws[0xC001]
+
+vu_char VC4K16;
+
+u_long display_width;
+u_long display_height;
+u_long display_bwidth;
+
+ulong search_vcxk_driver(void);
+void vcxk_cls(void);
+void vcxk_setbrightness(unsigned int side, short brightness);
+int vcxk_request(void);
+int vcxk_acknowledge_wait(void);
+void vcxk_clear(void);
+
+/*
+ ****f* bus_vcxk/vcxk_init
+ * FUNCTION
+ * initialalize Video Controller
+ * PARAMETERS
+ * width visible display width in pixel
+ * height visible display height in pixel
+ ***
+ */
+
+int vcxk_init(unsigned long width, unsigned long height)
+{
+#ifdef CONFIG_SYS_VCXK_RESET_PORT
+ VCXK_INIT_PIN(CONFIG_SYS_VCXK_RESET_PORT,
+ CONFIG_SYS_VCXK_RESET_PIN, CONFIG_SYS_VCXK_RESET_DDR, 1)
+ VCXK_SET_PIN(CONFIG_SYS_VCXK_RESET_PORT, CONFIG_SYS_VCXK_RESET_PIN);
+#endif
+
+#ifdef CONFIG_SYS_VCXK_DOUBLEBUFFERED
+ double_bws_word = (u_short *)double_bws;
+ double_bws_long = (u_long *)double_bws;
+ debug("%lx %lx %lx \n", double_bws, double_bws_word, double_bws_long);
+#endif
+ display_width = width;
+ display_height = height;
+#if (CONFIG_SYS_VCXK_DEFAULT_LINEALIGN == 4)
+ display_bwidth = ((width + 31) / 8) & ~0x3;
+#elif (CONFIG_SYS_VCXK_DEFAULT_LINEALIGN == 2)
+ display_bwidth = ((width + 15) / 8) & ~0x1;
+#else
+ #error CONFIG_SYS_VCXK_DEFAULT_LINEALIGN is invalid
+#endif
+ debug("linesize ((%d + 15) / 8 & ~0x1) = %d\n",
+ display_width, display_bwidth);
+
+#ifdef CONFIG_SYS_VCXK_AUTODETECT
+ VC4K16 = 0;
+ vcxk_bws_long[1] = 0x0;
+ vcxk_bws_long[1] = 0x55AAAA55;
+ vcxk_bws_long[5] = 0x0;
+ if (vcxk_bws_long[1] == 0x55AAAA55)
+ VC4K16 = 1;
+#else
+ VC4K16 = 1;
+ debug("No autodetect: use vc4k\n");
+#endif
+
+ VCXK_INIT_PIN(CONFIG_SYS_VCXK_INVERT_PORT,
+ CONFIG_SYS_VCXK_INVERT_PIN, CONFIG_SYS_VCXK_INVERT_DDR, 1)
+ VCXK_SET_PIN(CONFIG_SYS_VCXK_INVERT_PORT, CONFIG_SYS_VCXK_INVERT_PIN)
+
+ VCXK_SET_PIN(CONFIG_SYS_VCXK_REQUEST_PORT, CONFIG_SYS_VCXK_REQUEST_PIN);
+ VCXK_INIT_PIN(CONFIG_SYS_VCXK_REQUEST_PORT,
+ CONFIG_SYS_VCXK_REQUEST_PIN, CONFIG_SYS_VCXK_REQUEST_DDR, 1)
+
+ VCXK_INIT_PIN(CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT,
+ CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN,
+ CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR, 0)
+
+ VCXK_DISABLE;
+ VCXK_INIT_PIN(CONFIG_SYS_VCXK_ENABLE_PORT,
+ CONFIG_SYS_VCXK_ENABLE_PIN, CONFIG_SYS_VCXK_ENABLE_DDR, 1)
+
+ vcxk_cls();
+ vcxk_cls(); /* clear second/hidden page */
+
+ vcxk_setbrightness(3, 1000);
+ VCXK_ENABLE;
+ return 1;
+}
+
+/*
+ ****f* bus_vcxk/vcxk_setpixel
+ * FUNCTION
+ * set the pixel[x,y] with the given color
+ * PARAMETER
+ * x pixel colum
+ * y pixel row
+ * color <0x40 off/black
+ * >0x40 on
+ ***
+ */
+
+void vcxk_setpixel(int x, int y, unsigned long color)
+{
+ vu_short dataptr;
+
+ if ((x < display_width) && (y < display_height)) {
+ dataptr = ((x / 16)) + (y * (display_bwidth >> 1));
+
+ color = ((color >> 16) & 0xFF) |
+ ((color >> 8) & 0xFF) | (color & 0xFF);
+
+ if (color > 0x40) {
+ VCXK_BWS_WORD_SET(dataptr, VCBITMASK(x));
+ } else {
+ VCXK_BWS_WORD_CLEAR(dataptr, VCBITMASK(x));
+ }
+ }
+}
+
+/*
+ ****f* bus_vcxk/vcxk_loadimage
+ * FUNCTION
+ * copies a binary image to display memory
+ ***
+ */
+
+void vcxk_loadimage(ulong source)
+{
+ int cnt;
+ vcxk_acknowledge_wait();
+ if (VC4K16) {
+ for (cnt = 0; cnt < (16384 / 4); cnt++) {
+ VCXK_BWS_LONG(cnt, (*(ulong *) source));
+ source = source + 4;
+ }
+ } else {
+ for (cnt = 0; cnt < 16384; cnt++) {
+ VCXK_BWS_LONG(cnt*2, (*(vu_char *) source));
+ source++;
+ }
+ }
+ vcxk_request();
+}
+
+/*
+ ****f* bus_vcxk/vcxk_cls
+ * FUNCTION
+ * clear the display
+ ***
+ */
+
+void vcxk_cls(void)
+{
+ vcxk_acknowledge_wait();
+ vcxk_clear();
+ vcxk_request();
+}
+
+/*
+ ****f* bus_vcxk/vcxk_clear(void)
+ * FUNCTION
+ * clear the display memory
+ ***
+ */
+
+void vcxk_clear(void)
+{
+ int cnt;
+
+ for (cnt = 0; cnt < (16384 / 4); cnt++) {
+ VCXK_BWS_LONG(cnt, 0)
+ }
+}
+
+/*
+ ****f* bus_vcxk/vcxk_setbrightness
+ * FUNCTION
+ * set the display brightness
+ * PARAMETER
+ * side 1 set front side brightness
+ * 2 set back side brightness
+ * 3 set brightness for both sides
+ * brightness 0..1000
+ ***
+ */
+
+void vcxk_setbrightness(unsigned int side, short brightness)
+{
+ if (VC4K16) {
+ if ((side == 0) || (side & 0x1))
+ VC4K16_Bright1 = brightness + 23;
+ if ((side == 0) || (side & 0x2))
+ VC4K16_Bright2 = brightness + 23;
+ } else {
+ VC2K_Bright = (brightness >> 4) + 2;
+ VC8K_BrightH = (brightness + 23) >> 8;
+ VC8K_BrightL = (brightness + 23) & 0xFF;
+ }
+}
+
+/*
+ ****f* bus_vcxk/vcxk_request
+ * FUNCTION
+ * requests viewing of display memory
+ ***
+ */
+
+int vcxk_request(void)
+{
+ VCXK_CLR_PIN(CONFIG_SYS_VCXK_REQUEST_PORT,
+ CONFIG_SYS_VCXK_REQUEST_PIN)
+ VCXK_SET_PIN(CONFIG_SYS_VCXK_REQUEST_PORT,
+ CONFIG_SYS_VCXK_REQUEST_PIN);
+ return 1;
+}
+
+/*
+ ****f* bus_vcxk/vcxk_acknowledge_wait
+ * FUNCTION
+ * wait for acknowledge viewing requests
+ ***
+ */
+
+int vcxk_acknowledge_wait(void)
+{
+ while (VCXK_ACKNOWLEDGE)
+ ;
+ return 1;
+}
+
+/*
+ ****f* bus_vcxk/vcxk_draw_mono
+ * FUNCTION
+ * copies a monochrom bitmap (BMP-Format) from given memory
+ * PARAMETER
+ * dataptr pointer to bitmap
+ * x output bitmap @ columne
+ * y output bitmap @ row
+ ***
+ */
+
+void vcxk_draw_mono(unsigned char *dataptr, unsigned long linewidth,
+ unsigned long cp_width, unsigned long cp_height)
+{
+ unsigned char *lineptr;
+ unsigned long xcnt, ycnt;
+
+ for (ycnt = cp_height; ycnt > 0; ycnt--) {
+ lineptr = dataptr;
+ for (xcnt = 0; xcnt < cp_width; xcnt++) {
+ if ((*lineptr << (xcnt % 8)) & 0x80)
+ vcxk_setpixel(xcnt, ycnt - 1, 0xFFFFFF);
+ else
+ vcxk_setpixel(xcnt, ycnt-1, 0);
+
+ if ((xcnt % 8) == 7)
+ lineptr++;
+ } /* endfor xcnt */
+ dataptr = dataptr + linewidth;
+ } /* endfor ycnt */
+}
+
+/*
+ ****f* bus_vcxk/vcxk_display_bitmap
+ * FUNCTION
+ * copies a bitmap (BMP-Format) to the given position
+ * PARAMETER
+ * addr pointer to bitmap
+ * x output bitmap @ columne
+ * y output bitmap @ row
+ ***
+ */
+
+int vcxk_display_bitmap(ulong addr, int x, int y)
+{
+ bmp_image_t *bmp;
+ unsigned long width;
+ unsigned long height;
+ unsigned long bpp;
+ unsigned long compression;
+
+ unsigned long lw;
+
+ unsigned long c_width;
+ unsigned long c_height;
+ unsigned char *dataptr;
+ unsigned char *lineptr;
+
+ bmp = (bmp_image_t *) addr;
+ if ((bmp->header.signature[0] == 'B') &&
+ (bmp->header.signature[1] == 'M')) {
+ compression = le32_to_cpu(bmp->header.compression);
+ width = le32_to_cpu(bmp->header.width);
+ height = le32_to_cpu(bmp->header.height);
+ bpp = le16_to_cpu(bmp->header.bit_count);
+
+ dataptr = (unsigned char *) bmp +
+ le32_to_cpu(bmp->header.data_offset);
+
+ if (display_width < (width + x))
+ c_width = display_width - x;
+ else
+ c_width = width;
+ if (display_height < (height + y))
+ c_height = display_height - y;
+ else
+ c_height = height;
+
+ lw = (((width + 7) / 8) + 3) & ~0x3;
+
+ if (c_height < height)
+ dataptr = dataptr + lw * (height - c_height);
+ switch (bpp) {
+ case 1:
+ vcxk_draw_mono(dataptr, lw, c_width, c_height);
+ break;
+ default:
+ printf("Error: %ld bit per pixel "
+ "not supported by VCxK\n", bpp);
+ return 0;
+ }
+ } else {
+ printf("Error: no valid bmp at %lx\n", (ulong) bmp);
+ return 0;
+ }
+ return 1;
+}
+
+/*
+ ****f* bus_vcxk/video_display_bitmap
+ ***
+ */
+
+int video_display_bitmap(ulong addr, int x, int y)
+{
+ vcxk_acknowledge_wait();
+ if (vcxk_display_bitmap(addr, x, y)) {
+ vcxk_request();
+ return 0;
+ }
+ return 1;
+}
+
+/* EOF */
#include <version.h>
#include <linux/types.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <video_font.h>
#if defined(CONFIG_CMD_DATE)
#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
#include <watchdog.h>
#include <bmp_layout.h>
+
+#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+#define BMP_ALIGN_CENTER 0x7FFF
+#endif
+
#endif
/*****************************************************************************/
padded_line = (((width * bpp + 7) / 8) + 3) & ~0x3;
+#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+ if (x == BMP_ALIGN_CENTER)
+ x = max(0, (VIDEO_VISIBLE_COLS - width) / 2);
+ else if (x < 0)
+ x = max(0, VIDEO_VISIBLE_COLS - width + x + 1);
+
+ if (y == BMP_ALIGN_CENTER)
+ y = max(0, (VIDEO_VISIBLE_ROWS - height) / 2);
+ else if (y < 0)
+ y = max(0, VIDEO_VISIBLE_ROWS - height + y + 1);
+#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
+
if ((x + width) > VIDEO_VISIBLE_COLS)
width = VIDEO_VISIBLE_COLS - x;
if ((y + height) > VIDEO_VISIBLE_ROWS)
ulong addr;
if ((s = getenv ("splashimage")) != NULL) {
+ int x = 0, y = 0;
+
addr = simple_strtoul (s, NULL, 16);
+#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+ if ((s = getenv ("splashpos")) != NULL) {
+ if (s[0] == 'm')
+ x = BMP_ALIGN_CENTER;
+ else
+ x = simple_strtol (s, NULL, 0);
+
+ if ((s = strchr (s + 1, ',')) != NULL) {
+ if (s[1] == 'm')
+ y = BMP_ALIGN_CENTER;
+ else
+ y = simple_strtol (s + 1, NULL, 0);
+ }
+ }
+#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
- if (video_display_bitmap (addr, 0, 0) == 0) {
+ if (video_display_bitmap (addr, x, y) == 0) {
return ((void *) (video_fb_address));
}
}
int drv_video_init (void)
{
int skip_dev_init;
- device_t console_dev;
+ struct stdio_dev console_dev;
/* Check if video initialization should be skipped */
if (board_video_skip())
console_dev.getc = VIDEO_GETC_FCT; /* 'getc' function */
#endif /* CONFIG_VGA_AS_SINGLE_DEVICE */
- if (device_register (&console_dev) != 0)
+ if (stdio_register (&console_dev) != 0)
return 0;
/* Return success */
#if defined(CONFIG_POST)
#include <post.h>
#endif
+
/*
* Graphic Device
*/
#define rd_io in32r
#define wr_io out32r
#else
-#define rd_io(addr) in_be32((volatile unsigned*)(addr))
-#define wr_io(addr,val) out_be32((volatile unsigned*)(addr), (val))
+#define rd_io(addr) in_be32((volatile unsigned *)(addr))
+#define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val))
#endif
-#define HOST_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fc0000 + (off)))
-#define HOST_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fc0000 + (off)), (val))
-#define DISP_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fd0000 + (off)))
-#define DISP_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fd0000 + (off)), (val))
-#define DE_RD_REG(off) rd_io((pGD->dprBase + (off)))
-#define DE_WR_REG(off, val) wr_io((pGD->dprBase + (off)), (val))
+#define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))
+#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \
+ (val))
+#define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))
+#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \
+ (val))
+#define DE_RD_REG(off) rd_io((dev->dprBase + (off)))
+#define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
#if defined(CONFIG_VIDEO_CORALP)
-#define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x8400)), (val))
+#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val))
#else
-#define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x04a0)), (val))
+#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val))
#endif
-#define L0PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2)))
-#define L0PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2)), (val))
-#define L1PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2)))
-#define L1PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2)), (val))
-#define L2PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2)))
-#define L2PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2)), (val))
-#define L3PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2)))
-#define L3PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2)), (val))
+#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \
+ (GC_DISP_BASE | GC_L0PAL0) + \
+ ((idx) << 2)), (val))
-static void gdc_sw_reset(void)
+static void gdc_sw_reset (void)
{
- GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
- HOST_WR_REG (0x002c, 0x00000001);
+ GraphicDevice *dev = &mb862xx;
+
+ HOST_WR_REG (GC_SRST, 0x1);
udelay (500);
video_hw_init ();
}
-static void de_wait(void)
+static void de_wait (void)
{
- GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+ GraphicDevice *dev = &mb862xx;
int lc = 0x10000;
- /* Sync with software writes to framebuffer,
- try to reset if engine locked */
- while (DE_RD_REG (0x0400) & 0x00000131)
+ /*
+ * Sync with software writes to framebuffer,
+ * try to reset if engine locked
+ */
+ while (DE_RD_REG (GC_CTR) & 0x00000131)
if (lc-- < 0) {
gdc_sw_reset ();
- printf ("gdc reset done after drawing engine lock...\n");
+ puts ("gdc reset done after drawing engine lock.\n");
break;
}
}
-static void de_wait_slots(int slots)
+static void de_wait_slots (int slots)
{
- GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+ GraphicDevice *dev = &mb862xx;
int lc = 0x10000;
/* Wait for free fifo slots */
- while (DE_RD_REG (0x0408) < slots)
+ while (DE_RD_REG (GC_IFCNT) < slots)
if (lc-- < 0) {
gdc_sw_reset ();
- printf ("gdc reset done after drawing engine lock...\n");
+ puts ("gdc reset done after drawing engine lock.\n");
break;
}
}
#if !defined(CONFIG_VIDEO_CORALP)
-static void board_disp_init(void)
+static void board_disp_init (void)
{
- GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+ GraphicDevice *dev = &mb862xx;
const gdc_regs *regs = board_get_regs ();
while (regs->index) {
*/
static void de_init (void)
{
- GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
- int cf = (pGD->gdfBytesPP == 1) ? 0x0000 : 0x8000;
+ GraphicDevice *dev = &mb862xx;
+ int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
- pGD->dprBase = pGD->frameAdrs + 0x01ff0000;
+ dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
/* Setup mode and fbbase, xres, fg, bg */
de_wait_slots (2);
DE_WR_FIFO (0xf1010108);
DE_WR_FIFO (cf | 0x0300);
- DE_WR_REG (0x0440, 0x0000);
- DE_WR_REG (0x0444, pGD->winSizeX);
- DE_WR_REG (0x0480, 0x0000);
- DE_WR_REG (0x0484, 0x0000);
+ DE_WR_REG (GC_FBR, 0x0);
+ DE_WR_REG (GC_XRES, dev->winSizeX);
+ DE_WR_REG (GC_FC, 0x0);
+ DE_WR_REG (GC_BC, 0x0);
/* Reset clipping */
- DE_WR_REG (0x0454, 0x0000);
- DE_WR_REG (0x0458, pGD->winSizeX);
- DE_WR_REG (0x045c, 0x0000);
- DE_WR_REG (0x0460, pGD->winSizeY);
+ DE_WR_REG (GC_CXMIN, 0x0);
+ DE_WR_REG (GC_CXMAX, dev->winSizeX);
+ DE_WR_REG (GC_CYMIN, 0x0);
+ DE_WR_REG (GC_CYMAX, dev->winSizeY);
/* Clear framebuffer using drawing engine */
de_wait_slots (3);
DE_WR_FIFO (0x09410000);
DE_WR_FIFO (0x00000000);
- DE_WR_FIFO (pGD->winSizeY<<16 | pGD->winSizeX);
+ DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
/* sync with SW access to framebuffer */
de_wait ();
}
#if defined(CONFIG_VIDEO_CORALP)
-unsigned int pci_video_init(void)
+unsigned int pci_video_init (void)
{
- GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+ GraphicDevice *dev = &mb862xx;
pci_dev_t devbusfn;
- if ((devbusfn = pci_find_devices(supported, 0)) < 0)
- {
- printf ("PCI video controller not found!\n");
+ if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
+ puts ("PCI video controller not found!\n");
return 0;
}
/* PCI setup */
- pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
- pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pGD->frameAdrs);
- pGD->frameAdrs = pci_mem_to_phys (devbusfn, pGD->frameAdrs);
+ pci_write_config_dword (devbusfn, PCI_COMMAND,
+ (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
+ pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs);
+ dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
- if (pGD->frameAdrs == 0) {
- printf ("PCI config: failed to get base address\n");
+ if (dev->frameAdrs == 0) {
+ puts ("PCI config: failed to get base address\n");
return 0;
}
- pGD->pciBase = pGD->frameAdrs;
+ dev->pciBase = dev->frameAdrs;
/* Setup clocks and memory mode for Coral-P Eval. Board */
- HOST_WR_REG (0x0038, 0x00090000);
+ HOST_WR_REG (GC_CCF, 0x00090000);
udelay (200);
- HOST_WR_REG (0xfffc, 0x11d7fa13);
+ HOST_WR_REG (GC_MMR, 0x11d7fa13);
udelay (100);
- return pGD->frameAdrs;
+ return dev->frameAdrs;
}
unsigned int card_init (void)
{
- GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+ GraphicDevice *dev = &mb862xx;
unsigned int cf, videomode, div = 0;
unsigned long t1, hsync, vsync;
char *penv;
struct ctfb_res_modes *res_mode;
struct ctfb_res_modes var_mode;
- memset (pGD, 0, sizeof (GraphicDevice));
+ memset (dev, 0, sizeof (GraphicDevice));
- if (!pci_video_init ()) {
+ if (!pci_video_init ())
return 0;
- }
- printf ("CoralP\n");
+ puts ("CoralP\n");
tmp = 0;
videomode = 0x310;
/* get video mode via environment */
if ((penv = getenv ("videomode")) != NULL) {
- /* deceide if it is a string */
+ /* decide if it is a string */
if (penv[0] <= '9') {
videomode = (int) simple_strtoul (penv, NULL, 16);
tmp = 1;
} else {
tmp = 1;
}
+
if (tmp) {
- /* parameter are vesa modes */
- /* search params */
+ /* parameter are vesa modes, search params */
for (i = 0; i < VESA_MODES_COUNT; i++) {
if (vesa_modes[i].vesanr == videomode)
break;
}
if (i == VESA_MODES_COUNT) {
- printf ("\tno VESA Mode found, switching to mode 0x%x \n", videomode);
+ printf ("\tno VESA Mode found, fallback to mode 0x%x\n",
+ videomode);
i = 0;
}
- res_mode =
- (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex];
+ res_mode = (struct ctfb_res_modes *)
+ &res_mode_init[vesa_modes[i].resindex];
if (vesa_modes[i].resindex > 2) {
- printf ("\tUnsupported resolution, switching to default\n");
+ puts ("\tUnsupported resolution, using default\n");
bpp = vesa_modes[1].bits_per_pixel;
div = fr_div[1];
}
bpp = vesa_modes[i].bits_per_pixel;
div = fr_div[vesa_modes[i].resindex];
} else {
-
res_mode = (struct ctfb_res_modes *) &var_mode;
bpp = video_get_params (res_mode, penv);
}
vsync = 1000000000L / t1;
/* fill in Graphic device struct */
- sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
+ sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
res_mode->yres, bpp, (hsync / 1000), (vsync / 1000));
- printf ("\t%s\n", pGD->modeIdent);
- pGD->winSizeX = res_mode->xres;
- pGD->winSizeY = res_mode->yres;
- pGD->memSize = VIDEO_MEM_SIZE;
+ printf ("\t%s\n", dev->modeIdent);
+ dev->winSizeX = res_mode->xres;
+ dev->winSizeY = res_mode->yres;
+ dev->memSize = VIDEO_MEM_SIZE;
switch (bpp) {
case 8:
- pGD->gdfIndex = GDF__8BIT_INDEX;
- pGD->gdfBytesPP = 1;
+ dev->gdfIndex = GDF__8BIT_INDEX;
+ dev->gdfBytesPP = 1;
break;
case 15:
case 16:
- pGD->gdfIndex = GDF_15BIT_555RGB;
- pGD->gdfBytesPP = 2;
+ dev->gdfIndex = GDF_15BIT_555RGB;
+ dev->gdfBytesPP = 2;
break;
default:
- printf ("\t%d bpp configured, but only 8,15 and 16 supported.\n", bpp);
- printf ("\tSwitching back to 15bpp\n");
- pGD->gdfIndex = GDF_15BIT_555RGB;
- pGD->gdfBytesPP = 2;
+ printf ("\t%d bpp configured, but only 8,15 and 16 supported\n",
+ bpp);
+ puts ("\tfallback to 15bpp\n");
+ dev->gdfIndex = GDF_15BIT_555RGB;
+ dev->gdfBytesPP = 2;
}
/* Setup dot clock (internal pll, division rate) */
- DISP_WR_REG (0x0100, div);
+ DISP_WR_REG (GC_DCM1, div);
/* L0 init */
- cf = (pGD->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
- DISP_WR_REG (0x0020, ((pGD->winSizeX * pGD->gdfBytesPP)/64)<<16 |
- (pGD->winSizeY-1) |
- cf);
- DISP_WR_REG (0x0024, 0x00000000);
- DISP_WR_REG (0x0028, 0x00000000);
- DISP_WR_REG (0x002c, 0x00000000);
- DISP_WR_REG (0x0110, 0x00000000);
- DISP_WR_REG (0x0114, 0x00000000);
- DISP_WR_REG (0x0118, (pGD->winSizeY-1)<<16 | pGD->winSizeX);
+ cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
+ DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 |
+ (dev->winSizeY - 1) | cf);
+ DISP_WR_REG (GC_L0OA0, 0x0);
+ DISP_WR_REG (GC_L0DA0, 0x0);
+ DISP_WR_REG (GC_L0DY_L0DX, 0x0);
+ DISP_WR_REG (GC_L0EM, 0x0);
+ DISP_WR_REG (GC_L0WY_L0WX, 0x0);
+ DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX);
/* Display timing init */
- DISP_WR_REG (0x0004, (pGD->winSizeX+res_mode->left_margin+res_mode->right_margin+res_mode->hsync_len-1)<<16);
- DISP_WR_REG (0x0008, (pGD->winSizeX-1) << 16 | (pGD->winSizeX-1));
- DISP_WR_REG (0x000c, (res_mode->vsync_len-1)<<24|(res_mode->hsync_len-1)<<16|(pGD->winSizeX+res_mode->right_margin-1));
- DISP_WR_REG (0x0010, (pGD->winSizeY+res_mode->lower_margin+res_mode->upper_margin+res_mode->vsync_len-1)<<16);
- DISP_WR_REG (0x0014, (pGD->winSizeY-1) << 16 | (pGD->winSizeY+res_mode->lower_margin-1));
- DISP_WR_REG (0x0018, 0x00000000);
- DISP_WR_REG (0x001c, pGD->winSizeY << 16 | pGD->winSizeX);
+ DISP_WR_REG (GC_HTP_A, (dev->winSizeX +
+ res_mode->left_margin +
+ res_mode->right_margin +
+ res_mode->hsync_len - 1) << 16);
+ DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 |
+ (dev->winSizeX - 1));
+ DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 |
+ (res_mode->hsync_len - 1) << 16 |
+ (dev->winSizeX +
+ res_mode->right_margin - 1));
+ DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin +
+ res_mode->upper_margin +
+ res_mode->vsync_len - 1) << 16);
+ DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 |
+ (dev->winSizeY +
+ res_mode->lower_margin - 1));
+ DISP_WR_REG (GC_WY_WX, 0x0);
+ DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX);
/* Display enable, L0 layer */
- DISP_WR_REG (0x0100, 0x80010000 | div);
+ DISP_WR_REG (GC_DCM1, 0x80010000 | div);
- return pGD->frameAdrs;
+ return dev->frameAdrs;
}
#endif
void *video_hw_init (void)
{
- GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+ GraphicDevice *dev = &mb862xx;
- printf ("Video: Fujitsu ");
+ puts ("Video: Fujitsu ");
- memset (pGD, 0, sizeof (GraphicDevice));
+ memset (dev, 0, sizeof (GraphicDevice));
#if defined(CONFIG_VIDEO_CORALP)
- if (card_init () == 0) {
- return (NULL);
- }
+ if (card_init () == 0)
+ return NULL;
#else
- /* Preliminary init of the onboard graphic controller,
- retrieve base address */
- if ((pGD->frameAdrs = board_video_init ()) == 0) {
- printf ("Controller not found!\n");
- return (NULL);
+ /*
+ * Preliminary init of the onboard graphic controller,
+ * retrieve base address
+ */
+ if ((dev->frameAdrs = board_video_init ()) == 0) {
+ puts ("Controller not found!\n");
+ return NULL;
} else
- printf("Lime\n");
+ puts ("Lime\n");
#endif
de_init ();
#if !defined(CONFIG_VIDEO_CORALP)
- board_disp_init();
+ board_disp_init ();
#endif
#if (defined(CONFIG_LWMON5) || \
board_backlight_switch (1);
#endif
- return pGD;
+ return dev;
}
/*
* Set a RGB color in the LUT
*/
-void video_set_lut (unsigned int index, unsigned char r, unsigned char g, unsigned char b)
+void video_set_lut (unsigned int index, unsigned char r,
+ unsigned char g, unsigned char b)
{
- GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+ GraphicDevice *dev = &mb862xx;
L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
}
/*
* Drawing engine Fill and BitBlt screen region
*/
-void video_hw_rectfill (unsigned int bpp, unsigned int dst_x, unsigned int dst_y,
- unsigned int dim_x, unsigned int dim_y, unsigned int color)
+void video_hw_rectfill (unsigned int bpp, unsigned int dst_x,
+ unsigned int dst_y, unsigned int dim_x,
+ unsigned int dim_y, unsigned int color)
{
- GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+ GraphicDevice *dev = &mb862xx;
de_wait_slots (3);
- DE_WR_REG (0x0480, color);
+ DE_WR_REG (GC_FC, color);
DE_WR_FIFO (0x09410000);
DE_WR_FIFO ((dst_y << 16) | dst_x);
DE_WR_FIFO ((dim_y << 16) | dim_x);
de_wait ();
}
-void video_hw_bitblt (unsigned int bpp, unsigned int src_x, unsigned int src_y,
- unsigned int dst_x, unsigned int dst_y, unsigned int width,
+void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
+ unsigned int src_y, unsigned int dst_x,
+ unsigned int dst_y, unsigned int width,
unsigned int height)
{
- GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+ GraphicDevice *dev = &mb862xx;
unsigned int ctrl = 0x0d000000L;
if (src_x >= dst_x && src_y >= dst_y)
OUTPUT-$(CONFIG_API) = $(obj)demo
OUTPUT = $(OUTPUT-y)
-# Source files located in the api_examples directory
+# Source files located in the examples/api directory
SOBJ_FILES-$(CONFIG_API) += crt0.o
COBJ_FILES-$(CONFIG_API) += demo.o
COBJ_FILES-$(CONFIG_API) += glue.o
COBJ_FILES-$(CONFIG_API) += libgenwrap.o
-# Source files which exist outside the api_examples directory
+# Source files which exist outside the examples/api directory
EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/crc32.o
EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/ctype.o
+EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/div64.o
EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/string.o
EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/vsprintf.o
ifeq ($(ARCH),ppc)
# Create a list of source files so their dependencies can be auto-generated
SRCS += $(addprefix $(SRCTREE)/,$(EXT_COBJ_FILES-y:.o=.c))
SRCS += $(addprefix $(SRCTREE)/,$(EXT_SOBJ_FILES-y:.o=.S))
-SRCS += $(addprefix $(SRCTREE)/api_examples/,$(COBJ_FILES-y:.o=.c))
-SRCS += $(addprefix $(SRCTREE)/api_examples/,$(SOBJ_FILES-y:.o=.S))
+SRCS += $(addprefix $(SRCTREE)/examples/api/,$(COBJ_FILES-y:.o=.c))
+SRCS += $(addprefix $(SRCTREE)/examples/api/,$(SOBJ_FILES-y:.o=.S))
# Create a list of object files to be compiled
OBJS += $(addprefix $(obj),$(SOBJ_FILES-y))
uint32_t inode_table_id;
uint16_t free_blocks;
uint16_t free_inodes;
- uint16_t pad;
+ uint16_t used_dir_cnt;
uint32_t reserved[3];
};
static int ext2fs_blockgroup
(struct ext2_data *data, int group, struct ext2_block_group *blkgrp) {
+ unsigned int blkno;
+ unsigned int blkoff;
+ unsigned int desc_per_blk;
+
+ desc_per_blk = EXT2_BLOCK_SIZE(data) / sizeof(struct ext2_block_group);
+
+ blkno = __le32_to_cpu(data->sblock.first_data_block) + 1 +
+ group / desc_per_blk;
+ blkoff = (group % desc_per_blk) * sizeof(struct ext2_block_group);
#ifdef DEBUG
- printf ("ext2fs read blockgroup\n");
+ printf ("ext2fs read %d group descriptor (blkno %d blkoff %d)\n",
+ group, blkno, blkoff);
#endif
- return (ext2fs_devread
- (((__le32_to_cpu (data->sblock.first_data_block) +
- 1) << LOG2_EXT2_BLOCK_SIZE (data)),
- group * sizeof (struct ext2_block_group),
- sizeof (struct ext2_block_group), (char *) blkgrp));
+ return (ext2fs_devread (blkno << LOG2_EXT2_BLOCK_SIZE(data),
+ blkoff, sizeof(struct ext2_block_group), (char *)blkgrp));
+
}
unsigned int blkno;
unsigned int blkoff;
- /* It is easier to calculate if the first inode is 0. */
- ino--;
#ifdef DEBUG
printf ("ext2fs read inode %d\n", ino);
#endif
- status = ext2fs_blockgroup (data,
- ino /
- __le32_to_cpu (sblock->inodes_per_group),
- &blkgrp);
+ /* It is easier to calculate if the first inode is 0. */
+ ino--;
+ status = ext2fs_blockgroup (data, ino / __le32_to_cpu
+ (sblock->inodes_per_group), &blkgrp);
if (status == 0) {
return (0);
}
- inodes_per_block = EXT2_BLOCK_SIZE (data) / 128;
- blkno = (ino % __le32_to_cpu (sblock->inodes_per_group)) /
- inodes_per_block;
- blkoff = (ino % __le32_to_cpu (sblock->inodes_per_group)) %
- inodes_per_block;
+
+ inodes_per_block = EXT2_BLOCK_SIZE(data) / __le16_to_cpu(sblock->inode_size);
+
+#ifdef DEBUG
+ printf ("ext2fs read inode blkno %d blkoff %d\n", blkno, blkoff);
+#endif
+
+ blkno = __le32_to_cpu (blkgrp.inode_table_id) +
+ (ino % __le32_to_cpu (sblock->inodes_per_group))
+ / inodes_per_block;
+ blkoff = (ino % inodes_per_block) * __le16_to_cpu (sblock->inode_size);
#ifdef DEBUG
printf ("ext2fs read inode blkno %d blkoff %d\n", blkno, blkoff);
#endif
/* Read the inode. */
- status = ext2fs_devread (((__le32_to_cpu (blkgrp.inode_table_id) +
- blkno) << LOG2_EXT2_BLOCK_SIZE (data)),
- sizeof (struct ext2_inode) * blkoff,
+ status = ext2fs_devread (blkno << LOG2_EXT2_BLOCK_SIZE (data), blkoff,
sizeof (struct ext2_inode), (char *) inode);
if (status == 0) {
return (0);
}
+
return (1);
}
#if (defined(CONFIG_JFFS2_NAND) && \
defined(CONFIG_CMD_NAND) )
-#if defined(CONFIG_NAND_LEGACY)
-#include <linux/mtd/nand_legacy.h>
-#else
#include <nand.h>
-#endif
/*
* Support for jffs2 on top of NAND-flash
*
*
*/
-#if defined(CONFIG_NAND_LEGACY)
-/* this one defined in nand_legacy.c */
-int read_jffs2_nand(size_t start, size_t len,
- size_t * retlen, u_char * buf, int nanddev);
-#endif
-
#define NAND_PAGE_SIZE 512
#define NAND_PAGE_SHIFT 9
#define NAND_PAGE_MASK (~(NAND_PAGE_SIZE-1))
}
}
-#if defined(CONFIG_NAND_LEGACY)
- if (read_jffs2_nand(nand_cache_off, NAND_CACHE_SIZE,
- &retlen, nand_cache, id->num) < 0 ||
- retlen != NAND_CACHE_SIZE) {
- printf("read_nand_cached: error reading nand off %#x size %d bytes\n",
- nand_cache_off, NAND_CACHE_SIZE);
- return -1;
- }
-#else
retlen = NAND_CACHE_SIZE;
if (nand_read(&nand_info[id->num], nand_cache_off,
&retlen, nand_cache) != 0 ||
nand_cache_off, NAND_CACHE_SIZE);
return -1;
}
-#endif
}
cpy_bytes = nand_cache_off + NAND_CACHE_SIZE - (off + bytes_read);
if (cpy_bytes > size - bytes_read)
#include <common.h>
-#if !defined(CONFIG_NAND_LEGACY)
-
#include <malloc.h>
#include <linux/stat.h>
#include <linux/time.h>
}
return 1;
}
-
-#endif
/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
* Author: Jason Jin<Jason.jin@freescale.com>
* Zhang Wei<wei.zhang@freescale.com>
*
--- /dev/null
+/*
+ * arch/asm-arm/mach-kirkwood/include/mach/gpio.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/*
+ * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
+ * Removed kernel level irq handling. Took some macros from kernel to
+ * allow build.
+ *
+ * Dieter Kiermaier dk-arm-linux@gmx.de
+ */
+
+#ifndef __KIRKWOOD_GPIO_H
+#define __KIRKWOOD_GPIO_H
+
+/* got from kernel include/linux/kernel.h */
+#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
+/* got from kernel include/linux/bitops.h */
+#define BITS_PER_BYTE 8
+#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
+
+#define GPIO_MAX 50
+#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000)
+#define GPIO_OUT(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
+#define GPIO_IO_CONF(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
+#define GPIO_BLINK_EN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
+#define GPIO_IN_POL(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
+#define GPIO_DATA_IN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
+#define GPIO_EDGE_CAUSE(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
+#define GPIO_EDGE_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
+#define GPIO_LEVEL_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
+
+/*
+ * Kirkwood-specific GPIO API
+ */
+
+void kw_gpio_set_valid(unsigned pin, int mode);
+int kw_gpio_is_valid(unsigned pin, int mode);
+int kw_gpio_direction_input(unsigned pin);
+int kw_gpio_direction_output(unsigned pin, int value);
+int kw_gpio_get_value(unsigned pin);
+void kw_gpio_set_value(unsigned pin, int value);
+void kw_gpio_set_blink(unsigned pin, int blink);
+void kw_gpio_set_unused(unsigned pin);
+
+#define GPIO_INPUT_OK (1 << 0)
+#define GPIO_OUTPUT_OK (1 << 1)
+
+#endif
#define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470))
#define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478))
+#define KW_TWSI_BASE (KW_REGISTER(0x11000))
#define KW_UART0_BASE (KW_REGISTER(0x12000))
#define KW_UART1_BASE (KW_REGISTER(0x12100))
#define KW_MPP_BASE (KW_REGISTER(0x10000))
--- /dev/null
+/*
+ * (C) Copyright 2009 Alessandro Rubini
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __NMK_GPIO_H__
+#define __NMK_GPIO_H__
+
+/*
+ * These functions are called from the soft-i2c driver, but
+ * are also used by board files to set output bits.
+ */
+
+enum nmk_af { /* alternate function settings */
+ GPIO_GPIO = 0,
+ GPIO_ALT_A,
+ GPIO_ALT_B,
+ GPIO_ALT_C
+};
+
+extern void nmk_gpio_af(int gpio, int alternate_function);
+extern void nmk_gpio_dir(int gpio, int dir);
+extern void nmk_gpio_set(int gpio, int val);
+extern int nmk_gpio_get(int gpio);
+
+#endif /* __NMK_GPIO_H__ */
#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
+/* These values were copied from omap3, include/asm-arm/arch-omap3/i2c.h. */
+#define OMAP_I2C_STANDARD 100000
+#define OMAP_I2C_FAST_MODE 400000
+#define OMAP_I2C_HIGH_SPEED 3400000
+
+#define SYSTEM_CLOCK_12 12000000
+#define SYSTEM_CLOCK_13 13000000
+#define SYSTEM_CLOCK_192 19200000
+#define SYSTEM_CLOCK_96 96000000
+
+#ifndef I2C_IP_CLK
+#define I2C_IP_CLK SYSTEM_CLOCK_96
+#endif
+
+#ifndef I2C_INTERNAL_SAMPLING_CLK
+#define I2C_INTERNAL_SAMPLING_CLK 19200000
+#endif
+
+/* These are the trim values for standard and fast speed */
+#ifndef I2C_FASTSPEED_SCLL_TRIM
+#define I2C_FASTSPEED_SCLL_TRIM 6
+#endif
+#ifndef I2C_FASTSPEED_SCLH_TRIM
+#define I2C_FASTSPEED_SCLH_TRIM 6
+#endif
+
+/* These are the trim values for high speed */
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
+#endif
+
+#define I2C_PSC_MAX 0x0f
+#define I2C_PSC_MIN 0x00
+
+
#endif
#define I2C_SCLH_HSSCLH 8
#define I2C_SCLH_HSSCLH_M 0xFF
-#define OMAP_I2C_STANDARD 100
-#define OMAP_I2C_FAST_MODE 400
-#define OMAP_I2C_HIGH_SPEED 3400
+#define OMAP_I2C_STANDARD 100000
+#define OMAP_I2C_FAST_MODE 400000
+#define OMAP_I2C_HIGH_SPEED 3400000
-#define SYSTEM_CLOCK_12 12000
-#define SYSTEM_CLOCK_13 13000
-#define SYSTEM_CLOCK_192 19200
-#define SYSTEM_CLOCK_96 96000
+#define SYSTEM_CLOCK_12 12000000
+#define SYSTEM_CLOCK_13 13000000
+#define SYSTEM_CLOCK_192 19200000
+#define SYSTEM_CLOCK_96 96000000
+/* Use the reference value of 96MHz if not explicitly set by the board */
+#ifndef I2C_IP_CLK
#define I2C_IP_CLK SYSTEM_CLOCK_96
+#endif
+
+/*
+ * The reference minimum clock for high speed is 19.2MHz.
+ * The linux 2.6.30 kernel uses this value.
+ * The reference minimum clock for fast mode is 9.6MHz
+ * The reference minimum clock for standard mode is 4MHz
+ * In TRM, the value of 12MHz is used.
+ */
+#ifndef I2C_INTERNAL_SAMPLING_CLK
+#define I2C_INTERNAL_SAMPLING_CLK 19200000
+#endif
+
+/*
+ * The equation for the low and high time is
+ * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
+ * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
+ *
+ * If the duty cycle is 50%
+ *
+ * tlow = scll + scll_trim = sampling clock / (2 * speed)
+ * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
+ *
+ * In TRM
+ * scll_trim = 7
+ * sclh_trim = 5
+ *
+ * The linux 2.6.30 kernel uses
+ * scll_trim = 6
+ * sclh_trim = 6
+ *
+ * These are the trim values for standard and fast speed
+ */
+#ifndef I2C_FASTSPEED_SCLL_TRIM
+#define I2C_FASTSPEED_SCLL_TRIM 6
+#endif
+#ifndef I2C_FASTSPEED_SCLH_TRIM
+#define I2C_FASTSPEED_SCLH_TRIM 6
+#endif
+
+/* These are the trim values for high speed */
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
+#endif
+
#define I2C_PSC_MAX 0x0f
#define I2C_PSC_MIN 0x00
#define WIDTH_8BIT 0x0000
#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
-/* I2C power management companion definitions */
-#define PWRMGT_ADDR_ID1 0x48
-#define PWRMGT_ADDR_ID2 0x49
-#define PWRMGT_ADDR_ID3 0x4A
-#define PWRMGT_ADDR_ID4 0x4B
-
-/* I2C ID3 (slave3) register */
-#define LEDEN 0xEE
-
-#define LEDAON (0x1 << 0)
-#define LEDBON (0x1 << 1)
-#define LEDAPWM (0x1 << 4)
-#define LEDBPWM (0x1 << 5)
-
-/* I2C ID4 (slave4) register */
-#define VAUX2_DEV_GRP 0x76
-#define VAUX2_DEDICATED 0x79
-#define VAUX3_DEV_GRP 0x7A
-#define VAUX3_DEDICATED 0x7D
-#define VMMC1_DEV_GRP 0x82
-#define VMMC1_DEDICATED 0x85
-#define VPLL2_DEV_GRP 0x8E
-#define VPLL2_DEDICATED 0x91
-#define VDAC_DEV_GRP 0x96
-#define VDAC_DEDICATED 0x99
-
-#define DEV_GRP_P1 0x20
-#define DEV_GRP_ALL 0xE0
-
-#define VAUX2_VSEL_28 0x09
-#define VAUX3_VSEL_28 0x03
-#define VPLL2_VSEL_18 0x05
-#define VDAC_VSEL_18 0x03
-#define VMMC1_VSEL_30 0x02
-
#endif
#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
#define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3)
-#define GCDR(x) __REG2(0x40300420, ((x) & 0x60) >> 3)
+#define GCDR(x) __REG2(0x40E00420, ((x) & 0x60) >> 3)
/* Multi-funktion Pin Registers, uncomplete, only:
* - GPIO
-#ifndef _ARM_ERRNO_H
-#define _ARM_ERRNO_H
-
-#define EPERM 1 /* Operation not permitted */
-#define ENOENT 2 /* No such file or directory */
-#define ESRCH 3 /* No such process */
-#define EINTR 4 /* Interrupted system call */
-#define EIO 5 /* I/O error */
-#define ENXIO 6 /* No such device or address */
-#define E2BIG 7 /* Arg list too long */
-#define ENOEXEC 8 /* Exec format error */
-#define EBADF 9 /* Bad file number */
-#define ECHILD 10 /* No child processes */
-#define EAGAIN 11 /* Try again */
-#define ENOMEM 12 /* Out of memory */
-#define EACCES 13 /* Permission denied */
-#define EFAULT 14 /* Bad address */
-#define ENOTBLK 15 /* Block device required */
-#define EBUSY 16 /* Device or resource busy */
-#define EEXIST 17 /* File exists */
-#define EXDEV 18 /* Cross-device link */
-#define ENODEV 19 /* No such device */
-#define ENOTDIR 20 /* Not a directory */
-#define EISDIR 21 /* Is a directory */
-#define EINVAL 22 /* Invalid argument */
-#define ENFILE 23 /* File table overflow */
-#define EMFILE 24 /* Too many open files */
-#define ENOTTY 25 /* Not a typewriter */
-#define ETXTBSY 26 /* Text file busy */
-#define EFBIG 27 /* File too large */
-#define ENOSPC 28 /* No space left on device */
-#define ESPIPE 29 /* Illegal seek */
-#define EROFS 30 /* Read-only file system */
-#define EMLINK 31 /* Too many links */
-#define EPIPE 32 /* Broken pipe */
-#define EDOM 33 /* Math argument out of domain of func */
-#define ERANGE 34 /* Math result not representable */
-#define EDEADLK 35 /* Resource deadlock would occur */
-#define ENAMETOOLONG 36 /* File name too long */
-#define ENOLCK 37 /* No record locks available */
-#define ENOSYS 38 /* Function not implemented */
-#define ENOTEMPTY 39 /* Directory not empty */
-#define ELOOP 40 /* Too many symbolic links encountered */
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#define ENOMSG 42 /* No message of desired type */
-#define EIDRM 43 /* Identifier removed */
-#define ECHRNG 44 /* Channel number out of range */
-#define EL2NSYNC 45 /* Level 2 not synchronized */
-#define EL3HLT 46 /* Level 3 halted */
-#define EL3RST 47 /* Level 3 reset */
-#define ELNRNG 48 /* Link number out of range */
-#define EUNATCH 49 /* Protocol driver not attached */
-#define ENOCSI 50 /* No CSI structure available */
-#define EL2HLT 51 /* Level 2 halted */
-#define EBADE 52 /* Invalid exchange */
-#define EBADR 53 /* Invalid request descriptor */
-#define EXFULL 54 /* Exchange full */
-#define ENOANO 55 /* No anode */
-#define EBADRQC 56 /* Invalid request code */
-#define EBADSLT 57 /* Invalid slot */
-#define EDEADLOCK 58 /* File locking deadlock error */
-#define EBFONT 59 /* Bad font file format */
-#define ENOSTR 60 /* Device not a stream */
-#define ENODATA 61 /* No data available */
-#define ETIME 62 /* Timer expired */
-#define ENOSR 63 /* Out of streams resources */
-#define ENONET 64 /* Machine is not on the network */
-#define ENOPKG 65 /* Package not installed */
-#define EREMOTE 66 /* Object is remote */
-#define ENOLINK 67 /* Link has been severed */
-#define EADV 68 /* Advertise error */
-#define ESRMNT 69 /* Srmount error */
-#define ECOMM 70 /* Communication error on send */
-#define EPROTO 71 /* Protocol error */
-#define EMULTIHOP 72 /* Multihop attempted */
-#define EDOTDOT 73 /* RFS specific error */
-#define EBADMSG 74 /* Not a data message */
-#define EOVERFLOW 75 /* Value too large for defined data type */
-#define ENOTUNIQ 76 /* Name not unique on network */
-#define EBADFD 77 /* File descriptor in bad state */
-#define EREMCHG 78 /* Remote address changed */
-#define ELIBACC 79 /* Can not access a needed shared library */
-#define ELIBBAD 80 /* Accessing a corrupted shared library */
-#define ELIBSCN 81 /* .lib section in a.out corrupted */
-#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
-#define ELIBEXEC 83 /* Cannot exec a shared library directly */
-#define EILSEQ 84 /* Illegal byte sequence */
-#define ERESTART 85 /* Interrupted system call should be restarted */
-#define ESTRPIPE 86 /* Streams pipe error */
-#define EUSERS 87 /* Too many users */
-#define ENOTSOCK 88 /* Socket operation on non-socket */
-#define EDESTADDRREQ 89 /* Destination address required */
-#define EMSGSIZE 90 /* Message too long */
-#define EPROTOTYPE 91 /* Protocol wrong type for socket */
-#define ENOPROTOOPT 92 /* Protocol not available */
-#define EPROTONOSUPPORT 93 /* Protocol not supported */
-#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
-#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
-#define EADDRINUSE 98 /* Address already in use */
-#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
-#define ENETDOWN 100 /* Network is down */
-#define ENETUNREACH 101 /* Network is unreachable */
-#define ENETRESET 102 /* Network dropped connection because of reset */
-#define ECONNABORTED 103 /* Software caused connection abort */
-#define ECONNRESET 104 /* Connection reset by peer */
-#define ENOBUFS 105 /* No buffer space available */
-#define EISCONN 106 /* Transport endpoint is already connected */
-#define ENOTCONN 107 /* Transport endpoint is not connected */
-#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS 109 /* Too many references: cannot splice */
-#define ETIMEDOUT 110 /* Connection timed out */
-#define ECONNREFUSED 111 /* Connection refused */
-#define EHOSTDOWN 112 /* Host is down */
-#define EHOSTUNREACH 113 /* No route to host */
-#define EALREADY 114 /* Operation already in progress */
-#define EINPROGRESS 115 /* Operation now in progress */
-#define ESTALE 116 /* Stale NFS file handle */
-#define EUCLEAN 117 /* Structure needs cleaning */
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#define EISNAM 120 /* Is a named type file */
-#define EREMOTEIO 121 /* Remote I/O error */
-#define EDQUOT 122 /* Quota exceeded */
-
-#define ENOMEDIUM 123 /* No medium found */
-#define EMEDIUMTYPE 124 /* Wrong medium type */
-
-/* Should never be seen by user programs */
-#define ERESTARTSYS 512
-#define ERESTARTNOINTR 513
-#define ERESTARTNOHAND 514 /* restart if no handler.. */
-#define ENOIOCTLCMD 515 /* No ioctl command */
-
-#define _LAST_ERRNO 515
-
-#endif
+#include <asm-generic/errno.h>
--- /dev/null
+#ifndef _ASM_ARM_UNALIGNED_H
+#define _ASM_ARM_UNALIGNED_H
+
+#include <linux/unaligned/access_ok.h>
+#include <linux/unaligned/generic.h>
+
+/*
+ * Select endianness
+ */
+#ifndef __ARMEB__
+#define get_unaligned __get_unaligned_le
+#define put_unaligned __put_unaligned_le
+#else
+#define get_unaligned __get_unaligned_be
+#define put_unaligned __put_unaligned_be
+#endif
+
+#endif /* _ASM_ARM_UNALIGNED_H */
#define AT32AP700x_CHIP_HAS_MACB
#endif
+/* AP7000 and AP7002 have LCD controller, but AP7001 does not */
+#if defined(CONFIG_AT32AP7000) || defined(CONFIG_AT32AP7002)
+#define AT32AP700x_CHIP_HAS_LCDC
+#endif
+
#endif /* __ASM_AVR32_ARCH_CHIP_FEATURES_H__ */
return get_pba_clk_rate();
}
#endif
+#ifdef AT32AP700x_CHIP_HAS_LCDC
+static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
+{
+ return get_hsb_clk_rate();
+}
+#endif
extern void clk_init(void);
void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength);
void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength);
#endif
+#ifdef AT32AP700x_CHIP_HAS_LCDC
+void portmux_enable_lcdc(int pin_config);
+#endif
#endif /* __ASM_AVR32_ARCH_PORTMUX_H__ */
-#ifndef _ASM_AVR32_ERRNO_H
-#define _ASM_AVR32_ERRNO_H
-
-#define EPERM 1 /* Operation not permitted */
-#define ENOENT 2 /* No such file or directory */
-#define ESRCH 3 /* No such process */
-#define EINTR 4 /* Interrupted system call */
-#define EIO 5 /* I/O error */
-#define ENXIO 6 /* No such device or address */
-#define E2BIG 7 /* Argument list too long */
-#define ENOEXEC 8 /* Exec format error */
-#define EBADF 9 /* Bad file number */
-#define ECHILD 10 /* No child processes */
-#define EAGAIN 11 /* Try again */
-#define ENOMEM 12 /* Out of memory */
-#define EACCES 13 /* Permission denied */
-#define EFAULT 14 /* Bad address */
-#define ENOTBLK 15 /* Block device required */
-#define EBUSY 16 /* Device or resource busy */
-#define EEXIST 17 /* File exists */
-#define EXDEV 18 /* Cross-device link */
-#define ENODEV 19 /* No such device */
-#define ENOTDIR 20 /* Not a directory */
-#define EISDIR 21 /* Is a directory */
-#define EINVAL 22 /* Invalid argument */
-#define ENFILE 23 /* File table overflow */
-#define EMFILE 24 /* Too many open files */
-#define ENOTTY 25 /* Not a typewriter */
-#define ETXTBSY 26 /* Text file busy */
-#define EFBIG 27 /* File too large */
-#define ENOSPC 28 /* No space left on device */
-#define ESPIPE 29 /* Illegal seek */
-#define EROFS 30 /* Read-only file system */
-#define EMLINK 31 /* Too many links */
-#define EPIPE 32 /* Broken pipe */
-#define EDOM 33 /* Math argument out of domain of func */
-#define ERANGE 34 /* Math result not representable */
-#define EDEADLK 35 /* Resource deadlock would occur */
-#define ENAMETOOLONG 36 /* File name too long */
-#define ENOLCK 37 /* No record locks available */
-#define ENOSYS 38 /* Function not implemented */
-#define ENOTEMPTY 39 /* Directory not empty */
-#define ELOOP 40 /* Too many symbolic links encountered */
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#define ENOMSG 42 /* No message of desired type */
-#define EIDRM 43 /* Identifier removed */
-#define ECHRNG 44 /* Channel number out of range */
-#define EL2NSYNC 45 /* Level 2 not synchronized */
-#define EL3HLT 46 /* Level 3 halted */
-#define EL3RST 47 /* Level 3 reset */
-#define ELNRNG 48 /* Link number out of range */
-#define EUNATCH 49 /* Protocol driver not attached */
-#define ENOCSI 50 /* No CSI structure available */
-#define EL2HLT 51 /* Level 2 halted */
-#define EBADE 52 /* Invalid exchange */
-#define EBADR 53 /* Invalid request descriptor */
-#define EXFULL 54 /* Exchange full */
-#define ENOANO 55 /* No anode */
-#define EBADRQC 56 /* Invalid request code */
-#define EBADSLT 57 /* Invalid slot */
-
-#define EDEADLOCK EDEADLK
-
-#define EBFONT 59 /* Bad font file format */
-#define ENOSTR 60 /* Device not a stream */
-#define ENODATA 61 /* No data available */
-#define ETIME 62 /* Timer expired */
-#define ENOSR 63 /* Out of streams resources */
-#define ENONET 64 /* Machine is not on the network */
-#define ENOPKG 65 /* Package not installed */
-#define EREMOTE 66 /* Object is remote */
-#define ENOLINK 67 /* Link has been severed */
-#define EADV 68 /* Advertise error */
-#define ESRMNT 69 /* Srmount error */
-#define ECOMM 70 /* Communication error on send */
-#define EPROTO 71 /* Protocol error */
-#define EMULTIHOP 72 /* Multihop attempted */
-#define EDOTDOT 73 /* RFS specific error */
-#define EBADMSG 74 /* Not a data message */
-#define EOVERFLOW 75 /* Value too large for defined data type */
-#define ENOTUNIQ 76 /* Name not unique on network */
-#define EBADFD 77 /* File descriptor in bad state */
-#define EREMCHG 78 /* Remote address changed */
-#define ELIBACC 79 /* Can not access a needed shared library */
-#define ELIBBAD 80 /* Accessing a corrupted shared library */
-#define ELIBSCN 81 /* .lib section in a.out corrupted */
-#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
-#define ELIBEXEC 83 /* Cannot exec a shared library directly */
-#define EILSEQ 84 /* Illegal byte sequence */
-#define ERESTART 85 /* Interrupted system call should be restarted */
-#define ESTRPIPE 86 /* Streams pipe error */
-#define EUSERS 87 /* Too many users */
-#define ENOTSOCK 88 /* Socket operation on non-socket */
-#define EDESTADDRREQ 89 /* Destination address required */
-#define EMSGSIZE 90 /* Message too long */
-#define EPROTOTYPE 91 /* Protocol wrong type for socket */
-#define ENOPROTOOPT 92 /* Protocol not available */
-#define EPROTONOSUPPORT 93 /* Protocol not supported */
-#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
-#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
-#define EADDRINUSE 98 /* Address already in use */
-#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
-#define ENETDOWN 100 /* Network is down */
-#define ENETUNREACH 101 /* Network is unreachable */
-#define ENETRESET 102 /* Network dropped connection because of reset */
-#define ECONNABORTED 103 /* Software caused connection abort */
-#define ECONNRESET 104 /* Connection reset by peer */
-#define ENOBUFS 105 /* No buffer space available */
-#define EISCONN 106 /* Transport endpoint is already connected */
-#define ENOTCONN 107 /* Transport endpoint is not connected */
-#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS 109 /* Too many references: cannot splice */
-#define ETIMEDOUT 110 /* Connection timed out */
-#define ECONNREFUSED 111 /* Connection refused */
-#define EHOSTDOWN 112 /* Host is down */
-#define EHOSTUNREACH 113 /* No route to host */
-#define EALREADY 114 /* Operation already in progress */
-#define EINPROGRESS 115 /* Operation now in progress */
-#define ESTALE 116 /* Stale NFS file handle */
-#define EUCLEAN 117 /* Structure needs cleaning */
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#define EISNAM 120 /* Is a named type file */
-#define EREMOTEIO 121 /* Remote I/O error */
-#define EDQUOT 122 /* Quota exceeded */
-
-#define ENOMEDIUM 123 /* No medium found */
-#define EMEDIUMTYPE 124 /* Wrong medium type */
-
-#endif /* _ASM_AVR32_ERRNO_H */
+#include <asm-generic/errno.h>
unsigned long env_addr; /* Address of env struct */
unsigned long env_valid; /* Checksum of env valid? */
unsigned long cpu_hz; /* cpu core clock frequency */
+#if defined(CONFIG_LCD)
+ void *fb_base; /* framebuffer address */
+#endif
void **jt; /* jump table */
} gd_t;
# define bfin_revid() (*pCHIPID >> 28)
+extern bool bfin_os_log_check(void);
+extern void bfin_os_log_dump(void);
+
extern void blackfin_icache_flush_range(const void *, const void *);
extern void blackfin_dcache_flush_range(const void *, const void *);
extern void blackfin_icache_dcache_flush_range(const void *, const void *);
-/*
- * U-boot - errno.h Error number defines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _BLACKFIN_ERRNO_H
-#define _BLACKFIN_ERRNO_H
-
-#define EPERM 1 /* Operation not permitted */
-#define ENOENT 2 /* No such file or directory */
-#define ESRCH 3 /* No such process */
-#define EINTR 4 /* Interrupted system call */
-#define EIO 5 /* I/O error */
-#define ENXIO 6 /* No such device or address */
-#define E2BIG 7 /* Arg list too long */
-#define ENOEXEC 8 /* Exec format error */
-#define EBADF 9 /* Bad file number */
-#define ECHILD 10 /* No child processes */
-#define EAGAIN 11 /* Try again */
-#define ENOMEM 12 /* Out of memory */
-#define EACCES 13 /* Permission denied */
-#define EFAULT 14 /* Bad address */
-#define ENOTBLK 15 /* Block device required */
-#define EBUSY 16 /* Device or resource busy */
-#define EEXIST 17 /* File exists */
-#define EXDEV 18 /* Cross-device link */
-#define ENODEV 19 /* No such device */
-#define ENOTDIR 20 /* Not a directory */
-#define EISDIR 21 /* Is a directory */
-#define EINVAL 22 /* Invalid argument */
-#define ENFILE 23 /* File table overflow */
-#define EMFILE 24 /* Too many open files */
-#define ENOTTY 25 /* Not a typewriter */
-#define ETXTBSY 26 /* Text file busy */
-#define EFBIG 27 /* File too large */
-#define ENOSPC 28 /* No space left on device */
-#define ESPIPE 29 /* Illegal seek */
-#define EROFS 30 /* Read-only file system */
-#define EMLINK 31 /* Too many links */
-#define EPIPE 32 /* Broken pipe */
-#define EDOM 33 /* Math argument out of domain of func */
-#define ERANGE 34 /* Math result not representable */
-#define EDEADLK 35 /* Resource deadlock would occur */
-#define ENAMETOOLONG 36 /* File name too long */
-#define ENOLCK 37 /* No record locks available */
-#define ENOSYS 38 /* Function not implemented */
-#define ENOTEMPTY 39 /* Directory not empty */
-#define ELOOP 40 /* Too many symbolic links encountered */
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#define ENOMSG 42 /* No message of desired type */
-#define EIDRM 43 /* Identifier removed */
-#define ECHRNG 44 /* Channel number out of range */
-#define EL2NSYNC 45 /* Level 2 not synchronized */
-#define EL3HLT 46 /* Level 3 halted */
-#define EL3RST 47 /* Level 3 reset */
-#define ELNRNG 48 /* Link number out of range */
-#define EUNATCH 49 /* Protocol driver not attached */
-#define ENOCSI 50 /* No CSI structure available */
-#define EL2HLT 51 /* Level 2 halted */
-#define EBADE 52 /* Invalid exchange */
-#define EBADR 53 /* Invalid request descriptor */
-#define EXFULL 54 /* Exchange full */
-#define ENOANO 55 /* No anode */
-#define EBADRQC 56 /* Invalid request code */
-#define EBADSLT 57 /* Invalid slot */
-
-#define EDEADLOCK EDEADLK
-
-#define EBFONT 59 /* Bad font file format */
-#define ENOSTR 60 /* Device not a stream */
-#define ENODATA 61 /* No data available */
-#define ETIME 62 /* Timer expired */
-#define ENOSR 63 /* Out of streams resources */
-#define ENONET 64 /* Machine is not on the network */
-#define ENOPKG 65 /* Package not installed */
-#define EREMOTE 66 /* Object is remote */
-#define ENOLINK 67 /* Link has been severed */
-#define EADV 68 /* Advertise error */
-#define ESRMNT 69 /* Srmount error */
-#define ECOMM 70 /* Communication error on send */
-#define EPROTO 71 /* Protocol error */
-#define EMULTIHOP 72 /* Multihop attempted */
-#define EDOTDOT 73 /* RFS specific error */
-#define EBADMSG 74 /* Not a data message */
-#define EOVERFLOW 75 /* Value too large for defined data type */
-#define ENOTUNIQ 76 /* Name not unique on network */
-#define EBADFD 77 /* File descriptor in bad state */
-#define EREMCHG 78 /* Remote address changed */
-#define ELIBACC 79 /* Can not access a needed shared library */
-#define ELIBBAD 80 /* Accessing a corrupted shared library */
-#define ELIBSCN 81 /* .lib section in a.out corrupted */
-#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
-#define ELIBEXEC 83 /* Cannot exec a shared library directly */
-#define EILSEQ 84 /* Illegal byte sequence */
-#define ERESTART 85 /* Interrupted system call should be restarted */
-#define ESTRPIPE 86 /* Streams pipe error */
-#define EUSERS 87 /* Too many users */
-#define ENOTSOCK 88 /* Socket operation on non-socket */
-#define EDESTADDRREQ 89 /* Destination address required */
-#define EMSGSIZE 90 /* Message too long */
-#define EPROTOTYPE 91 /* Protocol wrong type for socket */
-#define ENOPROTOOPT 92 /* Protocol not available */
-#define EPROTONOSUPPORT 93 /* Protocol not supported */
-#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
-#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
-#define EADDRINUSE 98 /* Address already in use */
-#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
-#define ENETDOWN 100 /* Network is down */
-#define ENETUNREACH 101 /* Network is unreachable */
-#define ENETRESET 102 /* Network dropped connection because of reset */
-#define ECONNABORTED 103 /* Software caused connection abort */
-#define ECONNRESET 104 /* Connection reset by peer */
-#define ENOBUFS 105 /* No buffer space available */
-#define EISCONN 106 /* Transport endpoint is already connected */
-#define ENOTCONN 107 /* Transport endpoint is not connected */
-#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS 109 /* Too many references: cannot splice */
-#define ETIMEDOUT 110 /* Connection timed out */
-#define ECONNREFUSED 111 /* Connection refused */
-#define EHOSTDOWN 112 /* Host is down */
-#define EHOSTUNREACH 113 /* No route to host */
-#define EALREADY 114 /* Operation already in progress */
-#define EINPROGRESS 115 /* Operation now in progress */
-#define ESTALE 116 /* Stale NFS file handle */
-#define EUCLEAN 117 /* Structure needs cleaning */
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#define EISNAM 120 /* Is a named type file */
-#define EREMOTEIO 121 /* Remote I/O error */
-#define EDQUOT 122 /* Quota exceeded */
-
-#define ENOMEDIUM 123 /* No medium found */
-#define EMEDIUMTYPE 124 /* Wrong medium type */
-
-#endif
+#include <asm-generic/errno.h>
/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
+ * U-boot - errno.h Error number defines
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
-/*
- * BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus
- */
-#ifndef _MV_PPC_ERRNO_H
-#define _MV_PPC_ERRNO_H
+#ifndef _GENERIC_ERRNO_H
+#define _GENERIC_ERRNO_H
-#define EPERM 1 /* Operation not permitted */
-#define ENOENT 2 /* No such file or directory */
-#define ESRCH 3 /* No such process */
-#define EINTR 4 /* Interrupted system call */
-#define EIO 5 /* I/O error */
-#define ENXIO 6 /* No such device or address */
-#define E2BIG 7 /* Arg list too long */
-#define ENOEXEC 8 /* Exec format error */
-#define EBADF 9 /* Bad file number */
+#define EPERM 1 /* Operation not permitted */
+#define ENOENT 2 /* No such file or directory */
+#define ESRCH 3 /* No such process */
+#define EINTR 4 /* Interrupted system call */
+#define EIO 5 /* I/O error */
+#define ENXIO 6 /* No such device or address */
+#define E2BIG 7 /* Argument list too long */
+#define ENOEXEC 8 /* Exec format error */
+#define EBADF 9 /* Bad file number */
#define ECHILD 10 /* No child processes */
#define EAGAIN 11 /* Try again */
#define ENOMEM 12 /* Out of memory */
#define ENOANO 55 /* No anode */
#define EBADRQC 56 /* Invalid request code */
#define EBADSLT 57 /* Invalid slot */
-#define EDEADLOCK 58 /* File locking deadlock error */
+
+#define EDEADLOCK EDEADLK
+
#define EBFONT 59 /* Bad font file format */
#define ENOSTR 60 /* Device not a stream */
#define ENODATA 61 /* No data available */
#define EISNAM 120 /* Is a named type file */
#define EREMOTEIO 121 /* Remote I/O error */
#define EDQUOT 122 /* Quota exceeded */
-
#define ENOMEDIUM 123 /* No medium found */
#define EMEDIUMTYPE 124 /* Wrong medium type */
-/* Should never be seen by user programs */
-#define ERESTARTSYS 512
-#define ERESTARTNOINTR 513
-#define ERESTARTNOHAND 514 /* restart if no handler.. */
-#define ENOIOCTLCMD 515 /* No ioctl command */
-
-#define _LAST_ERRNO 515
-
#endif
-#ifndef _PPC_ERRNO_H
-#define _PPC_ERRNO_H
-
-#define EPERM 1 /* Operation not permitted */
-#define ENOENT 2 /* No such file or directory */
-#define ESRCH 3 /* No such process */
-#define EINTR 4 /* Interrupted system call */
-#define EIO 5 /* I/O error */
-#define ENXIO 6 /* No such device or address */
-#define E2BIG 7 /* Arg list too long */
-#define ENOEXEC 8 /* Exec format error */
-#define EBADF 9 /* Bad file number */
-#define ECHILD 10 /* No child processes */
-#define EAGAIN 11 /* Try again */
-#define ENOMEM 12 /* Out of memory */
-#define EACCES 13 /* Permission denied */
-#define EFAULT 14 /* Bad address */
-#define ENOTBLK 15 /* Block device required */
-#define EBUSY 16 /* Device or resource busy */
-#define EEXIST 17 /* File exists */
-#define EXDEV 18 /* Cross-device link */
-#define ENODEV 19 /* No such device */
-#define ENOTDIR 20 /* Not a directory */
-#define EISDIR 21 /* Is a directory */
-#define EINVAL 22 /* Invalid argument */
-#define ENFILE 23 /* File table overflow */
-#define EMFILE 24 /* Too many open files */
-#define ENOTTY 25 /* Not a typewriter */
-#define ETXTBSY 26 /* Text file busy */
-#define EFBIG 27 /* File too large */
-#define ENOSPC 28 /* No space left on device */
-#define ESPIPE 29 /* Illegal seek */
-#define EROFS 30 /* Read-only file system */
-#define EMLINK 31 /* Too many links */
-#define EPIPE 32 /* Broken pipe */
-#define EDOM 33 /* Math argument out of domain of func */
-#define ERANGE 34 /* Math result not representable */
-#define EDEADLK 35 /* Resource deadlock would occur */
-#define ENAMETOOLONG 36 /* File name too long */
-#define ENOLCK 37 /* No record locks available */
-#define ENOSYS 38 /* Function not implemented */
-#define ENOTEMPTY 39 /* Directory not empty */
-#define ELOOP 40 /* Too many symbolic links encountered */
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#define ENOMSG 42 /* No message of desired type */
-#define EIDRM 43 /* Identifier removed */
-#define ECHRNG 44 /* Channel number out of range */
-#define EL2NSYNC 45 /* Level 2 not synchronized */
-#define EL3HLT 46 /* Level 3 halted */
-#define EL3RST 47 /* Level 3 reset */
-#define ELNRNG 48 /* Link number out of range */
-#define EUNATCH 49 /* Protocol driver not attached */
-#define ENOCSI 50 /* No CSI structure available */
-#define EL2HLT 51 /* Level 2 halted */
-#define EBADE 52 /* Invalid exchange */
-#define EBADR 53 /* Invalid request descriptor */
-#define EXFULL 54 /* Exchange full */
-#define ENOANO 55 /* No anode */
-#define EBADRQC 56 /* Invalid request code */
-#define EBADSLT 57 /* Invalid slot */
-#define EDEADLOCK 58 /* File locking deadlock error */
-#define EBFONT 59 /* Bad font file format */
-#define ENOSTR 60 /* Device not a stream */
-#define ENODATA 61 /* No data available */
-#define ETIME 62 /* Timer expired */
-#define ENOSR 63 /* Out of streams resources */
-#define ENONET 64 /* Machine is not on the network */
-#define ENOPKG 65 /* Package not installed */
-#define EREMOTE 66 /* Object is remote */
-#define ENOLINK 67 /* Link has been severed */
-#define EADV 68 /* Advertise error */
-#define ESRMNT 69 /* Srmount error */
-#define ECOMM 70 /* Communication error on send */
-#define EPROTO 71 /* Protocol error */
-#define EMULTIHOP 72 /* Multihop attempted */
-#define EDOTDOT 73 /* RFS specific error */
-#define EBADMSG 74 /* Not a data message */
-#define EOVERFLOW 75 /* Value too large for defined data type */
-#define ENOTUNIQ 76 /* Name not unique on network */
-#define EBADFD 77 /* File descriptor in bad state */
-#define EREMCHG 78 /* Remote address changed */
-#define ELIBACC 79 /* Can not access a needed shared library */
-#define ELIBBAD 80 /* Accessing a corrupted shared library */
-#define ELIBSCN 81 /* .lib section in a.out corrupted */
-#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
-#define ELIBEXEC 83 /* Cannot exec a shared library directly */
-#define EILSEQ 84 /* Illegal byte sequence */
-#define ERESTART 85 /* Interrupted system call should be restarted */
-#define ESTRPIPE 86 /* Streams pipe error */
-#define EUSERS 87 /* Too many users */
-#define ENOTSOCK 88 /* Socket operation on non-socket */
-#define EDESTADDRREQ 89 /* Destination address required */
-#define EMSGSIZE 90 /* Message too long */
-#define EPROTOTYPE 91 /* Protocol wrong type for socket */
-#define ENOPROTOOPT 92 /* Protocol not available */
-#define EPROTONOSUPPORT 93 /* Protocol not supported */
-#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
-#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
-#define EADDRINUSE 98 /* Address already in use */
-#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
-#define ENETDOWN 100 /* Network is down */
-#define ENETUNREACH 101 /* Network is unreachable */
-#define ENETRESET 102 /* Network dropped connection because of reset */
-#define ECONNABORTED 103 /* Software caused connection abort */
-#define ECONNRESET 104 /* Connection reset by peer */
-#define ENOBUFS 105 /* No buffer space available */
-#define EISCONN 106 /* Transport endpoint is already connected */
-#define ENOTCONN 107 /* Transport endpoint is not connected */
-#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS 109 /* Too many references: cannot splice */
-#define ETIMEDOUT 110 /* Connection timed out */
-#define ECONNREFUSED 111 /* Connection refused */
-#define EHOSTDOWN 112 /* Host is down */
-#define EHOSTUNREACH 113 /* No route to host */
-#define EALREADY 114 /* Operation already in progress */
-#define EINPROGRESS 115 /* Operation now in progress */
-#define ESTALE 116 /* Stale NFS file handle */
-#define EUCLEAN 117 /* Structure needs cleaning */
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#define EISNAM 120 /* Is a named type file */
-#define EREMOTEIO 121 /* Remote I/O error */
-#define EDQUOT 122 /* Quota exceeded */
-
-#define ENOMEDIUM 123 /* No medium found */
-#define EMEDIUMTYPE 124 /* Wrong medium type */
-
-/* Should never be seen by user programs */
-#define ERESTARTSYS 512
-#define ERESTARTNOINTR 513
-#define ERESTARTNOHAND 514 /* restart if no handler.. */
-#define ENOIOCTLCMD 515 /* No ioctl command */
-
-#define _LAST_ERRNO 515
-
-#endif
+#include <asm-generic/errno.h>
I think this is a symptom of a bug in mb-gcc. JW 20040303
*/
-static __inline__ __const__ __u16 ___arch__swab16 (__u16 half_word)
+
+
+static __inline__ __u16 ___arch__swab16 (__u16 half_word)
{
/* 32 bit temp to cast result, forcing clearing of high word */
__u32 temp;
--- /dev/null
+#include <asm-generic/errno.h>
#endif
#endif
-#ifndef CONFIG_FSL_DMA
-#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \
- !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \
- (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
+/* Check if boards need to enable FSL DMA engine for SDRAM init */
+#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
+#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
+ ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
+ !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
#define CONFIG_FSL_DMA
#endif
#endif
-#ifndef _PPC_ERRNO_H
-#define _PPC_ERRNO_H
-
-#define EPERM 1 /* Operation not permitted */
-#define ENOENT 2 /* No such file or directory */
-#define ESRCH 3 /* No such process */
-#define EINTR 4 /* Interrupted system call */
-#define EIO 5 /* I/O error */
-#define ENXIO 6 /* No such device or address */
-#define E2BIG 7 /* Arg list too long */
-#define ENOEXEC 8 /* Exec format error */
-#define EBADF 9 /* Bad file number */
-#define ECHILD 10 /* No child processes */
-#define EAGAIN 11 /* Try again */
-#define ENOMEM 12 /* Out of memory */
-#define EACCES 13 /* Permission denied */
-#define EFAULT 14 /* Bad address */
-#define ENOTBLK 15 /* Block device required */
-#define EBUSY 16 /* Device or resource busy */
-#define EEXIST 17 /* File exists */
-#define EXDEV 18 /* Cross-device link */
-#define ENODEV 19 /* No such device */
-#define ENOTDIR 20 /* Not a directory */
-#define EISDIR 21 /* Is a directory */
-#define EINVAL 22 /* Invalid argument */
-#define ENFILE 23 /* File table overflow */
-#define EMFILE 24 /* Too many open files */
-#define ENOTTY 25 /* Not a typewriter */
-#define ETXTBSY 26 /* Text file busy */
-#define EFBIG 27 /* File too large */
-#define ENOSPC 28 /* No space left on device */
-#define ESPIPE 29 /* Illegal seek */
-#define EROFS 30 /* Read-only file system */
-#define EMLINK 31 /* Too many links */
-#define EPIPE 32 /* Broken pipe */
-#define EDOM 33 /* Math argument out of domain of func */
-#define ERANGE 34 /* Math result not representable */
-#define EDEADLK 35 /* Resource deadlock would occur */
-#define ENAMETOOLONG 36 /* File name too long */
-#define ENOLCK 37 /* No record locks available */
-#define ENOSYS 38 /* Function not implemented */
-#define ENOTEMPTY 39 /* Directory not empty */
-#define ELOOP 40 /* Too many symbolic links encountered */
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#define ENOMSG 42 /* No message of desired type */
-#define EIDRM 43 /* Identifier removed */
-#define ECHRNG 44 /* Channel number out of range */
-#define EL2NSYNC 45 /* Level 2 not synchronized */
-#define EL3HLT 46 /* Level 3 halted */
-#define EL3RST 47 /* Level 3 reset */
-#define ELNRNG 48 /* Link number out of range */
-#define EUNATCH 49 /* Protocol driver not attached */
-#define ENOCSI 50 /* No CSI structure available */
-#define EL2HLT 51 /* Level 2 halted */
-#define EBADE 52 /* Invalid exchange */
-#define EBADR 53 /* Invalid request descriptor */
-#define EXFULL 54 /* Exchange full */
-#define ENOANO 55 /* No anode */
-#define EBADRQC 56 /* Invalid request code */
-#define EBADSLT 57 /* Invalid slot */
-#define EDEADLOCK 58 /* File locking deadlock error */
-#define EBFONT 59 /* Bad font file format */
-#define ENOSTR 60 /* Device not a stream */
-#define ENODATA 61 /* No data available */
-#define ETIME 62 /* Timer expired */
-#define ENOSR 63 /* Out of streams resources */
-#define ENONET 64 /* Machine is not on the network */
-#define ENOPKG 65 /* Package not installed */
-#define EREMOTE 66 /* Object is remote */
-#define ENOLINK 67 /* Link has been severed */
-#define EADV 68 /* Advertise error */
-#define ESRMNT 69 /* Srmount error */
-#define ECOMM 70 /* Communication error on send */
-#define EPROTO 71 /* Protocol error */
-#define EMULTIHOP 72 /* Multihop attempted */
-#define EDOTDOT 73 /* RFS specific error */
-#define EBADMSG 74 /* Not a data message */
-#define EOVERFLOW 75 /* Value too large for defined data type */
-#define ENOTUNIQ 76 /* Name not unique on network */
-#define EBADFD 77 /* File descriptor in bad state */
-#define EREMCHG 78 /* Remote address changed */
-#define ELIBACC 79 /* Can not access a needed shared library */
-#define ELIBBAD 80 /* Accessing a corrupted shared library */
-#define ELIBSCN 81 /* .lib section in a.out corrupted */
-#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
-#define ELIBEXEC 83 /* Cannot exec a shared library directly */
-#define EILSEQ 84 /* Illegal byte sequence */
-#define ERESTART 85 /* Interrupted system call should be restarted */
-#define ESTRPIPE 86 /* Streams pipe error */
-#define EUSERS 87 /* Too many users */
-#define ENOTSOCK 88 /* Socket operation on non-socket */
-#define EDESTADDRREQ 89 /* Destination address required */
-#define EMSGSIZE 90 /* Message too long */
-#define EPROTOTYPE 91 /* Protocol wrong type for socket */
-#define ENOPROTOOPT 92 /* Protocol not available */
-#define EPROTONOSUPPORT 93 /* Protocol not supported */
-#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
-#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
-#define EADDRINUSE 98 /* Address already in use */
-#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
-#define ENETDOWN 100 /* Network is down */
-#define ENETUNREACH 101 /* Network is unreachable */
-#define ENETRESET 102 /* Network dropped connection because of reset */
-#define ECONNABORTED 103 /* Software caused connection abort */
-#define ECONNRESET 104 /* Connection reset by peer */
-#define ENOBUFS 105 /* No buffer space available */
-#define EISCONN 106 /* Transport endpoint is already connected */
-#define ENOTCONN 107 /* Transport endpoint is not connected */
-#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS 109 /* Too many references: cannot splice */
-#define ETIMEDOUT 110 /* Connection timed out */
-#define ECONNREFUSED 111 /* Connection refused */
-#define EHOSTDOWN 112 /* Host is down */
-#define EHOSTUNREACH 113 /* No route to host */
-#define EALREADY 114 /* Operation already in progress */
-#define EINPROGRESS 115 /* Operation now in progress */
-#define ESTALE 116 /* Stale NFS file handle */
-#define EUCLEAN 117 /* Structure needs cleaning */
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#define EISNAM 120 /* Is a named type file */
-#define EREMOTEIO 121 /* Remote I/O error */
-#define EDQUOT 122 /* Quota exceeded */
-
-#define ENOMEDIUM 123 /* No medium found */
-#define EMEDIUMTYPE 124 /* Wrong medium type */
-
-/* Should never be seen by user programs */
-#define ERESTARTSYS 512
-#define ERESTARTNOINTR 513
-#define ERESTARTNOHAND 514 /* restart if no handler.. */
-#define ENOIOCTLCMD 515 /* No ioctl command */
-
-#define _LAST_ERRNO 515
-
-#endif
+#include <asm-generic/errno.h>
#ifndef __ASM_PPC_GPIO_H
#define __ASM_PPC_GPIO_H
+#include <asm/types.h>
+
/* 4xx PPC's have 2 GPIO controllers */
#if defined(CONFIG_405EZ) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
#define GPIO_GROUP_MAX 1
#endif
+/* GPIO controller */
+struct ppc4xx_gpio {
+ u32 or; /* Output Control */
+ u32 tcr; /* Tri-State Control */
+ u32 osl; /* Output Select 16..31 */
+ u32 osh; /* Output Select 0..15 */
+ u32 tsl; /* Tri-State Select 16..31 */
+ u32 tsh; /* Tri-State Select 0..15 */
+ u32 odr; /* Open Drain */
+ u32 ir; /* Input */
+ u32 rr1; /* Receive Register 1 */
+ u32 rr2; /* Receive Register 2 */
+ u32 rr3; /* Receive Register 3 */
+ u32 reserved;
+ u32 is1l; /* Input Select 1 16..31 */
+ u32 is1h; /* Input Select 1 0..15 */
+ u32 is2l; /* Input Select 2 16..31 */
+ u32 is2h; /* Input Select 2 0..15 */
+ u32 is3l; /* Input Select 3 16..31 */
+ u32 is3h; /* Input Select 3 0..15 */
+};
+
/* Offsets */
#define GPIOx_OR 0x00 /* GPIO Output Register */
#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
u8 res7[0xC0000];
} immap_t;
+#ifdef CONFIG_HAS_FSL_MPH_USB
+#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x22000 /* use the MPH controller */
+#else
+#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 /* use the DR controller */
+#endif
+
#elif defined(CONFIG_MPC8313)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
#define CONFIG_SYS_MPC83xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
#define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
-#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000
+
+#ifndef CONFIG_SYS_MPC83xx_USB_OFFSET
+#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000
+#endif
#define CONFIG_SYS_MPC83xx_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
#endif /* __IMMAP_83xx__ */
uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
- uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */
+ uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration 1 */
uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
- uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
+ uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */
uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */
uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
--- /dev/null
+/*
+ * (C) Copyright 2008-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2009
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __PPC4xx_CONFIG_H
+#define __PPC4xx_CONFIG_H
+
+#include <common.h>
+
+struct ppc4xx_config {
+ char label[16];
+ char description[64];
+ u8 val[CONFIG_4xx_CONFIG_BLOCKSIZE];
+};
+
+extern struct ppc4xx_config ppc4xx_config_val[];
+extern int ppc4xx_config_count;
+
+#endif /* __PPC4xx_CONFIG_H */
#define CONFIG_BOOKE
#endif
+#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
+#ifdef CONFIG_BOOKE
+#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */
+#endif
#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
#define SPRN_CTR 0x009 /* Count Register */
#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
#define SPRN_DBSR 0x3F0 /* Debug Status Register */
#else
#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
+#ifdef CONFIG_BOOKE
+#define SPRN_DBDR 0x3f3 /* Debug Data Register */
+#endif
#define SPRN_DBSR 0x130 /* Book E Debug Status Register */
#define DBSR_IC 0x08000000 /* Book E Instruction Completion */
#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
#define DCCR_NOCACHE 0 /* Noncacheable */
#define DCCR_CACHE 1 /* Cacheable */
+#ifndef CONFIG_BOOKE
+#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */
+#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */
+#endif
#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
#define DCWR_COPY 0 /* Copy-back */
#endif /* CONFIG_BOOKE */
#define SPRN_DEC 0x016 /* Decrement Register */
#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
+#ifdef CONFIG_BOOKE
+#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */
+#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */
+#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */
+#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */
+#endif
#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
+#ifdef CONFIG_BOOKE
+#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */
+#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */
+#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */
+#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */
+#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */
+#endif
#define SPRN_EAR 0x11A /* External Address Register */
#ifndef CONFIG_BOOKE
#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
#define ICCR_NOCACHE 0 /* Noncacheable */
#define ICCR_CACHE 1 /* Cacheable */
#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
+#ifdef CONFIG_BOOKE
+#define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */
+#define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */
+#endif
#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
+#ifdef CONFIG_BOOKE
+#define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */
+#define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */
+#define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */
+#define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */
+#define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */
+#define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */
+#define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */
+#define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */
+#define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */
+#endif
#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
#define SPRN_LR 0x008 /* Link Register */
#define SPRN_MBAR 0x137 /* System memory base address */
#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
+#ifdef CONFIG_BOOKE
+#define SPRN_MMUCR 0x3b2 /* MMU Control Register */
+#endif
#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
#define SPRN_PVR 0x11F /* Processor Version Register */
#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
+#ifdef CONFIG_BOOKE
+#define SPRN_RSTCFG 0x39b /* Reset Configuration */
+#endif
#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
+
#ifdef CONFIG_BOOKE
#define SPRN_SVR 0x3FF /* System Version Register */
#else
#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */
#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */
#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */
+#define PVR_460EX_RB 0x130218A4 /* 460EX rev B with and without Sec Eng*/
#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */
#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */
+#define PVR_460GT_RB 0x130218A5 /* 460GT rev B with and without Sec Eng*/
#define PVR_460SX_RA 0x13541800 /* 460SX rev A */
#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
#define PVR_460GX_RA 0x13541802 /* 460GX rev A */
-/*
- * U-boot - errno.h Error number defines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _BLACKFIN_ERRNO_H
-#define _BLACKFIN_ERRNO_H
-
-#define EPERM 1 /* Operation not permitted */
-#define ENOENT 2 /* No such file or directory */
-#define ESRCH 3 /* No such process */
-#define EINTR 4 /* Interrupted system call */
-#define EIO 5 /* I/O error */
-#define ENXIO 6 /* No such device or address */
-#define E2BIG 7 /* Arg list too long */
-#define ENOEXEC 8 /* Exec format error */
-#define EBADF 9 /* Bad file number */
-#define ECHILD 10 /* No child processes */
-#define EAGAIN 11 /* Try again */
-#define ENOMEM 12 /* Out of memory */
-#define EACCES 13 /* Permission denied */
-#define EFAULT 14 /* Bad address */
-#define ENOTBLK 15 /* Block device required */
-#define EBUSY 16 /* Device or resource busy */
-#define EEXIST 17 /* File exists */
-#define EXDEV 18 /* Cross-device link */
-#define ENODEV 19 /* No such device */
-#define ENOTDIR 20 /* Not a directory */
-#define EISDIR 21 /* Is a directory */
-#define EINVAL 22 /* Invalid argument */
-#define ENFILE 23 /* File table overflow */
-#define EMFILE 24 /* Too many open files */
-#define ENOTTY 25 /* Not a typewriter */
-#define ETXTBSY 26 /* Text file busy */
-#define EFBIG 27 /* File too large */
-#define ENOSPC 28 /* No space left on device */
-#define ESPIPE 29 /* Illegal seek */
-#define EROFS 30 /* Read-only file system */
-#define EMLINK 31 /* Too many links */
-#define EPIPE 32 /* Broken pipe */
-#define EDOM 33 /* Math argument out of domain of func */
-#define ERANGE 34 /* Math result not representable */
-#define EDEADLK 35 /* Resource deadlock would occur */
-#define ENAMETOOLONG 36 /* File name too long */
-#define ENOLCK 37 /* No record locks available */
-#define ENOSYS 38 /* Function not implemented */
-#define ENOTEMPTY 39 /* Directory not empty */
-#define ELOOP 40 /* Too many symbolic links encountered */
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#define ENOMSG 42 /* No message of desired type */
-#define EIDRM 43 /* Identifier removed */
-#define ECHRNG 44 /* Channel number out of range */
-#define EL2NSYNC 45 /* Level 2 not synchronized */
-#define EL3HLT 46 /* Level 3 halted */
-#define EL3RST 47 /* Level 3 reset */
-#define ELNRNG 48 /* Link number out of range */
-#define EUNATCH 49 /* Protocol driver not attached */
-#define ENOCSI 50 /* No CSI structure available */
-#define EL2HLT 51 /* Level 2 halted */
-#define EBADE 52 /* Invalid exchange */
-#define EBADR 53 /* Invalid request descriptor */
-#define EXFULL 54 /* Exchange full */
-#define ENOANO 55 /* No anode */
-#define EBADRQC 56 /* Invalid request code */
-#define EBADSLT 57 /* Invalid slot */
-
-#define EDEADLOCK EDEADLK
-
-#define EBFONT 59 /* Bad font file format */
-#define ENOSTR 60 /* Device not a stream */
-#define ENODATA 61 /* No data available */
-#define ETIME 62 /* Timer expired */
-#define ENOSR 63 /* Out of streams resources */
-#define ENONET 64 /* Machine is not on the network */
-#define ENOPKG 65 /* Package not installed */
-#define EREMOTE 66 /* Object is remote */
-#define ENOLINK 67 /* Link has been severed */
-#define EADV 68 /* Advertise error */
-#define ESRMNT 69 /* Srmount error */
-#define ECOMM 70 /* Communication error on send */
-#define EPROTO 71 /* Protocol error */
-#define EMULTIHOP 72 /* Multihop attempted */
-#define EDOTDOT 73 /* RFS specific error */
-#define EBADMSG 74 /* Not a data message */
-#define EOVERFLOW 75 /* Value too large for defined data type */
-#define ENOTUNIQ 76 /* Name not unique on network */
-#define EBADFD 77 /* File descriptor in bad state */
-#define EREMCHG 78 /* Remote address changed */
-#define ELIBACC 79 /* Can not access a needed shared library */
-#define ELIBBAD 80 /* Accessing a corrupted shared library */
-#define ELIBSCN 81 /* .lib section in a.out corrupted */
-#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
-#define ELIBEXEC 83 /* Cannot exec a shared library directly */
-#define EILSEQ 84 /* Illegal byte sequence */
-#define ERESTART 85 /* Interrupted system call should be restarted */
-#define ESTRPIPE 86 /* Streams pipe error */
-#define EUSERS 87 /* Too many users */
-#define ENOTSOCK 88 /* Socket operation on non-socket */
-#define EDESTADDRREQ 89 /* Destination address required */
-#define EMSGSIZE 90 /* Message too long */
-#define EPROTOTYPE 91 /* Protocol wrong type for socket */
-#define ENOPROTOOPT 92 /* Protocol not available */
-#define EPROTONOSUPPORT 93 /* Protocol not supported */
-#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
-#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
-#define EADDRINUSE 98 /* Address already in use */
-#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
-#define ENETDOWN 100 /* Network is down */
-#define ENETUNREACH 101 /* Network is unreachable */
-#define ENETRESET 102 /* Network dropped connection because of reset */
-#define ECONNABORTED 103 /* Software caused connection abort */
-#define ECONNRESET 104 /* Connection reset by peer */
-#define ENOBUFS 105 /* No buffer space available */
-#define EISCONN 106 /* Transport endpoint is already connected */
-#define ENOTCONN 107 /* Transport endpoint is not connected */
-#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS 109 /* Too many references: cannot splice */
-#define ETIMEDOUT 110 /* Connection timed out */
-#define ECONNREFUSED 111 /* Connection refused */
-#define EHOSTDOWN 112 /* Host is down */
-#define EHOSTUNREACH 113 /* No route to host */
-#define EALREADY 114 /* Operation already in progress */
-#define EINPROGRESS 115 /* Operation now in progress */
-#define ESTALE 116 /* Stale NFS file handle */
-#define EUCLEAN 117 /* Structure needs cleaning */
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#define EISNAM 120 /* Is a named type file */
-#define EREMOTEIO 121 /* Remote I/O error */
-#define EDQUOT 122 /* Quota exceeded */
-
-#define ENOMEDIUM 123 /* No medium found */
-#define EMEDIUMTYPE 124 /* Wrong medium type */
-
-#endif
+#include <asm-generic/errno.h>
-/* SPARC errno definitions, taken from asm-ppc/errno.h
- *
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SPARC_ERRNO_H__
-#define __SPARC_ERRNO_H__
-
-#define EPERM 1 /* Operation not permitted */
-#define ENOENT 2 /* No such file or directory */
-#define ESRCH 3 /* No such process */
-#define EINTR 4 /* Interrupted system call */
-#define EIO 5 /* I/O error */
-#define ENXIO 6 /* No such device or address */
-#define E2BIG 7 /* Arg list too long */
-#define ENOEXEC 8 /* Exec format error */
-#define EBADF 9 /* Bad file number */
-#define ECHILD 10 /* No child processes */
-#define EAGAIN 11 /* Try again */
-#define ENOMEM 12 /* Out of memory */
-#define EACCES 13 /* Permission denied */
-#define EFAULT 14 /* Bad address */
-#define ENOTBLK 15 /* Block device required */
-#define EBUSY 16 /* Device or resource busy */
-#define EEXIST 17 /* File exists */
-#define EXDEV 18 /* Cross-device link */
-#define ENODEV 19 /* No such device */
-#define ENOTDIR 20 /* Not a directory */
-#define EISDIR 21 /* Is a directory */
-#define EINVAL 22 /* Invalid argument */
-#define ENFILE 23 /* File table overflow */
-#define EMFILE 24 /* Too many open files */
-#define ENOTTY 25 /* Not a typewriter */
-#define ETXTBSY 26 /* Text file busy */
-#define EFBIG 27 /* File too large */
-#define ENOSPC 28 /* No space left on device */
-#define ESPIPE 29 /* Illegal seek */
-#define EROFS 30 /* Read-only file system */
-#define EMLINK 31 /* Too many links */
-#define EPIPE 32 /* Broken pipe */
-#define EDOM 33 /* Math argument out of domain of func */
-#define ERANGE 34 /* Math result not representable */
-#define EDEADLK 35 /* Resource deadlock would occur */
-#define ENAMETOOLONG 36 /* File name too long */
-#define ENOLCK 37 /* No record locks available */
-#define ENOSYS 38 /* Function not implemented */
-#define ENOTEMPTY 39 /* Directory not empty */
-#define ELOOP 40 /* Too many symbolic links encountered */
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#define ENOMSG 42 /* No message of desired type */
-#define EIDRM 43 /* Identifier removed */
-#define ECHRNG 44 /* Channel number out of range */
-#define EL2NSYNC 45 /* Level 2 not synchronized */
-#define EL3HLT 46 /* Level 3 halted */
-#define EL3RST 47 /* Level 3 reset */
-#define ELNRNG 48 /* Link number out of range */
-#define EUNATCH 49 /* Protocol driver not attached */
-#define ENOCSI 50 /* No CSI structure available */
-#define EL2HLT 51 /* Level 2 halted */
-#define EBADE 52 /* Invalid exchange */
-#define EBADR 53 /* Invalid request descriptor */
-#define EXFULL 54 /* Exchange full */
-#define ENOANO 55 /* No anode */
-#define EBADRQC 56 /* Invalid request code */
-#define EBADSLT 57 /* Invalid slot */
-#define EDEADLOCK 58 /* File locking deadlock error */
-#define EBFONT 59 /* Bad font file format */
-#define ENOSTR 60 /* Device not a stream */
-#define ENODATA 61 /* No data available */
-#define ETIME 62 /* Timer expired */
-#define ENOSR 63 /* Out of streams resources */
-#define ENONET 64 /* Machine is not on the network */
-#define ENOPKG 65 /* Package not installed */
-#define EREMOTE 66 /* Object is remote */
-#define ENOLINK 67 /* Link has been severed */
-#define EADV 68 /* Advertise error */
-#define ESRMNT 69 /* Srmount error */
-#define ECOMM 70 /* Communication error on send */
-#define EPROTO 71 /* Protocol error */
-#define EMULTIHOP 72 /* Multihop attempted */
-#define EDOTDOT 73 /* RFS specific error */
-#define EBADMSG 74 /* Not a data message */
-#define EOVERFLOW 75 /* Value too large for defined data type */
-#define ENOTUNIQ 76 /* Name not unique on network */
-#define EBADFD 77 /* File descriptor in bad state */
-#define EREMCHG 78 /* Remote address changed */
-#define ELIBACC 79 /* Can not access a needed shared library */
-#define ELIBBAD 80 /* Accessing a corrupted shared library */
-#define ELIBSCN 81 /* .lib section in a.out corrupted */
-#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
-#define ELIBEXEC 83 /* Cannot exec a shared library directly */
-#define EILSEQ 84 /* Illegal byte sequence */
-#define ERESTART 85 /* Interrupted system call should be restarted */
-#define ESTRPIPE 86 /* Streams pipe error */
-#define EUSERS 87 /* Too many users */
-#define ENOTSOCK 88 /* Socket operation on non-socket */
-#define EDESTADDRREQ 89 /* Destination address required */
-#define EMSGSIZE 90 /* Message too long */
-#define EPROTOTYPE 91 /* Protocol wrong type for socket */
-#define ENOPROTOOPT 92 /* Protocol not available */
-#define EPROTONOSUPPORT 93 /* Protocol not supported */
-#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
-#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
-#define EADDRINUSE 98 /* Address already in use */
-#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
-#define ENETDOWN 100 /* Network is down */
-#define ENETUNREACH 101 /* Network is unreachable */
-#define ENETRESET 102 /* Network dropped connection because of reset */
-#define ECONNABORTED 103 /* Software caused connection abort */
-#define ECONNRESET 104 /* Connection reset by peer */
-#define ENOBUFS 105 /* No buffer space available */
-#define EISCONN 106 /* Transport endpoint is already connected */
-#define ENOTCONN 107 /* Transport endpoint is not connected */
-#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS 109 /* Too many references: cannot splice */
-#define ETIMEDOUT 110 /* Connection timed out */
-#define ECONNREFUSED 111 /* Connection refused */
-#define EHOSTDOWN 112 /* Host is down */
-#define EHOSTUNREACH 113 /* No route to host */
-#define EALREADY 114 /* Operation already in progress */
-#define EINPROGRESS 115 /* Operation now in progress */
-#define ESTALE 116 /* Stale NFS file handle */
-#define EUCLEAN 117 /* Structure needs cleaning */
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#define EISNAM 120 /* Is a named type file */
-#define EREMOTEIO 121 /* Remote I/O error */
-#define EDQUOT 122 /* Quota exceeded */
-
-#define ENOMEDIUM 123 /* No medium found */
-#define EMEDIUMTYPE 124 /* Wrong medium type */
-
-/* Should never be seen by user programs */
-#define ERESTARTSYS 512
-#define ERESTARTNOINTR 513
-#define ERESTARTNOHAND 514 /* restart if no handler.. */
-#define ENOIOCTLCMD 515 /* No ioctl command */
-
-#define _LAST_ERRNO 515
-
-#endif
+#include <asm-generic/errno.h>
/*
- * (C) Copyright 2005
- * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ * (C) Copyright 2005-2009
+ * Jens Scharsig @ BuS Elektronik GmbH & Co. KG, <esw@bus-elektronik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
-#ifndef __VCXK_H_
-#define __VCXK_H_
+#ifndef __BUS_VCXK_H_
+#define __BUS_VCXK_H_
-extern int init_vcxk(void);
-void vcxk_loadimage(ulong source);
-
-#define VIDEO_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
-#define VIDEO_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
-#define VIDEO_ACKNOWLEDGE_PIN 0x0001
-
-#define VIDEO_ENABLE_PORT MCFGPTB_GPTPORT
-#define VIDEO_ENABLE_DDR MCFGPTB_GPTDDR
-#define VIDEO_ENABLE_PIN 0x0002
-
-#define VIDEO_REQUEST_PORT MCFGPTB_GPTPORT
-#define VIDEO_REQUEST_DDR MCFGPTB_GPTDDR
-#define VIDEO_REQUEST_PIN 0x0004
-
-#define VIDEO_Invert_CFG MCFGPIO_PEPAR
-#define VIDEO_Invert_IO MCFGPIO_PEPAR_PEPA2
-#define VIDEO_INVERT_PORT MCFGPIO_PORTE
-#define VIDEO_INVERT_DDR MCFGPIO_DDRE
-#define VIDEO_INVERT_PIN MCFGPIO_PORT2
+extern int vcxk_init(unsigned long width, unsigned long height);
+extern void vcxk_setpixel(int x, int y, unsigned long color);
+extern int vcxk_acknowledge_wait(void);
+extern int vcxk_request(void);
+extern void vcxk_loadimage(ulong source);
+extern int vcxk_display_bitmap(ulong addr, int x, int y);
+extern void vcxk_setbrightness(unsigned int side, short brightness);
+extern int video_display_bitmap(ulong addr, int x, int y);
#endif
#undef _LINUX_CONFIG_H
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
+#ifndef __ASSEMBLY__ /* put C only stuff in this section */
+
typedef unsigned char uchar;
typedef volatile unsigned long vu_long;
typedef volatile unsigned short vu_short;
/*
* STDIO based functions (can always be used)
*/
-
/* serial stuff */
void serial_printf (const char *fmt, ...)
__attribute__ ((format (__printf__, 1, 2)));
-
/* stdin */
int getc(void);
int tstc(void);
/*
* FILE based functions (can only be used AFTER relocation!)
*/
-
#define stdin 0
#define stdout 1
#define stderr 2
*/
void show_boot_progress(int val);
+/* Multicore arch functions */
+#ifdef CONFIG_MP
+int cpu_status(int nr);
+int cpu_reset(int nr);
+int cpu_release(int nr, int argc, char *argv[]);
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+/* Put only stuff here that the assembler can digest */
+
+#ifdef CONFIG_POST
+#define CONFIG_HAS_POST
+#endif
+
#ifdef CONFIG_INIT_CRITICAL
#error CONFIG_INIT_CRITICAL is deprecated!
#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README.
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#define ROUND(a,b) (((a) + (b)) & ~((b) - 1))
#define DIV_ROUND(n,d) (((n) + ((d)/2)) / (d))
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
-/* Multicore arch functions */
-#ifdef CONFIG_MP
-int cpu_status(int nr);
-int cpu_reset(int nr);
-int cpu_release(int nr, int argc, char *argv[]);
-#endif
-
-#ifdef CONFIG_POST
-#define CONFIG_HAS_POST
-#endif
-
#endif /* __COMMON_H_ */
--- /dev/null
+/*
+ * Keep all the ugly #ifdef for system stuff here
+ */
+
+#ifndef __COMPILER_H__
+#define __COMPILER_H__
+
+#include <stddef.h>
+
+#ifdef USE_HOSTCC
+
+#if defined(__BEOS__) || \
+ defined(__NetBSD__) || \
+ defined(__FreeBSD__) || \
+ defined(__sun__) || \
+ defined(__APPLE__)
+# include <inttypes.h>
+#elif defined(__linux__) || defined(__WIN32__) || defined(__MINGW32__)
+# include <stdint.h>
+#endif
+
+#include <errno.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+extern int errno;
+
+#if !defined(__WIN32__) && !defined(__MINGW32__)
+# include <sys/mman.h>
+#endif
+
+/* Not all systems (like Windows) has this define, and yes
+ * we do replace/emulate mmap() on those systems ...
+ */
+#ifndef MAP_FAILED
+# define MAP_FAILED ((void *)-1)
+#endif
+
+#include <fcntl.h>
+#ifndef O_BINARY /* should be define'd on __WIN32__ */
+#define O_BINARY 0
+#endif
+
+#ifdef __linux__
+# include <endian.h>
+# include <byteswap.h>
+#elif defined(__MACH__)
+# include <machine/endian.h>
+typedef unsigned long ulong;
+typedef unsigned int uint;
+#endif
+
+typedef uint8_t __u8;
+typedef uint16_t __u16;
+typedef uint32_t __u32;
+
+#define uswap_16(x) \
+ ((((x) & 0xff00) >> 8) | \
+ (((x) & 0x00ff) << 8))
+#define uswap_32(x) \
+ ((((x) & 0xff000000) >> 24) | \
+ (((x) & 0x00ff0000) >> 8) | \
+ (((x) & 0x0000ff00) << 8) | \
+ (((x) & 0x000000ff) << 24))
+#define _uswap_64(x, sfx) \
+ ((((x) & 0xff00000000000000##sfx) >> 56) | \
+ (((x) & 0x00ff000000000000##sfx) >> 40) | \
+ (((x) & 0x0000ff0000000000##sfx) >> 24) | \
+ (((x) & 0x000000ff00000000##sfx) >> 8) | \
+ (((x) & 0x00000000ff000000##sfx) << 8) | \
+ (((x) & 0x0000000000ff0000##sfx) << 24) | \
+ (((x) & 0x000000000000ff00##sfx) << 40) | \
+ (((x) & 0x00000000000000ff##sfx) << 56))
+#if defined(__GNUC__)
+# define uswap_64(x) _uswap_64(x, ull)
+#else
+# define uswap_64(x) _uswap_64(x, )
+#endif
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+# define cpu_to_le16(x) (x)
+# define cpu_to_le32(x) (x)
+# define cpu_to_le64(x) (x)
+# define le16_to_cpu(x) (x)
+# define le32_to_cpu(x) (x)
+# define le64_to_cpu(x) (x)
+# define cpu_to_be16(x) uswap_16(x)
+# define cpu_to_be32(x) uswap_32(x)
+# define cpu_to_be64(x) uswap_64(x)
+# define be16_to_cpu(x) uswap_16(x)
+# define be32_to_cpu(x) uswap_32(x)
+# define be64_to_cpu(x) uswap_64(x)
+#else
+# define cpu_to_le16(x) uswap_16(x)
+# define cpu_to_le32(x) uswap_32(x)
+# define cpu_to_le64(x) uswap_64(x)
+# define le16_to_cpu(x) uswap_16(x)
+# define le32_to_cpu(x) uswap_32(x)
+# define le64_to_cpu(x) uswap_64(x)
+# define cpu_to_be16(x) (x)
+# define cpu_to_be32(x) (x)
+# define cpu_to_be64(x) (x)
+# define be16_to_cpu(x) (x)
+# define be32_to_cpu(x) (x)
+# define be64_to_cpu(x) (x)
+#endif
+
+#else /* !USE_HOSTCC */
+
+#include <linux/string.h>
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+/* Types for `void *' pointers. */
+#if __WORDSIZE == 64
+typedef unsigned long int uintptr_t;
+#else
+typedef unsigned int uintptr_t;
+#endif
+
+#endif
+
+#endif
#define CONFIG_CMD_BOOTD /* bootd */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_ECHO /* echo arguments */
-#define CONFIG_CMD_SAVEENV /* saveenv */
-#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_IMI /* iminfo */
+#define CONFIG_CMD_ITEST /* Integer (and string) test */
#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_IMLS /* List all found images */
#endif
-#define CONFIG_CMD_ITEST /* Integer (and string) test */
#define CONFIG_CMD_LOADB /* loadb */
#define CONFIG_CMD_LOADS /* loads */
#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_NFS /* NFS support */
#define CONFIG_CMD_RUN /* run command in env variable */
+#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
#define CONFIG_CMD_SOURCE /* "source" command support */
#define CONFIG_CMD_XIMG /* Load part of Multi Image */
#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
-#define CONFIG_SYS_NAND_QUIET 1
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CONFIG_SYS_NAND_QUIET 1
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/*-----------------------------------------------------------------------
* PCI stuff
#define CONFIG_USB_UHCI 1
#define CONFIG_USB_STORAGE 1
#define CONFIG_USB_KEYBOARD 1
-#define CONFIG_SYS_DEVICE_DEREGISTER 1 /* needed by CONFIG_USB_KEYBOARD */
+#define CONFIG_SYS_STDIO_DEREGISTER 1 /* needed by CONFIG_USB_KEYBOARD */
/*
* Autoboot stuff
#include <config_cmd_default.h>
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_ELF
-/* CONFIG_CMD_DOC required legacy NAND support */
-#define CONFIG_NAND_LEGACY
-
#if 0
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
/* For CATcenter there is only NAND on the module */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
#define NAND_NO_RB
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
#undef CONFIG_WATCHDOG /* watchdog disabled */
-/*-----------------------------------------------------------------------
- * Disk-On-Chip configuration
- */
-
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-
/*-----------------------------------------------------------------------
* Miscellaneous configuration options
*/
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PCI
#endif
-
-#define CONFIG_NAND_LEGACY
-
/*
* Miscellaneous configurable options
*/
/*
* Configuation settings for the BuS EB+MCF-EV123 boards.
*
- * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
#ifndef _CONFIG_EB_MCF_EV123_H_
#define _CONFIG_EB_MCF_EV123_H_
-#define CONFIG_EB_MCF_EV123
-
#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
-/*
- * High Level Configuration Options (easy to change)
- */
+/*----------------------------------------------------------------------*
+ * High Level Configuration Options (easy to change) *
+ *----------------------------------------------------------------------*/
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5282 /* define processor type */
+#define CONFIG_EB_MCF_EV123
#define CONFIG_MISC_INIT_R
#define CONFIG_BAUDRATE 9600
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
+#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
#define CONFIG_BOOTCOMMAND "printenv"
-/* Configuration for environment
- * Environment is embedded in u-boot in the second sector of the flash
- */
+/*----------------------------------------------------------------------*
+ * Options *
+ *----------------------------------------------------------------------*/
+
+#define CONFIG_BOOT_RETRY_TIME -1
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_SPLASH_SCREEN
+
+/*----------------------------------------------------------------------*
+ * Configuration for environment *
+ * Environment is in the second sector of the first 256k of flash *
+ *----------------------------------------------------------------------*/
+
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_ADDR 0xF003C000 /* End of 256K */
#define CONFIG_ENV_SECT_SIZE 0x4000
#define CONFIG_ENV_IS_IN_FLASH 1
-/*
-#define CONFIG_ENV_IS_EMBEDDED 1
-#define CONFIG_ENV_ADDR_REDUND 0xF0018000
-#define CONFIG_ENV_SECT_SIZE_REDUND 0x4000
-*/
#else
#define CONFIG_ENV_ADDR 0xFFE04000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_IS_IN_FLASH 1
#endif
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_MCFTMR
-#define CONFIG_MCFFEC
-#ifdef CONFIG_MCFFEC
-# define CONFIG_NET_MULTI 1
-# define CONFIG_MII 1
-# define CONFIG_MII_INIT 1
-# define CONFIG_SYS_DISCOVER_PHY
-# define CONFIG_SYS_RX_ETH_BUFFER 8
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-# ifndef CONFIG_SYS_DISCOVER_PHY
-# define FECDUPLEX FULL
-# define FECSPEED _100BASET
-# else
-# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# endif
-# endif /* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-#ifdef CONFIG_MCFFEC
-# define CONFIG_ETHADDR 00:CF:52:82:EB:01
-# define CONFIG_IPADDR 192.162.1.2
-# define CONFIG_NETMASK 255.255.255.0
-# define CONFIG_SERVERIP 192.162.1.1
-# define CONFIG_GATEWAYIP 192.162.1.1
-# define CONFIG_OVERWRITE_ETHADDR_ONCE
-#endif /* CONFIG_MCFFEC */
#define CONFIG_BOOTDELAY 5
-#define CONFIG_SYS_PROMPT "\nEV123 U-Boot> "
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "\nEV123 U-Boot> "
+#define CONFIG_SYS_LONGHELP 1
#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR 0x20000
/*#define CONFIG_SYS_DRAM_TEST 1 */
#undef CONFIG_SYS_DRAM_TEST
-/* Clock and PLL Configuration */
+/*----------------------------------------------------------------------*
+ * Clock and PLL Configuration *
+ *----------------------------------------------------------------------*/
#define CONFIG_SYS_HZ 10000000
#define CONFIG_SYS_CLK 58982400 /* 9,8304MHz * 6 */
/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
-#define CONFIG_SYS_MFD 0x01 /* PLL Multiplication Factor Devider */
-#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
+#define CONFIG_SYS_MFD 0x01 /* PLL Multiplication Factor Devider */
+#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
-/*
+/*----------------------------------------------------------------------*
+ * Network *
+ *----------------------------------------------------------------------*/
+
+#define CONFIG_MCFFEC
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1
+#define CONFIG_MII_INIT 1
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_SYS_RX_ETH_BUFFER 8
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#define CONFIG_SYS_FEC0_PINMUX 0
+#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
+#define MCFFEC_TOUT_LOOP 50000
+
+#define CONFIG_ETHADDR 00:CF:52:82:EB:01
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/*-------------------------------------------------------------------------
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
- */
-#define CONFIG_SYS_MBAR 0x40000000
+ *-----------------------------------------------------------------------*/
+
+#define CONFIG_SYS_MBAR 0x40000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ *-----------------------------------------------------------------------*/
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
+#define CONFIG_SYS_INIT_RAM_END 0x10000
+#define CONFIG_SYS_GBL_DATA_SIZE 64
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE1 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE1 16 /* SDRAM size in MB */
-
-/*
-#define CONFIG_SYS_SDRAM_BASE0 CONFIG_SYS_SDRAM_BASE1+CONFIG_SYS_SDRAM_SIZE1*1024*1024
-#define CONFIG_SYS_SDRAM_SIZE0 16 */ /* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_SIZE1 16 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE1
#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE1
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
-#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
/* If M5282 port is fully implemented the monitor base will be behind
* the vector table. */
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
+
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
+#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
+
#define CONFIG_SYS_MAX_FLASH_SECT 35
#define CONFIG_SYS_MAX_FLASH_BANKS 2
#define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
#define CONFIG_SYS_PCDAT 0x0000000
#define CONFIG_SYS_PEHLPAR 0xC0
-#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
+#define CONFIG_SYS_PUAPAR 0x0F
#define CONFIG_SYS_DDRUA 0x05
#define CONFIG_SYS_PJPAR 0xFF
/*-----------------------------------------------------------------------
- * CCM configuration
+ * VIDEO configuration
*/
-#define CONFIG_SYS_CCM_SIZ 0
+#define CONFIG_VIDEO
-/*---------------------------------------------------------------------*/
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_VCXK 1
+
+#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
+#define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
+#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS3_BASE
+#define CONFIG_SYS_VCXK_AUTODETECT 1
+
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001
+
+#define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT
+#define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR
+#define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002
+
+#define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT
+#define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR
+#define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004
+
+#define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE
+#define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE
+#define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2
+
+#endif /* CONFIG_VIDEO */
#endif /* _CONFIG_M5282EVB_H */
/*---------------------------------------------------------------------*/
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_FPS850L 1 /* ...on a FingerPrint Sensor */
-#undef CONFIG_8xx_CONS_SMC1
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_FPS860L 1 /* ...on a FingerPrint Sensor */
-#undef CONFIG_8xx_CONS_SMC1
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTCOUNT_LIMIT
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CONFIG_SYS_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#endif
/*-----------------------------------------------------------------------
#define CONFIG_CMD_MII
#define CONFIG_CMD_BEDBUG
-#if !defined(CONFIG_SC)
- #define CONFIG_CMD_DOC
-#endif
-
#ifdef CONFIG_POST
#define CONFIG_CMD_DIAG
#endif
#define CONFIG_FPGA_VIRTEX2
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
-
-#define CONFIG_NAND_LEGACY
-
/*
* Verbose help from command monitor.
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-/*
- * Disk On Chip (millenium) configuration
- */
-#if !defined(CONFIG_SC)
-#define CONFIG_SYS_MAX_DOC_DEVICE 1
-#undef CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-#undef CONFIG_SYS_DOC_PASSIVE_PROBE
-#endif
-
/*
* FEC interrupt assignment
*/
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
#endif
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
#define CONFIG_SYS_NAND0_BASE 0xE1000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
#endif /* CONFIG_CMD_NAND */
/*-----------------------------------------------------------------------
#if !defined(CONFIG_MIP405T)
#define CONFIG_CMD_USB
- #define CONFIG_CMD_DOC
#endif
-#define CONFIG_NAND_LEGACY
-
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/**************************************************************
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION /* Experimental */
-/************************************************************
- * Disk-On-Chip configuration
- ************************************************************/
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-#define CONFIG_SYS_DOC_SHORT_TIMEOUT
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
/************************************************************
* Keyboard support
************************************************************/
#define CONFIG_USB_STORAGE
/* Enable needed helper functions */
-#define CONFIG_SYS_DEVICE_DEREGISTER /* needs device_deregister */
+#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
#endif
/************************************************************
* Debug support
#define CONFIG_MPC8313ERDB 1
#define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI
#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/*
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+#define CONFIG_HWCONFIG
/*
* IMMR new address
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
#define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
-#define CONFIG_83XX_GENERIC_PCIE 1
+#define CONFIG_PCIE
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
#define CONFIG_PCI 1
-#define CONFIG_83XX_GENERIC_PCI 1
/*
* System Clock Setup
#endif
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
#endif
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#else
/*
* Environment Configuration
- */
-
-#define CONFIG_ENV_OVERWRITE
+ */ #define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
-#undef CONFIG_PCI
-#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-
#define PCI_66M
#ifdef PCI_66M
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_83XX_GENERIC_PCI
#define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100
/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
*
* See file CREDITS for list of people who contributed to this
* project.
#define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */
#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
#define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */
+#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
#endif
#define CONFIG_PCI
#endif
+#ifdef CONFIG_SYS_USB_HOST
+/*
+ * Support USB
+ */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+
+/* Current USB implementation supports the only USB controller,
+ * so we have to choose between the MPH or the DR ones */
+#if 1
+#define CONFIG_HAS_FSL_MPH_USB
+#else
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+#endif
+
/*
* DDR Setup
*/
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SDRAM
-#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114)
+#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
+ || defined(CONFIG_USB_STORAGE)
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FAT
+ #define CONFIG_SUPPORT_VFAT
#endif
#ifdef CONFIG_COMPACT_FLASH
#ifdef CONFIG_SATA_SIL3114
#define CONFIG_CMD_SATA
+#endif
+
+#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
#define CONFIG_CMD_EXT2
#endif
#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
+#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
/*
* System IO Config
*/
#define CONFIG_SYS_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */
-#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
+#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) /* USB DR as device + USB MPH as host */
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT
#endif
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#else
#define CONFIG_NAND_FSL_UPM 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */
* Addresses are mapped 1-1.
*/
#define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI 1
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_HWCONFIG
/*
* IMMR new address
#ifndef __ASSEMBLY__
extern int board_pci_host_broken(void);
#endif
-#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
-#define CONFIG_83XX_GENERIC_PCIE 1
+#define CONFIG_PCIE
#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
/*
* On-board devices
#define CONFIG_83XX_PCICLK 66666667 /* in HZ */
#else
#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-#define CONFIG_83XX_GENERIC_PCI 1
-#define CONFIG_83XX_GENERIC_PCIE 1
+#define CONFIG_PCIE
#endif
#ifndef CONFIG_SYS_CLK_FREQ
#undef CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/*
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+#define CONFIG_SYS_64BIT_STRTOUL 1
+#define CONFIG_SYS_64BIT_VSPRINTF 1
+
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_MMC 1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
+#define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
+#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
+#define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
+#define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
+#define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
+#define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
+#define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
+#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
+#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
/*
- * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
/* Initial Memory map for Linux*/
/*
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
+#define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
+#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
+#define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
+#define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
+#define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
#define CONFIG_PCI_OHCI 1
#define CONFIG_USB_OHCI_NEW 1
#define CONFIG_USB_KEYBOARD 1
-#define CONFIG_SYS_DEVICE_DEREGISTER
+#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_SYS_USB_EVENT_POLL 1
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
+#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
+#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define CONFIG_PCI_OHCI 1
#define CONFIG_USB_OHCI_NEW 1
#define CONFIG_USB_KEYBOARD 1
-#define CONFIG_SYS_DEVICE_DEREGISTER
+#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_SYS_USB_EVENT_POLL 1
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
#define MV_VCI mvBlueCOUGAR-P
#define MV_FPGA_DATA 0xff860000
#define MV_FPGA_SIZE 0x0003c886
-#define MV_KERNEL_ADDR 0xffc00000
+#define MV_KERNEL_ADDR 0xffd00000
#define MV_INITRD_ADDR 0xff900000
-#define MV_INITRD_LENGTH 0x00300000
+#define MV_INITRD_LENGTH 0x00400000
#define MV_SCRATCH_ADDR 0x00000000
#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
#define MV_SOURCE_ADDR 0xff840000
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PCI
#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_I2C
#undef CONFIG_WATCHDOG
"propdev_debug=0\0" \
"gevss_debug=0\0" \
"watchdog=1\0" \
+ "sensor_cnt=1\0" \
""
#undef XMK_STR
#define CONFIG_SYS_MALLOC_LEN (512 << 10)
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_MODULE 1
+#define CONFIG_SYS_I2C_SPEED 86000
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
/*
* Ethernet configuration
*/
#define CONFIG_SYS_IMMR 0xE0000000
#define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI
#define CONFIG_PCI_SKIP_HOST_BRIDGE
#define CONFIG_HARD_I2C
#define CONFIG_TSEC_ENET
*/
#include <config_cmd_default.h>
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
#define DSP_BASE 0xF1000000
#define NAND_BASE 0xF1010000
-/****************************************************************/
-
-/* NAND */
-#define CONFIG_NAND_LEGACY
-#define CONFIG_SYS_NAND_BASE NAND_BASE
-#define CONFIG_MTD_NAND_ECC_JFFS2
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_MTD_NAND_UNSAFE
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define SECTORSIZE 512
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
-#define NAND_DISABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \
- } while(0)
-
-#define NAND_ENABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
- } while(0)
-
-#define NAND_CTL_CLRALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
- } while(0)
-
-#define NAND_CTL_SETALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \
- } while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
- } while(0)
-
-#define NAND_CTL_SETCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \
- } while(0)
-
-#if CONFIG_NETPHONE_VERSION == 1
-#define NAND_WAIT_READY(nand) \
- do { \
- int _tries = 0; \
- while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
- if (++_tries > 100000) \
- break; \
- } while (0)
-#elif CONFIG_NETPHONE_VERSION == 2
-#define NAND_WAIT_READY(nand) \
- do { \
- int _tries = 0; \
- while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
- if (++_tries > 100000) \
- break; \
- } while (0)
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND_ADDRESS(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define READ_NAND(adr) \
- ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
-
/*****************************************************************************/
#define CONFIG_SYS_DIRECT_FLASH_TFTP
-#define CONFIG_SYS_DIRECT_NAND_TFTP
/*****************************************************************************/
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCMCIA
#define CONFIG_CMD_PING
#define ER_BASE 0xF1020000
#define DUMMY_BASE 0xF1FF0000
-/****************************************************************/
-
-/* NAND */
-#define CONFIG_NAND_LEGACY
-#define CONFIG_SYS_NAND_BASE NAND_BASE
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_MTD_NAND_UNSAFE
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-/* #define NAND_NO_RB */
-
-#define SECTORSIZE 512
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-/* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */
-#define NAND_DISABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 5)); \
- } while(0)
-
-#define NAND_ENABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 5)); \
- } while(0)
-
-#define NAND_CTL_CLRALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 3)); \
- } while(0)
-
-#define NAND_CTL_SETALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 3)); \
- } while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 4)); \
- } while(0)
-
-#define NAND_CTL_SETCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 4)); \
- } while(0)
-
-#ifndef NAND_NO_RB
-#define NAND_WAIT_READY(nand) \
- do { \
- while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 13))) == 0) { \
- WATCHDOG_RESET(); \
- } \
- } while (0)
-#else
-#define NAND_WAIT_READY(nand) udelay(12)
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND_ADDRESS(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define READ_NAND(adr) \
- ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
-
-#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nand0"
-#define CONFIG_JFFS2_PART_SIZE 0x00100000
-#define CONFIG_JFFS2_PART_OFFSET 0x00200000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nand0=netta-nand"
-#define MTDPARTS_DEFAULT "mtdparts=netta-nand:1m@2m(jffs2)"
-*/
-
/*****************************************************************************/
#define CONFIG_SYS_DIRECT_FLASH_TFTP
*/
#include <config_cmd_default.h>
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
#define DSP_BASE 0xF1000000
#define NAND_BASE 0xF1010000
-/****************************************************************/
-
-/* NAND */
-#define CONFIG_NAND_LEGACY
-#define CONFIG_SYS_NAND_BASE NAND_BASE
-#define CONFIG_MTD_NAND_ECC_JFFS2
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_MTD_NAND_UNSAFE
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define SECTORSIZE 512
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
-#define NAND_DISABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \
- } while(0)
-
-#define NAND_ENABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
- } while(0)
-
-#define NAND_CTL_CLRALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
- } while(0)
-
-#define NAND_CTL_SETALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \
- } while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
- } while(0)
-
-#define NAND_CTL_SETCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \
- } while(0)
-
-#if CONFIG_NETTA2_VERSION == 1
-#define NAND_WAIT_READY(nand) \
- do { \
- int _tries = 0; \
- while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
- if (++_tries > 100000) \
- break; \
- } while (0)
-#elif CONFIG_NETTA2_VERSION == 2
-#define NAND_WAIT_READY(nand) \
- do { \
- int _tries = 0; \
- while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
- if (++_tries > 100000) \
- break; \
- } while (0)
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND_ADDRESS(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define READ_NAND(adr) \
- ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
-
/*****************************************************************************/
#define CONFIG_SYS_DIRECT_FLASH_TFTP
-#define CONFIG_SYS_DIRECT_NAND_TFTP
/*****************************************************************************/
#define CONFIG_CMD_PING
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-#define CONFIG_CMD_NAND
+/* #define CONFIG_CMD_NAND */ /* disabled */
#endif
#endif
-/*****************************************************************************/
-
-#define CONFIG_NAND_LEGACY
-
-#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-
-/* NAND */
-#define CONFIG_SYS_NAND_BASE NAND_BASE
-#define CONFIG_MTD_NAND_ECC_JFFS2
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define SECTORSIZE 512
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-#define NAND_DISABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= 0x0040; \
- } while(0)
-
-#define NAND_ENABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~0x0040; \
- } while(0)
-
-#define NAND_CTL_CLRALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~0x0100; \
- } while(0)
-
-#define NAND_CTL_SETALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= 0x0100; \
- } while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~0x0080; \
- } while(0)
-
-#define NAND_CTL_SETCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= 0x0080; \
- } while(0)
-
-#define NAND_WAIT_READY(nand) \
- do { \
- while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & 0x100) == 0) \
- ; \
- } while (0)
-
-#define WRITE_NAND_COMMAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND_ADDRESS(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define READ_NAND(adr) \
- ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
-
-#endif
/*****************************************************************************/
#define CONFIG_NSCU 1
#define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_66MHz 1 /* running at 66 MHz, 1:1 clock */
#define PIXIS_VWATCH 0x24 /* Watchdog Register */
#define PIXIS_LED 0x25 /* LED Register */
+#define PIXIS_SW(x) 0x20 + (x - 1) * 2
+#define PIXIS_EN(x) 0x21 + (x - 1) * 2
+#define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */
+#define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */
+
/* old pixis referenced names */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_SLAVE 0x7F
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
-#define CONFIG_NAND_LEGACY
-
/*
* Miscellaneous configurable options
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-/*-----------------------------------------------------------------------
- * Disk-On-Chip configuration
- */
-
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#undef CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-
/*-----------------------------------------------------------------------
RTC m48t59
*/
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
-#define CONFIG_NAND_LEGACY
-
/*
* Miscellaneous configurable options
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-/*-----------------------------------------------------------------------
- * Disk-On-Chip configuration
- */
-
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#undef CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-
/*-----------------------------------------------------------------------
RTC m48t59
*/
#define CONFIG_CMD_USB
#define CONFIG_CMD_MII
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_BSP
-
-#define CONFIG_NAND_LEGACY
-
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/**************************************************************
#define CONFIG_USB_STORAGE
/* Enable needed helper functions */
-#define CONFIG_SYS_DEVICE_DEREGISTER /* needs device_deregister */
+#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
/************************************************************
* Debug support
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*
* PCI stuff
*/
#define CONFIG_USB_STORAGE
#endif
-#if !defined(CONFIG_BOOT_ROM)
-/* DoC requires legacy NAND for now */
-#define CONFIG_NAND_LEGACY
-#endif
-
-
/*
* BOOTP options
*/
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
-#if !defined(CONFIG_BOOT_ROM)
-#define CONFIG_CMD_DOC
-#endif
-
#if defined(CONFIG_MPC5200)
#define CONFIG_CMD_PCI
#endif
#define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR 0x51
-/*
- * Disk-On-Chip configuration
- */
-
-#define CONFIG_SYS_DOC_SHORT_TIMEOUT
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
#define CONFIG_SYS_DOC_BASE 0xE0000000
#define CONFIG_SYS_DOC_SIZE 0x00100000
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#endif
-
-#define CONFIG_NAND_LEGACY
-
-/*
- * Disk-On-Chip configuration
- */
-
-#define CONFIG_SYS_DOC_SHORT_TIMEOUT
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#endif
-
-/*
- * Disk-On-Chip configuration
- */
-#define CONFIG_NAND_LEGACY
-
-#define CONFIG_SYS_DOC_SHORT_TIMEOUT
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-
/*
* Miscellaneous configurable options
*/
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP 1 /* This is a PPC405 CPU */
+#define CONFIG_4xx 1 /* ...member of PPC4xx family */
+#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
+#define CONFIG_BOARD_TYPES 1 /* support board types */
+
+#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
+
+#undef CONFIG_BOOTARGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT /* enable preboot variable */
+
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change*/
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 1 /* PHY address */
+#define CONFIG_PHY1_ADDR 2 /* 2nd PHY address */
+
+#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CHIP_CONFIG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+#define CONFIG_PRAM 0
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+
+#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */
+
+#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */
+
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK
+#define CONFIG_SYS_BASE_BAUD 691200
+#define CONFIG_UART1_CONSOLE
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
+#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * PCI stuff
+ */
+#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
+#define PCI_HOST_FORCE 1 /* configure as pci host */
+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
+
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
+#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+/*
+ * PCI identification
+ */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
+#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
+#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */
+#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
+#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
+
+#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
+
+#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
+#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable=1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to CPLD, GPIO */
+#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI 1 /* CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max. no. memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* erase timeout (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* write timeout (in ms) */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buffered writes (faster) */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* 'E' for empty sector (flinfo) */
+#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_FLASH_BASE 0xfe000000
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
+
+/*
+ * Environment in EEPROM setup
+ */
+#define CONFIG_ENV_IS_IN_EEPROM 1
+#define CONFIG_ENV_OFFSET 0x100
+#define CONFIG_ENV_SIZE 0x700
+
+/*
+ * I2C EEPROM (24W16) for environment
+ */
+#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24W16 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
+ /* 16 byte page write mode using*/
+ /* last 4 bits of the address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+#define CONFIG_SYS_EEPROM_WREN 1
+
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0x40
+#define CONFIG_4xx_CONFIG_BLOCKSIZE 0x20
+
+/*
+ * RTC
+ */
+#define CONFIG_RTC_RX8025
+
+/*
+ * External Bus Controller (EBC) Setup
+ * (max. 55MHZ EBC clock)
+ */
+/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP 0x03017200
+#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xba000)
+
+/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_CPLD_BASE 0xef000000
+#define CONFIG_SYS_EBC_PB1AP 0x00800000
+#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
+/* inside SDRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
+/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes res. for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+ CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alt1 */ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO6 TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO9 TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
+} \
+}
+
+#define CONFIG_SYS_GPIO_HWREV_MASK (0xf0000000 >> 1) /* GPIO1..4 */
+#define CONFIG_SYS_GPIO_HWREV_SHIFT 27
+#define CONFIG_SYS_GPIO_LEDRUN_N (0x80000000 >> 5) /* GPIO5 */
+#define CONFIG_SYS_GPIO_LEDA_N (0x80000000 >> 6) /* GPIO6 */
+#define CONFIG_SYS_GPIO_LEDB_N (0x80000000 >> 7) /* GPIO7 */
+#define CONFIG_SYS_GPIO_SELFRST_N (0x80000000 >> 8) /* GPIO8 */
+#define CONFIG_SYS_GPIO_EEPROM_WP (0x80000000 >> 9) /* GPIO9 */
+#define CONFIG_SYS_GPIO_MONARCH_N (0x80000000 >> 11) /* GPIO11 */
+#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 12) /* GPIO12 */
+#define CONFIG_SYS_GPIO_M66EN (0x80000000 >> 13) /* GPIO13 */
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#undef CONFIG_SYS_FCPU333MHZ
+#define CONFIG_SYS_FCPU266MHZ
+#undef CONFIG_SYS_FCPU133MHZ
+
+#if defined(CONFIG_SYS_FCPU333MHZ)
+/*
+ * CPU: 333MHz
+ * PLB/SDRAM/MAL: 111MHz
+ * OPB: 55MHz
+ * EBC: 55MHz
+ * PCI: 55MHz (111MHz on M66EN=1)
+ */
+#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PLLMR1_DEFAULT (PLL_FBKDIV_10 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+#endif
+
+#if defined(CONFIG_SYS_FCPU266MHZ)
+/*
+ * CPU: 266MHz
+ * PLB/SDRAM/MAL: 133MHz
+ * OPB: 66MHz
+ * EBC: 44MHz
+ * PCI: 44MHz (66MHz on M66EN=1)
+ */
+#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_3)
+#define PLLMR1_DEFAULT (PLL_FBKDIV_8 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#endif
+
+#if defined(CONFIG_SYS_FCPU133MHZ)
+/*
+ * CPU: 133MHz
+ * PLB/SDRAM/MAL: 133MHz
+ * OPB: 66MHz
+ * EBC: 44MHz
+ * PCI: 44MHz (66MHz on M66EN=1)
+ */
+#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_3)
+#define PLLMR1_DEFAULT (PLL_FBKDIV_4 | \
+ PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#endif
+
+#endif /* __CONFIG_H */
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*
* nand device 1 on dave (PPChameleonEVB) needs more time,
* so we just introduce additional wait in nand_wait(),
} \
} while(0)
-#if 0
-#define SECTORSIZE 512
-#define NAND_NO_RB
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-#ifdef NAND_NO_RB
-/* constant delay (see also tR in the datasheet) */
-#define NAND_WAIT_READY(nand) do { \
- udelay(12); \
-} while (0)
-#else
-/* use the R/B pin */
-/* TBD */
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-#endif
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
#define CONFIG_CMD_CDP
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#endif
-/************************************************************
- * Disk-On-Chip configuration
- ************************************************************/
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-#define CONFIG_SYS_DOC_SHORT_TIMEOUT
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
#define CONFIG_MPC8313 1
#define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI
#define CONFIG_MISC_INIT_R
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_SM850 1 /*...on a MPC850 Service Module */
-#undef CONFIG_8xx_CONS_SMC1 /* SMC1 not usable because Ethernet on SCC3 */
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_DATE
-
-#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition */
-#undef CONFIG_CMD_MTDPARTS
-
-/*
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0x00780000
-#define CONFIG_JFFS2_PART_OFFSET 0x00080000
-*/
-
-#define CONFIG_JFFS2_DEV "nand0"
-#define CONFIG_JFFS2_PART_SIZE 0x00200000
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=sixnet-0,nand0=sixnet-nand"
-#define MTDPARTS_DEFAULT "mtdparts=sixnet-0:7680k@512k();sixnet-nand:2m(jffs2-nand)"
-*/
-
-/* NAND flash support */
-#define CONFIG_NAND_LEGACY
-#define CONFIG_MTD_NAND_ECC_JFFS2
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-/* DFBUSY is available on Port C, bit 12; 0 if busy */
-#define NAND_WAIT_READY(nand) \
- while (!(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & 0x0008));
-#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr))
-#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr))
-#define WRITE_NAND(d, adr) \
- do { (*(volatile uint8_t *)(adr) = (uint8_t)(d)); } while (0)
-#define READ_NAND(adr) (*(volatile uint8_t *)(adr))
-#define CLE_LO 0x01 /* 0 selects CLE mode (CLE high) */
-#define ALE_LO 0x02 /* 0 selects ALE mode (ALE high) */
-#define CE_LO 0x04 /* 1 selects chip (CE low) */
-#define nand_setcr(cr, val) do {*(volatile uint8_t*)(cr) = (val);} while (0)
-#define NAND_DISABLE_CE(nand) \
- nand_setcr((nand)->IO_ADDR + 1, ALE_LO | CLE_LO)
-#define NAND_ENABLE_CE(nand) \
- nand_setcr((nand)->IO_ADDR + 1, CE_LO | ALE_LO | CLE_LO)
-#define NAND_CTL_CLRALE(nandptr) \
- nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
-#define NAND_CTL_SETALE(nandptr) \
- nand_setcr((nandptr) + 1, CE_LO | CLE_LO)
-#define NAND_CTL_CLRCLE(nandptr) \
- nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
-#define NAND_CTL_SETCLE(nandptr) \
- nand_setcr((nandptr) + 1, CE_LO | ALE_LO)
-
/*
* Miscellaneous configurable options
*/
/* 'cpuclk' variable with valid value) */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
#endif
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
#endif
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
WRITE_NAND(d, addr); \
} while(0)
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
#endif /* CONFIG_CMD_NAND */
#define CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
/* PCI1 host bridge */
-#define CONFIG_SYS_PCI1_MEM_BASE 0xc0000000
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
#ifdef CONFIG_PCI
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
#else
#define CONFIG_SYS_IBAT3L (0)
#define CONFIG_SYS_IBAT3U (0)
#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
/* NAND FLASH */
#ifdef CONFIG_NAND
-#undef CONFIG_NAND_LEGACY
-
#define CONFIG_NAND_FSL_UPM 1
#define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */
#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
#endif /* CONFIG_NAND */
/*
#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
#endif
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
/* 'cpuclk' variable with valid value) */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_DOS_PARTITION 1
/* Enable needed helper functions */
-#define CONFIG_SYS_DEVICE_DEREGISTER /* needs device_deregister */
+#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
/************************************************************
* RTC
#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
-/*-----------------------------------------------------------------------
- * NAND flash settings
- */
-#if defined(CONFIG_CMD_NAND)
-
-#define CONFIG_NAND_LEGACY
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-#define NAND_WAIT_READY(nand) NF_WaitRB()
-
-#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
-#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
-
-
-#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
-#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
-#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
-#define WRITE_NAND(d, adr) NF_Write(d)
-#define READ_NAND(adr) NF_Read()
-/* the following functions are NOP's because S3C24X0 handles this in hardware */
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1
-#define CONFIG_MTD_NAND_ECC_JFFS2 1
-
-#endif
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
--- /dev/null
+/*
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * config for XPedite1000 from XES Inc.
+ * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
+ * (C) Copyright 2003 Sandburst Corporation
+ * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_XPEDITE1000 1
+#define CONFIG_SYS_BOARD_NAME "XPedite1000"
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_440 1
+#define CONFIG_440GX 1 /* 440 GX */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+/*
+ * DDR config
+ */
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
+#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */
+#define CONFIG_VERY_BIG_RAM 1
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
+#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
+#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
+#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
+#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x0400000
+#define CONFIG_SYS_MEMTEST_END 0x0C00000
+
+/* POST support */
+#define CONFIG_POST (CONFIG_SYS_POST_RTC | \
+ CONFIG_SYS_POST_I2C)
+
+/*
+ * LED support
+ */
+#define USR_LED0 0x00000080
+#define USR_LED1 0x00000100
+#define USR_LED2 0x00000200
+#define USR_LED3 0x00000400
+
+#ifndef __ASSEMBLY__
+extern unsigned long in32(unsigned int);
+extern void out32(unsigned int, unsigned long);
+
+#define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0))
+#define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1))
+#define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2))
+#define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3))
+
+#define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED0))
+#define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED1))
+#define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED2))
+#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3))
+#endif
+
+/*
+ * Use internal SRAM for initial stack
+ */
+#define CONFIG_SYS_TEMP_STACK_OCM 1
+#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 3
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, 0xf0000000, 0xf4000000 }
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST /* MirrorBit flashes are optional */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7f
+#define CONFIG_I2C_MULTI_BUS
+
+/* I2C EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C RTC: STMicro M41T00 */
+#define CONFIG_RTC_M41T11 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
+
+/*
+ * PCI
+ */
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */
+
+/*
+ * Networking options
+ */
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_ETHPRIME "ppc_4xx_eth2"
+#define CONFIG_PHY_ADDR 4 /* PHY address phy0 not populated */
+#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */
+#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */
+#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */
+#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SNTP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
+#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_PREBOOT /* enable preboot variable */
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
+#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE 0x8000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff U-Boot (512 KB)
+ * fff40000 - fff7ffff U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff FDT (256KB)
+ * ffc00000 - ffefffff OS image (3MB)
+ * ff000000 - ffbfffff OS Use/Filesystem (12MB)
+ */
+
+#define CONFIG_UBOOT_ENV_ADDR MK_STR(TEXT_BASE)
+#define CONFIG_FDT_ENV_ADDR MK_STR(0xfff00000)
+#define CONFIG_OS_ENV_ADDR MK_STR(0xffc00000)
+
+#define CONFIG_PROG_UBOOT \
+ "$download_cmd $loadaddr $ubootfile; " \
+ "if test $? -eq 0; then " \
+ "protect off "CONFIG_UBOOT_ENV_ADDR" +80000; " \
+ "erase "CONFIG_UBOOT_ENV_ADDR" +80000; " \
+ "cp.w $loadaddr "CONFIG_UBOOT_ENV_ADDR" 40000; " \
+ "protect on "CONFIG_UBOOT_ENV_ADDR" +80000; " \
+ "cmp.b $loadaddr "CONFIG_UBOOT_ENV_ADDR" 80000; " \
+ "if test $? -ne 0; then " \
+ "echo PROGRAM FAILED; " \
+ "else; " \
+ "echo PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_BOOT_OS_NET \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "if test -n $fdtaddr; then " \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "bootm $osaddr - $fdtaddr; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi; " \
+ "else; " \
+ "bootm $osaddr; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_OS \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_OS_ENV_ADDR" +$filesize; " \
+ "cp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \
+ "cmp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo OS PROGRAM FAILED; " \
+ "else; " \
+ "echo OS PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_FDT \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_FDT_ENV_ADDR" +$filesize;" \
+ "cp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \
+ "cmp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo FDT PROGRAM FAILED; " \
+ "else; " \
+ "echo FDT PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autoload=yes\0" \
+ "download_cmd=tftp\0" \
+ "console_args=console=ttyS0,115200\0" \
+ "root_args=root=/dev/nfs rw\0" \
+ "misc_args=ip=on\0" \
+ "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+ "bootfile=/home/user/file\0" \
+ "osfile=/home/user/uImage-XPedite1000\0" \
+ "fdtfile=/home/user/xpedite1000.dtb\0" \
+ "ubootfile=/home/user/u-boot.bin\0" \
+ "fdtaddr=c00000\0" \
+ "osaddr=0x1000000\0" \
+ "loadaddr=0x1000000\0" \
+ "prog_uboot="CONFIG_PROG_UBOOT"\0" \
+ "prog_os="CONFIG_PROG_OS"\0" \
+ "prog_fdt="CONFIG_PROG_FDT"\0" \
+ "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
+ "bootcmd_flash=run set_bootargs; " \
+ "bootm "CONFIG_OS_ENV_ADDR" - "CONFIG_FDT_ENV_ADDR"\0" \
+ "bootcmd=run bootcmd_flash\0"
+#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * config for XPedite1000 from XES Inc.
- * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
- * (C) Copyright 2003 Sandburst Corporation
- * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_440 1
-#define CONFIG_440GX 1 /* 440 GX */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#define CONFIG_MISC_INIT_R
-#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time! */
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_RTC | \
- CONFIG_SYS_POST_I2C)
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* start of monitor */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
-#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
-#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
-#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
-
-#define USR_LED0 0x00000080
-#define USR_LED1 0x00000100
-#define USR_LED2 0x00000200
-#define USR_LED3 0x00000400
-
-#ifndef __ASSEMBLY__
-extern unsigned long in32(unsigned int);
-extern void out32(unsigned int, unsigned long);
-
-#define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0))
-#define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1))
-#define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2))
-#define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3))
-
-#define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED0))
-#define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED1))
-#define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED2))
-#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3))
-#endif
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
- * The DS1743 code assumes this condition (i.e. -- it assumes the base
- * address for the RTC registers is:
- *
- * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
- *
- *----------------------------------------------------------------------*/
-/* TBS: Xpedite 1000 has STMicro M41T00 via IIC */
-#define CONFIG_RTC_M41T11 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 2000
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */
-#define CONFIG_VERY_BIG_RAM 1
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7f
-#define CONFIG_SYS_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69} /* Don't probe these addrs */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_SIZE 0x100 /* Size of Environment vars */
-#define CONFIG_ENV_OFFSET 0x100
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* this is actually the second page of the eeprom */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#define CONFIG_BOOTARGS "root=/dev/hda1 "
-#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
-#define CONFIG_BOOTDELAY 5 /* disable autoboot */
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address phy0 not populated */
-#define CONFIG_PHY1_ADDR 1 /* PHY address phy1 not populated */
-#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */
-#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */
-#define CONFIG_NET_MULTI 1
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */
-#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_FAT
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-#endif /* __CONFIG_H */
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
/* PEX8518 slave I2C interface */
#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
/*
* Boot Flags
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
{0xfbf40000, 0xc0000} }
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
/*
* Boot Flags
*/
#define CONFIG_SYS_NAND_BASE 0xef800000
#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
+#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
+ CONFIG_SYS_NAND_BASE2}
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */
+#define CONFIG_NAND_FSL_ELBC
/*
* NOR flash configuration
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
{0xf7f40000, 0xc0000} }
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SNTP
/*
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
/*
* Boot Flags
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* NOR flash - no real flash on this board */
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the 40x Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
/*
* Internal Definitions
" console=" xstr(CONFIG_USE_TTY) ",${baudrate}\0" \
CONFIG_ADDMISC \
"initrd_high=30000000\0" \
- "kernel_addr_r=400000\0" \
- "fdt_addr_r=800000\0" \
- "ramdisk_addr_r=C00000\0" \
+ "kernel_addr_r=1000000\0" \
+ "fdt_addr_r=1800000\0" \
+ "ramdisk_addr_r=1900000\0" \
"hostname=" xstr(CONFIG_HOSTNAME) "\0" \
"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SMC9118 */
-#define CONFIG_DRIVER_SMC911X 1
-#define CONFIG_DRIVER_SMC911X_32_BIT 1
-#define CONFIG_DRIVER_SMC911X_BASE 0xB6080000
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_32_BIT 1
+#define CONFIG_SMC911X_BASE 0xB6080000
/* MEMORY */
#define AP325RXA_SDRAM_BASE (0x88000000)
#define CONFIG_ENV_IS_IN_ONENAND 1
#define CONFIG_ENV_ADDR 0x00020000
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
#ifdef CONFIG_SYS_USE_UBI
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "onenand0=onenand"
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SPEED 100000
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
-#endif
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+#endif
+
/* Ethernet */
#define CONFIG_MACB 1
#define CONFIG_RMII 1
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-
-#define CONFIG_NAND_LEGACY
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
-#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
#include <asm/arch/AT91RM9200.h> /* needed for port definitions */
-#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
-#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
-
-#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-/* the following are NOP's in our implementation */
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
*/
#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* NOR flash - no real flash on this board */
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* NOR flash - no real flash on this board */
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
/* NOR flash, if populated */
#ifndef CONFIG_CMD_NAND
#define CONFIG_SYS_NO_FLASH 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#else
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet - not present */
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
+#define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */
/*
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_ROOTPATH /romfs
-/* Use a fixed MAC address for booting up. Firstboot linux
- * must fetch a valid MAC from the production server. */
-#define CONFIG_ETHADDR 02:80:ad:20:31:42
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:42 */
/*
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_ROOTPATH /romfs
-/* Use a fixed MAC address for booting up. Firstboot linux
- * must fetch a valid MAC from the production server. */
-#define CONFIG_ETHADDR 02:80:ad:20:31:42
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:42 */
/*
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
-#define CONFIG_DRIVER_SMC911X 1
-#define CONFIG_DRIVER_SMC911X_BASE 0x24000000
-#define CONFIG_DRIVER_SMC911X_16_BIT
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_BASE 0x24000000
+#define CONFIG_SMC911X_16_BIT
#define CONFIG_HOSTNAME bf548-ezkit
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
+
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
#define CONFIG_DTT_AD7414 1 /* use AD7414 */
/*
* Commands additional to the ones defined in amcc-common.h
*/
+#define CONFIG_CMD_CHIP_CONFIG
#if defined(CONFIG_ARCHES)
#define CONFIG_CMD_DTT
#define CONFIG_CMD_PCI
#define CONFIG_CMD_FAT
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SATA
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
#endif /* CONFIG_ARCHES */
#endif /* CONFIG_460GT */
+/*
+ * SATA driver setup
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_SATA_DWC
+#define CONFIG_LIBATA
+#define SATA_BASE_ADDR 0xe20d1000 /* PPC460EX SATA Base Address */
+#define SATA_DMA_REG_ADDR 0xe20d0800 /* PPC460EX SATA Base Address */
+#define CONFIG_SYS_SATA_MAX_DEVICE 1 /* SATA MAX DEVICE */
+/* Convert sectorsize to wordsize */
+#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
+#endif
+
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
-#define CONFIG_DRIVER_SMC911X 1
-#define CONFIG_DRIVER_SMC911X_BASE 0x24000000
-#define CONFIG_DRIVER_SMC911X_16_BIT
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_BASE 0x24000000
+#define CONFIG_SMC911X_16_BIT
#define CONFIG_HOSTNAME cm-bf548
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:24:31:91 */
#define CONFIG_SMC91111_BASE 0x28000300
/* The next 3 lines are for use with EXT-BF5xx-USB-ETH2 */
/* #define CONFIG_DRIVER_SMC911X 1 */
-/* #define CONFIG_DRIVER_SMC911X_BASE 0x24080000 // AMS1 */
+/* #define CONFIG_DRIVER_SMC911X_BASE 0x24080000 /! AMS1 */
/* #define CONFIG_DRIVER_SMC911X_32_BIT 1 */
#define CONFIG_HOSTNAME cm-bf561
/* Uncomment next line to use fixed MAC address */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on include/configs/canyonlands.h
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * compactcenter.h - configuration for CompactCenter (460EX)
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+/*
+ * This config file is used for CompactCenter and DevCon-Center
+ */
+#define CONFIG_460EX 1 /* Specific PPC460EX */
+#ifdef CONFIG_DEVCONCENTER
+#define CONFIG_HOSTNAME devconcenter
+#define CONFIG_IDENT_STRING " devconcenter 0.02"
+#else
+#define CONFIG_HOSTNAME compactcenter
+#define CONFIG_IDENT_STRING " compactcenter 0.02"
+#endif
+#define CONFIG_440 1
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#include "amcc-common.h"
+
+#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+#define CONFIG_BOARD_TYPES 1 /* support board types */
+#define CONFIG_FIT
+#define CFG_ALT_MEMTEST
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
+#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
+#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
+
+/* EBC stuff */
+#ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */
+#define CONFIG_SYS_FLASH_BASE 0xF8000000 /* later mapped here */
+#define CONFIG_SYS_FLASH_SIZE (128 << 20)
+#else
+#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped here */
+#define CONFIG_SYS_FLASH_SIZE (64 << 20)
+#endif
+
+#define CONFIG_SYS_NVRAM_BASE 0xE0000000
+#define CONFIG_SYS_UART_BASE 0xE0100000
+#define CONFIG_SYS_IO_BASE 0xE0200000
+
+#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
+#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
+#ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */
+#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xC8000000
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
+#endif
+#define CONFIG_SYS_FLASH_BASE_PHYS \
+ (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
+ | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
+
+#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
+#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
+#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
+
+#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */
+
+#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */
+
+/*
+ * Initial RAM & stack pointer (placed in OCM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
+#define CONFIG_SYS_INIT_RAM_END (4 << 10)
+#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Serial Port
+ */
+#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */
+
+/*
+ * Environment
+ */
+/*
+ * Define here the location of the environment variables (FLASH).
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
+
+/*
+ * FLASH related
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#ifdef CONFIG_DEVCONCENTER
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max num of sectors per chip*/
+#else
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
+#endif
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buff'd writes (20x faster) */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*
+ * DDR SDRAM
+ */
+
+#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
+
+#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
+#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
+#undef CONFIG_PPC4xx_DDR_METHOD_A
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+/* Memory Queue */
+#define CONFIG_SYS_SDRAM_R0BAS 0x0000f800
+#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
+#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
+#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
+#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
+#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
+#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C80
+#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80
+#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
+
+/* SDRAM Controller */
+#define CONFIG_SYS_SDRAM0_MB0CF 0x00000201
+#define CONFIG_SYS_SDRAM0_MB1CF 0x00000000
+#define CONFIG_SYS_SDRAM0_MB2CF 0x00000000
+#define CONFIG_SYS_SDRAM0_MB3CF 0x00000000
+#define CONFIG_SYS_SDRAM0_MCOPT1 0x05122000
+#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
+#define CONFIG_SYS_SDRAM0_MODT0 0x00000000
+#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
+#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
+#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
+#define CONFIG_SYS_SDRAM0_CODT 0x00000020
+#define CONFIG_SYS_SDRAM0_RTR 0x06180000
+#define CONFIG_SYS_SDRAM0_INITPLR0 0xA8380000
+#define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400
+#define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000
+#define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000
+#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010000
+#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000542
+#define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400
+#define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000
+#define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000
+#define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000
+#define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000
+#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442
+#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010380
+#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010000
+#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
+#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
+#define CONFIG_SYS_SDRAM0_RQDC 0x80000038
+#define CONFIG_SYS_SDRAM0_RFDC 0x003F0000
+#define CONFIG_SYS_SDRAM0_RDCC 0x80000000
+#define CONFIG_SYS_SDRAM0_DLCR 0x00000000
+#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
+#define CONFIG_SYS_SDRAM0_WRDTR 0x84000800
+#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
+#define CONFIG_SYS_SDRAM0_SDTR2 0x32204232
+#define CONFIG_SYS_SDRAM0_SDTR3 0x090B0D15
+#define CONFIG_SYS_SDRAM0_MMODE 0x00000442
+#define CONFIG_SYS_SDRAM0_MEMODE 0x00000000
+
+#define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
+
+/* I2C SYSMON */
+#define CONFIG_DTT_LM63 1 /* National LM63 */
+#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
+#define CONFIG_DTT_PWM_LOOKUPTABLE \
+ { { 40, 10 }, { 50, 20 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT 0xa10
+
+/* RTC configuration */
+#define CONFIG_RTC_DS1337 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/*
+ * Ethernet
+ */
+#define CONFIG_IBM_EMAC4_V4 1
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
+#define CONFIG_PHY1_ADDR 3
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CONFIG_PHY_DYNAMIC_ANEG 1
+
+/*
+ * USB-OHCI
+ */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#undef CONFIG_SYS_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors*/
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */
+#define CONFIG_SYS_OHCI_USE_NPS /* force NoPowerSwitching mode */
+#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000)
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ "kernel_addr=fc000000\0" \
+ "fdt_addr=fc1e0000\0" \
+ "ramdisk_addr=fc200000\0" \
+ "pciconfighost=1\0" \
+ "pcie_mode=RP:RP\0" \
+ ""
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CHIP_CONFIG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * PCI stuff
+ */
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+#define CONFIG_PCI_DISABLE_PCIE
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
+#undef CONFIG_SYS_PCI_MASTER_INIT
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/*
+ * CompactCenter has 64MBytes of NOR FLASH (Spansion 29GL512), but the
+ * boot EBC mapping only supports a maximum of 16MBytes
+ * (4.ff00.0000 - 4.ffff.ffff).
+ * To solve this problem, the FLASH has to get remapped to another
+ * EBC address which accepts bigger regions:
+ *
+ * 0xfc00.0000 -> 4.cc00.0000
+ */
+
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP 0x10055e00
+#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
+
+/* Memory Bank 1 (NVRAM) initialization */
+#define CONFIG_SYS_EBC_PB1AP 0x02815480
+/* BAS=NVRAM,BS=1MB,BU=R/W,BW=8bit*/
+#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NVRAM_BASE | 0x18000)
+
+/* Memory Bank 2 (UART) initialization */
+#define CONFIG_SYS_EBC_PB2AP 0x02815480
+/* BAS=UART,BS=1MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_UART_BASE | 0x1A000)
+
+/* Memory Bank 3 (IO) initialization */
+#define CONFIG_SYS_EBC_PB3AP 0x02815480
+/* BAS=IO,BS=1MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_IO_BASE | 0x1A000)
+
+/*
+ * PPC4xx GPIO Configuration
+ */
+/* 460EX: Use USB configuration */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
+{ \
+/* GPIO Core 0 */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
+}, \
+{ \
+/* GPIO Core 1 */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
+{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 USB_SERVICE_SUSPEND_N */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO51 SPI_CSS_N */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO52 FPGA_PROGRAM_UC_N */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 FPGA_INIT_UC_N */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO54 WD_STROBE */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 LED_2_OUT */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO56 LED_1_OUT */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO61 STARTUP_FINISHED_N */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO62 STARTUP_FINISHED */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 SERVICE_PORT_ACTIVE */ \
+} \
+}
+
+#endif /* __CONFIG_H */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_PING
-#ifdef NAND_SUPPORT_HAS_BEEN_FIXED /* NAND support is broken / unimplemented */
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
-#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
-
-#include <asm/arch/AT91RM9200.h> /* needed for port definitions */
-#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
-#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
-
-#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-/* the following are NOP's in our implementation */
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-
-#endif /* NAND_SUPPORT_HAS_BEEN_FIXED */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/*=====================*/
/* Board related stuff */
/*=====================*/
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/* I2C switch definitions for PCA9543 chip */
#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70
#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
/*
* NAND Flash
*/
-#undef CONFIG_NAND_LEGACY
-
#define CONFIG_SYS_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
#undef CONFIG_SYS_NAND1_BASE
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/* nand timeout values */
#define CONFIG_SYS_NAND_PROG_ERASE_TO 3000
#define CONFIG_SYS_NAND_OTHER_TO 100
#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE 1
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_ENV_IS_IN_NAND 1
*/
#define CONFIG_SYS_LONGHELP
#define CONFIG_AUTO_COMPLETE 1
+#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP 1 /* this is a PPC405 CPU */
+#define CONFIG_4xx 1 /* member of PPC4xx family */
+#define CONFIG_DLVISION 1 /* on a Neo board */
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME dlvision
+#define CONFIG_IDENT_STRING " dlvision 0.01"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
+#define CONFIG_MISC_INIT_R /* call misc_init_r */
+
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+
+/*
+ * Configure PLL
+ */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ "kernel_addr=fc000000\0" \
+ "fdt_addr=fc1e0000\0" \
+ "ramdisk_addr=fc200000\0" \
+ ""
+
+#define CONFIG_PHY_ADDR 4 /* PHY address */
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
+#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
+#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD 691200
+
+/*
+ * I2C stuff
+ */
+#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address*/
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CONFIG_SYS_FLASH_BASE 0xFC000000
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#endif
+
+/*
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
+} \
+}
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
+#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP 0x92015480
+/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
+
+/* Memory Bank 1 (NVRAM) initializatio */
+#define CONFIG_SYS_EBC_PB1AP 0x92015480
+/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB1CR 0xFB858000
+
+/* Memory Bank 2 (UART) initialization */
+#define CONFIG_UART_BASE 0x7f100000
+#define CONFIG_SYS_EBC_PB2AP 0x92015480
+/* BAS=0x7f1,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB2CR 0x7f118000
+
+/* Memory Bank 3 (Latches) initialization */
+#define CONFIG_SYS_LATCH_BASE 0x7f200000
+#define CONFIG_SYS_EBC_PB3AP 0x92015480
+/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
+
+#endif /* __CONFIG_H */
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
/* Enable needed helper functions */
-#define CONFIG_SYS_DEVICE_DEREGISTER /* needs device_deregister */
+#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
#endif
/*
"prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0"
-#define CONFIG_DRIVER_SMC911X 1
-#define CONFIG_DRIVER_SMC911X_BASE (CS4_BASE + 0x00020000)
-#define CONFIG_DRIVER_SMC911X_32_BIT 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_BASE (CS4_BASE + 0x00020000)
+#define CONFIG_SMC911X_32_BIT 1
/*
* Miscellaneous configurable options
"prg_jffs2=tftpboot 0x80000000 $(jffs2); erase 0xa01c0000 0xa1ffffff; cp.b 0x80000000 0xa01c0000 $(filesize)\0"
-#define CONFIG_DRIVER_SMC911X 1
-#define CONFIG_DRIVER_SMC911X_BASE 0xa8000000
-#define CONFIG_DRIVER_SMC911X_32_BIT 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_BASE 0xa8000000
+#define CONFIG_SMC911X_32_BIT 1
/*
* Miscellaneous configurable options
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_JFFS2_CMDLINE
+#define CONFIG_CMD_MTDPARTS
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */
#define CONFIG_I2C_MULTI_BUS 1
-#define CONFIG_SYS_MAX_I2C_BUS 2
+#define CONFIG_SYS_MAX_I2C_BUS 1
#define CONFIG_SYS_I2C_INIT_BOARD 1
#define CONFIG_I2C_MUX 1
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */
+
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for UBI/UBIFS */
+
+/* UBI Support for all Keymile boards */
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_CONCAT
+
/* define this to use the keymile's io muxing feature */
/*#define CONFIG_IO_MUXING */
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
*
* DDR Autocalibration Method_B is the default.
*/
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
#undef CONFIG_PPC4xx_DDR_METHOD_A
+#endif
#define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
*----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
/* Standard DTT sensor configuration */
#define CONFIG_DTT_DS1775 1
/*
* Commands additional to the ones defined in amcc-common.h
*/
+#define CONFIG_CMD_CHIP_CONFIG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_LOG
#define CONFIG_CMD_NAND
#define CONFIG_SYS_FLASH_BASE 0xf0000000
#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */
/*
* For booting Linux, the board info and command line data
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
-#define CONFIG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */
#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
-#undef CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_MISC_INIT_R 1
/*
* System Clock Setup
#undef CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
/*
* Initial RAM Base Address Setup
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
-#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
/* Address and size of Redundant Environment Sector */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_I2C_MULTI_BUS 1
-#define CONFIG_SYS_MAX_I2C_BUS 2
#define CONFIG_I2C_MUX 1
/* EEprom support */
#define CONFIG_SYS_DTT_MAX_TEMP 70
#define CONFIG_SYS_DTT_LOW_TEMP -30
#define CONFIG_SYS_DTT_HYSTERESIS 3
-#define CONFIG_SYS_DTT_BUS_NUM (2)
+#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
-#define MTDIDS_DEFAULT "nor0=app"
+#define MTDIDS_DEFAULT "nor2=app"
#define MTDPARTS_DEFAULT \
"mtdparts=app:256k(u-boot),128k(env),128k(envred)," \
"1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)"
*/
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
#define CONFIG_SYS_PROMPT_HUSH_PS2 ">>"
#define CONFIG_SYS_MAX_NAND_DEVICE 0 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet */
"addcon=setenv bootargs ${bootargs} " \
"console=ttyCPM0,${baudrate}\0" \
"mtdids=nor0=boot,nor1=app \0" \
- "mtdparts=mtdparts=boot:384k(u-boot),128k(env),128k(envred)," \
- "3456k(free);app:3m(esw0),10m(rootfs0),3m(esw1)," \
- "10m(rootfs1),1m(var),5m(cfg) \0" \
"partition=nor1,5 \0" \
"new_env=prot off FE060000 FE09FFFF; era FE060000 FE09FFFF \0" \
"EEprom_ivm=pca9544a:70:4 \0" \
- "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \
+ "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \
+ "unlock=yes\0" \
""
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_SIZE 32
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_BASE_1 0x50000000
-#define CONFIG_SYS_FLASH_SIZE_1 64
+#define CONFIG_SYS_FLASH_SIZE_1 32
+#define CONFIG_SYS_FLASH_BASE_2 0x52000000
+#define CONFIG_SYS_FLASH_SIZE_2 32
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
+ CONFIG_SYS_FLASH_BASE_1, \
+ CONFIG_SYS_FLASH_BASE_2 }
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
-#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1) |\
- ORxG_CSNT | ORxG_ACS_DIV2 |\
- ORxG_SCY_5_CLK | ORxG_TRLX )
+#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
+ CONFIG_SYS_FLASH_SIZE_2) |\
+ ORxG_CSNT | ORxG_ACS_DIV2 |\
+ ORxG_SCY_5_CLK | ORxG_TRLX )
#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
#define CONFIG_DISABLE_CONSOLE 1 /* disable console */
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
+#define CONFIG_LCD 1
+
/*
* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
* data on the serial line may interrupt the boot sequence.
#define CONFIG_MMC 1
#define CONFIG_ATMEL_MCI 1
+#if defined(CONFIG_LCD)
+#define CONFIG_CMD_BMP
+#define CONFIG_ATMEL_LCD 1
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_BMP_16BPP 1
+#define CONFIG_FB_ADDR 0x10600000
+#define CONFIG_WHITE_ON_BLACK 1
+#define CONFIG_VIDEO_BMP_GZIP 1
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE 262144
+#define CONFIG_ATMEL_LCD_BGR555 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+#define CONFIG_SPLASH_SCREEN 1
+#endif
+
#define CONFIG_SYS_DCACHE_LINESZ 32
#define CONFIG_SYS_ICACHE_LINESZ 32
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_DEVICE_DEREGISTER /* needs device_deregister */
+#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_MV88F6281GTW_GE_H
+#define _CONFIG_MV88F6281GTW_GE_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING "\nMarvell-MV88F6281GTW_GE"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL 1
+#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
+#define CONFIG_KW88F6281 1 /* SOC Name */
+#define CONFIG_MACH_MV88F6281GTW_GE /* Machine type */
+
+#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
+
+/*
+ * CLKs configurations
+ */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
+ 115200,230400, 460800, 921600 }
+/* auto boot */
+#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
+
+#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_USB
+
+/*
+ * Flash configuration
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH 1
+#define CONFIG_HARD_SPI 1
+#define CONFIG_KIRKWOOD_SPI 1
+#define CONFIG_SPI_FLASH_MACRONIX 1
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */
+#endif
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */
+#else
+#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
+#endif
+#define CONFIG_ENV_SIZE 0x1000 /* 4k */
+#define CONFIG_ENV_ADDR 0x30000
+#define CONFIG_ENV_OFFSET 0x30000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
+ "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
+ "${x_bootcmd_usb}; bootm 0x6400000;"
+
+#define CONFIG_MTDPARTS "spi0.0:512k(uboot)," \
+ "512k@512k(psm),2m@1m(kernel),13m@3m(rootfs)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
+ "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
+ "x_bootcmd_kernel=cp.b 0xE8100000 0x6400000 0x200000\0" \
+ "x_bootcmd_usb=usb start\0" \
+ "x_bootargs_root=root=/dev/mtdblock3 ro rootfstype=squashfs\0"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS 4
+#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
+#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
+#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
+#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * Marvell 88Exxxx Switch configurations
+ */
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init phy/swtich */
+#define CONFIG_MV88E61XX_SWITCH /* Enable mv88e61xx switch driver */
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI /* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_CMD_USB */
+
+#endif /* _CONFIG_MV88F6281GTW_GE_H */
"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
"tftpboot 0x81000000 uImage-mx31; bootm\0"
-#define CONFIG_DRIVER_SMC911X 1
-#define CONFIG_DRIVER_SMC911X_BASE 0xB6000000
-#define CONFIG_DRIVER_SMC911X_32_BIT 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_BASE 0xB6000000
+#define CONFIG_SMC911X_32_BIT 1
/*
* Miscellaneous configurable options
#define CONFIG_SYS_NAND_BASE 0x04000000 + (2 << 23)
#define NAND_ALLOW_ERASE_ALL 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
#define CONFIG_SYS_64BIT_VSPRINTF /* mtd desires this */
-#define CONFIG_MISC_INIT_R /* call misc_init_r during start up */
+#define BOARD_LATE_INIT /* call board_late_init during start up */
/* timing informazion */
#define CONFIG_SYS_HZ 1000 /* Mandatory... */
#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
#define CONFIG_PL011_CLOCK 48000000
+/* i2c, for the port extenders (uses gpio.c in board directory) */
+#ifndef __ASSEMBLY__
+#include <asm/arch/gpio.h>
+#define CONFIG_CMD_I2C
+#define CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C_SPEED 400000
+#define __SDA 63
+#define __SCL 62
+#define I2C_SDA(x) nmk_gpio_set(__SDA, x)
+#define I2C_SCL(x) nmk_gpio_set(__SCL, x)
+#define I2C_READ (nmk_gpio_get(__SDA)!=0)
+#define I2C_ACTIVE nmk_gpio_dir(__SDA, 1)
+#define I2C_TRISTATE nmk_gpio_dir(__SDA, 0)
+#define I2C_DELAY (udelay(2))
+#endif /* __ASSEMBLY__ */
+
/* Ethernet */
#define PCI_MEMORY_VADDR 0xe8000000
#define PCI_IO_VADDR 0xee000000
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
-
-/*
- * Board NAND Info.
- */
-#define CONFIG_NAND_LEGACY
-#define CONFIG_SYS_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)
-#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0)
-#define READ_NAND(adr) (*(volatile u16 *)0x6800A084)
-#define NAND_WAIT_READY(nand) udelay(10)
-
-#define NAND_NO_RB 1
-
-#define CONFIG_SYS_NAND_WP
-#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
-#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
-
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-
#define CONFIG_BOOTDELAY 3
#ifdef NFS_BOOT_DEFAULTS
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+#define CONFIG_TWL4030_LED 1
+
/*
* Board NAND Info.
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+
/*
* Board NAND Info.
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
*/
#if defined(CONFIG_CMD_NET)
-#define CONFIG_DRIVER_SMC911X
-#define CONFIG_DRIVER_SMC911X_32_BIT
-#define CONFIG_DRIVER_SMC911X_BASE 0x2C000000
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE 0x2C000000
#endif /* (CONFIG_CMD_NET) */
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+#define CONFIG_TWL4030_LED 1
+
/*
* Board NAND Info.
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+#define CONFIG_TWL4030_LED 1
+
/*
* Board NAND Info.
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+#define CONFIG_TWL4030_LED 1
+
/*
* Board NAND Info.
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+#define CONFIG_TWL4030_LED 1
+
/*
* Board NAND Info.
*/
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/* Environment information */
#define CONFIG_BOOTDELAY 10
* NAND-FLASH stuff
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
+#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/*
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA16
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/* NOR flash */
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
#define CONFIG_CMD_JFFS2 1
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
#undef CONFIG_MEMSIZE_IN_BYTES
+#define CONFIG_LZMA
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */
#define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/*-----------------------------------------------------------------------
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_RD6281A_H
+#define _CONFIG_RD6281A_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING "\nMarvell-RD6281A"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL 1
+#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
+#define CONFIG_KW88F6281 1 /* SOC Name */
+#define CONFIG_MACH_RD6281A /* Machine type */
+
+#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
+
+/*
+ * CLKs configurations
+ */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
+ 115200,230400, 460800, 921600 }
+/* auto boot */
+#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
+
+#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL 1
+#endif
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE 0x20000 /* 128k */
+#define CONFIG_ENV_ADDR 0x40000
+#define CONFIG_ENV_OFFSET 0x40000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
+ "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
+ "${x_bootcmd_usb}; bootm 0x6400000;"
+
+#define CONFIG_MTDPARTS "orion_nand:512k(uboot)," \
+ "3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
+ "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
+ "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
+ "x_bootcmd_usb=usb start\0" \
+ "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS 4
+#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
+#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
+#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */
+#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
+#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */
+#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */
+#define CONFIG_PHY_BASE_ADR 0x0A
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init switch and PHY */
+#define CONFIG_MV88E61XX_SWITCH /* Enable MV88E61XX switch driver */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI /* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_CMD_USB */
+
+#endif /* _CONFIG_RD6281A_H */
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
/* Network interface */
-#define CONFIG_DRIVER_SMC911X
-#define CONFIG_DRIVER_SMC911X_16_BIT
-#define CONFIG_DRIVER_SMC911X_BASE (0x24000000)
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_BASE (0x24000000)
#endif /* __RSK7203_H */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_S3C2410
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-#define NAND_WAIT_READY(nand) NF_WaitRB()
-#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
-#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
-#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
-#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
-#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
-#define WRITE_NAND(d, adr) NF_Write(d)
-#define READ_NAND(adr) NF_Read()
-/* the following functions are NOP's because S3C24X0 handles this in hardware */
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
#endif /* CONFIG_CMD_NAND */
#define CONFIG_SETUP_MEMORY_TAGS
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
- "update=protect off fff00000 fff3ffff; " \
- "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
+ "update=protect off ff800000 ff83ffff; " \
+ "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
"upd=run load update\0" \
"fdtaddr=400000\0" \
"fdtfile=sbc8349.dtb\0" \
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x77D00000
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_SHEEVAPLUG_H
+#define _CONFIG_SHEEVAPLUG_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING "\nMarvell-Sheevaplug"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL 1
+#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
+#define CONFIG_KW88F6281 1 /* SOC Name */
+#define CONFIG_MACH_SHEEVAPLUG /* Machine type */
+
+#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
+
+/*
+ * CLKs configurations
+ */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
+ 115200,230400, 460800, 921600 }
+/* auto boot */
+#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
+
+#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL 1
+#endif
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE 0x20000 /* 128k */
+#define CONFIG_ENV_ADDR 0x40000
+#define CONFIG_ENV_OFFSET 0x40000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
+ "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
+ "${x_bootcmd_usb}; bootm 0x6400000;"
+
+#define CONFIG_MTDPARTS "orion_nand:512k(uboot)," \
+ "3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
+ "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
+ "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
+ "x_bootcmd_usb=usb start\0" \
+ "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS 4
+#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
+#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
+#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
+#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 0
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI /* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_CMD_USB */
+
+#endif /* _CONFIG_SHEEVAPLUG_H */
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63}
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/* Boot configuration (define only one of next 3) */
#define CONFIG_BOOT_NAND
/* None of these are currently implemented. Left from the original Samsung
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_CMD_NAND
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/* LIME GDC */
#define CONFIG_SYS_LIME_BASE 0xc8000000
#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define NAND_SIZE 0x00010000 /* 64K */
#define NAND_BASE 0xF1000000
-/****************************************************************/
-
-/* NAND */
-#define CONFIG_NAND_LEGACY
-#define CONFIG_SYS_NAND_BASE NAND_BASE
-#define CONFIG_MTD_NAND_ECC_JFFS2
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_MTD_NAND_UNSAFE
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#undef NAND_NO_RB
-
-#define SECTORSIZE 512
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */
-#define NAND_DISABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat) |= (1 << (15 - 7)); \
- } while(0)
-
-#define NAND_ENABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \
- } while(0)
-
-#define NAND_CTL_CLRALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \
- } while(0)
-
-#define NAND_CTL_SETALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) |= (1 << (15 - 15)); \
- } while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \
- } while(0)
-
-#define NAND_CTL_SETCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |= (1 << (31 - 23)); \
- } while(0)
-
-#ifndef NAND_NO_RB
-#define NAND_WAIT_READY(nand) \
- do { \
- int _tries = 0; \
- while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \
- if (++_tries > 100000) \
- break; \
- } while (0)
-#else
-#define NAND_WAIT_READY(nand) udelay(12)
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND_ADDRESS(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define READ_NAND(adr) \
- ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
-
/*****************************************************************************/
#define CONFIG_SYS_DIRECT_FLASH_TFTP
-#define CONFIG_SYS_DIRECT_NAND_TFTP
/*****************************************************************************/
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_DATE
-
-#define CONFIG_NAND_LEGACY
-
/*
* Miscellaneous configurable options
*/
/*
* SMSC91C11x Network Card
*/
-#define CONFIG_DRIVER_SMC911X
-#define CONFIG_DRIVER_SMC911X_BASE 0x00000000
-#define CONFIG_DRIVER_SMC911X_32_BIT
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE 0x00000000
+#define CONFIG_SMC911X_32_BIT
#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_NET_MULTI
#endif
/*
#undef CONFIG_CMD_TERMINAL
#undef CONFIG_CMD_USB
-#undef CONFIG_DRIVER_SMC911X
+#undef CONFIG_SMC911X
#undef CONFIG_SOFT_I2C
#undef CONFIG_SOURCE
#undef CONFIG_SYS_LONGHELP
#define CONFIG_TQM8xxL 1
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
--- /dev/null
+/*
+ * esd vme8349 U-Boot configuration file
+ * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
+ *
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * reinhard.arlt@esd-electronics.de
+ * Based on the MPC8349EMDS config.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * vme8349 board configuration file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+#define CONFIG_MPC83xx 1 /* MPC83xx family */
+#define CONFIG_MPC834x 1 /* MPC834x family */
+#define CONFIG_MPC8349 1 /* MPC8349 specific */
+#define CONFIG_VME8349 1 /* ESD VME8349 board specific */
+
+#define CONFIG_PCI
+/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
+#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
+
+#define PCI_66M
+#ifdef PCI_66M
+#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
+#else
+#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifdef PCI_66M
+#define CONFIG_SYS_CLK_FREQ 66000000
+#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
+#else
+#define CONFIG_SYS_CLK_FREQ 33000000
+#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
+#endif
+#endif
+
+#define CONFIG_SYS_IMMR 0xE0000000
+
+#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END 0x00100000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
+#undef CONFIG_SPD_EEPROM /* dont use SPD EEPROM for DDR setup*/
+#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+#define CONFIG_DDR_2T_TIMING
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_SIZE 512 /* MB */
+
+#if (CONFIG_SYS_DDR_SIZE == 512)
+#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
+ CSCONFIG_COL_BIT_10 | \
+ CSCONFIG_BANK_BIT_3)
+#endif
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_TIMING_0 0x00220802
+#define CONFIG_SYS_DDR_TIMING_1 0x39377322
+#define CONFIG_SYS_DDR_TIMING_2 0x2f9848ca /* P9-45, tuning? */
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuf,no DYN_PWR */
+#define CONFIG_SYS_DDR_MODE 0x07940242
+#define CONFIG_SYS_DDR_MODE2 0x00000000
+/* autocharge,no open page */
+#define CONFIG_SYS_DDR_INTERVAL 0x04060100
+#define CONFIG_SYS_DDR_SDRAM_CFG 0x63000000
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x04061000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
+/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
+ (2 << BR_PS_SHIFT) | /* 32bit */ \
+ BR_V) /* valid */
+
+#define CONFIG_SYS_OR0_PRELIM 0xF8006FF7 /* 128 MB flash size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001A /* 128 MB window size */
+
+#define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801)
+#define CONFIG_SYS_OR1_PRELIM (0xffff8000 | 0x00000200)
+#define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000
+#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x0000000e)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
+
+#define CONFIG_SYS_MID_FLASH_JUMP 0x7F000000
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_END 0x1000 /* size */
+
+#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* size init data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+ CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Malloc size */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ * LCRR: DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LBC_LBCR 0x00000000
+
+#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
+
+#define CONFIG_CMDLINE_EDITING /* add command line history */
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* I2C */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_NOPROBES {{0, 0x69}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C1_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET
+/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */
+
+#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
+
+/* TSEC */
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define PCI_64BIT
+#define PCI_ONE_PCI1
+#if defined(PCI_64BIT)
+#undef PCI_ALL_PCI1
+#undef PCI_TWO_PCI1
+#undef PCI_ONE_PCI1
+#endif
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#define CONFIG_NET_MULTI
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xFIXME
+ #define PCI_ENET0_MEMADDR 0xFIXME
+ #define PCI_IDSEL_NUMBER 0xFIXME
+#endif
+
+#endif /* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+#define CONFIG_TSEC_ENET /* TSEC ethernet support */
+
+#if defined(CONFIG_TSEC_ENET)
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
+#endif
+
+#define CONFIG_GMII /* MII PHY management */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2
+#define CONFIG_TSEC2_NAME "TSEC1"
+#define CONFIG_PHY_M88E1111
+#define TSEC1_PHY_ADDR 0x08
+#define TSEC2_PHY_ADDR 0x10
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC0"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+ #define CONFIG_ENV_IS_IN_FLASH
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
+ #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+ #define CONFIG_ENV_SIZE 0x2000
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#else
+ #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
+ #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+ #define CONFIG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+#define CONFIG_SYS_RTC_BUS_NUM 0x01
+#define CONFIG_SYS_I2C_RTC_ADDR 0x32
+#define CONFIG_RTC_RX8025
+#define CONFIG_CMD_TSI148
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
+#endif
+
+#define CONFIG_CMD_ELF
+/* Pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+
+#if defined(CONFIG_CMD_KGDB)
+ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max num of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */
+#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Init Memory map for Linux*/
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
+
+#define CONFIG_SYS_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_CSB_TO_CLKIN |\
+ HRCWL_VCO_1X2 |\
+ HRCWL_CORE_TO_CSB_2X1)
+
+#if defined(PCI_64BIT)
+#define CONFIG_SYS_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_64_BIT_PCI |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_PCI2_ARBITER_DISABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_TSEC1M_IN_GMII |\
+ HRCWH_TSEC2M_IN_GMII)
+#else
+#define CONFIG_SYS_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_32_BIT_PCI |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_PCI2_ARBITER_ENABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_TSEC1M_IN_GMII |\
+ HRCWH_TSEC2M_IN_GMII)
+#endif
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH 0
+#define CONFIG_SYS_SICRL SICRL_LDP_A
+
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+
+#define CONFIG_SYS_HID2 HID2_HBE
+
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR 0x00100000
+#define CONFIG_SYS_GPIO1_DAT 0x00100000
+
+#define CONFIG_SYS_GPIO2_PRELIM
+#define CONFIG_SYS_GPIO2_DIR 0x78900000
+#define CONFIG_SYS_GPIO2_DAT 0x70100000
+
+#define CONFIG_HIGH_BATS /* High BATs supported */
+
+/* DDR @ 0x00000000 */
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+
+/* PCI @ 0x80000000 */
+#ifdef CONFIG_PCI
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#else
+#define CONFIG_SYS_IBAT1L (0)
+#define CONFIG_SYS_IBAT1U (0)
+#define CONFIG_SYS_IBAT2L (0)
+#define CONFIG_SYS_IBAT2U (0)
+#endif
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#else
+#define CONFIG_SYS_IBAT3L (0)
+#define CONFIG_SYS_IBAT3U (0)
+#define CONFIG_SYS_IBAT4L (0)
+#define CONFIG_SYS_IBAT4U (0)
+#endif
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#if (CONFIG_SYS_DDR_SIZE == 512)
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
+ BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
+ BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CONFIG_SYS_IBAT7L (0)
+#define CONFIG_SYS_IBAT7U (0)
+#endif
+
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_HOSTNAME VME8349
+#define CONFIG_ROOTPATH /tftpboot/rootfs
+#define CONFIG_BOOTFILE uImage
+
+#define CONFIG_LOADADDR 500000 /* def location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=vme8349\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
+ "update=protect off fff00000 fff3ffff; " \
+ "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
+ "upd=run load update\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=vme8349.dtb\0" \
+ ""
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#endif /* __CONFIG_H */
/*
* NAND Flash
*/
-#define CONFIG_NEW_NAND_CODE
#define CONFIG_SYS_NAND0_BASE 0x0
#undef CONFIG_SYS_NAND1_BASE
#define CONFIG_SYS_NAND_SENDCMD_RETRY 3
#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/* NAND Timing Parameters (in ns) */
#define NAND_TIMING_tCH 10
#define NAND_TIMING_tCS 0
#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE 1
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_ENV_IS_IN_NAND 1
#ifndef _ELF_H
#define _ELF_H
-#if defined(__BEOS__) || \
- defined(__NetBSD__) || \
- defined(__FreeBSD__) || \
- defined(__sun__) || \
- defined(__APPLE__)
-#include <inttypes.h>
-#elif (defined(__linux__) && defined(USE_HOSTCC)) || defined(__WIN32__)
-#include <stdint.h>
-#endif
+#include "compiler.h"
/*
* This version doesn't work for 64-bit ABIs - Erik.
# endif
#endif /* CONFIG_ENV_IS_IN_MG_DISK */
-#ifdef USE_HOSTCC
-# include <stdint.h>
-#else
-# include <linux/types.h>
-#endif
+#include "compiler.h"
#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
# define ENV_HEADER_SIZE (sizeof(uint32_t) + 1)
#ifndef __FSL_ESDHC_H__
#define __FSL_ESDHC_H__
+#include <asm/errno.h>
+
/* FSL eSDHC-specific constants */
#define SYSCTL 0x0002e02c
#define SYSCTL_INITA 0x08000000
#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
#define ESDHC_HOSTCAPBLT_HSS 0x00200000
+#ifdef CONFIG_FSL_ESDHC
int fsl_esdhc_mmc_init(bd_t *bis);
+void fdt_fixup_esdhc(void *blob, bd_t *bd);
+#else
+static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
+static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
+#endif /* CONFIG_FSL_ESDHC */
#endif /* __FSL_ESDHC_H__ */
--- /dev/null
+/*
+ * An inteface for configuring a hardware via u-boot environment.
+ *
+ * Copyright (c) 2009 MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef _HWCONFIG_H
+#define _HWCONFIG_H
+
+#include <linux/types.h>
+#include <asm/errno.h>
+
+#ifdef CONFIG_HWCONFIG
+
+extern int hwconfig(const char *opt);
+extern const char *hwconfig_arg(const char *opt, size_t *arglen);
+extern int hwconfig_arg_cmp(const char *opt, const char *arg);
+extern int hwconfig_sub(const char *opt, const char *subopt);
+extern const char *hwconfig_subarg(const char *opt, const char *subopt,
+ size_t *subarglen);
+extern int hwconfig_subarg_cmp(const char *opt, const char *subopt,
+ const char *subarg);
+
+#else
+
+static inline int hwconfig(const char *opt)
+{
+ return -ENOSYS;
+}
+
+static inline const char *hwconfig_arg(const char *opt, size_t *arglen)
+{
+ *arglen = 0;
+ return "";
+}
+
+static inline int hwconfig_arg_cmp(const char *opt, const char *arg)
+{
+ return -ENOSYS;
+}
+
+static inline int hwconfig_sub(const char *opt, const char *subopt)
+{
+ return -ENOSYS;
+}
+
+static inline const char *hwconfig_subarg(const char *opt, const char *subopt,
+ size_t *subarglen)
+{
+ *subarglen = 0;
+ return "";
+}
+
+static inline int hwconfig_subarg_cmp(const char *opt, const char *subopt,
+ const char *subarg)
+{
+ return -ENOSYS;
+}
+
+#endif /* CONFIG_HWCONFIG */
+
+#endif /* _HWCONFIG_H */
#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
#if defined(CONFIG_I2C_MULTI_BUS)
+#if !defined(CONFIG_SYS_MAX_I2C_BUS)
#define CONFIG_SYS_MAX_I2C_BUS 2
+#endif
#define I2C_GET_BUS() i2c_get_bus_num()
#define I2C_SET_BUS(a) i2c_set_bus_num(a)
#else
#ifndef __IMAGE_H__
#define __IMAGE_H__
-#if USE_HOSTCC
-#ifndef __MINGW32__
-#include <endian.h>
-#endif
+#include "compiler.h"
+
+#ifdef USE_HOSTCC
/* new uImage format support enabled on host */
#define CONFIG_FIT 1
#else
#include <lmb.h>
-#include <linux/string.h>
#include <asm/u-boot.h>
-#include <asm/byteorder.h>
#endif /* USE_HOSTCC */
#define CHUNKSZ_SHA1 (64 * 1024)
#endif
-#define uimage_to_cpu(x) ntohl(x)
-#define cpu_to_uimage(x) htonl(x)
+#define uimage_to_cpu(x) be32_to_cpu(x)
+#define cpu_to_uimage(x) cpu_to_be32(x)
const char *genimg_get_os_name (uint8_t os);
const char *genimg_get_arch_name (uint8_t arch);
#ifndef _IO_MUX_H
#define _IO_MUX_H
-#include <devices.h>
+#include <stdio_dev.h>
/*
* Stuff required to support console multiplexing.
* Pointers to devices used for each file type. Defined in console.c
* but storage is allocated in iomux.c.
*/
-extern device_t **console_devices[MAX_FILES];
+extern struct stdio_dev **console_devices[MAX_FILES];
/*
* The count of devices assigned to each FILE. Defined in console.c
* and populated in iomux.c.
int iomux_doenv(const int, const char *);
void iomux_printdevs(const int);
-device_t *search_device(int, char *);
+struct stdio_dev *search_device(int, char *);
#endif /* _IO_MUX_H */
extern short console_col;
extern short console_row;
+extern struct vidinfo panel_info;
+
+extern void lcd_ctrl_init (void *lcdbase);
+extern void lcd_enable (void);
+
+/* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */
+extern void lcd_setcolreg (ushort regno,
+ ushort red, ushort green, ushort blue);
+extern void lcd_initcolregs (void);
+
+/* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */
+extern struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp);
#if defined CONFIG_MPC823
/*
u_char vl_wbf; /* Wait between frames */
} vidinfo_t;
-extern vidinfo_t panel_info;
-
#elif defined CONFIG_PXA250
/*
* PXA LCD DMA descriptor
struct pxafb_info pxa;
} vidinfo_t;
-extern vidinfo_t panel_info;
-
#elif defined(CONFIG_ATMEL_LCD)
typedef struct vidinfo {
u_long mmio; /* Memory mapped registers */
} vidinfo_t;
-extern vidinfo_t panel_info;
-
#else
typedef struct vidinfo {
#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 or CONFIG_ATMEL_LCD */
+extern vidinfo_t panel_info;
+
/* Video functions */
#if defined(CONFIG_RBC823)
#if LCD_BPP == LCD_MONOCHROME
# define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \
(c) << 4 | (c) << 5 | (c) << 6 | (c) << 7)
-#elif LCD_BPP == LCD_COLOR8
+#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16)
# define COLOR_MASK(c) (c)
#else
# error Unsupported LCD BPP.
#ifndef _LIBFDT_ENV_H
#define _LIBFDT_ENV_H
-#ifdef USE_HOSTCC
-#include <stdint.h>
-#include <string.h>
-#ifdef __MINGW32__
-#include <linux/types.h>
-#include <linux/byteorder/swab.h>
-#else
-#include <endian.h>
-#include <byteswap.h>
-#endif /* __MINGW32__ */
-#else
-#include <linux/string.h>
-#include <linux/types.h>
-#include <asm/byteorder.h>
-#endif /* USE_HOSTCC */
+#include "compiler.h"
-#include <stddef.h>
extern struct fdt_header *working_fdt; /* Pointer to the working fdt */
-#if __BYTE_ORDER == __LITTLE_ENDIAN
-#ifdef __MINGW32__
-#define fdt32_to_cpu(x) ___swab32(x)
-#define cpu_to_fdt32(x) ___swab32(x)
-#define fdt64_to_cpu(x) ___swab64(x)
-#define cpu_to_fdt64(x) ___swab64(x)
-#else
-#define fdt32_to_cpu(x) bswap_32(x)
-#define cpu_to_fdt32(x) bswap_32(x)
-#define fdt64_to_cpu(x) bswap_64(x)
-#define cpu_to_fdt64(x) bswap_64(x)
-#endif
-#else
-#define fdt32_to_cpu(x) (x)
-#define cpu_to_fdt32(x) (x)
-#define fdt64_to_cpu(x) (x)
-#define cpu_to_fdt64(x) (x)
-#endif
-
-#ifndef USE_HOSTCC
-/*
- * Types for `void *' pointers.
- *
- * Note: libfdt uses this definition from /usr/include/stdint.h.
- * Define it here rather than pulling in all of stdint.h.
- */
-#if __WORDSIZE == 64
-typedef unsigned long int uintptr_t;
-#else
-typedef unsigned int uintptr_t;
-#endif
-#endif /* not USE_HOSTCC */
+#define fdt32_to_cpu(x) be32_to_cpu(x)
+#define cpu_to_fdt32(x) cpu_to_be32(x)
+#define fdt64_to_cpu(x) be64_to_cpu(x)
+#define cpu_to_fdt64(x) cpu_to_be64(x)
#endif /* _LIBFDT_ENV_H */
* is supported now. If you add a chip with bigger oobsize/page
* adjust this accordingly.
*/
-#define NAND_MAX_OOBSIZE 128
+#define NAND_MAX_OOBSIZE 218
#define NAND_MAX_PAGESIZE 4096
/*
+++ /dev/null
-/*
- * u-boot/include/linux/mtd/nand_ids.h
- *
- * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
- * Steven J. Hill <sjhill@cotw.com>
- *
- * $Id: nand_ids.h,v 1.1 2000/10/13 16:16:26 mdeans Exp $
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Info:
- * Contains standard defines and IDs for NAND flash devices
- *
- * Changelog:
- * 01-31-2000 DMW Created
- * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
- * so it can be used by other NAND flash device
- * drivers. I also changed the copyright since none
- * of the original contents of this file are specific
- * to DoC devices. David can whack me with a baseball
- * bat later if I did something naughty.
- * 10-11-2000 SJH Added private NAND flash structure for driver
- * 2000-10-13 BE Moved out of 'nand.h' - avoids duplication.
- */
-
-#ifndef __LINUX_MTD_NAND_IDS_H
-#define __LINUX_MTD_NAND_IDS_H
-
-#ifndef CONFIG_NAND_LEGACY
-#error This module is for the legacy NAND support
-#endif
-
-static struct nand_flash_dev nand_flash_ids[] = {
- {"Toshiba TC5816BDC", NAND_MFR_TOSHIBA, 0x64, 21, 1, 2, 0x1000, 0},
- {"Toshiba TC5832DC", NAND_MFR_TOSHIBA, 0x6b, 22, 0, 2, 0x2000, 0},
- {"Toshiba TH58V128DC", NAND_MFR_TOSHIBA, 0x73, 24, 0, 2, 0x4000, 0},
- {"Toshiba TC58256FT/DC", NAND_MFR_TOSHIBA, 0x75, 25, 0, 2, 0x4000, 0},
- {"Toshiba TH58512FT", NAND_MFR_TOSHIBA, 0x76, 26, 0, 3, 0x4000, 0},
- {"Toshiba TC58V32DC", NAND_MFR_TOSHIBA, 0xe5, 22, 0, 2, 0x2000, 0},
- {"Toshiba TC58V64AFT/DC", NAND_MFR_TOSHIBA, 0xe6, 23, 0, 2, 0x2000, 0},
- {"Toshiba TC58V16BDC", NAND_MFR_TOSHIBA, 0xea, 21, 1, 2, 0x1000, 0},
- {"Toshiba TH58100FT", NAND_MFR_TOSHIBA, 0x79, 27, 0, 3, 0x4000, 0},
- {"Samsung KM29N16000", NAND_MFR_SAMSUNG, 0x64, 21, 1, 2, 0x1000, 0},
- {"Samsung unknown 4Mb", NAND_MFR_SAMSUNG, 0x6b, 22, 0, 2, 0x2000, 0},
- {"Samsung KM29U128T", NAND_MFR_SAMSUNG, 0x73, 24, 0, 2, 0x4000, 0},
- {"Samsung KM29U256T", NAND_MFR_SAMSUNG, 0x75, 25, 0, 2, 0x4000, 0},
- {"Samsung unknown 64Mb", NAND_MFR_SAMSUNG, 0x76, 26, 0, 3, 0x4000, 0},
- {"Samsung KM29W32000", NAND_MFR_SAMSUNG, 0xe3, 22, 0, 2, 0x2000, 0},
- {"Samsung unknown 4Mb", NAND_MFR_SAMSUNG, 0xe5, 22, 0, 2, 0x2000, 0},
- {"Samsung KM29U64000", NAND_MFR_SAMSUNG, 0xe6, 23, 0, 2, 0x2000, 0},
- {"Samsung KM29W16000", NAND_MFR_SAMSUNG, 0xea, 21, 1, 2, 0x1000, 0},
- {"Samsung K9F5616Q0C", NAND_MFR_SAMSUNG, 0x45, 25, 0, 2, 0x4000, 1},
- {"Samsung K9K1216Q0C", NAND_MFR_SAMSUNG, 0x46, 26, 0, 3, 0x4000, 1},
- {"Samsung K9F1G08U0M", NAND_MFR_SAMSUNG, 0xf1, 27, 0, 2, 0, 0},
- {NULL,}
-};
-
-#endif /* __LINUX_MTD_NAND_IDS_H */
+++ /dev/null
-/*
- * linux/include/linux/mtd/nand.h
- *
- * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
- * Steven J. Hill <sjhill@cotw.com>
- * Thomas Gleixner <gleixner@autronix.de>
- *
- * $Id: nand.h,v 1.7 2003/07/24 23:30:46 a0384864 Exp $
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Info:
- * Contains standard defines and IDs for NAND flash devices
- *
- * Changelog:
- * 01-31-2000 DMW Created
- * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
- * so it can be used by other NAND flash device
- * drivers. I also changed the copyright since none
- * of the original contents of this file are specific
- * to DoC devices. David can whack me with a baseball
- * bat later if I did something naughty.
- * 10-11-2000 SJH Added private NAND flash structure for driver
- * 10-24-2000 SJH Added prototype for 'nand_scan' function
- * 10-29-2001 TG changed nand_chip structure to support
- * hardwarespecific function for accessing control lines
- * 02-21-2002 TG added support for different read/write adress and
- * ready/busy line access function
- * 02-26-2002 TG added chip_delay to nand_chip structure to optimize
- * command delay times for different chips
- * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate
- * defines in jffs2/wbuf.c
- */
-#ifndef __LINUX_MTD_NAND_LEGACY_H
-#define __LINUX_MTD_NAND_LEGACY_H
-
-#ifndef CONFIG_NAND_LEGACY
-#error This module is for the legacy NAND support
-#endif
-
-/* The maximum number of NAND chips in an array */
-#ifndef CONFIG_SYS_NAND_MAX_CHIPS
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
-#endif
-
-/*
- * Standard NAND flash commands
- */
-#define NAND_CMD_READ0 0
-#define NAND_CMD_READ1 1
-#define NAND_CMD_PAGEPROG 0x10
-#define NAND_CMD_READOOB 0x50
-#define NAND_CMD_ERASE1 0x60
-#define NAND_CMD_STATUS 0x70
-#define NAND_CMD_SEQIN 0x80
-#define NAND_CMD_READID 0x90
-#define NAND_CMD_ERASE2 0xd0
-#define NAND_CMD_RESET 0xff
-
-/*
- * NAND Private Flash Chip Data
- *
- * Structure overview:
- *
- * IO_ADDR - address to access the 8 I/O lines of the flash device
- *
- * hwcontrol - hardwarespecific function for accesing control-lines
- *
- * dev_ready - hardwarespecific function for accesing device ready/busy line
- *
- * chip_lock - spinlock used to protect access to this structure
- *
- * wq - wait queue to sleep on if a NAND operation is in progress
- *
- * state - give the current state of the NAND device
- *
- * page_shift - number of address bits in a page (column address bits)
- *
- * data_buf - data buffer passed to/from MTD user modules
- *
- * data_cache - data cache for redundant page access and shadow for
- * ECC failure
- *
- * ecc_code_buf - used only for holding calculated or read ECCs for
- * a page read or written when ECC is in use
- *
- * reserved - padding to make structure fall on word boundary if
- * when ECC is in use
- */
-struct Nand {
- char floor, chip;
- unsigned long curadr;
- unsigned char curmode;
- /* Also some erase/write/pipeline info when we get that far */
-};
-
-struct nand_chip {
- int page_shift;
- u_char *data_buf;
- u_char *data_cache;
- int cache_page;
- u_char ecc_code_buf[6];
- u_char reserved[2];
- char ChipID; /* Type of DiskOnChip */
- struct Nand *chips;
- int chipshift;
- char* chips_name;
- unsigned long erasesize;
- unsigned long mfr; /* Flash IDs - only one type of flash per device */
- unsigned long id;
- char* name;
- int numchips;
- char page256;
- char pageadrlen;
- unsigned long IO_ADDR; /* address to access the 8 I/O lines to the flash device */
- unsigned long totlen;
- uint oobblock; /* Size of OOB blocks (e.g. 512) */
- uint oobsize; /* Amount of OOB data per block (e.g. 16) */
- uint eccsize;
- int bus16;
-};
-
-/*
- * NAND Flash Manufacturer ID Codes
- */
-#define NAND_MFR_TOSHIBA 0x98
-#define NAND_MFR_SAMSUNG 0xec
-
-/*
- * NAND Flash Device ID Structure
- *
- * Structure overview:
- *
- * name - Complete name of device
- *
- * manufacture_id - manufacturer ID code of device.
- *
- * model_id - model ID code of device.
- *
- * chipshift - total number of address bits for the device which
- * is used to calculate address offsets and the total
- * number of bytes the device is capable of.
- *
- * page256 - denotes if flash device has 256 byte pages or not.
- *
- * pageadrlen - number of bytes minus one needed to hold the
- * complete address into the flash array. Keep in
- * mind that when a read or write is done to a
- * specific address, the address is input serially
- * 8 bits at a time. This structure member is used
- * by the read/write routines as a loop index for
- * shifting the address out 8 bits at a time.
- *
- * erasesize - size of an erase block in the flash device.
- */
-struct nand_flash_dev {
- char * name;
- int manufacture_id;
- int model_id;
- int chipshift;
- char page256;
- char pageadrlen;
- unsigned long erasesize;
- int bus16;
-};
-
-/*
-* Constants for oob configuration
-*/
-#define NAND_NOOB_ECCPOS0 0
-#define NAND_NOOB_ECCPOS1 1
-#define NAND_NOOB_ECCPOS2 2
-#define NAND_NOOB_ECCPOS3 3
-#define NAND_NOOB_ECCPOS4 6
-#define NAND_NOOB_ECCPOS5 7
-#define NAND_NOOB_BADBPOS -1
-#define NAND_NOOB_ECCVPOS -1
-
-#define NAND_JFFS2_OOB_ECCPOS0 0
-#define NAND_JFFS2_OOB_ECCPOS1 1
-#define NAND_JFFS2_OOB_ECCPOS2 2
-#define NAND_JFFS2_OOB_ECCPOS3 3
-#define NAND_JFFS2_OOB_ECCPOS4 6
-#define NAND_JFFS2_OOB_ECCPOS5 7
-#define NAND_JFFS2_OOB_BADBPOS 5
-#define NAND_JFFS2_OOB_ECCVPOS 4
-
-#define NAND_JFFS2_OOB8_FSDAPOS 6
-#define NAND_JFFS2_OOB16_FSDAPOS 8
-#define NAND_JFFS2_OOB8_FSDALEN 2
-#define NAND_JFFS2_OOB16_FSDALEN 8
-
-unsigned long nand_probe(unsigned long physadr);
-#endif /* __LINUX_MTD_NAND_LEGACY_H */
/*
- * Fake include for LzmaDecode.h
+ * Fake include for LzmaDec.h
*
- * Copyright (C) 2007-2008 Industrie Dial Face S.p.A.
+ * Copyright (C) 2007-2009 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini (luigi.mantellini@idf-hit.com)
*
* See file CREDITS for list of people who contributed to this
* MA 02111-1307 USA
*/
-#ifndef __LZMADECODE_H__FAKE__
-#define __LZMADECODE_H__FAKE__
+#ifndef __LZMADEC_H__FAKE__
+#define __LZMADEC_H__FAKE__
-#include "../../lib_generic/lzma/LzmaDecode.h"
+#include "../../lib_generic/lzma/LzmaDec.h"
#endif
/*
* Fake include for LzmaTools.h
*
- * Copyright (C) 2007-2008 Industrie Dial Face S.p.A.
+ * Copyright (C) 2007-2009 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini (luigi.mantellini@idf-hit.com)
*
* See file CREDITS for list of people who contributed to this
/*
- * Fake include for LzmaTypes.h
+ * Fake include for Types.h
*
- * Copyright (C) 2007-2008 Industrie Dial Face S.p.A.
+ * Copyright (C) 2007-2009 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini (luigi.mantellini@idf-hit.com)
*
* See file CREDITS for list of people who contributed to this
* MA 02111-1307 USA
*/
-#ifndef __LZMATYPES_H__FAKE__
-#define __LZMATYPES_H__FAKE__
+#ifndef __TYPES_H__FAKE__
+#define __TYPES_H__FAKE__
-#include "../../lib_generic/lzma/LzmaTypes.h"
+/*
+ *This avoids the collition with zlib.h Byte definition
+ */
+#define Byte LZByte
+
+#include "../../lib_generic/lzma/Types.h"
#endif
*/
\f
-
+#ifndef __MALLOC_H__
+#define __MALLOC_H__
/* Preliminaries */
#ifdef __cplusplus
}; /* end of extern "C" */
#endif
+
+#endif /* __MALLOC_H__ */
#define PCI_DEVICE_ID_CORAL_P 0x2019
#define PCI_DEVICE_ID_CORAL_PA 0x201E
+#define GC_HOST_BASE 0x01fc0000
+#define GC_DISP_BASE 0x01fd0000
+#define GC_DRAW_BASE 0x01ff0000
+
+/* Host interface registers */
+#define GC_SRST 0x0000002c
+#define GC_CCF 0x00000038
+#define GC_MMR 0x0000fffc
+
+/*
+ * Display Controller registers
+ * _A means the offset is aligned, we use these for boards
+ * with 8-/16-bit GDC access not working or buggy.
+ */
+#define GC_DCM0 0x00000000
+#define GC_HTP_A 0x00000004
+#define GC_HTP 0x00000006
+#define GC_HDB_HDP_A 0x00000008
+#define GC_HDP 0x00000008
+#define GC_HDB 0x0000000a
+#define GC_VSW_HSW_HSP_A 0x0000000c
+#define GC_HSP 0x0000000c
+#define GC_HSW 0x0000000e
+#define GC_VSW 0x0000000f
+#define GC_VTR_A 0x00000010
+#define GC_VTR 0x00000012
+#define GC_VDP_VSP_A 0x00000014
+#define GC_VSP 0x00000014
+#define GC_VDP 0x00000016
+#define GC_WY_WX 0x00000018
+#define GC_WH_WW 0x0000001c
+#define GC_L0M 0x00000020
+#define GC_L0OA0 0x00000024
+#define GC_L0DA0 0x00000028
+#define GC_L0DY_L0DX 0x0000002c
+#define GC_L2M 0x00000040
+#define GC_L2OA0 0x00000044
+#define GC_L2DA0 0x00000048
+#define GC_L2OA1 0x0000004c
+#define GC_L2DA1 0x00000050
+#define GC_L2DX 0x00000054
+#define GC_L2DY 0x00000056
+#define GC_DCM1 0x00000100
+#define GC_DCM2 0x00000104
+#define GC_DCM3 0x00000108
+#define GC_L0EM 0x00000110
+#define GC_L0WY_L0WX 0x00000114
+#define GC_L0WH_L0WW 0x00000118
+#define GC_L2EM 0x00000130
+#define GC_L2WX 0x00000134
+#define GC_L2WY 0x00000136
+#define GC_L2WW 0x00000138
+#define GC_L2WH 0x0000013a
+#define GC_L0PAL0 0x00000400
+
+/* Drawing registers */
+#define GC_CTR 0x00000400
+#define GC_IFCNT 0x00000408
+#define GC_FBR 0x00000440
+#define GC_XRES 0x00000444
+#define GC_CXMIN 0x00000454
+#define GC_CXMAX 0x00000458
+#define GC_CYMIN 0x0000045c
+#define GC_CYMAX 0x00000460
+#define GC_FC 0x00000480
+#define GC_BC 0x00000484
+#define GC_FIFO 0x000004a0
+#define GC_GEO_FIFO 0x00008400
+
typedef struct {
unsigned int index;
unsigned int value;
extern void nand_init(void);
-#ifndef CONFIG_NAND_LEGACY
#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
__attribute__((noreturn)) void nand_boot(void);
-#endif /* !CONFIG_NAND_LEGACY */
#endif
extern IPaddr_t NetServerIP; /* Server IP addr (0 = unknown) */
extern volatile uchar * NetTxPacket; /* THE transmit packet */
extern volatile uchar * NetRxPackets[PKTBUFSRX];/* Receive packets */
-extern volatile uchar * NetRxPkt; /* Current receive packet */
-extern int NetRxPktLen; /* Current rx packet length */
+extern volatile uchar * NetRxPacket; /* Current receive packet */
+extern int NetRxPacketLen; /* Current rx packet length */
extern unsigned NetIPID; /* IP ID (counting) */
extern uchar NetBcastAddr[6]; /* Ethernet boardcast address */
extern uchar NetEtherNullAddr[6];
/* from net/net.c */
extern char BootFile[128]; /* Boot File name */
+#if defined(CONFIG_CMD_DNS)
+extern char *NetDNSResolve; /* The host to resolve */
+extern char *NetDNSenvvar; /* the env var to put the ip into */
+#endif
+
#if defined(CONFIG_CMD_PING)
extern IPaddr_t NetPingIP; /* the ip address to ping */
#endif
int eepro100_initialize(bd_t *bis);
int eth_3com_initialize (bd_t * bis);
int fec_initialize (bd_t *bis);
+int fecmxc_initialize (bd_t *bis);
int greth_initialize(bd_t *bis);
void gt6426x_eth_initialize(bd_t *bis);
int inca_switch_initialize(bd_t *bis);
int rtl8169_initialize(bd_t *bis);
int scc_initialize(bd_t *bis);
int skge_initialize(bd_t *bis);
+int smc911x_initialize(u8 dev_num, int base_addr);
int tsi108_eth_initialize(bd_t *bis);
int uec_initialize(int index);
+int uec_standard_init(bd_t *bis);
int uli526x_initialize(bd_t *bis);
int sh_eth_initialize(bd_t *bis);
int dm9000_initialize(bd_t *bis);
#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480 (403) */
#endif
-/*--------------------------------------------------------------------- */
-/* Special Purpose Registers */
-/*--------------------------------------------------------------------- */
- #define srr2 0x3de /* save/restore register 2 */
- #define srr3 0x3df /* save/restore register 3 */
-
- /*
- * 405 does not really have CSRR0/1 but SRR2/3 are used during critical
- * exception for the exact same purposes - let's alias them and have a
- * common handling in crit_return() and CRIT_EXCEPTION
- */
- #define csrr0 srr2
- #define csrr1 srr3
-
- #define dbsr 0x3f0 /* debug status register */
- #define dbcr0 0x3f2 /* debug control register 0 */
- #define dbcr1 0x3bd /* debug control register 1 */
- #define iac1 0x3f4 /* instruction address comparator 1 */
- #define iac2 0x3f5 /* instruction address comparator 2 */
- #define iac3 0x3b4 /* instruction address comparator 3 */
- #define iac4 0x3b5 /* instruction address comparator 4 */
- #define dac1 0x3f6 /* data address comparator 1 */
- #define dac2 0x3f7 /* data address comparator 2 */
- #define dccr 0x3fa /* data cache control register */
- #define iccr 0x3fb /* instruction cache control register */
- #define esr 0x3d4 /* execption syndrome register */
- #define dear 0x3d5 /* data exeption address register */
- #define evpr 0x3d6 /* exeption vector prefix register */
- #define tsr 0x3d8 /* timer status register */
- #define tcr 0x3da /* timer control register */
- #define pit 0x3db /* programmable interval timer */
- #define sgr 0x3b9 /* storage guarded reg */
- #define dcwr 0x3ba /* data cache write-thru reg*/
- #define sler 0x3bb /* storage little-endian reg */
- #define cdbcr 0x3d7 /* cache debug cntrl reg */
- #define icdbdr 0x3d3 /* instr cache dbug data reg*/
- #define ccr0 0x3b3 /* core configuration register */
- #define dvc1 0x3b6 /* data value compare register 1 */
- #define dvc2 0x3b7 /* data value compare register 2 */
- #define pid 0x3b1 /* process ID */
- #define su0r 0x3bc /* storage user-defined register 0 */
- #define zpr 0x3b0 /* zone protection regsiter */
-
- #define tbl 0x11c /* time base lower - privileged write */
- #define tbu 0x11d /* time base upper - privileged write */
-
- #define sprg4r 0x104 /* Special purpose general 4 - read only */
- #define sprg5r 0x105 /* Special purpose general 5 - read only */
- #define sprg6r 0x106 /* Special purpose general 6 - read only */
- #define sprg7r 0x107 /* Special purpose general 7 - read only */
- #define sprg4w 0x114 /* Special purpose general 4 - write only */
- #define sprg5w 0x115 /* Special purpose general 5 - write only */
- #define sprg6w 0x116 /* Special purpose general 6 - write only */
- #define sprg7w 0x117 /* Special purpose general 7 - write only */
-
/******************************************************************************
* Special for PPC405GP
******************************************************************************/
#define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
-/*--------------------------------------------------------------------- */
-/* Special Purpose Registers */
-/*--------------------------------------------------------------------- */
-#define xer_reg 0x001
-#define lr_reg 0x008
-#define dec 0x016 /* decrementer */
-#define srr0 0x01a /* save/restore register 0 */
-#define srr1 0x01b /* save/restore register 1 */
-#define pid 0x030 /* process id */
-#define decar 0x036 /* decrementer auto-reload */
-#define csrr0 0x03a /* critical save/restore register 0 */
-#define csrr1 0x03b /* critical save/restore register 1 */
-#define dear 0x03d /* data exception address register */
-#define esr 0x03e /* exception syndrome register */
-#define ivpr 0x03f /* interrupt prefix register */
-#define usprg0 0x100 /* user special purpose register general 0 */
-#define usprg1 0x110 /* user special purpose register general 1 */
-#define tblr 0x10c /* time base lower, read only */
-#define tbur 0x10d /* time base upper, read only */
-#define sprg1 0x111 /* special purpose register general 1 */
-#define sprg2 0x112 /* special purpose register general 2 */
-#define sprg3 0x113 /* special purpose register general 3 */
-#define sprg4 0x114 /* special purpose register general 4 */
-#define sprg5 0x115 /* special purpose register general 5 */
-#define sprg6 0x116 /* special purpose register general 6 */
-#define sprg7 0x117 /* special purpose register general 7 */
-#define tbl 0x11c /* time base lower (supervisor)*/
-#define tbu 0x11d /* time base upper (supervisor)*/
-#define pir 0x11e /* processor id register */
-#define dbsr 0x130 /* debug status register */
-#define dbcr0 0x134 /* debug control register 0 */
-#define dbcr1 0x135 /* debug control register 1 */
-#define dbcr2 0x136 /* debug control register 2 */
-#define iac1 0x138 /* instruction address compare 1 */
-#define iac2 0x139 /* instruction address compare 2 */
-#define iac3 0x13a /* instruction address compare 3 */
-#define iac4 0x13b /* instruction address compare 4 */
-#define dac1 0x13c /* data address compare 1 */
-#define dac2 0x13d /* data address compare 2 */
-#define dvc1 0x13e /* data value compare 1 */
-#define dvc2 0x13f /* data value compare 2 */
-#define tsr 0x150 /* timer status register */
-#define tcr 0x154 /* timer control register */
-#define ivor0 0x190 /* interrupt vector offset register 0 */
-#define ivor1 0x191 /* interrupt vector offset register 1 */
-#define ivor2 0x192 /* interrupt vector offset register 2 */
-#define ivor3 0x193 /* interrupt vector offset register 3 */
-#define ivor4 0x194 /* interrupt vector offset register 4 */
-#define ivor5 0x195 /* interrupt vector offset register 5 */
-#define ivor6 0x196 /* interrupt vector offset register 6 */
-#define ivor7 0x197 /* interrupt vector offset register 7 */
-#define ivor8 0x198 /* interrupt vector offset register 8 */
-#define ivor9 0x199 /* interrupt vector offset register 9 */
-#define ivor10 0x19a /* interrupt vector offset register 10 */
-#define ivor11 0x19b /* interrupt vector offset register 11 */
-#define ivor12 0x19c /* interrupt vector offset register 12 */
-#define ivor13 0x19d /* interrupt vector offset register 13 */
-#define ivor14 0x19e /* interrupt vector offset register 14 */
-#define ivor15 0x19f /* interrupt vector offset register 15 */
-#if defined(CONFIG_440)
-#define mcsrr0 0x23a /* machine check save/restore register 0 */
-#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
-#define mcsr 0x23c /* machine check status register */
-#endif
-#define inv0 0x370 /* instruction cache normal victim 0 */
-#define inv1 0x371 /* instruction cache normal victim 1 */
-#define inv2 0x372 /* instruction cache normal victim 2 */
-#define inv3 0x373 /* instruction cache normal victim 3 */
-#define itv0 0x374 /* instruction cache transient victim 0 */
-#define itv1 0x375 /* instruction cache transient victim 1 */
-#define itv2 0x376 /* instruction cache transient victim 2 */
-#define itv3 0x377 /* instruction cache transient victim 3 */
-#define dnv0 0x390 /* data cache normal victim 0 */
-#define dnv1 0x391 /* data cache normal victim 1 */
-#define dnv2 0x392 /* data cache normal victim 2 */
-#define dnv3 0x393 /* data cache normal victim 3 */
-#define dtv0 0x394 /* data cache transient victim 0 */
-#define dtv1 0x395 /* data cache transient victim 1 */
-#define dtv2 0x396 /* data cache transient victim 2 */
-#define dtv3 0x397 /* data cache transient victim 3 */
-#define dvlim 0x398 /* data cache victim limit */
-#define ivlim 0x399 /* instruction cache victim limit */
-#define rstcfg 0x39b /* reset configuration */
-#define dcdbtrl 0x39c /* data cache debug tag register low */
-#define dcdbtrh 0x39d /* data cache debug tag register high */
-#define icdbtrl 0x39e /* instruction cache debug tag register low */
-#define icdbtrh 0x39f /* instruction cache debug tag register high */
-#define mmucr 0x3b2 /* mmu control register */
-#define ccr0 0x3b3 /* core configuration register 0 */
-#define ccr1 0x378 /* core configuration for 440x5 only */
-#define icdbdr 0x3d3 /* instruction cache debug data register */
-#define dbdr 0x3f3 /* debug data register */
-
/******************************************************************************
* DCRs & Related
******************************************************************************/
#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
+#define SDR0_ECID0 0x0080
+#define SDR0_ECID1 0x0081
+#define SDR0_ECID2 0x0082
+#define SDR0_ECID3 0x0083
+
/* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */
#define SDR0_ETH_PLL 0x4102
#define SDR0_ETH_PLL_PLLLOCK 0x80000000 /*Ethernet PLL lock indication*/
extern struct serial_device serial_stuart_device;
extern void serial_initialize(void);
-extern void serial_devices_init(void);
+extern void serial_stdio_init(void);
extern int serial_assign(char * name);
extern void serial_reinit_all(void);
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* MA 02111-1307 USA
*/
-#include <linux/list.h>
+#ifndef _STDIO_DEV_H_
+#define _STDIO_DEV_H_
-#ifndef _DEVICES_H_
-#define _DEVICES_H_
+#include <linux/list.h>
/*
- * CONSOLE DEVICES
+ * STDIO DEVICES
*/
#define DEV_FLAGS_INPUT 0x00000001 /* Device can be used as input console */
#define DEV_EXT_VIDEO 0x00000001 /* Video extensions supported */
/* Device information */
-typedef struct {
+struct stdio_dev {
int flags; /* Device flags: input/output/system */
int ext; /* Supported extensions */
char name[16]; /* Device name */
void *priv; /* Private extensions */
struct list_head list;
-} device_t;
+};
/*
* VIDEO EXTENSIONS
/*
* VARIABLES
*/
-extern device_t *stdio_devices[];
+extern struct stdio_dev *stdio_devices[];
extern char *stdio_names[MAX_FILES];
/*
* PROTOTYPES
*/
-int device_register (device_t * dev);
-int devices_init (void);
-#ifdef CONFIG_SYS_DEVICE_DEREGISTER
-int device_deregister(char *devname);
+int stdio_register (struct stdio_dev * dev);
+int stdio_init (void);
+void stdio_print_current_devices(void);
+#ifdef CONFIG_SYS_STDIO_DEREGISTER
+int stdio_deregister(char *devname);
#endif
-struct list_head* device_get_list(void);
-device_t* device_get_by_name(char* name);
-device_t* device_clone(device_t *dev);
+struct list_head* stdio_get_list(void);
+struct stdio_dev* stdio_get_by_name(char* name);
+struct stdio_dev* stdio_clone(struct stdio_dev *dev);
#ifdef CONFIG_ARM_DCC_MULTI
int drv_arm_dcc_init(void);
int drv_jtag_console_init (void);
#endif
-#endif /* _DEVICES_H_ */
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009 Reinhard Arlt, reinhard.arlt@esd-electronics.com
+ *
+ * base on universe.h by
+ *
+ * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _tsi148_h
+#define _tsi148_h
+
+#ifndef PCI_DEVICE_ID_TUNDRA_TSI148
+#define PCI_DEVICE_ID_TUNDRA_TSI148 0x0148
+#endif
+
+typedef struct _TSI148 TSI148;
+typedef struct _OUTBOUND OUTBOUND;
+typedef struct _INBOUND INBOUND;
+typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET;
+
+struct _OUTBOUND {
+ unsigned int otsau; /* 0x000 Outbound start upper */
+ unsigned int otsal; /* 0x004 Outbouud start lower */
+ unsigned int oteau; /* 0x008 Outbound end upper */
+ unsigned int oteal; /* 0x00c Outbound end lower */
+ unsigned int otofu; /* 0x010 Outbound translation upper */
+ unsigned int otofl; /* 0x014 Outbound translation lower */
+ unsigned int otbs; /* 0x018 Outbound translation 2eSST */
+ unsigned int otat; /* 0x01c Outbound translation attr */
+};
+
+struct _INBOUND {
+ unsigned int itsau; /* 0x000 inbound start upper */
+ unsigned int itsal; /* 0x004 inbouud start lower */
+ unsigned int iteau; /* 0x008 inbound end upper */
+ unsigned int iteal; /* 0x00c inbound end lower */
+ unsigned int itofu; /* 0x010 inbound translation upper */
+ unsigned int itofl; /* 0x014 inbound translation lower */
+ unsigned int itat; /* 0x018 inbound translation attr */
+ unsigned int spare; /* 0x01c not used */
+};
+
+struct _TSI148 {
+ unsigned int pci_id; /* 0x000 */
+ unsigned int pci_csr; /* 0x004 */
+ unsigned int pci_class; /* 0x008 */
+ unsigned int pci_misc0; /* 0x00c */
+ unsigned int pci_mbarl; /* 0x010 */
+ unsigned int pci_mbarh; /* 0x014 */
+ unsigned int spare0[(0x03c-0x018)/4]; /* 0x018 */
+ unsigned int pci_misc1; /* 0x03c */
+ unsigned int pci_pcixcap; /* 0x040 */
+ unsigned int pci_pcixstat; /* 0x044 */
+ unsigned int spare1[(0x100-0x048)/4]; /* 0x048 */
+ OUTBOUND outbound[8]; /* 0x100 */
+ unsigned int viack[8]; /* 0x204 */
+ unsigned int rmwau; /* 0x220 */
+ unsigned int rmwal; /* 0x224 */
+ unsigned int rmwen; /* 0x228 */
+ unsigned int rmwc; /* 0x22c */
+ unsigned int rmws; /* 0x230 */
+ unsigned int vmctrl; /* 0x234 */
+ unsigned int vctrl; /* 0x238 */
+ unsigned int vstat; /* 0x23c */
+ unsigned int pcsr; /* 0x240 */
+ unsigned int spare2[3]; /* 0x244 - 0x24c */
+ unsigned int vmefl; /* 0x250 */
+ unsigned int spare3[3]; /* 0x254 - 0x25c */
+ unsigned int veau; /* 0x260 */
+ unsigned int veal; /* 0x264 */
+ unsigned int veat; /* 0x268 */
+ unsigned int spare4[1]; /* 0x26c */
+ unsigned int edpau; /* 0x270 */
+ unsigned int edpal; /* 0x274 */
+ unsigned int edpxa; /* 0x278 */
+ unsigned int edpxs; /* 0x27c */
+ unsigned int edpat; /* 0x280 */
+ unsigned int spare5[31]; /* 0x284 - 0x2fc */
+ INBOUND inbound[8]; /* 0x100 */
+ unsigned int gbau; /* 0x400 */
+ unsigned int gbal; /* 0x404 */
+ unsigned int gcsrat; /* 0x408 */
+ unsigned int cbau; /* 0x40c */
+ unsigned int cbal; /* 0x410 */
+ unsigned int crgat; /* 0x414 */
+ unsigned int crou; /* 0x418 */
+ unsigned int crol; /* 0x41c */
+ unsigned int crat; /* 0x420 */
+ unsigned int lmbau; /* 0x424 */
+ unsigned int lmbal; /* 0x428 */
+ unsigned int lmat; /* 0x42c */
+ unsigned int r64bcu; /* 0x430 */
+ unsigned int r64bcl; /* 0x434 */
+ unsigned int bpgtr; /* 0x438 */
+ unsigned int bpctr; /* 0x43c */
+ unsigned int vicr; /* 0x440 */
+ unsigned int spare6[1]; /* 0x444 */
+ unsigned int inten; /* 0x448 */
+ unsigned int inteo; /* 0x44c */
+ unsigned int ints; /* 0x450 */
+ unsigned int intc; /* 0x454 */
+ unsigned int intm1; /* 0x458 */
+ unsigned int intm2; /* 0x45c */
+ unsigned int spare7[40]; /* 0x460 - 0x4fc */
+ unsigned int dctl0; /* 0x500 */
+ unsigned int dsta0; /* 0x504 */
+ unsigned int dcsau0; /* 0x508 */
+ unsigned int dcsal0; /* 0x50c */
+ unsigned int dcdau0; /* 0x510 */
+ unsigned int dcdal0; /* 0x514 */
+ unsigned int dclau0; /* 0x518 */
+ unsigned int dclal0; /* 0x51c */
+ unsigned int dsau0; /* 0x520 */
+ unsigned int dsal0; /* 0x524 */
+ unsigned int ddau0; /* 0x528 */
+ unsigned int ddal0; /* 0x52c */
+ unsigned int dsat0; /* 0x530 */
+ unsigned int ddat0; /* 0x534 */
+ unsigned int dnlau0; /* 0x538 */
+ unsigned int dnlal0; /* 0x53c */
+ unsigned int dcnt0; /* 0x540 */
+ unsigned int ddbs0; /* 0x544 */
+ unsigned int r20[14]; /* 0x548 - 0x57c */
+ unsigned int dctl1; /* 0x580 */
+ unsigned int dsta1; /* 0x584 */
+ unsigned int dcsau1; /* 0x588 */
+ unsigned int dcsal1; /* 0x58c */
+ unsigned int dcdau1; /* 0x590 */
+ unsigned int dcdal1; /* 0x594 */
+ unsigned int dclau1; /* 0x598 */
+ unsigned int dclal1; /* 0x59c */
+ unsigned int dsau1; /* 0x5a0 */
+ unsigned int dsal1; /* 0x5a4 */
+ unsigned int ddau1; /* 0x5a8 */
+ unsigned int ddal1; /* 0x5ac */
+ unsigned int dsat1; /* 0x5b0 */
+ unsigned int ddat1; /* 0x5b4 */
+ unsigned int dnlau1; /* 0x5b8 */
+ unsigned int dnlal1; /* 0x5bc */
+ unsigned int dcnt1; /* 0x5c0 */
+ unsigned int ddbs1; /* 0x5c4 */
+ unsigned int r21[14]; /* 0x5c8 - 0x5fc */
+ unsigned int devi_veni_2; /* 0x600 */
+ unsigned int gctrl_ga_revid; /* 0x604 */
+ unsigned int semaphore0_1_2_3; /* 0x608 */
+ unsigned int semaphore4_5_6_7; /* 0x60c */
+ unsigned int mbox0; /* 0x610 */
+ unsigned int mbox1; /* 0x614 */
+ unsigned int mbox2; /* 0x618 */
+ unsigned int mbox3; /* 0x61c */
+ unsigned int r22[629]; /* 0x620 - 0xff0 */
+ unsigned int csrbcr; /* 0xff4 */
+ unsigned int csrbsr; /* 0xff8 */
+ unsigned int cbar; /* 0xffc */
+};
+
+#define IRQ_VOWN 0x0001
+#define IRQ_VIRQ1 0x0002
+#define IRQ_VIRQ2 0x0004
+#define IRQ_VIRQ3 0x0008
+#define IRQ_VIRQ4 0x0010
+#define IRQ_VIRQ5 0x0020
+#define IRQ_VIRQ6 0x0040
+#define IRQ_VIRQ7 0x0080
+#define IRQ_DMA 0x0100
+#define IRQ_LERR 0x0200
+#define IRQ_VERR 0x0400
+#define IRQ_res 0x0800
+#define IRQ_IACK 0x1000
+#define IRQ_SWINT 0x2000
+#define IRQ_SYSFAIL 0x4000
+#define IRQ_ACFAIL 0x8000
+
+struct _TDMA_CMD_PACKET {
+ unsigned int dctl; /* DMA Control */
+ unsigned int dtbc; /* Transfer Byte Count */
+ unsigned int dlv; /* PCI Address */
+ unsigned int res1; /* Reserved */
+ unsigned int dva; /* Vme Address */
+ unsigned int res2; /* Reserved */
+ unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */
+ unsigned int res3; /* Reserved */
+};
+
+#define VME_AM_A16 0x01
+#define VME_AM_A24 0x02
+#define VME_AM_A32 0x03
+#define VME_AM_Axx 0x03
+#define VME_AM_USR 0x04
+#define VME_AM_SUP 0x08
+#define VME_AM_DATA 0x10
+#define VME_AM_PROG 0x20
+#define VME_AM_Mxx (VME_AM_DATA | VME_AM_PROG)
+
+#define VME_FLAG_D8 0x01
+#define VME_FLAG_D16 0x02
+#define VME_FLAG_D32 0x03
+#define VME_FLAG_Dxx 0x03
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix at windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Derived from code on omapzoom, git://git.omapzoom.com/repo/u-boot.git
+ *
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ */
+
+#ifndef TWL4030_H
+#define TWL4030_H
+
+#include <common.h>
+#include <i2c.h>
+
+/* I2C chip addresses */
+
+/* USB */
+#define TWL4030_CHIP_USB 0x48
+/* AUD */
+#define TWL4030_CHIP_AUDIO_VOICE 0x49
+#define TWL4030_CHIP_GPIO 0x49
+#define TWL4030_CHIP_INTBR 0x49
+#define TWL4030_CHIP_PIH 0x49
+#define TWL4030_CHIP_TEST 0x49
+/* AUX */
+#define TWL4030_CHIP_KEYPAD 0x4a
+#define TWL4030_CHIP_MADC 0x4a
+#define TWL4030_CHIP_INTERRUPTS 0x4a
+#define TWL4030_CHIP_LED 0x4a
+#define TWL4030_CHIP_MAIN_CHARGE 0x4a
+#define TWL4030_CHIP_PRECHARGE 0x4a
+#define TWL4030_CHIP_PWM0 0x4a
+#define TWL4030_CHIP_PWM1 0x4a
+#define TWL4030_CHIP_PWMA 0x4a
+#define TWL4030_CHIP_PWMB 0x4a
+/* POWER */
+#define TWL4030_CHIP_BACKUP 0x4b
+#define TWL4030_CHIP_INT 0x4b
+#define TWL4030_CHIP_PM_MASTER 0x4b
+#define TWL4030_CHIP_PM_RECEIVER 0x4b
+#define TWL4030_CHIP_RTC 0x4b
+#define TWL4030_CHIP_SECURED_REG 0x4b
+
+/* Register base addresses */
+
+/* USB */
+#define TWL4030_BASEADD_USB 0x0000
+/* AUD */
+#define TWL4030_BASEADD_AUDIO_VOICE 0x0000
+#define TWL4030_BASEADD_GPIO 0x0098
+#define TWL4030_BASEADD_INTBR 0x0085
+#define TWL4030_BASEADD_PIH 0x0080
+#define TWL4030_BASEADD_TEST 0x004C
+/* AUX */
+#define TWL4030_BASEADD_INTERRUPTS 0x00B9
+#define TWL4030_BASEADD_LED 0x00EE
+#define TWL4030_BASEADD_MADC 0x0000
+#define TWL4030_BASEADD_MAIN_CHARGE 0x0074
+#define TWL4030_BASEADD_PRECHARGE 0x00AA
+#define TWL4030_BASEADD_PWM0 0x00F8
+#define TWL4030_BASEADD_PWM1 0x00FB
+#define TWL4030_BASEADD_PWMA 0x00EF
+#define TWL4030_BASEADD_PWMB 0x00F1
+#define TWL4030_BASEADD_KEYPAD 0x00D2
+/* POWER */
+#define TWL4030_BASEADD_BACKUP 0x0014
+#define TWL4030_BASEADD_INT 0x002E
+#define TWL4030_BASEADD_PM_MASTER 0x0036
+#define TWL4030_BASEADD_PM_RECIEVER 0x005B
+#define TWL4030_BASEADD_RTC 0x001C
+#define TWL4030_BASEADD_SECURED_REG 0x0000
+
+/*
+ * Power Management Master
+ */
+#define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x36
+#define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x37
+#define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x38
+#define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x39
+#define TWL4030_PM_MASTER_STS_BOOT 0x3A
+#define TWL4030_PM_MASTER_CFG_BOOT 0x3B
+#define TWL4030_PM_MASTER_SHUNDAN 0x3C
+#define TWL4030_PM_MASTER_BOOT_BCI 0x3D
+#define TWL4030_PM_MASTER_CFG_PWRANA1 0x3E
+#define TWL4030_PM_MASTER_CFG_PWRANA2 0x3F
+#define TWL4030_PM_MASTER_BGAP_TRIM 0x40
+#define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x41
+#define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x42
+#define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x43
+#define TWL4030_PM_MASTER_PROTECT_KEY 0x44
+#define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x45
+#define TWL4030_PM_MASTER_P1_SW_EVENTS 0x46
+#define TWL4030_PM_MASTER_P2_SW_EVENTS 0x47
+#define TWL4030_PM_MASTER_P3_SW_EVENTS 0x48
+#define TWL4030_PM_MASTER_STS_P123_STATE 0x49
+#define TWL4030_PM_MASTER_PB_CFG 0x4A
+#define TWL4030_PM_MASTER_PB_WORD_MSB 0x4B
+#define TWL4030_PM_MASTER_PB_WORD_LSB 0x4C
+#define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x52
+#define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x53
+#define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x54
+#define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x55
+#define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x56
+#define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x57
+#define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x58
+#define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x59
+#define TWL4030_PM_MASTER_MEMORY_DATA 0x5A
+#define TWL4030_PM_MASTER_SC_CONFIG 0x5B
+#define TWL4030_PM_MASTER_SC_DETECT1 0x5C
+#define TWL4030_PM_MASTER_SC_DETECT2 0x5D
+#define TWL4030_PM_MASTER_WATCHDOG_CFG 0x5E
+#define TWL4030_PM_MASTER_IT_CHECK_CFG 0x5F
+#define TWL4030_PM_MASTER_VIBRATOR_CFG 0x60
+#define TWL4030_PM_MASTER_DCDC_GLOBAL_CFG 0x61
+#define TWL4030_PM_MASTER_VDD1_TRIM1 0x62
+#define TWL4030_PM_MASTER_VDD1_TRIM2 0x63
+#define TWL4030_PM_MASTER_VDD2_TRIM1 0x64
+#define TWL4030_PM_MASTER_VDD2_TRIM2 0x65
+#define TWL4030_PM_MASTER_VIO_TRIM1 0x66
+#define TWL4030_PM_MASTER_VIO_TRIM2 0x67
+#define TWL4030_PM_MASTER_MISC_CFG 0x68
+#define TWL4030_PM_MASTER_LS_TST_A 0x69
+#define TWL4030_PM_MASTER_LS_TST_B 0x6A
+#define TWL4030_PM_MASTER_LS_TST_C 0x6B
+#define TWL4030_PM_MASTER_LS_TST_D 0x6C
+#define TWL4030_PM_MASTER_BB_CFG 0x6D
+#define TWL4030_PM_MASTER_MISC_TST 0x6E
+#define TWL4030_PM_MASTER_TRIM1 0x6F
+/* P[1-3]_SW_EVENTS */
+#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON (1 << 6)
+#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_SYSEN (1 << 5)
+#define TWL4030_PM_MASTER_SW_EVENTS_ENABLE_WARMRESET (1 << 4)
+#define TWL4030_PM_MASTER_SW_EVENTS_LVL_WAKEUP (1 << 3)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVACT (1 << 2)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0)
+
+/* Power Managment Receiver */
+#define TWL4030_PM_RECEIVER_SC_CONFIG 0x5B
+#define TWL4030_PM_RECEIVER_SC_DETECT1 0x5C
+#define TWL4030_PM_RECEIVER_SC_DETECT2 0x5D
+#define TWL4030_PM_RECEIVER_WATCHDOG_CFG 0x5E
+#define TWL4030_PM_RECEIVER_IT_CHECK_CFG 0x5F
+#define TWL4030_PM_RECEIVER_VIBRATOR_CFG 0x5F
+#define TWL4030_PM_RECEIVER_DC_TO_DC_CFG 0x61
+#define TWL4030_PM_RECEIVER_VDD1_TRIM1 0x62
+#define TWL4030_PM_RECEIVER_VDD1_TRIM2 0x63
+#define TWL4030_PM_RECEIVER_VDD2_TRIM1 0x64
+#define TWL4030_PM_RECEIVER_VDD2_TRIM2 0x65
+#define TWL4030_PM_RECEIVER_VIO_TRIM1 0x66
+#define TWL4030_PM_RECEIVER_VIO_TRIM2 0x67
+#define TWL4030_PM_RECEIVER_MISC_CFG 0x68
+#define TWL4030_PM_RECEIVER_LS_TST_A 0x69
+#define TWL4030_PM_RECEIVER_LS_TST_B 0x6A
+#define TWL4030_PM_RECEIVER_LS_TST_C 0x6B
+#define TWL4030_PM_RECEIVER_LS_TST_D 0x6C
+#define TWL4030_PM_RECEIVER_BB_CFG 0x6D
+#define TWL4030_PM_RECEIVER_MISC_TST 0x6E
+#define TWL4030_PM_RECEIVER_TRIM1 0x6F
+#define TWL4030_PM_RECEIVER_TRIM2 0x70
+#define TWL4030_PM_RECEIVER_DC_DC_TIMEOUT 0x71
+#define TWL4030_PM_RECEIVER_VAUX1_DEV_GRP 0x72
+#define TWL4030_PM_RECEIVER_VAUX1_TYPE 0x73
+#define TWL4030_PM_RECEIVER_VAUX1_REMAP 0x74
+#define TWL4030_PM_RECEIVER_VAUX1_DEDICATED 0x75
+#define TWL4030_PM_RECEIVER_VAUX2_DEV_GRP 0x76
+#define TWL4030_PM_RECEIVER_VAUX2_TYPE 0x77
+#define TWL4030_PM_RECEIVER_VAUX2_REMAP 0x78
+#define TWL4030_PM_RECEIVER_VAUX2_DEDICATED 0x79
+#define TWL4030_PM_RECEIVER_VAUX3_DEV_GRP 0x7A
+#define TWL4030_PM_RECEIVER_VAUX3_TYPE 0x7B
+#define TWL4030_PM_RECEIVER_VAUX3_REMAP 0x7C
+#define TWL4030_PM_RECEIVER_VAUX3_DEDICATED 0x7D
+#define TWL4030_PM_RECEIVER_VAUX4_DEV_GRP 0x7E
+#define TWL4030_PM_RECEIVER_VAUX4_TYPE 0x7F
+#define TWL4030_PM_RECEIVER_VAUX4_REMAP 0x80
+#define TWL4030_PM_RECEIVER_VAUX4_DEDICATED 0x81
+#define TWL4030_PM_RECEIVER_VMMC1_DEV_GRP 0x82
+#define TWL4030_PM_RECEIVER_VMMC1_TYPE 0x83
+#define TWL4030_PM_RECEIVER_VMMC1_REMAP 0x84
+#define TWL4030_PM_RECEIVER_VMMC1_DEDICATED 0x85
+#define TWL4030_PM_RECEIVER_VMMC2_DEV_GRP 0x86
+#define TWL4030_PM_RECEIVER_VMMC2_TYPE 0x87
+#define TWL4030_PM_RECEIVER_VMMC2_REMAP 0x88
+#define TWL4030_PM_RECEIVER_VMMC2_DEDICATED 0x89
+#define TWL4030_PM_RECEIVER_VPLL1_DEV_GRP 0x8A
+#define TWL4030_PM_RECEIVER_VPLL1_TYPE 0x8B
+#define TWL4030_PM_RECEIVER_VPLL1_REMAP 0x8C
+#define TWL4030_PM_RECEIVER_VPLL1_DEDICATED 0x8D
+#define TWL4030_PM_RECEIVER_VPLL2_DEV_GRP 0x8E
+#define TWL4030_PM_RECEIVER_VPLL2_TYPE 0x8F
+#define TWL4030_PM_RECEIVER_VPLL2_REMAP 0x90
+#define TWL4030_PM_RECEIVER_VPLL2_DEDICATED 0x91
+#define TWL4030_PM_RECEIVER_VSIM_DEV_GRP 0x92
+#define TWL4030_PM_RECEIVER_VSIM_TYPE 0x93
+#define TWL4030_PM_RECEIVER_VSIM_REMAP 0x94
+#define TWL4030_PM_RECEIVER_VSIM_DEDICATED 0x95
+#define TWL4030_PM_RECEIVER_VDAC_DEV_GRP 0x96
+#define TWL4030_PM_RECEIVER_VDAC_TYPE 0x97
+#define TWL4030_PM_RECEIVER_VDAC_REMAP 0x98
+#define TWL4030_PM_RECEIVER_VDAC_DEDICATED 0x99
+#define TWL4030_PM_RECEIVER_VINTANA1_DEV_GRP 0x9A
+#define TWL4030_PM_RECEIVER_VINTANA1_TYP 0x9B
+#define TWL4030_PM_RECEIVER_VINTANA1_REMAP 0x9C
+#define TWL4030_PM_RECEIVER_VINTANA1_DEDICATED 0x9D
+#define TWL4030_PM_RECEIVER_VINTANA2_DEV_GRP 0x9E
+#define TWL4030_PM_RECEIVER_VINTANA2_TYPE 0x9F
+#define TWL4030_PM_RECEIVER_VINTANA2_REMAP 0xA0
+#define TWL4030_PM_RECEIVER_VINTANA2_DEDICATED 0xA1
+#define TWL4030_PM_RECEIVER_VINTDIG_DEV_GRP 0xA2
+#define TWL4030_PM_RECEIVER_VINTDIG_TYPE 0xA3
+#define TWL4030_PM_RECEIVER_VINTDIG_REMAP 0xA4
+#define TWL4030_PM_RECEIVER_VINTDIG_DEDICATED 0xA5
+#define TWL4030_PM_RECEIVER_VIO_DEV_GRP 0xA6
+#define TWL4030_PM_RECEIVER_VIO_TYPE 0xA7
+#define TWL4030_PM_RECEIVER_VIO_REMAP 0xA8
+#define TWL4030_PM_RECEIVER_VIO_CFG 0xA9
+#define TWL4030_PM_RECEIVER_VIO_MISC_CFG 0xAA
+#define TWL4030_PM_RECEIVER_VIO_TEST1 0xAB
+#define TWL4030_PM_RECEIVER_VIO_TEST2 0xAC
+#define TWL4030_PM_RECEIVER_VIO_OSC 0xAD
+#define TWL4030_PM_RECEIVER_VIO_RESERVED 0xAE
+#define TWL4030_PM_RECEIVER_VIO_VSEL 0xAF
+#define TWL4030_PM_RECEIVER_VDD1_DEV_GRP 0xB0
+#define TWL4030_PM_RECEIVER_VDD1_TYPE 0xB1
+#define TWL4030_PM_RECEIVER_VDD1_REMAP 0xB2
+#define TWL4030_PM_RECEIVER_VDD1_CFG 0xB3
+#define TWL4030_PM_RECEIVER_VDD1_MISC_CFG 0xB4
+#define TWL4030_PM_RECEIVER_VDD1_TEST1 0xB5
+#define TWL4030_PM_RECEIVER_VDD1_TEST2 0xB6
+#define TWL4030_PM_RECEIVER_VDD1_OSC 0xB7
+#define TWL4030_PM_RECEIVER_VDD1_RESERVED 0xB8
+#define TWL4030_PM_RECEIVER_VDD1_VSEL 0xB9
+#define TWL4030_PM_RECEIVER_VDD1_VMODE_CFG 0xBA
+#define TWL4030_PM_RECEIVER_VDD1_VFLOOR 0xBB
+#define TWL4030_PM_RECEIVER_VDD1_VROOF 0xBC
+#define TWL4030_PM_RECEIVER_VDD1_STEP 0xBD
+#define TWL4030_PM_RECEIVER_VDD2_DEV_GRP 0xBE
+#define TWL4030_PM_RECEIVER_VDD2_TYPE 0xBF
+#define TWL4030_PM_RECEIVER_VDD2_REMAP 0xC0
+#define TWL4030_PM_RECEIVER_VDD2_CFG 0xC1
+#define TWL4030_PM_RECEIVER_VDD2_MISC_CFG 0xC2
+#define TWL4030_PM_RECEIVER_VDD2_TEST1 0xC3
+#define TWL4030_PM_RECEIVER_VDD2_TEST2 0xC4
+#define TWL4030_PM_RECEIVER_VDD2_OSC 0xC5
+#define TWL4030_PM_RECEIVER_VDD2_RESERVED 0xC6
+#define TWL4030_PM_RECEIVER_VDD2_VSEL 0xC7
+#define TWL4030_PM_RECEIVER_VDD2_VMODE_CFG 0xC8
+#define TWL4030_PM_RECEIVER_VDD2_VFLOOR 0xC9
+#define TWL4030_PM_RECEIVER_VDD2_VROOF 0xCA
+#define TWL4030_PM_RECEIVER_VDD2_STEP 0xCB
+#define TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP 0xCC
+#define TWL4030_PM_RECEIVER_VUSB1V5_TYPE 0xCD
+#define TWL4030_PM_RECEIVER_VUSB1V5_REMAP 0xCE
+#define TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP 0xCF
+#define TWL4030_PM_RECEIVER_VUSB1V8_TYPE 0xD0
+#define TWL4030_PM_RECEIVER_VUSB1V8_REMAP 0xD1
+#define TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP 0xD2
+#define TWL4030_PM_RECEIVER_VUSB3V1_TYPE 0xD3
+#define TWL4030_PM_RECEIVER_VUSB3V1_REMAP 0xD4
+#define TWL4030_PM_RECEIVER_VUSBCP_DEV_GRP 0xD5
+#define TWL4030_PM_RECEIVER_VUSBCP_TYPE 0xD6
+#define TWL4030_PM_RECEIVER_VUSBCP_REMAP 0xD7
+#define TWL4030_PM_RECEIVER_VUSB_DEDICATED1 0xD8
+#define TWL4030_PM_RECEIVER_VUSB_DEDICATED2 0xD9
+#define TWL4030_PM_RECEIVER_REGEN_DEV_GRP 0xDA
+#define TWL4030_PM_RECEIVER_REGEN_TYPE 0xDB
+#define TWL4030_PM_RECEIVER_REGEN_REMAP 0xDC
+#define TWL4030_PM_RECEIVER_NRESPWRON_DEV_GRP 0xDD
+#define TWL4030_PM_RECEIVER_NRESPWRON_TYPE 0xDE
+#define TWL4030_PM_RECEIVER_NRESPWRON_REMAP 0xDF
+#define TWL4030_PM_RECEIVER_CLKEN_DEV_GRP 0xE0
+#define TWL4030_PM_RECEIVER_CLKEN_TYPE 0xE1
+#define TWL4030_PM_RECEIVER_CLKEN_REMAP 0xE2
+#define TWL4030_PM_RECEIVER_SYSEN_DEV_GRP 0xE3
+#define TWL4030_PM_RECEIVER_SYSEN_TYPE 0xE4
+#define TWL4030_PM_RECEIVER_SYSEN_REMAP 0xE5
+#define TWL4030_PM_RECEIVER_HFCLKOUT_DEV_GRP 0xE6
+#define TWL4030_PM_RECEIVER_HFCLKOUT_TYPE 0xE7
+#define TWL4030_PM_RECEIVER_HFCLKOUT_REMAP 0xE8
+#define TWL4030_PM_RECEIVER_32KCLKOUT_DEV_GRP 0xE9
+#define TWL4030_PM_RECEIVER_32KCLKOUT_TYPE 0xEA
+#define TWL4030_PM_RECEIVER_32KCLKOUT_REMAP 0xEB
+#define TWL4030_PM_RECEIVER_TRITON_RESET_DEV_GRP 0xEC
+#define TWL4030_PM_RECEIVER_TRITON_RESET_TYPE 0xED
+#define TWL4030_PM_RECEIVER_TRITON_RESET_REMAP 0xEE
+#define TWL4030_PM_RECEIVER_MAINREF_DEV_GRP 0xEF
+#define TWL4030_PM_RECEIVER_MAINREF_TYPE 0xF0
+#define TWL4030_PM_RECEIVER_MAINREF_REMAP 0xF1
+
+/* LED */
+#define TWL4030_LED_LEDEN 0xEE
+
+/* Keypad */
+#define TWL4030_KEYPAD_KEYP_CTRL_REG 0xD2
+#define TWL4030_KEYPAD_KEY_DEB_REG 0xD3
+#define TWL4030_KEYPAD_LONG_KEY_REG1 0xD4
+#define TWL4030_KEYPAD_LK_PTV_REG 0xD5
+#define TWL4030_KEYPAD_TIME_OUT_REG1 0xD6
+#define TWL4030_KEYPAD_TIME_OUT_REG2 0xD7
+#define TWL4030_KEYPAD_KBC_REG 0xD8
+#define TWL4030_KEYPAD_KBR_REG 0xD9
+#define TWL4030_KEYPAD_KEYP_SMS 0xDA
+#define TWL4030_KEYPAD_FULL_CODE_7_0 0xDB
+#define TWL4030_KEYPAD_FULL_CODE_15_8 0xDC
+#define TWL4030_KEYPAD_FULL_CODE_23_16 0xDD
+#define TWL4030_KEYPAD_FULL_CODE_31_24 0xDE
+#define TWL4030_KEYPAD_FULL_CODE_39_32 0xDF
+#define TWL4030_KEYPAD_FULL_CODE_47_40 0xE0
+#define TWL4030_KEYPAD_FULL_CODE_55_48 0xE1
+#define TWL4030_KEYPAD_FULL_CODE_63_56 0xE2
+#define TWL4030_KEYPAD_KEYP_ISR1 0xE3
+#define TWL4030_KEYPAD_KEYP_IMR1 0xE4
+#define TWL4030_KEYPAD_KEYP_ISR2 0xE5
+#define TWL4030_KEYPAD_KEYP_IMR2 0xE6
+#define TWL4030_KEYPAD_KEYP_SIR 0xE7
+#define TWL4030_KEYPAD_KEYP_EDR 0xE8
+#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0xE9
+
+#define TWL4030_KEYPAD_CTRL_KBD_ON (1 << 6)
+#define TWL4030_KEYPAD_CTRL_RP_EN (1 << 5)
+#define TWL4030_KEYPAD_CTRL_TOLE_EN (1 << 4)
+#define TWL4030_KEYPAD_CTRL_TOE_EN (1 << 3)
+#define TWL4030_KEYPAD_CTRL_LK_EN (1 << 2)
+#define TWL4030_KEYPAD_CTRL_SOFTMODEN (1 << 1)
+#define TWL4030_KEYPAD_CTRL_SOFT_NRST (1 << 0)
+
+/* USB */
+#define TWL4030_USB_FUNC_CTRL (0x04)
+#define TWL4030_USB_OPMODE_MASK (3 << 3)
+#define TWL4030_USB_XCVRSELECT_MASK (3 << 0)
+#define TWL4030_USB_IFC_CTRL (0x07)
+#define TWL4030_USB_CARKITMODE (1 << 2)
+#define TWL4030_USB_POWER_CTRL (0xAC)
+#define TWL4030_USB_OTG_ENAB (1 << 5)
+#define TWL4030_USB_PHY_PWR_CTRL (0xFD)
+#define TWL4030_USB_PHYPWD (1 << 0)
+#define TWL4030_USB_PHY_CLK_CTRL (0xFE)
+#define TWL4030_USB_CLOCKGATING_EN (1 << 2)
+#define TWL4030_USB_CLK32K_EN (1 << 1)
+#define TWL4030_USB_REQ_PHY_DPLL_CLK (1 << 0)
+#define TWL4030_USB_PHY_CLK_CTRL_STS (0xFF)
+#define TWL4030_USB_PHY_DPLL_CLK (1 << 0)
+
+/*
+ * Convience functions to read and write from TWL4030
+ *
+ * chip_no is the i2c address, it must be one of the chip addresses
+ * defined at the top of this file with the prefix TWL4030_CHIP_
+ * examples are TWL4030_CHIP_PM_RECEIVER and TWL4030_CHIP_KEYPAD
+ *
+ * val is the data either written to or read from the twl4030
+ *
+ * reg is the register to act on, it must be one of the defines
+ * above and with the format TWL4030_<chip suffix>_<register name>
+ * examples are TWL4030_PM_RECEIVER_VMMC1_DEV_GRP and
+ * TWL4030_LED_LEDEN.
+ */
+static inline int twl4030_i2c_write_u8(u8 chip_no, u8 val, u8 reg)
+{
+ return i2c_write(chip_no, reg, 1, &val, 1);
+}
+
+static inline int twl4030_i2c_read_u8(u8 chip_no, u8 *val, u8 reg)
+{
+ return i2c_read(chip_no, reg, 1, val, 1);
+}
+
+/*
+ * Power
+ */
+
+/* For hardware resetting */
+void twl4030_power_reset_init(void);
+/* For initializing power device */
+void twl4030_power_init(void);
+/* For initializing mmc power */
+void twl4030_power_mmc_init(void);
+
+/*
+ * LED
+ */
+void twl4030_led_init(void);
+
+#endif /* TWL4030_H */
#ifndef _MD5_H
#define _MD5_H
-#include <linux/types.h>
+#include "compiler.h"
struct MD5Context {
__u32 buf[4];
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(ARCH).a
+LIBGCC = $(obj)libgcc.a
-SOBJS-y += _ashldi3.o
-SOBJS-y += _ashrdi3.o
-SOBJS-y += _divsi3.o
-SOBJS-y += _modsi3.o
-SOBJS-y += _udivsi3.o
-SOBJS-y += _umodsi3.o
+GLSOBJS += _ashldi3.o
+GLSOBJS += _ashrdi3.o
+GLSOBJS += _divsi3.o
+GLSOBJS += _lshrdi3.o
+GLSOBJS += _modsi3.o
+GLSOBJS += _udivsi3.o
+GLSOBJS += _umodsi3.o
+
+GLCOBJS += div0.o
COBJS-y += board.o
COBJS-y += bootm.o
ifndef CONFIG_SYS_NO_CP15_CACHE
COBJS-y += cache-cp15.o
endif
-COBJS-y += div0.o
COBJS-y += interrupts.o
COBJS-y += reset.o
-SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \
+ $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+LGOBJS := $(addprefix $(obj),$(GLSOBJS)) \
+ $(addprefix $(obj),$(GLCOBJS))
+
+ifdef USE_PRIVATE_LIBGCC
+all: $(LIB) $(LIBGCC)
+else
+all: $(LIB)
+endif
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
+$(LIBGCC): $(obj).depend $(LGOBJS)
+ $(AR) $(ARFLAGS) $@ $(LGOBJS)
+
#########################################################################
# defines $(obj).depend target
--- /dev/null
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
+ Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file into combinations with other programs,
+and to distribute those combinations without any restriction coming
+from the use of this file. (The General Public License restrictions
+do apply in other respects; for example, they cover modification of
+the file, and distribution when not linked into a combine
+executable.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING. If not, write to
+the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+Boston, MA 02110-1301, USA. */
+
+
+#ifdef __ARMEB__
+#define al r1
+#define ah r0
+#else
+#define al r0
+#define ah r1
+#endif
+
+.globl __lshrdi3
+__lshrdi3:
+
+ subs r3, r2, #32
+ rsb ip, r2, #32
+ movmi al, al, lsr r2
+ movpl al, ah, lsr r3
+ orrmi al, al, ah, lsl ip
+ mov ah, ah, lsr r2
+ mov pc, lr
#include <common.h>
#include <command.h>
#include <malloc.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <timestamp.h>
#include <version.h>
#include <net.h>
/* IP Address */
gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
- devices_init (); /* get the devices list going. */
+ stdio_init (); /* get the devices list going. */
jumptable_init ();
# MA 02111-1307 USA
#
+CROSS_COMPILE ?= arm-linux-
+
PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
LDSCRIPT := $(SRCTREE)/cpu/$(CPU)/u-boot.lds
#include <common.h>
#include <command.h>
#include <malloc.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <timestamp.h>
#include <version.h>
#include <net.h>
addr -= CONFIG_SYS_DMA_ALLOC_LEN;
#endif
+#ifdef CONFIG_LCD
+#ifdef CONFIG_FB_ADDR
+ printf("LCD: Frame buffer allocated at preset 0x%08x\n",
+ CONFIG_FB_ADDR);
+ gd->fb_base = (void *)CONFIG_FB_ADDR;
+#else
+ addr = lcd_setmem(addr);
+ printf("LCD: Frame buffer allocated at 0x%08lx\n", addr);
+ gd->fb_base = (void *)addr;
+#endif /* CONFIG_FB_ADDR */
+#endif /* CONFIG_LCD */
+
/* Allocate a Board Info struct on a word boundary */
addr -= sizeof(bd_t);
addr &= ~3UL;
bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
- devices_init();
+ stdio_init();
jumptable_init();
console_init_r();
# MA 02111-1307 USA
#
+CROSS_COMPILE ?= avr32-linux-
+
PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax
PLATFORM_LDFLAGS += --relax
#include <common.h>
#include <command.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <environment.h>
#include <malloc.h>
#include <net.h>
/* relocate environment function pointers etc. */
env_relocate();
- /* Initialize devices */
- devices_init();
+ /* Initialize stdio devices */
+ stdio_init();
jumptable_init();
/* Initialize the console (after the relocation and devices init) */
post_run(NULL, POST_RAM | post_bootmode_get(0));
#endif
+ if (bfin_os_log_check()) {
+ puts("\nLog buffer from operating system:\n");
+ bfin_os_log_dump();
+ puts("\n");
+ }
+
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;)
main_loop();
# MA 02111-1307 USA
#
+CROSS_COMPILE ?= bfin-uclinux-
+
CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU)))
CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE)))
CONFIG_ENV_OFFSET := $(strip $(subst ",,$(CONFIG_ENV_OFFSET)))
*/
#include <common.h>
-#include <console.h>
+#include <stdio_dev.h>
#include <watchdog.h>
#include <post.h>
# define L1_DATA_B_SRAM_SIZE 0
#endif
+/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
+#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
+# define L1_CODE_ORIGIN L1_INST_SRAM
+#else
+# define L1_CODE_ORIGIN L1_INST_SRAM + 0xC
+#endif
+
OUTPUT_ARCH(bfin)
MEMORY
{
ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
- l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_code : ORIGIN = L1_CODE_ORIGIN, LENGTH = L1_INST_SRAM_SIZE
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
return crc ^ 0xffffffffL;
}
-#if defined(CONFIG_CMD_JFFS2) || \
- (defined(CONFIG_CMD_NAND) \
- && !defined(CONFIG_NAND_LEGACY))
+#if defined(CONFIG_CMD_JFFS2) || defined(CONFIG_CMD_NAND)
/* No ones complement version. JFFS2 (and other things ?)
* don't use ones compliment in their CRC calculations.
+++ /dev/null
- GNU LESSER GENERAL PUBLIC LICENSE
- Version 2.1, February 1999
-
- Copyright (C) 1991, 1999 Free Software Foundation, Inc.
- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
-[This is the first released version of the Lesser GPL. It also counts
- as the successor of the GNU Library Public License, version 2, hence
- the version number 2.1.]
-
- Preamble
-
- The licenses for most software are designed to take away your
-freedom to share and change it. By contrast, the GNU General Public
-Licenses are intended to guarantee your freedom to share and change
-free software--to make sure the software is free for all its users.
-
- This license, the Lesser General Public License, applies to some
-specially designated software packages--typically libraries--of the
-Free Software Foundation and other authors who decide to use it. You
-can use it too, but we suggest you first think carefully about whether
-this license or the ordinary General Public License is the better
-strategy to use in any particular case, based on the explanations below.
-
- When we speak of free software, we are referring to freedom of use,
-not price. Our General Public Licenses are designed to make sure that
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-That's all there is to it!
--- /dev/null
+/* LzmaDec.c -- LZMA Decoder
+2008-11-06 : Igor Pavlov : Public domain */
+
+#include <config.h>
+#include <common.h>
+#include <watchdog.h>
+#include "LzmaDec.h"
+
+#include <string.h>
+
+#define kNumTopBits 24
+#define kTopValue ((UInt32)1 << kNumTopBits)
+
+#define kNumBitModelTotalBits 11
+#define kBitModelTotal (1 << kNumBitModelTotalBits)
+#define kNumMoveBits 5
+
+#define RC_INIT_SIZE 5
+
+#define NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | (*buf++); }
+
+#define IF_BIT_0(p) ttt = *(p); NORMALIZE; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound)
+#define UPDATE_0(p) range = bound; *(p) = (CLzmaProb)(ttt + ((kBitModelTotal - ttt) >> kNumMoveBits));
+#define UPDATE_1(p) range -= bound; code -= bound; *(p) = (CLzmaProb)(ttt - (ttt >> kNumMoveBits));
+#define GET_BIT2(p, i, A0, A1) IF_BIT_0(p) \
+ { UPDATE_0(p); i = (i + i); A0; } else \
+ { UPDATE_1(p); i = (i + i) + 1; A1; }
+#define GET_BIT(p, i) GET_BIT2(p, i, ; , ;)
+
+#define TREE_GET_BIT(probs, i) { GET_BIT((probs + i), i); }
+#define TREE_DECODE(probs, limit, i) \
+ { i = 1; do { TREE_GET_BIT(probs, i); } while (i < limit); i -= limit; }
+
+/* #define _LZMA_SIZE_OPT */
+
+#ifdef _LZMA_SIZE_OPT
+#define TREE_6_DECODE(probs, i) TREE_DECODE(probs, (1 << 6), i)
+#else
+#define TREE_6_DECODE(probs, i) \
+ { i = 1; \
+ TREE_GET_BIT(probs, i); \
+ TREE_GET_BIT(probs, i); \
+ TREE_GET_BIT(probs, i); \
+ TREE_GET_BIT(probs, i); \
+ TREE_GET_BIT(probs, i); \
+ TREE_GET_BIT(probs, i); \
+ i -= 0x40; }
+#endif
+
+#define NORMALIZE_CHECK if (range < kTopValue) { if (buf >= bufLimit) return DUMMY_ERROR; range <<= 8; code = (code << 8) | (*buf++); }
+
+#define IF_BIT_0_CHECK(p) ttt = *(p); NORMALIZE_CHECK; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound)
+#define UPDATE_0_CHECK range = bound;
+#define UPDATE_1_CHECK range -= bound; code -= bound;
+#define GET_BIT2_CHECK(p, i, A0, A1) IF_BIT_0_CHECK(p) \
+ { UPDATE_0_CHECK; i = (i + i); A0; } else \
+ { UPDATE_1_CHECK; i = (i + i) + 1; A1; }
+#define GET_BIT_CHECK(p, i) GET_BIT2_CHECK(p, i, ; , ;)
+#define TREE_DECODE_CHECK(probs, limit, i) \
+ { i = 1; do { GET_BIT_CHECK(probs + i, i) } while (i < limit); i -= limit; }
+
+
+#define kNumPosBitsMax 4
+#define kNumPosStatesMax (1 << kNumPosBitsMax)
+
+#define kLenNumLowBits 3
+#define kLenNumLowSymbols (1 << kLenNumLowBits)
+#define kLenNumMidBits 3
+#define kLenNumMidSymbols (1 << kLenNumMidBits)
+#define kLenNumHighBits 8
+#define kLenNumHighSymbols (1 << kLenNumHighBits)
+
+#define LenChoice 0
+#define LenChoice2 (LenChoice + 1)
+#define LenLow (LenChoice2 + 1)
+#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))
+#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))
+#define kNumLenProbs (LenHigh + kLenNumHighSymbols)
+
+
+#define kNumStates 12
+#define kNumLitStates 7
+
+#define kStartPosModelIndex 4
+#define kEndPosModelIndex 14
+#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))
+
+#define kNumPosSlotBits 6
+#define kNumLenToPosStates 4
+
+#define kNumAlignBits 4
+#define kAlignTableSize (1 << kNumAlignBits)
+
+#define kMatchMinLen 2
+#define kMatchSpecLenStart (kMatchMinLen + kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols)
+
+#define IsMatch 0
+#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))
+#define IsRepG0 (IsRep + kNumStates)
+#define IsRepG1 (IsRepG0 + kNumStates)
+#define IsRepG2 (IsRepG1 + kNumStates)
+#define IsRep0Long (IsRepG2 + kNumStates)
+#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))
+#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))
+#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)
+#define LenCoder (Align + kAlignTableSize)
+#define RepLenCoder (LenCoder + kNumLenProbs)
+#define Literal (RepLenCoder + kNumLenProbs)
+
+#define LZMA_BASE_SIZE 1846
+#define LZMA_LIT_SIZE 768
+
+#define LzmaProps_GetNumProbs(p) ((UInt32)LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((p)->lc + (p)->lp)))
+
+#if Literal != LZMA_BASE_SIZE
+StopCompilingDueBUG
+#endif
+
+static const Byte kLiteralNextStates[kNumStates * 2] =
+{
+ 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 4, 5,
+ 7, 7, 7, 7, 7, 7, 7, 10, 10, 10, 10, 10
+};
+
+#define LZMA_DIC_MIN (1 << 12)
+
+/* First LZMA-symbol is always decoded.
+And it decodes new LZMA-symbols while (buf < bufLimit), but "buf" is without last normalization
+Out:
+ Result:
+ SZ_OK - OK
+ SZ_ERROR_DATA - Error
+ p->remainLen:
+ < kMatchSpecLenStart : normal remain
+ = kMatchSpecLenStart : finished
+ = kMatchSpecLenStart + 1 : Flush marker
+ = kMatchSpecLenStart + 2 : State Init Marker
+*/
+
+static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte *bufLimit)
+{
+ CLzmaProb *probs = p->probs;
+
+ unsigned state = p->state;
+ UInt32 rep0 = p->reps[0], rep1 = p->reps[1], rep2 = p->reps[2], rep3 = p->reps[3];
+ unsigned pbMask = ((unsigned)1 << (p->prop.pb)) - 1;
+ unsigned lpMask = ((unsigned)1 << (p->prop.lp)) - 1;
+ unsigned lc = p->prop.lc;
+
+ Byte *dic = p->dic;
+ SizeT dicBufSize = p->dicBufSize;
+ SizeT dicPos = p->dicPos;
+
+ UInt32 processedPos = p->processedPos;
+ UInt32 checkDicSize = p->checkDicSize;
+ unsigned len = 0;
+
+ const Byte *buf = p->buf;
+ UInt32 range = p->range;
+ UInt32 code = p->code;
+
+ WATCHDOG_RESET();
+
+ do
+ {
+ CLzmaProb *prob;
+ UInt32 bound;
+ unsigned ttt;
+ unsigned posState = processedPos & pbMask;
+
+ prob = probs + IsMatch + (state << kNumPosBitsMax) + posState;
+ IF_BIT_0(prob)
+ {
+ unsigned symbol;
+ UPDATE_0(prob);
+ prob = probs + Literal;
+ if (checkDicSize != 0 || processedPos != 0)
+ prob += (LZMA_LIT_SIZE * (((processedPos & lpMask) << lc) +
+ (dic[(dicPos == 0 ? dicBufSize : dicPos) - 1] >> (8 - lc))));
+
+ if (state < kNumLitStates)
+ {
+ symbol = 1;
+
+ WATCHDOG_RESET();
+
+ do { GET_BIT(prob + symbol, symbol) } while (symbol < 0x100);
+ }
+ else
+ {
+ unsigned matchByte = p->dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];
+ unsigned offs = 0x100;
+ symbol = 1;
+
+ WATCHDOG_RESET();
+
+ do
+ {
+ unsigned bit;
+ CLzmaProb *probLit;
+ matchByte <<= 1;
+ bit = (matchByte & offs);
+ probLit = prob + offs + bit + symbol;
+ GET_BIT2(probLit, symbol, offs &= ~bit, offs &= bit)
+ }
+ while (symbol < 0x100);
+ }
+ dic[dicPos++] = (Byte)symbol;
+ processedPos++;
+
+ state = kLiteralNextStates[state];
+ /* if (state < 4) state = 0; else if (state < 10) state -= 3; else state -= 6; */
+ continue;
+ }
+ else
+ {
+ UPDATE_1(prob);
+ prob = probs + IsRep + state;
+ IF_BIT_0(prob)
+ {
+ UPDATE_0(prob);
+ state += kNumStates;
+ prob = probs + LenCoder;
+ }
+ else
+ {
+ UPDATE_1(prob);
+ if (checkDicSize == 0 && processedPos == 0)
+ return SZ_ERROR_DATA;
+ prob = probs + IsRepG0 + state;
+ IF_BIT_0(prob)
+ {
+ UPDATE_0(prob);
+ prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState;
+ IF_BIT_0(prob)
+ {
+ UPDATE_0(prob);
+ dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];
+ dicPos++;
+ processedPos++;
+ state = state < kNumLitStates ? 9 : 11;
+ continue;
+ }
+ UPDATE_1(prob);
+ }
+ else
+ {
+ UInt32 distance;
+ UPDATE_1(prob);
+ prob = probs + IsRepG1 + state;
+ IF_BIT_0(prob)
+ {
+ UPDATE_0(prob);
+ distance = rep1;
+ }
+ else
+ {
+ UPDATE_1(prob);
+ prob = probs + IsRepG2 + state;
+ IF_BIT_0(prob)
+ {
+ UPDATE_0(prob);
+ distance = rep2;
+ }
+ else
+ {
+ UPDATE_1(prob);
+ distance = rep3;
+ rep3 = rep2;
+ }
+ rep2 = rep1;
+ }
+ rep1 = rep0;
+ rep0 = distance;
+ }
+ state = state < kNumLitStates ? 8 : 11;
+ prob = probs + RepLenCoder;
+ }
+ {
+ unsigned limit, offset;
+ CLzmaProb *probLen = prob + LenChoice;
+ IF_BIT_0(probLen)
+ {
+ UPDATE_0(probLen);
+ probLen = prob + LenLow + (posState << kLenNumLowBits);
+ offset = 0;
+ limit = (1 << kLenNumLowBits);
+ }
+ else
+ {
+ UPDATE_1(probLen);
+ probLen = prob + LenChoice2;
+ IF_BIT_0(probLen)
+ {
+ UPDATE_0(probLen);
+ probLen = prob + LenMid + (posState << kLenNumMidBits);
+ offset = kLenNumLowSymbols;
+ limit = (1 << kLenNumMidBits);
+ }
+ else
+ {
+ UPDATE_1(probLen);
+ probLen = prob + LenHigh;
+ offset = kLenNumLowSymbols + kLenNumMidSymbols;
+ limit = (1 << kLenNumHighBits);
+ }
+ }
+ TREE_DECODE(probLen, limit, len);
+ len += offset;
+ }
+
+ if (state >= kNumStates)
+ {
+ UInt32 distance;
+ prob = probs + PosSlot +
+ ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits);
+ TREE_6_DECODE(prob, distance);
+ if (distance >= kStartPosModelIndex)
+ {
+ unsigned posSlot = (unsigned)distance;
+ int numDirectBits = (int)(((distance >> 1) - 1));
+ distance = (2 | (distance & 1));
+ if (posSlot < kEndPosModelIndex)
+ {
+ distance <<= numDirectBits;
+ prob = probs + SpecPos + distance - posSlot - 1;
+ {
+ UInt32 mask = 1;
+ unsigned i = 1;
+
+ WATCHDOG_RESET();
+
+ do
+ {
+ GET_BIT2(prob + i, i, ; , distance |= mask);
+ mask <<= 1;
+ }
+ while (--numDirectBits != 0);
+ }
+ }
+ else
+ {
+ numDirectBits -= kNumAlignBits;
+
+ WATCHDOG_RESET();
+
+ do
+ {
+ NORMALIZE
+ range >>= 1;
+
+ {
+ UInt32 t;
+ code -= range;
+ t = (0 - ((UInt32)code >> 31)); /* (UInt32)((Int32)code >> 31) */
+ distance = (distance << 1) + (t + 1);
+ code += range & t;
+ }
+ /*
+ distance <<= 1;
+ if (code >= range)
+ {
+ code -= range;
+ distance |= 1;
+ }
+ */
+ }
+ while (--numDirectBits != 0);
+ prob = probs + Align;
+ distance <<= kNumAlignBits;
+ {
+ unsigned i = 1;
+ GET_BIT2(prob + i, i, ; , distance |= 1);
+ GET_BIT2(prob + i, i, ; , distance |= 2);
+ GET_BIT2(prob + i, i, ; , distance |= 4);
+ GET_BIT2(prob + i, i, ; , distance |= 8);
+ }
+ if (distance == (UInt32)0xFFFFFFFF)
+ {
+ len += kMatchSpecLenStart;
+ state -= kNumStates;
+ break;
+ }
+ }
+ }
+ rep3 = rep2;
+ rep2 = rep1;
+ rep1 = rep0;
+ rep0 = distance + 1;
+ if (checkDicSize == 0)
+ {
+ if (distance >= processedPos)
+ return SZ_ERROR_DATA;
+ }
+ else if (distance >= checkDicSize)
+ return SZ_ERROR_DATA;
+ state = (state < kNumStates + kNumLitStates) ? kNumLitStates : kNumLitStates + 3;
+ /* state = kLiteralNextStates[state]; */
+ }
+
+ len += kMatchMinLen;
+
+ if (limit == dicPos)
+ return SZ_ERROR_DATA;
+ {
+ SizeT rem = limit - dicPos;
+ unsigned curLen = ((rem < len) ? (unsigned)rem : len);
+ SizeT pos = (dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0);
+
+ processedPos += curLen;
+
+ len -= curLen;
+ if (pos + curLen <= dicBufSize)
+ {
+ Byte *dest = dic + dicPos;
+ ptrdiff_t src = (ptrdiff_t)pos - (ptrdiff_t)dicPos;
+ const Byte *lim = dest + curLen;
+ dicPos += curLen;
+
+ WATCHDOG_RESET();
+
+ do
+ *(dest) = (Byte)*(dest + src);
+ while (++dest != lim);
+ }
+ else
+ {
+
+ WATCHDOG_RESET();
+
+ do
+ {
+ dic[dicPos++] = dic[pos];
+ if (++pos == dicBufSize)
+ pos = 0;
+ }
+ while (--curLen != 0);
+ }
+ }
+ }
+ }
+ while (dicPos < limit && buf < bufLimit);
+
+ WATCHDOG_RESET();
+
+ NORMALIZE;
+ p->buf = buf;
+ p->range = range;
+ p->code = code;
+ p->remainLen = len;
+ p->dicPos = dicPos;
+ p->processedPos = processedPos;
+ p->reps[0] = rep0;
+ p->reps[1] = rep1;
+ p->reps[2] = rep2;
+ p->reps[3] = rep3;
+ p->state = state;
+
+ return SZ_OK;
+}
+
+static void MY_FAST_CALL LzmaDec_WriteRem(CLzmaDec *p, SizeT limit)
+{
+ if (p->remainLen != 0 && p->remainLen < kMatchSpecLenStart)
+ {
+ Byte *dic = p->dic;
+ SizeT dicPos = p->dicPos;
+ SizeT dicBufSize = p->dicBufSize;
+ unsigned len = p->remainLen;
+ UInt32 rep0 = p->reps[0];
+ if (limit - dicPos < len)
+ len = (unsigned)(limit - dicPos);
+
+ if (p->checkDicSize == 0 && p->prop.dicSize - p->processedPos <= len)
+ p->checkDicSize = p->prop.dicSize;
+
+ p->processedPos += len;
+ p->remainLen -= len;
+ while (len-- != 0)
+ {
+ dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];
+ dicPos++;
+ }
+ p->dicPos = dicPos;
+ }
+}
+
+static int MY_FAST_CALL LzmaDec_DecodeReal2(CLzmaDec *p, SizeT limit, const Byte *bufLimit)
+{
+ do
+ {
+ SizeT limit2 = limit;
+ if (p->checkDicSize == 0)
+ {
+ UInt32 rem = p->prop.dicSize - p->processedPos;
+ if (limit - p->dicPos > rem)
+ limit2 = p->dicPos + rem;
+ }
+ RINOK(LzmaDec_DecodeReal(p, limit2, bufLimit));
+ if (p->processedPos >= p->prop.dicSize)
+ p->checkDicSize = p->prop.dicSize;
+ LzmaDec_WriteRem(p, limit);
+ }
+ while (p->dicPos < limit && p->buf < bufLimit && p->remainLen < kMatchSpecLenStart);
+
+ if (p->remainLen > kMatchSpecLenStart)
+ {
+ p->remainLen = kMatchSpecLenStart;
+ }
+ return 0;
+}
+
+typedef enum
+{
+ DUMMY_ERROR, /* unexpected end of input stream */
+ DUMMY_LIT,
+ DUMMY_MATCH,
+ DUMMY_REP
+} ELzmaDummy;
+
+static ELzmaDummy LzmaDec_TryDummy(const CLzmaDec *p, const Byte *buf, SizeT inSize)
+{
+ UInt32 range = p->range;
+ UInt32 code = p->code;
+ const Byte *bufLimit = buf + inSize;
+ CLzmaProb *probs = p->probs;
+ unsigned state = p->state;
+ ELzmaDummy res;
+
+ {
+ CLzmaProb *prob;
+ UInt32 bound;
+ unsigned ttt;
+ unsigned posState = (p->processedPos) & ((1 << p->prop.pb) - 1);
+
+ prob = probs + IsMatch + (state << kNumPosBitsMax) + posState;
+ IF_BIT_0_CHECK(prob)
+ {
+ UPDATE_0_CHECK
+
+ /* if (bufLimit - buf >= 7) return DUMMY_LIT; */
+
+ prob = probs + Literal;
+ if (p->checkDicSize != 0 || p->processedPos != 0)
+ prob += (LZMA_LIT_SIZE *
+ ((((p->processedPos) & ((1 << (p->prop.lp)) - 1)) << p->prop.lc) +
+ (p->dic[(p->dicPos == 0 ? p->dicBufSize : p->dicPos) - 1] >> (8 - p->prop.lc))));
+
+ if (state < kNumLitStates)
+ {
+ unsigned symbol = 1;
+ do { GET_BIT_CHECK(prob + symbol, symbol) } while (symbol < 0x100);
+ }
+ else
+ {
+ unsigned matchByte = p->dic[p->dicPos - p->reps[0] +
+ ((p->dicPos < p->reps[0]) ? p->dicBufSize : 0)];
+ unsigned offs = 0x100;
+ unsigned symbol = 1;
+ do
+ {
+ unsigned bit;
+ CLzmaProb *probLit;
+ matchByte <<= 1;
+ bit = (matchByte & offs);
+ probLit = prob + offs + bit + symbol;
+ GET_BIT2_CHECK(probLit, symbol, offs &= ~bit, offs &= bit)
+ }
+ while (symbol < 0x100);
+ }
+ res = DUMMY_LIT;
+ }
+ else
+ {
+ unsigned len;
+ UPDATE_1_CHECK;
+
+ prob = probs + IsRep + state;
+ IF_BIT_0_CHECK(prob)
+ {
+ UPDATE_0_CHECK;
+ state = 0;
+ prob = probs + LenCoder;
+ res = DUMMY_MATCH;
+ }
+ else
+ {
+ UPDATE_1_CHECK;
+ res = DUMMY_REP;
+ prob = probs + IsRepG0 + state;
+ IF_BIT_0_CHECK(prob)
+ {
+ UPDATE_0_CHECK;
+ prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState;
+ IF_BIT_0_CHECK(prob)
+ {
+ UPDATE_0_CHECK;
+ NORMALIZE_CHECK;
+ return DUMMY_REP;
+ }
+ else
+ {
+ UPDATE_1_CHECK;
+ }
+ }
+ else
+ {
+ UPDATE_1_CHECK;
+ prob = probs + IsRepG1 + state;
+ IF_BIT_0_CHECK(prob)
+ {
+ UPDATE_0_CHECK;
+ }
+ else
+ {
+ UPDATE_1_CHECK;
+ prob = probs + IsRepG2 + state;
+ IF_BIT_0_CHECK(prob)
+ {
+ UPDATE_0_CHECK;
+ }
+ else
+ {
+ UPDATE_1_CHECK;
+ }
+ }
+ }
+ state = kNumStates;
+ prob = probs + RepLenCoder;
+ }
+ {
+ unsigned limit, offset;
+ CLzmaProb *probLen = prob + LenChoice;
+ IF_BIT_0_CHECK(probLen)
+ {
+ UPDATE_0_CHECK;
+ probLen = prob + LenLow + (posState << kLenNumLowBits);
+ offset = 0;
+ limit = 1 << kLenNumLowBits;
+ }
+ else
+ {
+ UPDATE_1_CHECK;
+ probLen = prob + LenChoice2;
+ IF_BIT_0_CHECK(probLen)
+ {
+ UPDATE_0_CHECK;
+ probLen = prob + LenMid + (posState << kLenNumMidBits);
+ offset = kLenNumLowSymbols;
+ limit = 1 << kLenNumMidBits;
+ }
+ else
+ {
+ UPDATE_1_CHECK;
+ probLen = prob + LenHigh;
+ offset = kLenNumLowSymbols + kLenNumMidSymbols;
+ limit = 1 << kLenNumHighBits;
+ }
+ }
+ TREE_DECODE_CHECK(probLen, limit, len);
+ len += offset;
+ }
+
+ if (state < 4)
+ {
+ unsigned posSlot;
+ prob = probs + PosSlot +
+ ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) <<
+ kNumPosSlotBits);
+ TREE_DECODE_CHECK(prob, 1 << kNumPosSlotBits, posSlot);
+ if (posSlot >= kStartPosModelIndex)
+ {
+ int numDirectBits = ((posSlot >> 1) - 1);
+
+ /* if (bufLimit - buf >= 8) return DUMMY_MATCH; */
+
+ if (posSlot < kEndPosModelIndex)
+ {
+ prob = probs + SpecPos + ((2 | (posSlot & 1)) << numDirectBits) - posSlot - 1;
+ }
+ else
+ {
+ numDirectBits -= kNumAlignBits;
+ do
+ {
+ NORMALIZE_CHECK
+ range >>= 1;
+ code -= range & (((code - range) >> 31) - 1);
+ /* if (code >= range) code -= range; */
+ }
+ while (--numDirectBits != 0);
+ prob = probs + Align;
+ numDirectBits = kNumAlignBits;
+ }
+ {
+ unsigned i = 1;
+ do
+ {
+ GET_BIT_CHECK(prob + i, i);
+ }
+ while (--numDirectBits != 0);
+ }
+ }
+ }
+ }
+ }
+ NORMALIZE_CHECK;
+ return res;
+}
+
+
+static void LzmaDec_InitRc(CLzmaDec *p, const Byte *data)
+{
+ p->code = ((UInt32)data[1] << 24) | ((UInt32)data[2] << 16) | ((UInt32)data[3] << 8) | ((UInt32)data[4]);
+ p->range = 0xFFFFFFFF;
+ p->needFlush = 0;
+}
+
+void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState)
+{
+ p->needFlush = 1;
+ p->remainLen = 0;
+ p->tempBufSize = 0;
+
+ if (initDic)
+ {
+ p->processedPos = 0;
+ p->checkDicSize = 0;
+ p->needInitState = 1;
+ }
+ if (initState)
+ p->needInitState = 1;
+}
+
+void LzmaDec_Init(CLzmaDec *p)
+{
+ p->dicPos = 0;
+ LzmaDec_InitDicAndState(p, True, True);
+}
+
+static void LzmaDec_InitStateReal(CLzmaDec *p)
+{
+ UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (p->prop.lc + p->prop.lp));
+ UInt32 i;
+ CLzmaProb *probs = p->probs;
+ for (i = 0; i < numProbs; i++)
+ probs[i] = kBitModelTotal >> 1;
+ p->reps[0] = p->reps[1] = p->reps[2] = p->reps[3] = 1;
+ p->state = 0;
+ p->needInitState = 0;
+}
+
+SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen,
+ ELzmaFinishMode finishMode, ELzmaStatus *status)
+{
+ SizeT inSize = *srcLen;
+ (*srcLen) = 0;
+ LzmaDec_WriteRem(p, dicLimit);
+
+ *status = LZMA_STATUS_NOT_SPECIFIED;
+
+ while (p->remainLen != kMatchSpecLenStart)
+ {
+ int checkEndMarkNow;
+
+ if (p->needFlush != 0)
+ {
+ for (; inSize > 0 && p->tempBufSize < RC_INIT_SIZE; (*srcLen)++, inSize--)
+ p->tempBuf[p->tempBufSize++] = *src++;
+ if (p->tempBufSize < RC_INIT_SIZE)
+ {
+ *status = LZMA_STATUS_NEEDS_MORE_INPUT;
+ return SZ_OK;
+ }
+ if (p->tempBuf[0] != 0)
+ return SZ_ERROR_DATA;
+
+ LzmaDec_InitRc(p, p->tempBuf);
+ p->tempBufSize = 0;
+ }
+
+ checkEndMarkNow = 0;
+ if (p->dicPos >= dicLimit)
+ {
+ if (p->remainLen == 0 && p->code == 0)
+ {
+ *status = LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK;
+ return SZ_OK;
+ }
+ if (finishMode == LZMA_FINISH_ANY)
+ {
+ *status = LZMA_STATUS_NOT_FINISHED;
+ return SZ_OK;
+ }
+ if (p->remainLen != 0)
+ {
+ *status = LZMA_STATUS_NOT_FINISHED;
+ return SZ_ERROR_DATA;
+ }
+ checkEndMarkNow = 1;
+ }
+
+ if (p->needInitState)
+ LzmaDec_InitStateReal(p);
+
+ if (p->tempBufSize == 0)
+ {
+ SizeT processed;
+ const Byte *bufLimit;
+ if (inSize < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow)
+ {
+ int dummyRes = LzmaDec_TryDummy(p, src, inSize);
+ if (dummyRes == DUMMY_ERROR)
+ {
+ memcpy(p->tempBuf, src, inSize);
+ p->tempBufSize = (unsigned)inSize;
+ (*srcLen) += inSize;
+ *status = LZMA_STATUS_NEEDS_MORE_INPUT;
+ return SZ_OK;
+ }
+ if (checkEndMarkNow && dummyRes != DUMMY_MATCH)
+ {
+ *status = LZMA_STATUS_NOT_FINISHED;
+ return SZ_ERROR_DATA;
+ }
+ bufLimit = src;
+ }
+ else
+ bufLimit = src + inSize - LZMA_REQUIRED_INPUT_MAX;
+ p->buf = src;
+ if (LzmaDec_DecodeReal2(p, dicLimit, bufLimit) != 0)
+ return SZ_ERROR_DATA;
+ processed = (SizeT)(p->buf - src);
+ (*srcLen) += processed;
+ src += processed;
+ inSize -= processed;
+ }
+ else
+ {
+ unsigned rem = p->tempBufSize, lookAhead = 0;
+ while (rem < LZMA_REQUIRED_INPUT_MAX && lookAhead < inSize)
+ p->tempBuf[rem++] = src[lookAhead++];
+ p->tempBufSize = rem;
+ if (rem < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow)
+ {
+ int dummyRes = LzmaDec_TryDummy(p, p->tempBuf, rem);
+ if (dummyRes == DUMMY_ERROR)
+ {
+ (*srcLen) += lookAhead;
+ *status = LZMA_STATUS_NEEDS_MORE_INPUT;
+ return SZ_OK;
+ }
+ if (checkEndMarkNow && dummyRes != DUMMY_MATCH)
+ {
+ *status = LZMA_STATUS_NOT_FINISHED;
+ return SZ_ERROR_DATA;
+ }
+ }
+ p->buf = p->tempBuf;
+ if (LzmaDec_DecodeReal2(p, dicLimit, p->buf) != 0)
+ return SZ_ERROR_DATA;
+ lookAhead -= (rem - (unsigned)(p->buf - p->tempBuf));
+ (*srcLen) += lookAhead;
+ src += lookAhead;
+ inSize -= lookAhead;
+ p->tempBufSize = 0;
+ }
+ }
+ if (p->code == 0)
+ *status = LZMA_STATUS_FINISHED_WITH_MARK;
+ return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA;
+}
+
+SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status)
+{
+ SizeT outSize = *destLen;
+ SizeT inSize = *srcLen;
+ *srcLen = *destLen = 0;
+ for (;;)
+ {
+ SizeT inSizeCur = inSize, outSizeCur, dicPos;
+ ELzmaFinishMode curFinishMode;
+ SRes res;
+ if (p->dicPos == p->dicBufSize)
+ p->dicPos = 0;
+ dicPos = p->dicPos;
+ if (outSize > p->dicBufSize - dicPos)
+ {
+ outSizeCur = p->dicBufSize;
+ curFinishMode = LZMA_FINISH_ANY;
+ }
+ else
+ {
+ outSizeCur = dicPos + outSize;
+ curFinishMode = finishMode;
+ }
+
+ res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status);
+ src += inSizeCur;
+ inSize -= inSizeCur;
+ *srcLen += inSizeCur;
+ outSizeCur = p->dicPos - dicPos;
+ memcpy(dest, p->dic + dicPos, outSizeCur);
+ dest += outSizeCur;
+ outSize -= outSizeCur;
+ *destLen += outSizeCur;
+ if (res != 0)
+ return res;
+ if (outSizeCur == 0 || outSize == 0)
+ return SZ_OK;
+ }
+}
+
+void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc)
+{
+ alloc->Free(alloc, p->probs);
+ p->probs = 0;
+}
+
+static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc)
+{
+ alloc->Free(alloc, p->dic);
+ p->dic = 0;
+}
+
+void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc)
+{
+ LzmaDec_FreeProbs(p, alloc);
+ LzmaDec_FreeDict(p, alloc);
+}
+
+SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size)
+{
+ UInt32 dicSize;
+ Byte d;
+
+ if (size < LZMA_PROPS_SIZE)
+ return SZ_ERROR_UNSUPPORTED;
+ else
+ dicSize = data[1] | ((UInt32)data[2] << 8) | ((UInt32)data[3] << 16) | ((UInt32)data[4] << 24);
+
+ if (dicSize < LZMA_DIC_MIN)
+ dicSize = LZMA_DIC_MIN;
+ p->dicSize = dicSize;
+
+ d = data[0];
+ if (d >= (9 * 5 * 5))
+ return SZ_ERROR_UNSUPPORTED;
+
+ p->lc = d % 9;
+ d /= 9;
+ p->pb = d / 5;
+ p->lp = d % 5;
+
+ return SZ_OK;
+}
+
+static SRes LzmaDec_AllocateProbs2(CLzmaDec *p, const CLzmaProps *propNew, ISzAlloc *alloc)
+{
+ UInt32 numProbs = LzmaProps_GetNumProbs(propNew);
+ if (p->probs == 0 || numProbs != p->numProbs)
+ {
+ LzmaDec_FreeProbs(p, alloc);
+ p->probs = (CLzmaProb *)alloc->Alloc(alloc, numProbs * sizeof(CLzmaProb));
+ p->numProbs = numProbs;
+ if (p->probs == 0)
+ return SZ_ERROR_MEM;
+ }
+ return SZ_OK;
+}
+
+SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)
+{
+ CLzmaProps propNew;
+ RINOK(LzmaProps_Decode(&propNew, props, propsSize));
+ RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc));
+ p->prop = propNew;
+ return SZ_OK;
+}
+
+SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)
+{
+ CLzmaProps propNew;
+ SizeT dicBufSize;
+ RINOK(LzmaProps_Decode(&propNew, props, propsSize));
+ RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc));
+ dicBufSize = propNew.dicSize;
+ if (p->dic == 0 || dicBufSize != p->dicBufSize)
+ {
+ LzmaDec_FreeDict(p, alloc);
+ p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize);
+ if (p->dic == 0)
+ {
+ LzmaDec_FreeProbs(p, alloc);
+ return SZ_ERROR_MEM;
+ }
+ }
+ p->dicBufSize = dicBufSize;
+ p->prop = propNew;
+ return SZ_OK;
+}
+
+SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen,
+ const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode,
+ ELzmaStatus *status, ISzAlloc *alloc)
+{
+ CLzmaDec p;
+ SRes res;
+ SizeT inSize = *srcLen;
+ SizeT outSize = *destLen;
+ *srcLen = *destLen = 0;
+ if (inSize < RC_INIT_SIZE)
+ return SZ_ERROR_INPUT_EOF;
+
+ LzmaDec_Construct(&p);
+ res = LzmaDec_AllocateProbs(&p, propData, propSize, alloc);
+ if (res != 0)
+ return res;
+ p.dic = dest;
+ p.dicBufSize = outSize;
+
+ LzmaDec_Init(&p);
+
+ *srcLen = inSize;
+ res = LzmaDec_DecodeToDic(&p, outSize, src, srcLen, finishMode, status);
+
+ if (res == SZ_OK && *status == LZMA_STATUS_NEEDS_MORE_INPUT)
+ res = SZ_ERROR_INPUT_EOF;
+
+ (*destLen) = p.dicPos;
+ LzmaDec_FreeProbs(&p, alloc);
+ return res;
+}
--- /dev/null
+/* LzmaDec.h -- LZMA Decoder
+2008-10-04 : Igor Pavlov : Public domain */
+
+#ifndef __LZMADEC_H
+#define __LZMADEC_H
+
+#include "Types.h"
+
+/* #define _LZMA_PROB32 */
+/* _LZMA_PROB32 can increase the speed on some CPUs,
+ but memory usage for CLzmaDec::probs will be doubled in that case */
+
+#ifdef _LZMA_PROB32
+#define CLzmaProb UInt32
+#else
+#define CLzmaProb UInt16
+#endif
+
+
+/* ---------- LZMA Properties ---------- */
+
+#define LZMA_PROPS_SIZE 5
+
+typedef struct _CLzmaProps
+{
+ unsigned lc, lp, pb;
+ UInt32 dicSize;
+} CLzmaProps;
+
+/* LzmaProps_Decode - decodes properties
+Returns:
+ SZ_OK
+ SZ_ERROR_UNSUPPORTED - Unsupported properties
+*/
+
+SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size);
+
+
+/* ---------- LZMA Decoder state ---------- */
+
+/* LZMA_REQUIRED_INPUT_MAX = number of required input bytes for worst case.
+ Num bits = log2((2^11 / 31) ^ 22) + 26 < 134 + 26 = 160; */
+
+#define LZMA_REQUIRED_INPUT_MAX 20
+
+typedef struct
+{
+ CLzmaProps prop;
+ CLzmaProb *probs;
+ Byte *dic;
+ const Byte *buf;
+ UInt32 range, code;
+ SizeT dicPos;
+ SizeT dicBufSize;
+ UInt32 processedPos;
+ UInt32 checkDicSize;
+ unsigned state;
+ UInt32 reps[4];
+ unsigned remainLen;
+ int needFlush;
+ int needInitState;
+ UInt32 numProbs;
+ unsigned tempBufSize;
+ Byte tempBuf[LZMA_REQUIRED_INPUT_MAX];
+} CLzmaDec;
+
+#define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; }
+
+void LzmaDec_Init(CLzmaDec *p);
+
+/* There are two types of LZMA streams:
+ 0) Stream with end mark. That end mark adds about 6 bytes to compressed size.
+ 1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */
+
+typedef enum
+{
+ LZMA_FINISH_ANY, /* finish at any point */
+ LZMA_FINISH_END /* block must be finished at the end */
+} ELzmaFinishMode;
+
+/* ELzmaFinishMode has meaning only if the decoding reaches output limit !!!
+
+ You must use LZMA_FINISH_END, when you know that current output buffer
+ covers last bytes of block. In other cases you must use LZMA_FINISH_ANY.
+
+ If LZMA decoder sees end marker before reaching output limit, it returns SZ_OK,
+ and output value of destLen will be less than output buffer size limit.
+ You can check status result also.
+
+ You can use multiple checks to test data integrity after full decompression:
+ 1) Check Result and "status" variable.
+ 2) Check that output(destLen) = uncompressedSize, if you know real uncompressedSize.
+ 3) Check that output(srcLen) = compressedSize, if you know real compressedSize.
+ You must use correct finish mode in that case. */
+
+typedef enum
+{
+ LZMA_STATUS_NOT_SPECIFIED, /* use main error code instead */
+ LZMA_STATUS_FINISHED_WITH_MARK, /* stream was finished with end mark. */
+ LZMA_STATUS_NOT_FINISHED, /* stream was not finished */
+ LZMA_STATUS_NEEDS_MORE_INPUT, /* you must provide more input bytes */
+ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK /* there is probability that stream was finished without end mark */
+} ELzmaStatus;
+
+/* ELzmaStatus is used only as output value for function call */
+
+
+/* ---------- Interfaces ---------- */
+
+/* There are 3 levels of interfaces:
+ 1) Dictionary Interface
+ 2) Buffer Interface
+ 3) One Call Interface
+ You can select any of these interfaces, but don't mix functions from different
+ groups for same object. */
+
+
+/* There are two variants to allocate state for Dictionary Interface:
+ 1) LzmaDec_Allocate / LzmaDec_Free
+ 2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs
+ You can use variant 2, if you set dictionary buffer manually.
+ For Buffer Interface you must always use variant 1.
+
+LzmaDec_Allocate* can return:
+ SZ_OK
+ SZ_ERROR_MEM - Memory allocation error
+ SZ_ERROR_UNSUPPORTED - Unsupported properties
+*/
+
+SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc);
+void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc);
+
+SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc);
+void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc);
+
+/* ---------- Dictionary Interface ---------- */
+
+/* You can use it, if you want to eliminate the overhead for data copying from
+ dictionary to some other external buffer.
+ You must work with CLzmaDec variables directly in this interface.
+
+ STEPS:
+ LzmaDec_Constr()
+ LzmaDec_Allocate()
+ for (each new stream)
+ {
+ LzmaDec_Init()
+ while (it needs more decompression)
+ {
+ LzmaDec_DecodeToDic()
+ use data from CLzmaDec::dic and update CLzmaDec::dicPos
+ }
+ }
+ LzmaDec_Free()
+*/
+
+/* LzmaDec_DecodeToDic
+
+ The decoding to internal dictionary buffer (CLzmaDec::dic).
+ You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!!
+
+finishMode:
+ It has meaning only if the decoding reaches output limit (dicLimit).
+ LZMA_FINISH_ANY - Decode just dicLimit bytes.
+ LZMA_FINISH_END - Stream must be finished after dicLimit.
+
+Returns:
+ SZ_OK
+ status:
+ LZMA_STATUS_FINISHED_WITH_MARK
+ LZMA_STATUS_NOT_FINISHED
+ LZMA_STATUS_NEEDS_MORE_INPUT
+ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK
+ SZ_ERROR_DATA - Data error
+*/
+
+SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit,
+ const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);
+
+
+/* ---------- Buffer Interface ---------- */
+
+/* It's zlib-like interface.
+ See LzmaDec_DecodeToDic description for information about STEPS and return results,
+ but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need
+ to work with CLzmaDec variables manually.
+
+finishMode:
+ It has meaning only if the decoding reaches output limit (*destLen).
+ LZMA_FINISH_ANY - Decode just destLen bytes.
+ LZMA_FINISH_END - Stream must be finished after (*destLen).
+*/
+
+SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen,
+ const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);
+
+
+/* ---------- One Call Interface ---------- */
+
+/* LzmaDecode
+
+finishMode:
+ It has meaning only if the decoding reaches output limit (*destLen).
+ LZMA_FINISH_ANY - Decode just destLen bytes.
+ LZMA_FINISH_END - Stream must be finished after (*destLen).
+
+Returns:
+ SZ_OK
+ status:
+ LZMA_STATUS_FINISHED_WITH_MARK
+ LZMA_STATUS_NOT_FINISHED
+ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK
+ SZ_ERROR_DATA - Data error
+ SZ_ERROR_MEM - Memory allocation error
+ SZ_ERROR_UNSUPPORTED - Unsupported properties
+ SZ_ERROR_INPUT_EOF - It needs more bytes in input buffer (src).
+*/
+
+SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen,
+ const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode,
+ ELzmaStatus *status, ISzAlloc *alloc);
+
+#endif
+++ /dev/null
-/*
- LzmaDecode.c
- LZMA Decoder (optimized for Speed version)
-
- LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
- http://www.7-zip.org/
-
- LZMA SDK is licensed under two licenses:
- 1) GNU Lesser General Public License (GNU LGPL)
- 2) Common Public License (CPL)
- It means that you can select one of these two licenses and
- follow rules of that license.
-
- SPECIAL EXCEPTION:
- Igor Pavlov, as the author of this Code, expressly permits you to
- statically or dynamically link your Code (or bind by name) to the
- interfaces of this file without subjecting your linked Code to the
- terms of the CPL or GNU LGPL. Any modifications or additions
- to this file, however, are subject to the LGPL or CPL terms.
-*/
-
-#include "LzmaDecode.h"
-
-#define kNumTopBits 24
-#define kTopValue ((UInt32)1 << kNumTopBits)
-
-#define kNumBitModelTotalBits 11
-#define kBitModelTotal (1 << kNumBitModelTotalBits)
-#define kNumMoveBits 5
-
-#define RC_READ_BYTE (*Buffer++)
-
-#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \
- { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}
-
-#ifdef _LZMA_IN_CB
-
-#define RC_TEST { if (Buffer == BufferLim) \
- { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \
- BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }}
-
-#define RC_INIT Buffer = BufferLim = 0; RC_INIT2
-
-#else
-
-#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; }
-
-#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2
-
-#endif
-
-#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }
-
-#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)
-#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;
-#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;
-
-#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \
- { UpdateBit0(p); mi <<= 1; A0; } else \
- { UpdateBit1(p); mi = (mi + mi) + 1; A1; }
-
-#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)
-
-#define RangeDecoderBitTreeDecode(probs, numLevels, res) \
- { int i = numLevels; res = 1; \
- do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \
- res -= (1 << numLevels); }
-
-
-#define kNumPosBitsMax 4
-#define kNumPosStatesMax (1 << kNumPosBitsMax)
-
-#define kLenNumLowBits 3
-#define kLenNumLowSymbols (1 << kLenNumLowBits)
-#define kLenNumMidBits 3
-#define kLenNumMidSymbols (1 << kLenNumMidBits)
-#define kLenNumHighBits 8
-#define kLenNumHighSymbols (1 << kLenNumHighBits)
-
-#define LenChoice 0
-#define LenChoice2 (LenChoice + 1)
-#define LenLow (LenChoice2 + 1)
-#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))
-#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))
-#define kNumLenProbs (LenHigh + kLenNumHighSymbols)
-
-
-#define kNumStates 12
-#define kNumLitStates 7
-
-#define kStartPosModelIndex 4
-#define kEndPosModelIndex 14
-#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))
-
-#define kNumPosSlotBits 6
-#define kNumLenToPosStates 4
-
-#define kNumAlignBits 4
-#define kAlignTableSize (1 << kNumAlignBits)
-
-#define kMatchMinLen 2
-
-#define IsMatch 0
-#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))
-#define IsRepG0 (IsRep + kNumStates)
-#define IsRepG1 (IsRepG0 + kNumStates)
-#define IsRepG2 (IsRepG1 + kNumStates)
-#define IsRep0Long (IsRepG2 + kNumStates)
-#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))
-#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))
-#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)
-#define LenCoder (Align + kAlignTableSize)
-#define RepLenCoder (LenCoder + kNumLenProbs)
-#define Literal (RepLenCoder + kNumLenProbs)
-
-#if Literal != LZMA_BASE_SIZE
-StopCompilingDueBUG
-#endif
-
-int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)
-{
- unsigned char prop0;
- if (size < LZMA_PROPERTIES_SIZE)
- return LZMA_RESULT_DATA_ERROR;
- prop0 = propsData[0];
- if (prop0 >= (9 * 5 * 5))
- return LZMA_RESULT_DATA_ERROR;
- {
- for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));
- for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);
- propsRes->lc = prop0;
- /*
- unsigned char remainder = (unsigned char)(prop0 / 9);
- propsRes->lc = prop0 % 9;
- propsRes->pb = remainder / 5;
- propsRes->lp = remainder % 5;
- */
- }
-
- #ifdef _LZMA_OUT_READ
- {
- int i;
- propsRes->DictionarySize = 0;
- for (i = 0; i < 4; i++)
- propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8);
- if (propsRes->DictionarySize == 0)
- propsRes->DictionarySize = 1;
- }
- #endif
- return LZMA_RESULT_OK;
-}
-
-#define kLzmaStreamWasFinishedId (-1)
-
-int LzmaDecode(CLzmaDecoderState *vs,
- #ifdef _LZMA_IN_CB
- ILzmaInCallback *InCallback,
- #else
- const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
- #endif
- unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)
-{
- CProb *p = vs->Probs;
- SizeT nowPos = 0;
- Byte previousByte = 0;
- UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;
- UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;
- int lc = vs->Properties.lc;
-
- #ifdef _LZMA_OUT_READ
-
- UInt32 Range = vs->Range;
- UInt32 Code = vs->Code;
- #ifdef _LZMA_IN_CB
- const Byte *Buffer = vs->Buffer;
- const Byte *BufferLim = vs->BufferLim;
- #else
- const Byte *Buffer = inStream;
- const Byte *BufferLim = inStream + inSize;
- #endif
- int state = vs->State;
- UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3];
- int len = vs->RemainLen;
- UInt32 globalPos = vs->GlobalPos;
- UInt32 distanceLimit = vs->DistanceLimit;
-
- Byte *dictionary = vs->Dictionary;
- UInt32 dictionarySize = vs->Properties.DictionarySize;
- UInt32 dictionaryPos = vs->DictionaryPos;
-
- Byte tempDictionary[4];
-
- #ifndef _LZMA_IN_CB
- *inSizeProcessed = 0;
- #endif
- *outSizeProcessed = 0;
- if (len == kLzmaStreamWasFinishedId)
- return LZMA_RESULT_OK;
-
- if (dictionarySize == 0)
- {
- dictionary = tempDictionary;
- dictionarySize = 1;
- tempDictionary[0] = vs->TempDictionary[0];
- }
-
- if (len == kLzmaNeedInitId)
- {
- {
- UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
- UInt32 i;
- for (i = 0; i < numProbs; i++)
- p[i] = kBitModelTotal >> 1;
- rep0 = rep1 = rep2 = rep3 = 1;
- state = 0;
- globalPos = 0;
- distanceLimit = 0;
- dictionaryPos = 0;
- dictionary[dictionarySize - 1] = 0;
- #ifdef _LZMA_IN_CB
- RC_INIT;
- #else
- RC_INIT(inStream, inSize);
- #endif
- }
- len = 0;
- }
- while(len != 0 && nowPos < outSize)
- {
- UInt32 pos = dictionaryPos - rep0;
- if (pos >= dictionarySize)
- pos += dictionarySize;
- outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos];
- if (++dictionaryPos == dictionarySize)
- dictionaryPos = 0;
- len--;
- }
- if (dictionaryPos == 0)
- previousByte = dictionary[dictionarySize - 1];
- else
- previousByte = dictionary[dictionaryPos - 1];
-
- #else /* if !_LZMA_OUT_READ */
-
- int state = 0;
- UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;
- int len = 0;
- const Byte *Buffer;
- const Byte *BufferLim;
- UInt32 Range;
- UInt32 Code;
-
- #ifndef _LZMA_IN_CB
- *inSizeProcessed = 0;
- #endif
- *outSizeProcessed = 0;
-
- {
- UInt32 i;
- UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
- for (i = 0; i < numProbs; i++)
- p[i] = kBitModelTotal >> 1;
- }
-
- #ifdef _LZMA_IN_CB
- RC_INIT;
- #else
- RC_INIT(inStream, inSize);
- #endif
-
- #endif /* _LZMA_OUT_READ */
-
- while(nowPos < outSize)
- {
- CProb *prob;
- UInt32 bound;
- int posState = (int)(
- (nowPos
- #ifdef _LZMA_OUT_READ
- + globalPos
- #endif
- )
- & posStateMask);
-
- prob = p + IsMatch + (state << kNumPosBitsMax) + posState;
- IfBit0(prob)
- {
- int symbol = 1;
- UpdateBit0(prob)
- prob = p + Literal + (LZMA_LIT_SIZE *
- (((
- (nowPos
- #ifdef _LZMA_OUT_READ
- + globalPos
- #endif
- )
- & literalPosMask) << lc) + (previousByte >> (8 - lc))));
-
- if (state >= kNumLitStates)
- {
- int matchByte;
- #ifdef _LZMA_OUT_READ
- UInt32 pos = dictionaryPos - rep0;
- if (pos >= dictionarySize)
- pos += dictionarySize;
- matchByte = dictionary[pos];
- #else
- matchByte = outStream[nowPos - rep0];
- #endif
- do
- {
- int bit;
- CProb *probLit;
- matchByte <<= 1;
- bit = (matchByte & 0x100);
- probLit = prob + 0x100 + bit + symbol;
- RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)
- }
- while (symbol < 0x100);
- }
- while (symbol < 0x100)
- {
- CProb *probLit = prob + symbol;
- RC_GET_BIT(probLit, symbol)
- }
- previousByte = (Byte)symbol;
-
- outStream[nowPos++] = previousByte;
- #ifdef _LZMA_OUT_READ
- if (distanceLimit < dictionarySize)
- distanceLimit++;
-
- dictionary[dictionaryPos] = previousByte;
- if (++dictionaryPos == dictionarySize)
- dictionaryPos = 0;
- #endif
- if (state < 4) state = 0;
- else if (state < 10) state -= 3;
- else state -= 6;
- }
- else
- {
- UpdateBit1(prob);
- prob = p + IsRep + state;
- IfBit0(prob)
- {
- UpdateBit0(prob);
- rep3 = rep2;
- rep2 = rep1;
- rep1 = rep0;
- state = state < kNumLitStates ? 0 : 3;
- prob = p + LenCoder;
- }
- else
- {
- UpdateBit1(prob);
- prob = p + IsRepG0 + state;
- IfBit0(prob)
- {
- UpdateBit0(prob);
- prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;
- IfBit0(prob)
- {
- #ifdef _LZMA_OUT_READ
- UInt32 pos;
- #endif
- UpdateBit0(prob);
-
- #ifdef _LZMA_OUT_READ
- if (distanceLimit == 0)
- #else
- if (nowPos == 0)
- #endif
- return LZMA_RESULT_DATA_ERROR;
-
- state = state < kNumLitStates ? 9 : 11;
- #ifdef _LZMA_OUT_READ
- pos = dictionaryPos - rep0;
- if (pos >= dictionarySize)
- pos += dictionarySize;
- previousByte = dictionary[pos];
- dictionary[dictionaryPos] = previousByte;
- if (++dictionaryPos == dictionarySize)
- dictionaryPos = 0;
- #else
- previousByte = outStream[nowPos - rep0];
- #endif
- outStream[nowPos++] = previousByte;
- #ifdef _LZMA_OUT_READ
- if (distanceLimit < dictionarySize)
- distanceLimit++;
- #endif
-
- continue;
- }
- else
- {
- UpdateBit1(prob);
- }
- }
- else
- {
- UInt32 distance;
- UpdateBit1(prob);
- prob = p + IsRepG1 + state;
- IfBit0(prob)
- {
- UpdateBit0(prob);
- distance = rep1;
- }
- else
- {
- UpdateBit1(prob);
- prob = p + IsRepG2 + state;
- IfBit0(prob)
- {
- UpdateBit0(prob);
- distance = rep2;
- }
- else
- {
- UpdateBit1(prob);
- distance = rep3;
- rep3 = rep2;
- }
- rep2 = rep1;
- }
- rep1 = rep0;
- rep0 = distance;
- }
- state = state < kNumLitStates ? 8 : 11;
- prob = p + RepLenCoder;
- }
- {
- int numBits, offset;
- CProb *probLen = prob + LenChoice;
- IfBit0(probLen)
- {
- UpdateBit0(probLen);
- probLen = prob + LenLow + (posState << kLenNumLowBits);
- offset = 0;
- numBits = kLenNumLowBits;
- }
- else
- {
- UpdateBit1(probLen);
- probLen = prob + LenChoice2;
- IfBit0(probLen)
- {
- UpdateBit0(probLen);
- probLen = prob + LenMid + (posState << kLenNumMidBits);
- offset = kLenNumLowSymbols;
- numBits = kLenNumMidBits;
- }
- else
- {
- UpdateBit1(probLen);
- probLen = prob + LenHigh;
- offset = kLenNumLowSymbols + kLenNumMidSymbols;
- numBits = kLenNumHighBits;
- }
- }
- RangeDecoderBitTreeDecode(probLen, numBits, len);
- len += offset;
- }
-
- if (state < 4)
- {
- int posSlot;
- state += kNumLitStates;
- prob = p + PosSlot +
- ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) <<
- kNumPosSlotBits);
- RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);
- if (posSlot >= kStartPosModelIndex)
- {
- int numDirectBits = ((posSlot >> 1) - 1);
- rep0 = (2 | ((UInt32)posSlot & 1));
- if (posSlot < kEndPosModelIndex)
- {
- rep0 <<= numDirectBits;
- prob = p + SpecPos + rep0 - posSlot - 1;
- }
- else
- {
- numDirectBits -= kNumAlignBits;
- do
- {
- RC_NORMALIZE
- Range >>= 1;
- rep0 <<= 1;
- if (Code >= Range)
- {
- Code -= Range;
- rep0 |= 1;
- }
- }
- while (--numDirectBits != 0);
- prob = p + Align;
- rep0 <<= kNumAlignBits;
- numDirectBits = kNumAlignBits;
- }
- {
- int i = 1;
- int mi = 1;
- do
- {
- CProb *prob3 = prob + mi;
- RC_GET_BIT2(prob3, mi, ; , rep0 |= i);
- i <<= 1;
- }
- while(--numDirectBits != 0);
- }
- }
- else
- rep0 = posSlot;
- if (++rep0 == (UInt32)(0))
- {
- /* it's for stream version */
- len = kLzmaStreamWasFinishedId;
- break;
- }
- }
-
- len += kMatchMinLen;
- #ifdef _LZMA_OUT_READ
- if (rep0 > distanceLimit)
- #else
- if (rep0 > nowPos)
- #endif
- return LZMA_RESULT_DATA_ERROR;
-
- #ifdef _LZMA_OUT_READ
- if (dictionarySize - distanceLimit > (UInt32)len)
- distanceLimit += len;
- else
- distanceLimit = dictionarySize;
- #endif
-
- do
- {
- #ifdef _LZMA_OUT_READ
- UInt32 pos = dictionaryPos - rep0;
- if (pos >= dictionarySize)
- pos += dictionarySize;
- previousByte = dictionary[pos];
- dictionary[dictionaryPos] = previousByte;
- if (++dictionaryPos == dictionarySize)
- dictionaryPos = 0;
- #else
- previousByte = outStream[nowPos - rep0];
- #endif
- len--;
- outStream[nowPos++] = previousByte;
- }
- while(len != 0 && nowPos < outSize);
- }
- }
- RC_NORMALIZE;
-
- #ifdef _LZMA_OUT_READ
- vs->Range = Range;
- vs->Code = Code;
- vs->DictionaryPos = dictionaryPos;
- vs->GlobalPos = globalPos + (UInt32)nowPos;
- vs->DistanceLimit = distanceLimit;
- vs->Reps[0] = rep0;
- vs->Reps[1] = rep1;
- vs->Reps[2] = rep2;
- vs->Reps[3] = rep3;
- vs->State = state;
- vs->RemainLen = len;
- vs->TempDictionary[0] = tempDictionary[0];
- #endif
-
- #ifdef _LZMA_IN_CB
- vs->Buffer = Buffer;
- vs->BufferLim = BufferLim;
- #else
- *inSizeProcessed = (SizeT)(Buffer - inStream);
- #endif
- *outSizeProcessed = nowPos;
- return LZMA_RESULT_OK;
-}
+++ /dev/null
-/*
- LzmaDecode.h
- LZMA Decoder interface
-
- LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
- http://www.7-zip.org/
-
- LZMA SDK is licensed under two licenses:
- 1) GNU Lesser General Public License (GNU LGPL)
- 2) Common Public License (CPL)
- It means that you can select one of these two licenses and
- follow rules of that license.
-
- SPECIAL EXCEPTION:
- Igor Pavlov, as the author of this code, expressly permits you to
- statically or dynamically link your code (or bind by name) to the
- interfaces of this file without subjecting your linked code to the
- terms of the CPL or GNU LGPL. Any modifications or additions
- to this file, however, are subject to the LGPL or CPL terms.
-*/
-
-#ifndef __LZMADECODE_H
-#define __LZMADECODE_H
-
-#include "LzmaTypes.h"
-
-/* #define _LZMA_IN_CB */
-/* Use callback for input data */
-
-/* #define _LZMA_OUT_READ */
-/* Use read function for output data */
-
-/* #define _LZMA_PROB32 */
-/* It can increase speed on some 32-bit CPUs,
- but memory usage will be doubled in that case */
-
-/* #define _LZMA_LOC_OPT */
-/* Enable local speed optimizations inside code */
-
-#ifdef _LZMA_PROB32
-#define CProb UInt32
-#else
-#define CProb UInt16
-#endif
-
-#define LZMA_RESULT_OK 0
-#define LZMA_RESULT_DATA_ERROR 1
-
-#ifdef _LZMA_IN_CB
-typedef struct _ILzmaInCallback
-{
- int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize);
-} ILzmaInCallback;
-#endif
-
-#define LZMA_BASE_SIZE 1846
-#define LZMA_LIT_SIZE 768
-
-#define LZMA_PROPERTIES_SIZE 5
-
-typedef struct _CLzmaProperties
-{
- int lc;
- int lp;
- int pb;
- #ifdef _LZMA_OUT_READ
- UInt32 DictionarySize;
- #endif
-}CLzmaProperties;
-
-int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);
-
-#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))
-
-#define kLzmaNeedInitId (-2)
-
-typedef struct _CLzmaDecoderState
-{
- CLzmaProperties Properties;
- CProb *Probs;
-
- #ifdef _LZMA_IN_CB
- const unsigned char *Buffer;
- const unsigned char *BufferLim;
- #endif
-
- #ifdef _LZMA_OUT_READ
- unsigned char *Dictionary;
- UInt32 Range;
- UInt32 Code;
- UInt32 DictionaryPos;
- UInt32 GlobalPos;
- UInt32 DistanceLimit;
- UInt32 Reps[4];
- int State;
- int RemainLen;
- unsigned char TempDictionary[4];
- #endif
-} CLzmaDecoderState;
-
-#ifdef _LZMA_OUT_READ
-#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; }
-#endif
-
-int LzmaDecode(CLzmaDecoderState *vs,
- #ifdef _LZMA_IN_CB
- ILzmaInCallback *inCallback,
- #else
- const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
- #endif
- unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);
-
-#endif
/*
- * Usefuls routines based on the LzmaTest.c file from LZMA SDK 4.57
+ * Usefuls routines based on the LzmaTest.c file from LZMA SDK 4.65
*
- * Copyright (C) 2007-2008 Industrie Dial Face S.p.A.
+ * Copyright (C) 2007-2009 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini (luigi.mantellini@idf-hit.com)
*
* Copyright (C) 1999-2005 Igor Pavlov
#include <config.h>
#include <common.h>
+#include <watchdog.h>
#ifdef CONFIG_LZMA
#define LZMA_PROPERTIES_OFFSET 0
-#define LZMA_SIZE_OFFSET LZMA_PROPERTIES_SIZE
+#define LZMA_SIZE_OFFSET LZMA_PROPS_SIZE
#define LZMA_DATA_OFFSET LZMA_SIZE_OFFSET+sizeof(uint64_t)
#include "LzmaTools.h"
-#include "LzmaDecode.h"
+#include "LzmaDec.h"
#include <linux/string.h>
#include <malloc.h>
+static void *SzAlloc(void *p, size_t size) { p = p; return malloc(size); }
+static void SzFree(void *p, void *address) { p = p; free(address); }
+
int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize,
- unsigned char *inStream, SizeT length)
+ unsigned char *inStream, SizeT length)
{
- int res = LZMA_RESULT_DATA_ERROR;
- int i;
-
- SizeT outSizeFull = 0xFFFFFFFF; /* 4GBytes limit */
- SizeT inProcessed;
- SizeT outProcessed;
- SizeT outSize;
- SizeT outSizeHigh;
- CLzmaDecoderState state; /* it's about 24-80 bytes structure, if int is 32-bit */
- unsigned char properties[LZMA_PROPERTIES_SIZE];
- SizeT compressedSize = (SizeT)(length - LZMA_DATA_OFFSET);
-
- debug ("LZMA: Image address............... 0x%lx\n", inStream);
- debug ("LZMA: Properties address.......... 0x%lx\n", inStream + LZMA_PROPERTIES_OFFSET);
- debug ("LZMA: Uncompressed size address... 0x%lx\n", inStream + LZMA_SIZE_OFFSET);
- debug ("LZMA: Compressed data address..... 0x%lx\n", inStream + LZMA_DATA_OFFSET);
- debug ("LZMA: Destination address......... 0x%lx\n", outStream);
-
- memcpy(properties, inStream + LZMA_PROPERTIES_OFFSET, LZMA_PROPERTIES_SIZE);
-
- memset(&state, 0, sizeof(state));
- res = LzmaDecodeProperties(&state.Properties,
- properties,
- LZMA_PROPERTIES_SIZE);
- if (res != LZMA_RESULT_OK) {
- return res;
- }
-
- outSize = 0;
- outSizeHigh = 0;
- /* Read the uncompressed size */
- for (i = 0; i < 8; i++) {
- unsigned char b = inStream[LZMA_SIZE_OFFSET + i];
- if (i < 4) {
- outSize += (UInt32)(b) << (i * 8);
- } else {
- outSizeHigh += (UInt32)(b) << ((i - 4) * 8);
- }
- }
-
- outSizeFull = (SizeT)outSize;
- if (sizeof(SizeT) >= 8) {
- /*
- * SizeT is a 64 bit uint => We can manage files larger than 4GB!
- *
- */
- outSizeFull |= (((SizeT)outSizeHigh << 16) << 16);
- } else if (outSizeHigh != 0 || (UInt32)(SizeT)outSize != outSize) {
- /*
- * SizeT is a 32 bit uint => We cannot manage files larger than
- * 4GB!
- *
- */
- debug ("LZMA: 64bit support not enabled.\n");
- return LZMA_RESULT_DATA_ERROR;
- }
-
- debug ("LZMA: Uncompresed size............ 0x%lx\n", outSizeFull);
- debug ("LZMA: Compresed size.............. 0x%lx\n", compressedSize);
- debug ("LZMA: Dynamic memory needed....... 0x%lx", LzmaGetNumProbs(&state.Properties) * sizeof(CProb));
-
- state.Probs = (CProb *)malloc(LzmaGetNumProbs(&state.Properties) * sizeof(CProb));
-
- if (state.Probs == 0
- || (outStream == 0 && outSizeFull != 0)
- || (inStream == 0 && compressedSize != 0)) {
- free(state.Probs);
- debug ("\n");
- return LZMA_RESULT_DATA_ERROR;
- }
-
- debug (" allocated.\n");
-
- /* Decompress */
-
- res = LzmaDecode(&state,
- inStream + LZMA_DATA_OFFSET, compressedSize, &inProcessed,
- outStream, outSizeFull, &outProcessed);
- if (res != LZMA_RESULT_OK) {
- return res;
- }
-
- *uncompressedSize = outProcessed;
- free(state.Probs);
- return res;
+ int res = SZ_ERROR_DATA;
+ int i;
+ ISzAlloc g_Alloc;
+
+ SizeT outSizeFull = 0xFFFFFFFF; /* 4GBytes limit */
+ SizeT inProcessed;
+ SizeT outProcessed;
+ SizeT outSize;
+ SizeT outSizeHigh;
+ ELzmaStatus state;
+ SizeT compressedSize = (SizeT)(length - LZMA_PROPS_SIZE);
+
+ debug ("LZMA: Image address............... 0x%lx\n", inStream);
+ debug ("LZMA: Properties address.......... 0x%lx\n", inStream + LZMA_PROPERTIES_OFFSET);
+ debug ("LZMA: Uncompressed size address... 0x%lx\n", inStream + LZMA_SIZE_OFFSET);
+ debug ("LZMA: Compressed data address..... 0x%lx\n", inStream + LZMA_DATA_OFFSET);
+ debug ("LZMA: Destination address......... 0x%lx\n", outStream);
+
+ memset(&state, 0, sizeof(state));
+
+ outSize = 0;
+ outSizeHigh = 0;
+ /* Read the uncompressed size */
+ for (i = 0; i < 8; i++) {
+ unsigned char b = inStream[LZMA_SIZE_OFFSET + i];
+ if (i < 4) {
+ outSize += (UInt32)(b) << (i * 8);
+ } else {
+ outSizeHigh += (UInt32)(b) << ((i - 4) * 8);
+ }
+ }
+
+ outSizeFull = (SizeT)outSize;
+ if (sizeof(SizeT) >= 8) {
+ /*
+ * SizeT is a 64 bit uint => We can manage files larger than 4GB!
+ *
+ */
+ outSizeFull |= (((SizeT)outSizeHigh << 16) << 16);
+ } else if (outSizeHigh != 0 || (UInt32)(SizeT)outSize != outSize) {
+ /*
+ * SizeT is a 32 bit uint => We cannot manage files larger than
+ * 4GB!
+ *
+ */
+ debug ("LZMA: 64bit support not enabled.\n");
+ return SZ_ERROR_DATA;
+ }
+
+ debug ("LZMA: Uncompresed size............ 0x%lx\n", outSizeFull);
+ debug ("LZMA: Compresed size.............. 0x%lx\n", compressedSize);
+
+ g_Alloc.Alloc = SzAlloc;
+ g_Alloc.Free = SzFree;
+
+ /* Decompress */
+ outProcessed = outSizeFull;
+
+ WATCHDOG_RESET();
+
+ res = LzmaDecode(
+ outStream, &outProcessed,
+ inStream + LZMA_DATA_OFFSET, &compressedSize,
+ inStream, LZMA_PROPS_SIZE, LZMA_FINISH_ANY, &state, &g_Alloc);
+ *uncompressedSize = outProcessed;
+ if (res != SZ_OK) {
+ return res;
+ }
+
+ return res;
}
#endif
/*
- * Usefuls routines based on the LzmaTest.c file from LZMA SDK 4.57
+ * Usefuls routines based on the LzmaTest.c file from LZMA SDK 4.65
*
* Copyright (C) 2007-2008 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini (luigi.mantellini@idf-hit.com)
#ifndef __LZMA_TOOL_H__
#define __LZMA_TOOL_H__
-#include "LzmaTypes.h"
+#include <lzma/LzmaTypes.h>
extern int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize,
unsigned char *inStream, SizeT length);
+++ /dev/null
-/*
-LzmaTypes.h
-
-Types for LZMA Decoder
-
-This file written and distributed to public domain by Igor Pavlov.
-This file is part of LZMA SDK 4.40 (2006-05-01)
-*/
-
-#ifndef __LZMATYPES_H
-#define __LZMATYPES_H
-
-#ifndef _7ZIP_BYTE_DEFINED
-#define _7ZIP_BYTE_DEFINED
-typedef unsigned char Byte;
-#endif
-
-#ifndef _7ZIP_UINT16_DEFINED
-#define _7ZIP_UINT16_DEFINED
-typedef unsigned short UInt16;
-#endif
-
-#ifndef _7ZIP_UINT32_DEFINED
-#define _7ZIP_UINT32_DEFINED
-#ifdef _LZMA_UINT32_IS_ULONG
-typedef unsigned long UInt32;
-#else
-typedef unsigned int UInt32;
-#endif
-#endif
-
-/* #define _LZMA_NO_SYSTEM_SIZE_T */
-/* You can use it, if you don't want <stddef.h> */
-
-#ifndef _7ZIP_SIZET_DEFINED
-#define _7ZIP_SIZET_DEFINED
-#ifdef _LZMA_NO_SYSTEM_SIZE_T
-typedef UInt32 SizeT;
-#else
-#include <stddef.h>
-typedef size_t SizeT;
-#endif
-#endif
-
-#endif
SOBJS =
-COBJS-$(CONFIG_LZMA) += LzmaDecode.o LzmaTools.o
+CFLAGS += -D_LZMA_PROB32 -I$(TOPDIR)/include/linux
+
+COBJS-$(CONFIG_LZMA) += LzmaDec.o LzmaTools.o
COBJS = $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
The import is made using the import_lzmasdk.sh script that:
* untars the lzmaXYY.tar.bz2 file (from the download web page)
-* copies the files LzmaDecode.h, LzmaTypes.h, LzmaDecode.c, history.txt,
- LGPL.txt, and lzma.txt from source archive into the lib_lzma directory (pwd).
+* copies the files LzmaDec.h, Types.h, LzmaDec.c, history.txt,
+ and lzma.txt from source archive into the lib_lzma directory (pwd).
Example:
- ./import_lzmasdk.sh ~/lzma457.tar.bz2
+ . import_lzmasdk.sh ~/lzma465.tar.bz2
-Notice: The files from lzma sdk are not _modified_ by this script!
+Notice: The files from lzma sdk are _not modified_ by this script!
The files LzmaTools.{c,h} are provided to export the lzmaBuffToBuffDecompress()
function that wraps the complex LzmaDecode() function from the LZMA SDK. The
--- /dev/null
+/* Types.h -- Basic types
+2008-11-23 : Igor Pavlov : Public domain */
+
+#ifndef __7Z_TYPES_H
+#define __7Z_TYPES_H
+
+#include <stddef.h>
+
+#ifdef _WIN32
+#include <windows.h>
+#endif
+
+#define SZ_OK 0
+
+#define SZ_ERROR_DATA 1
+#define SZ_ERROR_MEM 2
+#define SZ_ERROR_CRC 3
+#define SZ_ERROR_UNSUPPORTED 4
+#define SZ_ERROR_PARAM 5
+#define SZ_ERROR_INPUT_EOF 6
+#define SZ_ERROR_OUTPUT_EOF 7
+#define SZ_ERROR_READ 8
+#define SZ_ERROR_WRITE 9
+#define SZ_ERROR_PROGRESS 10
+#define SZ_ERROR_FAIL 11
+#define SZ_ERROR_THREAD 12
+
+#define SZ_ERROR_ARCHIVE 16
+#define SZ_ERROR_NO_ARCHIVE 17
+
+typedef int SRes;
+
+#ifdef _WIN32
+typedef DWORD WRes;
+#else
+typedef int WRes;
+#endif
+
+#ifndef RINOK
+#define RINOK(x) { int __result__ = (x); if (__result__ != 0) return __result__; }
+#endif
+
+typedef unsigned char Byte;
+typedef short Int16;
+typedef unsigned short UInt16;
+
+#ifdef _LZMA_UINT32_IS_ULONG
+typedef long Int32;
+typedef unsigned long UInt32;
+#else
+typedef int Int32;
+typedef unsigned int UInt32;
+#endif
+
+#ifdef _SZ_NO_INT_64
+
+/* define _SZ_NO_INT_64, if your compiler doesn't support 64-bit integers.
+ NOTES: Some code will work incorrectly in that case! */
+
+typedef long Int64;
+typedef unsigned long UInt64;
+
+#else
+
+#if defined(_MSC_VER) || defined(__BORLANDC__)
+typedef __int64 Int64;
+typedef unsigned __int64 UInt64;
+#else
+typedef long long int Int64;
+typedef unsigned long long int UInt64;
+#endif
+
+#endif
+
+#ifdef _LZMA_NO_SYSTEM_SIZE_T
+typedef UInt32 SizeT;
+#else
+typedef size_t SizeT;
+#endif
+
+typedef int Bool;
+#define True 1
+#define False 0
+
+
+#ifdef _MSC_VER
+
+#if _MSC_VER >= 1300
+#define MY_NO_INLINE __declspec(noinline)
+#else
+#define MY_NO_INLINE
+#endif
+
+#define MY_CDECL __cdecl
+#define MY_STD_CALL __stdcall
+#define MY_FAST_CALL MY_NO_INLINE __fastcall
+
+#else
+
+#define MY_CDECL
+#define MY_STD_CALL
+#define MY_FAST_CALL
+
+#endif
+
+
+/* The following interfaces use first parameter as pointer to structure */
+
+typedef struct
+{
+ SRes (*Read)(void *p, void *buf, size_t *size);
+ /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream.
+ (output(*size) < input(*size)) is allowed */
+} ISeqInStream;
+
+/* it can return SZ_ERROR_INPUT_EOF */
+SRes SeqInStream_Read(ISeqInStream *stream, void *buf, size_t size);
+SRes SeqInStream_Read2(ISeqInStream *stream, void *buf, size_t size, SRes errorType);
+SRes SeqInStream_ReadByte(ISeqInStream *stream, Byte *buf);
+
+typedef struct
+{
+ size_t (*Write)(void *p, const void *buf, size_t size);
+ /* Returns: result - the number of actually written bytes.
+ (result < size) means error */
+} ISeqOutStream;
+
+typedef enum
+{
+ SZ_SEEK_SET = 0,
+ SZ_SEEK_CUR = 1,
+ SZ_SEEK_END = 2
+} ESzSeek;
+
+typedef struct
+{
+ SRes (*Read)(void *p, void *buf, size_t *size); /* same as ISeqInStream::Read */
+ SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin);
+} ISeekInStream;
+
+typedef struct
+{
+ SRes (*Look)(void *p, void **buf, size_t *size);
+ /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream.
+ (output(*size) > input(*size)) is not allowed
+ (output(*size) < input(*size)) is allowed */
+ SRes (*Skip)(void *p, size_t offset);
+ /* offset must be <= output(*size) of Look */
+
+ SRes (*Read)(void *p, void *buf, size_t *size);
+ /* reads directly (without buffer). It's same as ISeqInStream::Read */
+ SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin);
+} ILookInStream;
+
+SRes LookInStream_LookRead(ILookInStream *stream, void *buf, size_t *size);
+SRes LookInStream_SeekTo(ILookInStream *stream, UInt64 offset);
+
+/* reads via ILookInStream::Read */
+SRes LookInStream_Read2(ILookInStream *stream, void *buf, size_t size, SRes errorType);
+SRes LookInStream_Read(ILookInStream *stream, void *buf, size_t size);
+
+#define LookToRead_BUF_SIZE (1 << 14)
+
+typedef struct
+{
+ ILookInStream s;
+ ISeekInStream *realStream;
+ size_t pos;
+ size_t size;
+ Byte buf[LookToRead_BUF_SIZE];
+} CLookToRead;
+
+void LookToRead_CreateVTable(CLookToRead *p, int lookahead);
+void LookToRead_Init(CLookToRead *p);
+
+typedef struct
+{
+ ISeqInStream s;
+ ILookInStream *realStream;
+} CSecToLook;
+
+void SecToLook_CreateVTable(CSecToLook *p);
+
+typedef struct
+{
+ ISeqInStream s;
+ ILookInStream *realStream;
+} CSecToRead;
+
+void SecToRead_CreateVTable(CSecToRead *p);
+
+typedef struct
+{
+ SRes (*Progress)(void *p, UInt64 inSize, UInt64 outSize);
+ /* Returns: result. (result != SZ_OK) means break.
+ Value (UInt64)(Int64)-1 for size means unknown value. */
+} ICompressProgress;
+
+typedef struct
+{
+ void *(*Alloc)(void *p, size_t size);
+ void (*Free)(void *p, void *address); /* address can be 0 */
+} ISzAlloc;
+
+#define IAlloc_Alloc(p, size) (p)->Alloc((p), size)
+#define IAlloc_Free(p, a) (p)->Free((p), a)
+
+#endif
HISTORY of the LZMA SDK
-----------------------
- 4.57 2007-12-12
- -------------------------
- - Speed optimizations in Ñ++ LZMA Decoder.
- - Small changes for more compatibility with some C/C++ compilers.
+4.65 2009-02-03
+-------------------------
+- Some minor fixes
- 4.49 beta 2007-07-05
- -------------------------
- - .7z ANSI-C Decoder:
- - now it supports BCJ and BCJ2 filters
- - now it supports files larger than 4 GB.
- - now it supports "Last Write Time" field for files.
- - C++ code for .7z archives compressing/decompressing from 7-zip
- was included to LZMA SDK.
+4.63 2008-12-31
+-------------------------
+- Some minor fixes
- 4.43 2006-06-04
- -------------------------
- - Small changes for more compatibility with some C/C++ compilers.
+4.61 beta 2008-11-23
+-------------------------
+- The bug in ANSI-C LZMA Decoder was fixed:
+ If encoded stream was corrupted, decoder could access memory
+ outside of allocated range.
+- Some changes in ANSI-C 7z Decoder interfaces.
+- LZMA SDK is placed in the public domain.
- 4.42 2006-05-15
- -------------------------
- - Small changes in .h files in ANSI-C version.
+4.60 beta 2008-08-19
+-------------------------
+- Some minor fixes.
- 4.39 beta 2006-04-14
- -------------------------
- - Bug in versions 4.33b:4.38b was fixed:
- C++ version of LZMA encoder could not correctly compress
- files larger than 2 GB with HC4 match finder (-mfhc4).
+4.59 beta 2008-08-13
+-------------------------
+- The bug was fixed:
+ LZMA Encoder in fast compression mode could access memory outside of
+ allocated range in some rare cases.
- 4.37 beta 2005-04-06
- -------------------------
- - Fixes in C++ code: code could no be compiled if _NO_EXCEPTIONS was defined.
+4.58 beta 2008-05-05
+-------------------------
+- ANSI-C LZMA Decoder was rewritten for speed optimizations.
+- ANSI-C LZMA Encoder was included to LZMA SDK.
+- C++ LZMA code now is just wrapper over ANSI-C code.
- 4.35 beta 2005-03-02
- -------------------------
- - Bug was fixed in C++ version of LZMA Decoder:
- If encoded stream was corrupted, decoder could access memory
- outside of allocated range.
+4.57 2007-12-12
+-------------------------
+- Speed optimizations in Ñ++ LZMA Decoder.
+- Small changes for more compatibility with some C/C++ compilers.
- 4.34 beta 2006-02-27
- -------------------------
- - Compressing speed and memory requirements for compressing were increased
- - LZMA now can use only these match finders: HC4, BT2, BT3, BT4
+4.49 beta 2007-07-05
+-------------------------
+- .7z ANSI-C Decoder:
+ - now it supports BCJ and BCJ2 filters
+ - now it supports files larger than 4 GB.
+ - now it supports "Last Write Time" field for files.
+- C++ code for .7z archives compressing/decompressing from 7-zip
+ was included to LZMA SDK.
- 4.32 2005-12-09
- -------------------------
- - Java version of LZMA SDK was included
+4.43 2006-06-04
+-------------------------
+- Small changes for more compatibility with some C/C++ compilers.
- 4.30 2005-11-20
- -------------------------
- - Compression ratio was improved in -a2 mode
- - Speed optimizations for compressing in -a2 mode
- - -fb switch now supports values up to 273
- - Bug in 7z_C (7zIn.c) was fixed:
- It used Alloc/Free functions from different memory pools.
- So if program used two memory pools, it worked incorrectly.
- - 7z_C: .7z format supporting was improved
- - LZMA# SDK (C#.NET version) was included
+4.42 2006-05-15
+-------------------------
+- Small changes in .h files in ANSI-C version.
- 4.27 (Updated) 2005-09-21
- -------------------------
- - Some GUIDs/interfaces in C++ were changed.
- IStream.h:
- ISequentialInStream::Read now works as old ReadPart
- ISequentialOutStream::Write now works as old WritePart
+4.39 beta 2006-04-14
+-------------------------
+- The bug in versions 4.33b:4.38b was fixed:
+ C++ version of LZMA encoder could not correctly compress
+ files larger than 2 GB with HC4 match finder (-mfhc4).
- 4.27 2005-08-07
- -------------------------
- - Bug in LzmaDecodeSize.c was fixed:
- if _LZMA_IN_CB and _LZMA_OUT_READ were defined,
- decompressing worked incorrectly.
+4.37 beta 2005-04-06
+-------------------------
+- Fixes in C++ code: code could no be compiled if _NO_EXCEPTIONS was defined.
- 4.26 2005-08-05
- -------------------------
- - Fixes in 7z_C code and LzmaTest.c:
- previous versions could work incorrectly,
- if malloc(0) returns 0
+4.35 beta 2005-03-02
+-------------------------
+- The bug was fixed in C++ version of LZMA Decoder:
+ If encoded stream was corrupted, decoder could access memory
+ outside of allocated range.
- 4.23 2005-06-29
- -------------------------
- - Small fixes in C++ code
+4.34 beta 2006-02-27
+-------------------------
+- Compressing speed and memory requirements for compressing were increased
+- LZMA now can use only these match finders: HC4, BT2, BT3, BT4
- 4.22 2005-06-10
- -------------------------
- - Small fixes
+4.32 2005-12-09
+-------------------------
+- Java version of LZMA SDK was included
- 4.21 2005-06-08
- -------------------------
- - Interfaces for ANSI-C LZMA Decoder (LzmaDecode.c) were changed
- - New additional version of ANSI-C LZMA Decoder with zlib-like interface:
- - LzmaStateDecode.h
- - LzmaStateDecode.c
- - LzmaStateTest.c
- - ANSI-C LZMA Decoder now can decompress files larger than 4 GB
+4.30 2005-11-20
+-------------------------
+- Compression ratio was improved in -a2 mode
+- Speed optimizations for compressing in -a2 mode
+- -fb switch now supports values up to 273
+- The bug in 7z_C (7zIn.c) was fixed:
+ It used Alloc/Free functions from different memory pools.
+ So if program used two memory pools, it worked incorrectly.
+- 7z_C: .7z format supporting was improved
+- LZMA# SDK (C#.NET version) was included
- 4.17 2005-04-18
- -------------------------
- - New example for RAM->RAM compressing/decompressing:
- LZMA + BCJ (filter for x86 code):
- - LzmaRam.h
- - LzmaRam.cpp
- - LzmaRamDecode.h
- - LzmaRamDecode.c
- - -f86 switch for lzma.exe
+4.27 (Updated) 2005-09-21
+-------------------------
+- Some GUIDs/interfaces in C++ were changed.
+ IStream.h:
+ ISequentialInStream::Read now works as old ReadPart
+ ISequentialOutStream::Write now works as old WritePart
- 4.16 2005-03-29
- -------------------------
- - Bug was fixed in LzmaDecode.c (ANSI-C LZMA Decoder):
- If _LZMA_OUT_READ was defined, and if encoded stream was corrupted,
- decoder could access memory outside of allocated range.
- - Speed optimization of ANSI-C LZMA Decoder (now it's about 20% faster).
- Old version of LZMA Decoder now is in file LzmaDecodeSize.c.
- LzmaDecodeSize.c can provide slightly smaller code than LzmaDecode.c
- - Small speed optimization in LZMA C++ code
- - filter for SPARC's code was added
- - Simplified version of .7z ANSI-C Decoder was included
+4.27 2005-08-07
+-------------------------
+- The bug in LzmaDecodeSize.c was fixed:
+ if _LZMA_IN_CB and _LZMA_OUT_READ were defined,
+ decompressing worked incorrectly.
- 4.06 2004-09-05
- -------------------------
- - Bug in v4.05 was fixed:
- LZMA-Encoder didn't release output stream in some cases.
+4.26 2005-08-05
+-------------------------
+- Fixes in 7z_C code and LzmaTest.c:
+ previous versions could work incorrectly,
+ if malloc(0) returns 0
- 4.05 2004-08-25
- -------------------------
- - Source code of filters for x86, IA-64, ARM, ARM-Thumb
- and PowerPC code was included to SDK
- - Some internal minor changes
+4.23 2005-06-29
+-------------------------
+- Small fixes in C++ code
- 4.04 2004-07-28
- -------------------------
- - More compatibility with some C++ compilers
+4.22 2005-06-10
+-------------------------
+- Small fixes
- 4.03 2004-06-18
- -------------------------
- - "Benchmark" command was added. It measures compressing
- and decompressing speed and shows rating values.
- Also it checks hardware errors.
+4.21 2005-06-08
+-------------------------
+- Interfaces for ANSI-C LZMA Decoder (LzmaDecode.c) were changed
+- New additional version of ANSI-C LZMA Decoder with zlib-like interface:
+ - LzmaStateDecode.h
+ - LzmaStateDecode.c
+ - LzmaStateTest.c
+- ANSI-C LZMA Decoder now can decompress files larger than 4 GB
- 4.02 2004-06-10
- -------------------------
- - C++ LZMA Encoder/Decoder code now is more portable
- and it can be compiled by GCC on Linux.
+4.17 2005-04-18
+-------------------------
+- New example for RAM->RAM compressing/decompressing:
+ LZMA + BCJ (filter for x86 code):
+ - LzmaRam.h
+ - LzmaRam.cpp
+ - LzmaRamDecode.h
+ - LzmaRamDecode.c
+ - -f86 switch for lzma.exe
- 4.01 2004-02-15
- -------------------------
- - Some detection of data corruption was enabled.
- LzmaDecode.c / RangeDecoderReadByte
- .....
- {
- rd->ExtraBytes = 1;
- return 0xFF;
- }
+4.16 2005-03-29
+-------------------------
+- The bug was fixed in LzmaDecode.c (ANSI-C LZMA Decoder):
+ If _LZMA_OUT_READ was defined, and if encoded stream was corrupted,
+ decoder could access memory outside of allocated range.
+- Speed optimization of ANSI-C LZMA Decoder (now it's about 20% faster).
+ Old version of LZMA Decoder now is in file LzmaDecodeSize.c.
+ LzmaDecodeSize.c can provide slightly smaller code than LzmaDecode.c
+- Small speed optimization in LZMA C++ code
+- filter for SPARC's code was added
+- Simplified version of .7z ANSI-C Decoder was included
- 4.00 2004-02-13
- -------------------------
- - Original version of LZMA SDK
+4.06 2004-09-05
+-------------------------
+- The bug in v4.05 was fixed:
+ LZMA-Encoder didn't release output stream in some cases.
+
+
+4.05 2004-08-25
+-------------------------
+- Source code of filters for x86, IA-64, ARM, ARM-Thumb
+ and PowerPC code was included to SDK
+- Some internal minor changes
+
+
+4.04 2004-07-28
+-------------------------
+- More compatibility with some C++ compilers
+
+
+4.03 2004-06-18
+-------------------------
+- "Benchmark" command was added. It measures compressing
+ and decompressing speed and shows rating values.
+ Also it checks hardware errors.
+
+
+4.02 2004-06-10
+-------------------------
+- C++ LZMA Encoder/Decoder code now is more portable
+ and it can be compiled by GCC on Linux.
+
+
+4.01 2004-02-15
+-------------------------
+- Some detection of data corruption was enabled.
+ LzmaDecode.c / RangeDecoderReadByte
+ .....
+ {
+ rd->ExtraBytes = 1;
+ return 0xFF;
+ }
+
+
+4.00 2004-02-13
+-------------------------
+- Original version of LZMA SDK
HISTORY of the LZMA
-------------------
- 2001-2007: Improvements to LZMA compressing/decompressing code,
- keeping compatibility with original LZMA format
+ 2001-2008: Improvements to LZMA compressing/decompressing code,
+ keeping compatibility with original LZMA format
1996-2001: Development of LZMA compression format
Some milestones:
BASENAME=`basename $1 .tar.bz2`
TMPDIR=/tmp/tmp_lib_$BASENAME
-FILES="C/Compress/Lzma/LzmaDecode.h
- C/Compress/Lzma/LzmaTypes.h
- C/Compress/Lzma/LzmaDecode.c
+FILES="C/LzmaDec.h
+ C/Types.h
+ C/LzmaDec.c
history.txt
- LGPL.txt
lzma.txt"
-
mkdir -p $TMPDIR
echo "Untar $1 -> $TMPDIR"
tar -jxf $1 -C $TMPDIR
--- /dev/null
+ License
+
+LZMA SDK is placed in the public domain.
-LZMA SDK 4.57
+LZMA SDK 4.65
-------------
-LZMA SDK Copyright (C) 1999-2007 Igor Pavlov
-
LZMA SDK provides the documentation, samples, header files, libraries,
and tools you need to develop applications that use LZMA compression.
LICENSE
-------
-LZMA SDK is available under any of the following licenses:
-
-1) GNU Lesser General Public License (GNU LGPL)
-2) Common Public License (CPL)
-3) Simplified license for unmodified code (read SPECIAL EXCEPTION)
-4) Proprietary license
-
-It means that you can select one of these four options and follow rules of that license.
-
-
-1,2) GNU LGPL and CPL licenses are pretty similar and both these
-licenses are classified as
- - "Free software licenses" at http://www.gnu.org/
- - "OSI-approved" at http://www.opensource.org/
-
-
-3) SPECIAL EXCEPTION
-
-Igor Pavlov, as the author of this code, expressly permits you
-to statically or dynamically link your code (or bind by name)
-to the files from LZMA SDK without subjecting your linked
-code to the terms of the CPL or GNU LGPL.
-Any modifications or additions to files from LZMA SDK, however,
-are subject to the GNU LGPL or CPL terms.
-
-SPECIAL EXCEPTION allows you to use LZMA SDK in applications with closed code,
-while you keep LZMA SDK code unmodified.
-
-
-SPECIAL EXCEPTION #2: Igor Pavlov, as the author of this code, expressly permits
-you to use this code under the same terms and conditions contained in the License
-Agreement you have for any previous version of LZMA SDK developed by Igor Pavlov.
-
-SPECIAL EXCEPTION #2 allows owners of proprietary licenses to use latest version
-of LZMA SDK as update for previous versions.
-
-
-SPECIAL EXCEPTION #3: Igor Pavlov, as the author of this code, expressly permits
-you to use code of the following files:
-BranchTypes.h, LzmaTypes.h, LzmaTest.c, LzmaStateTest.c, LzmaAlone.cpp,
-LzmaAlone.cs, LzmaAlone.java
-as public domain code.
-
-
-4) Proprietary license
-
-LZMA SDK also can be available under a proprietary license which
-can include:
-
-1) Right to modify code without subjecting modified code to the
-terms of the CPL or GNU LGPL
-2) Technical support for code
-
-To request such proprietary license or any additional consultations,
-send email message from that page:
-http://www.7-zip.org/support.html
-
-
-You should have received a copy of the GNU Lesser General Public
-License along with this library; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
-You should have received a copy of the Common Public License
-along with this library.
+LZMA SDK is written and placed in the public domain by Igor Pavlov.
LZMA SDK Contents
LZMA SDK includes:
- - C++ source code of LZMA compressing and decompressing
- - ANSI-C compatible source code for LZMA decompressing
- - C# source code for LZMA compressing and decompressing
- - Java source code for LZMA compressing and decompressing
+ - ANSI-C/C++/C#/Java source code for LZMA compressing and decompressing
- Compiled file->file LZMA compressing/decompressing program for Windows system
-ANSI-C LZMA decompression code was ported from original C++ sources to C.
-Also it was simplified and optimized for code size.
-But it is fully compatible with LZMA from 7-Zip.
-
UNIX/Linux version
------------------
-To compile C++ version of file->file LZMA, go to directory
-C/7zip/Compress/LZMA_Alone
-and type "make" or "make clean all" to recompile all.
+To compile C++ version of file->file LZMA encoding, go to directory
+C++/7zip/Compress/LZMA_Alone
+and call make to recompile it:
+ make -f makefile.gcc clean all
In some UNIX/Linux versions you must compile LZMA with static libraries.
-To compile with static libraries, change string in makefile
-LIB = -lm
-to string
+To compile with static libraries, you can use
LIB = -lm -static
Files
---------------------
-C - C source code
-CPP - CPP source code
-CS - C# source code
-Java - Java source code
-lzma.txt - LZMA SDK description (this file)
+lzma.txt - LZMA SDK description (this file)
7zFormat.txt - 7z Format description
-7zC.txt - 7z ANSI-C Decoder description (this file)
+7zC.txt - 7z ANSI-C Decoder description
methods.txt - Compression method IDs for .7z
-LGPL.txt - GNU Lesser General Public License
-CPL.html - Common Public License
-lzma.exe - Compiled file->file LZMA encoder/decoder for Windows
-history.txt - history of the LZMA SDK
+lzma.exe - Compiled file->file LZMA encoder/decoder for Windows
+history.txt - history of the LZMA SDK
Source code structure
---------------------
-C - C files
- Compress - files related to compression/decompression
- Lz - files related to LZ (Lempel-Ziv) compression algorithm
- Lzma - ANSI-C compatible LZMA decompressor
+C/ - C files
+ 7zCrc*.* - CRC code
+ Alloc.* - Memory allocation functions
+ Bra*.* - Filters for x86, IA-64, ARM, ARM-Thumb, PowerPC and SPARC code
+ LzFind.* - Match finder for LZ (LZMA) encoders
+ LzFindMt.* - Match finder for LZ (LZMA) encoders for multithreading encoding
+ LzHash.h - Additional file for LZ match finder
+ LzmaDec.* - LZMA decoding
+ LzmaEnc.* - LZMA encoding
+ LzmaLib.* - LZMA Library for DLL calling
+ Types.h - Basic types for another .c files
+ Threads.* - The code for multithreading.
- LzmaDecode.h - interface for LZMA decoding on ANSI-C
- LzmaDecode.c - LZMA decoding on ANSI-C (new fastest version)
- LzmaDecodeSize.c - LZMA decoding on ANSI-C (old size-optimized version)
- LzmaTest.c - test application that decodes LZMA encoded file
- LzmaTypes.h - basic types for LZMA Decoder
- LzmaStateDecode.h - interface for LZMA decoding (State version)
- LzmaStateDecode.c - LZMA decoding on ANSI-C (State version)
- LzmaStateTest.c - test application (State version)
+ LzmaLib - LZMA Library (.DLL for Windows)
- Branch - Filters for x86, IA-64, ARM, ARM-Thumb, PowerPC and SPARC code
+ LzmaUtil - LZMA Utility (file->file LZMA encoder/decoder).
Archive - files related to archiving
- 7z_C - 7z ANSI-C Decoder
-
+ 7z - 7z ANSI-C Decoder
-CPP -- CPP files
+CPP/ -- CPP files
Common - common files for C++ projects
Windows - common files for Windows related code
- 7zip - files related to 7-Zip Project
+
+ 7zip - files related to 7-Zip Project
Common - common files for 7-Zip
Compress - files related to compression/decompression
- LZ - files related to LZ (Lempel-Ziv) compression algorithm
-
- Copy - Copy coder
+ Copy - Copy coder
RangeCoder - Range Coder (special code of compression/decompression)
- LZMA - LZMA compression/decompression on C++
+ LZMA - LZMA compression/decompression on C++
LZMA_Alone - file->file LZMA compression/decompression
-
- Branch - Filters for x86, IA-64, ARM, ARM-Thumb, PowerPC and SPARC code
+ Branch - Filters for x86, IA-64, ARM, ARM-Thumb, PowerPC and SPARC code
Archive - files related to archiving
Bundles - Modules that are bundles of other modules
- Alone7z - 7zr.exe: Standalone version of 7z.exe that supports only 7z/LZMA/BCJ/BCJ2
- Format7zR - 7zr.dll: Reduced version of 7za.dll: extracting/compressing to 7z/LZMA/BCJ/BCJ2
- Format7zExtractR - 7zxr.dll: Reduced version of 7zxa.dll: extracting from 7z/LZMA/BCJ/BCJ2.
+ Alone7z - 7zr.exe: Standalone version of 7z.exe that supports only 7z/LZMA/BCJ/BCJ2
+ Format7zR - 7zr.dll: Reduced version of 7za.dll: extracting/compressing to 7z/LZMA/BCJ/BCJ2
+ Format7zExtractR - 7zxr.dll: Reduced version of 7zxa.dll: extracting from 7z/LZMA/BCJ/BCJ2.
- UI - User Interface files
+ UI - User Interface files
- Client7z - Test application for 7za.dll, 7zr.dll, 7zxr.dll
+ Client7z - Test application for 7za.dll, 7zr.dll, 7zxr.dll
Common - Common UI files
Console - Code for console archiver
-CS - C# files
+CS/ - C# files
7zip
Common - some common files for 7-Zip
Compress - files related to compression/decompression
LZ - files related to LZ (Lempel-Ziv) compression algorithm
- LZMA - LZMA compression/decompression
+ LZMA - LZMA compression/decompression
LzmaAlone - file->file LZMA compression/decompression
RangeCoder - Range Coder (special code of compression/decompression)
-Java - Java files
+Java/ - Java files
SevenZip
Compression - files related to compression/decompression
- LZ - files related to LZ (Lempel-Ziv) compression algorithm
- LZMA - LZMA compression/decompression
+ LZ - files related to LZ (Lempel-Ziv) compression algorithm
+ LZMA - LZMA compression/decompression
RangeCoder - Range Coder (special code of compression/decompression)
-C/C++ source code of LZMA SDK is part of 7-Zip project.
-
-You can find ANSI-C LZMA decompressing code at folder
- C/7zip/Compress/Lzma
-7-Zip doesn't use that ANSI-C LZMA code and that code was developed
-specially for this SDK. And files from C/7zip/Compress/Lzma do not need
-files from other directories of SDK for compiling.
+C/C++ source code of LZMA SDK is part of 7-Zip project.
7-Zip source code can be downloaded from 7-Zip's SourceForge page:
http://sourceforge.net/projects/sevenzip/
+
LZMA features
-------------
- Variable dictionary size (up to 1 GB)
- - Estimated compressing speed: about 1 MB/s on 1 GHz CPU
+ - Estimated compressing speed: about 2 MB/s on 2 GHz CPU
- Estimated decompressing speed:
- - 8-12 MB/s on 1 GHz Intel Pentium 3 or AMD Athlon
- - 500-1000 KB/s on 100 MHz ARM, MIPS, PowerPC or other simple RISC
- - Small memory requirements for decompressing (8-32 KB + DictionarySize)
- - Small code size for decompressing: 2-8 KB (depending from
- speed optimizations)
+ - 20-30 MB/s on 2 GHz Core 2 or AMD Athlon 64
+ - 1-2 MB/s on 200 MHz ARM, MIPS, PowerPC or other simple RISC
+ - Small memory requirements for decompressing (16 KB + DictionarySize)
+ - Small code size for decompressing: 5-8 KB
LZMA decoder uses only integer operations and can be
implemented in any modern 32-bit CPU (or on 16-bit CPU with some conditions).
-Some critical operations that affect to speed of LZMA decompression:
+Some critical operations that affect the speed of LZMA decompression:
1) 32*16 bit integer multiply
2) Misspredicted branches (penalty mostly depends from pipeline length)
3) 32-bit shift and arithmetic operations
-Speed of LZMA decompressing mostly depends from CPU speed.
+The speed of LZMA decompressing mostly depends from CPU speed.
Memory speed has no big meaning. But if your CPU has small data cache,
overall weight of memory speed will slightly increase.
Using LZMA encoder/decoder executable
--------------------------------------
-Usage: LZMA <e|d> inputFile outputFile [<switches>...]
+Usage: LZMA <e|d> inputFile outputFile [<switches>...]
e: encode file
b: Benchmark. There are two tests: compressing and decompressing
with LZMA method. Benchmark shows rating in MIPS (million
instructions per second). Rating value is calculated from
- measured speed and it is normalized with AMD Athlon 64 X2 CPU
- results. Also Benchmark checks possible hardware errors (RAM
+ measured speed and it is normalized with Intel's Core 2 results.
+ Also Benchmark checks possible hardware errors (RAM
errors in most cases). Benchmark uses these settings:
- (-a1, -d21, -fb32, -mfbt4). You can change only -d. Also you
- can change number of iterations. Example for 30 iterations:
+ (-a1, -d21, -fb32, -mfbt4). You can change only -d parameter.
+ Also you can change the number of iterations. Example for 30 iterations:
LZMA b 30
Default number of iterations is 10.
-a{N}: set compression mode 0 = fast, 1 = normal
- default: 1 (normal)
+ default: 1 (normal)
d{N}: Sets Dictionary size - [0, 30], default: 23 (8MB)
- The maximum value for dictionary size is 1 GB = 2^30 bytes.
- Dictionary size is calculated as DictionarySize = 2^N bytes.
- For decompressing file compressed by LZMA method with dictionary
- size D = 2^N you need about D bytes of memory (RAM).
+ The maximum value for dictionary size is 1 GB = 2^30 bytes.
+ Dictionary size is calculated as DictionarySize = 2^N bytes.
+ For decompressing file compressed by LZMA method with dictionary
+ size D = 2^N you need about D bytes of memory (RAM).
-fb{N}: set number of fast bytes - [5, 273], default: 128
- Usually big number gives a little bit better compression ratio
- and slower compression process.
+ Usually big number gives a little bit better compression ratio
+ and slower compression process.
-lc{N}: set number of literal context bits - [0, 8], default: 3
- Sometimes lc=4 gives gain for big files.
+ Sometimes lc=4 gives gain for big files.
-lp{N}: set number of literal pos bits - [0, 4], default: 0
- lp switch is intended for periodical data when period is
- equal 2^N. For example, for 32-bit (4 bytes)
- periodical data you can use lp=2. Often it's better to set lc0,
- if you change lp switch.
+ lp switch is intended for periodical data when period is
+ equal 2^N. For example, for 32-bit (4 bytes)
+ periodical data you can use lp=2. Often it's better to set lc0,
+ if you change lp switch.
-pb{N}: set number of pos bits - [0, 4], default: 2
- pb switch is intended for periodical data
- when period is equal 2^N.
+ pb switch is intended for periodical data
+ when period is equal 2^N.
-mf{MF_ID}: set Match Finder. Default: bt4.
- Algorithms from hc* group doesn't provide good compression
- ratio, but they often works pretty fast in combination with
- fast mode (-a0).
+ Algorithms from hc* group doesn't provide good compression
+ ratio, but they often works pretty fast in combination with
+ fast mode (-a0).
- Memory requirements depend from dictionary size
- (parameter "d" in table below).
+ Memory requirements depend from dictionary size
+ (parameter "d" in table below).
- MF_ID Memory Description
+ MF_ID Memory Description
- bt2 d * 9.5 + 4MB Binary Tree with 2 bytes hashing.
- bt3 d * 11.5 + 4MB Binary Tree with 3 bytes hashing.
- bt4 d * 11.5 + 4MB Binary Tree with 4 bytes hashing.
- hc4 d * 7.5 + 4MB Hash Chain with 4 bytes hashing.
+ bt2 d * 9.5 + 4MB Binary Tree with 2 bytes hashing.
+ bt3 d * 11.5 + 4MB Binary Tree with 3 bytes hashing.
+ bt4 d * 11.5 + 4MB Binary Tree with 4 bytes hashing.
+ hc4 d * 7.5 + 4MB Hash Chain with 4 bytes hashing.
-eos: write End Of Stream marker. By default LZMA doesn't write
- eos marker, since LZMA decoder knows uncompressed size
- stored in .lzma file header.
+ eos marker, since LZMA decoder knows uncompressed size
+ stored in .lzma file header.
- -si: Read data from stdin (it will write End Of Stream marker).
- -so: Write data to stdout
+ -si: Read data from stdin (it will write End Of Stream marker).
+ -so: Write data to stdout
Examples:
Recommendations
---------------
-To increase compression ratio for LZMA compressing it's desirable
+To increase the compression ratio for LZMA compressing it's desirable
to have aligned data (if it's possible) and also it's desirable to locate
data in such order, where code is grouped in one place and data is
grouped in other place (it's better than such mixing: code, data, code,
data, ...).
-Using Filters
--------------
-You can increase compression ratio for some data types, using
+Filters
+-------
+You can increase the compression ratio for some data types, using
special filters before compressing. For example, it's possible to
-increase compression ratio on 5-10% for code for those CPU ISAs:
+increase the compression ratio on 5-10% for code for those CPU ISAs:
x86, IA-64, ARM, ARM-Thumb, PowerPC, SPARC.
-You can find C/C++ source code of such filters in folder "7zip/Compress/Branch"
+You can find C source code of such filters in C/Bra*.* files
-You can check compression ratio gain of these filters with such
+You can check the compression ratio gain of these filters with such
7-Zip commands (example for ARM code):
No filter:
7z a a1.7z a.bin -m0=lzma
With filter for little-endian ARM code:
- 7z a a2.7z a.bin -m0=bc_arm -m1=lzma
-
-With filter for big-endian ARM code (using additional Swap4 filter):
- 7z a a3.7z a.bin -m0=swap4 -m1=bc_arm -m2=lzma
+ 7z a a2.7z a.bin -m0=arm -m1=lzma
It works in such manner:
Compressing = Filter_encoding + LZMA_encoding
These filters convert CALL (calling procedure) instructions
from relative offsets to absolute addresses, so such data becomes more
-compressible. Source code of these CALL filters is pretty simple
-(about 20 lines of C++), so you can convert it from C++ version yourself.
+compressible.
For some ISAs (for example, for MIPS) it's impossible to get gain from such filter.
LZMA compressed file format
---------------------------
Offset Size Description
- 0 1 Special LZMA properties for compressed data
- 1 4 Dictionary size (little endian)
- 5 8 Uncompressed size (little endian). -1 means unknown size
- 13 Compressed data
+ 0 1 Special LZMA properties (lc,lp, pb in encoded form)
+ 1 4 Dictionary size (little endian)
+ 5 8 Uncompressed size (little endian). -1 means unknown size
+ 13 Compressed data
ANSI-C LZMA Decoder
~~~~~~~~~~~~~~~~~~~
-To compile ANSI-C LZMA Decoder you can use one of the following files sets:
-1) LzmaDecode.h + LzmaDecode.c + LzmaTest.c (fastest version)
-2) LzmaDecode.h + LzmaDecodeSize.c + LzmaTest.c (old size-optimized version)
-3) LzmaStateDecode.h + LzmaStateDecode.c + LzmaStateTest.c (zlib-like interface)
+Please note that interfaces for ANSI-C code were changed in LZMA SDK 4.58.
+If you want to use old interfaces you can download previous version of LZMA SDK
+from sourceforge.net site.
+
+To use ANSI-C LZMA Decoder you need the following files:
+1) LzmaDec.h + LzmaDec.c + Types.h
+LzmaUtil/LzmaUtil.c is example application that uses these files.
Memory requirements for LZMA decoding
-------------------------------------
-LZMA decoder doesn't allocate memory itself, so you must
-allocate memory and send it to LZMA.
-
Stack usage of LZMA decoding function for local variables is not
-larger than 200 bytes.
+larger than 200-400 bytes.
+
+LZMA Decoder uses dictionary buffer and internal state structure.
+Internal state structure consumes
+ state_size = (4 + (1.5 << (lc + lp))) KB
+by default (lc=3, lp=0), state_size = 16 KB.
+
How To decompress data
----------------------
-LZMA Decoder (ANSI-C version) now supports 5 interfaces:
+LZMA Decoder (ANSI-C version) now supports 2 interfaces:
1) Single-call Decompressing
-2) Single-call Decompressing with input stream callback
-3) Multi-call Decompressing with output buffer
-4) Multi-call Decompressing with input callback and output buffer
-5) Multi-call State Decompressing (zlib-like interface)
-
-Variant-5 is similar to Variant-4, but Variant-5 doesn't use callback functions.
-
-Decompressing steps
--------------------
-
-1) read LZMA properties (5 bytes):
- unsigned char properties[LZMA_PROPERTIES_SIZE];
-
-2) read uncompressed size (8 bytes, little-endian)
+2) Multi-call State Decompressing (zlib-like interface)
-3) Decode properties:
+You must use external allocator:
+Example:
+void *SzAlloc(void *p, size_t size) { p = p; return malloc(size); }
+void SzFree(void *p, void *address) { p = p; free(address); }
+ISzAlloc alloc = { SzAlloc, SzFree };
- CLzmaDecoderState state; /* it's 24-140 bytes structure, if int is 32-bit */
+You can use p = p; operator to disable compiler warnings.
- if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK)
- return PrintError(rs, "Incorrect stream properties");
-4) Allocate memory block for internal Structures:
-
- state.Probs = (CProb *)malloc(LzmaGetNumProbs(&state.Properties) * sizeof(CProb));
- if (state.Probs == 0)
- return PrintError(rs, kCantAllocateMessage);
-
- LZMA decoder uses array of CProb variables as internal structure.
- By default, CProb is unsigned_short. But you can define _LZMA_PROB32 to make
- it unsigned_int. It can increase speed on some 32-bit CPUs, but memory
- usage will be doubled in that case.
-
-
-5) Main Decompressing
-
-You must use one of the following interfaces:
-
-5.1 Single-call Decompressing
------------------------------
+Single-call Decompressing
+-------------------------
When to use: RAM->RAM decompressing
-Compile files: LzmaDecode.h, LzmaDecode.c
+Compile files: LzmaDec.h + LzmaDec.c + Types.h
Compile defines: no defines
Memory Requirements:
- Input buffer: compressed size
- Output buffer: uncompressed size
- - LZMA Internal Structures (~16 KB for default settings)
+ - LZMA Internal Structures: state_size (16 KB for default settings)
Interface:
- int res = LzmaDecode(&state,
- inStream, compressedSize, &inProcessed,
- outStream, outSize, &outProcessed);
+ int LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen,
+ const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode,
+ ELzmaStatus *status, ISzAlloc *alloc);
+ In:
+ dest - output data
+ destLen - output data size
+ src - input data
+ srcLen - input data size
+ propData - LZMA properties (5 bytes)
+ propSize - size of propData buffer (5 bytes)
+ finishMode - It has meaning only if the decoding reaches output limit (*destLen).
+ LZMA_FINISH_ANY - Decode just destLen bytes.
+ LZMA_FINISH_END - Stream must be finished after (*destLen).
+ You can use LZMA_FINISH_END, when you know that
+ current output buffer covers last bytes of stream.
+ alloc - Memory allocator.
+
+ Out:
+ destLen - processed output size
+ srcLen - processed input size
+
+ Output:
+ SZ_OK
+ status:
+ LZMA_STATUS_FINISHED_WITH_MARK
+ LZMA_STATUS_NOT_FINISHED
+ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK
+ SZ_ERROR_DATA - Data error
+ SZ_ERROR_MEM - Memory allocation error
+ SZ_ERROR_UNSUPPORTED - Unsupported properties
+ SZ_ERROR_INPUT_EOF - It needs more bytes in input buffer (src).
+
+ If LZMA decoder sees end_marker before reaching output limit, it returns OK result,
+ and output value of destLen will be less than output buffer size limit.
+
+ You can use multiple checks to test data integrity after full decompression:
+ 1) Check Result and "status" variable.
+ 2) Check that output(destLen) = uncompressedSize, if you know real uncompressedSize.
+ 3) Check that output(srcLen) = compressedSize, if you know real compressedSize.
+ You must use correct finish mode in that case. */
+
+
+Multi-call State Decompressing (zlib-like interface)
+----------------------------------------------------
+When to use: file->file decompressing
+Compile files: LzmaDec.h + LzmaDec.c + Types.h
-5.2 Single-call Decompressing with input stream callback
---------------------------------------------------------
-When to use: File->RAM or Flash->RAM decompressing.
-Compile files: LzmaDecode.h, LzmaDecode.c
-Compile defines: _LZMA_IN_CB
Memory Requirements:
- - Buffer for input stream: any size (for example, 16 KB)
- - Output buffer: uncompressed size
- - LZMA Internal Structures (~16 KB for default settings)
+ - Buffer for input stream: any size (for example, 16 KB)
+ - Buffer for output stream: any size (for example, 16 KB)
+ - LZMA Internal Structures: state_size (16 KB for default settings)
+ - LZMA dictionary (dictionary size is encoded in LZMA properties header)
-Interface:
- typedef struct _CBuffer
- {
- ILzmaInCallback InCallback;
- FILE *File;
- unsigned char Buffer[kInBufferSize];
- } CBuffer;
+1) read LZMA properties (5 bytes) and uncompressed size (8 bytes, little-endian) to header:
+ unsigned char header[LZMA_PROPS_SIZE + 8];
+ ReadFile(inFile, header, sizeof(header)
- int LzmaReadCompressed(void *object, const unsigned char **buffer, SizeT *size)
+2) Allocate CLzmaDec structures (state + dictionary) using LZMA properties
+
+ CLzmaDec state;
+ LzmaDec_Constr(&state);
+ res = LzmaDec_Allocate(&state, header, LZMA_PROPS_SIZE, &g_Alloc);
+ if (res != SZ_OK)
+ return res;
+
+3) Init LzmaDec structure before any new LZMA stream. And call LzmaDec_DecodeToBuf in loop
+
+ LzmaDec_Init(&state);
+ for (;;)
{
- CBuffer *bo = (CBuffer *)object;
- *buffer = bo->Buffer;
- *size = MyReadFile(bo->File, bo->Buffer, kInBufferSize);
- return LZMA_RESULT_OK;
+ ...
+ int res = LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen,
+ const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode);
+ ...
}
- CBuffer g_InBuffer;
- g_InBuffer.File = inFile;
- g_InBuffer.InCallback.Read = LzmaReadCompressed;
- int res = LzmaDecode(&state,
- &g_InBuffer.InCallback,
- outStream, outSize, &outProcessed);
+4) Free all allocated structures
+ LzmaDec_Free(&state, &g_Alloc);
+
+For full code example, look at C/LzmaUtil/LzmaUtil.c code.
+
+
+How To compress data
+--------------------
+Compile files: LzmaEnc.h + LzmaEnc.c + Types.h +
+LzFind.c + LzFind.h + LzFindMt.c + LzFindMt.h + LzHash.h
-5.3 Multi-call decompressing with output buffer
------------------------------------------------
-When to use: RAM->File decompressing
-Compile files: LzmaDecode.h, LzmaDecode.c
-Compile defines: _LZMA_OUT_READ
Memory Requirements:
- - Input buffer: compressed size
- - Buffer for output stream: any size (for example, 16 KB)
- - LZMA Internal Structures (~16 KB for default settings)
- - LZMA dictionary (dictionary size is encoded in stream properties)
+ - (dictSize * 11.5 + 6 MB) + state_size
-Interface:
+Lzma Encoder can use two memory allocators:
+1) alloc - for small arrays.
+2) allocBig - for big arrays.
- state.Dictionary = (unsigned char *)malloc(state.Properties.DictionarySize);
+For example, you can use Large RAM Pages (2 MB) in allocBig allocator for
+better compression speed. Note that Windows has bad implementation for
+Large RAM Pages.
+It's OK to use same allocator for alloc and allocBig.
- LzmaDecoderInit(&state);
- do
- {
- LzmaDecode(&state,
- inBuffer, inAvail, &inProcessed,
- g_OutBuffer, outAvail, &outProcessed);
- inAvail -= inProcessed;
- inBuffer += inProcessed;
- }
- while you need more bytes
- see LzmaTest.c for more details.
+Single-call Compression with callbacks
+--------------------------------------
+Check C/LzmaUtil/LzmaUtil.c as example,
-5.4 Multi-call decompressing with input callback and output buffer
-------------------------------------------------------------------
-When to use: File->File decompressing
-Compile files: LzmaDecode.h, LzmaDecode.c
-Compile defines: _LZMA_IN_CB, _LZMA_OUT_READ
-Memory Requirements:
- - Buffer for input stream: any size (for example, 16 KB)
- - Buffer for output stream: any size (for example, 16 KB)
- - LZMA Internal Structures (~16 KB for default settings)
- - LZMA dictionary (dictionary size is encoded in stream properties)
+When to use: file->file decompressing
-Interface:
+1) you must implement callback structures for interfaces:
+ISeqInStream
+ISeqOutStream
+ICompressProgress
+ISzAlloc
- state.Dictionary = (unsigned char *)malloc(state.Properties.DictionarySize);
+static void *SzAlloc(void *p, size_t size) { p = p; return MyAlloc(size); }
+static void SzFree(void *p, void *address) { p = p; MyFree(address); }
+static ISzAlloc g_Alloc = { SzAlloc, SzFree };
- LzmaDecoderInit(&state);
- do
- {
- LzmaDecode(&state,
- &bo.InCallback,
- g_OutBuffer, outAvail, &outProcessed);
- }
- while you need more bytes
+ CFileSeqInStream inStream;
+ CFileSeqOutStream outStream;
- see LzmaTest.c for more details:
+ inStream.funcTable.Read = MyRead;
+ inStream.file = inFile;
+ outStream.funcTable.Write = MyWrite;
+ outStream.file = outFile;
-5.5 Multi-call State Decompressing (zlib-like interface)
-------------------------------------------------------------------
-When to use: file->file decompressing
-Compile files: LzmaStateDecode.h, LzmaStateDecode.c
-Compile defines:
-Memory Requirements:
- - Buffer for input stream: any size (for example, 16 KB)
- - Buffer for output stream: any size (for example, 16 KB)
- - LZMA Internal Structures (~16 KB for default settings)
- - LZMA dictionary (dictionary size is encoded in stream properties)
+2) Create CLzmaEncHandle object;
-Interface:
+ CLzmaEncHandle enc;
- state.Dictionary = (unsigned char *)malloc(state.Properties.DictionarySize);
+ enc = LzmaEnc_Create(&g_Alloc);
+ if (enc == 0)
+ return SZ_ERROR_MEM;
- LzmaDecoderInit(&state);
- do
- {
- res = LzmaDecode(&state,
- inBuffer, inAvail, &inProcessed,
- g_OutBuffer, outAvail, &outProcessed,
- finishDecoding);
- inAvail -= inProcessed;
- inBuffer += inProcessed;
- }
- while you need more bytes
+3) initialize CLzmaEncProps properties;
- see LzmaStateTest.c for more details:
+ LzmaEncProps_Init(&props);
+ Then you can change some properties in that structure.
-6) Free all allocated blocks
+4) Send LZMA properties to LZMA Encoder
+ res = LzmaEnc_SetProps(enc, &props);
-Note
-----
-LzmaDecodeSize.c is size-optimized version of LzmaDecode.c.
-But compiled code of LzmaDecodeSize.c can be larger than
-compiled code of LzmaDecode.c. So it's better to use
-LzmaDecode.c in most cases.
+5) Write encoded properties to header
+ Byte header[LZMA_PROPS_SIZE + 8];
+ size_t headerSize = LZMA_PROPS_SIZE;
+ UInt64 fileSize;
+ int i;
-EXIT codes
------------
+ res = LzmaEnc_WriteProperties(enc, header, &headerSize);
+ fileSize = MyGetFileLength(inFile);
+ for (i = 0; i < 8; i++)
+ header[headerSize++] = (Byte)(fileSize >> (8 * i));
+ MyWriteFileAndCheck(outFile, header, headerSize)
-LZMA decoder can return one of the following codes:
+6) Call encoding function:
+ res = LzmaEnc_Encode(enc, &outStream.funcTable, &inStream.funcTable,
+ NULL, &g_Alloc, &g_Alloc);
-#define LZMA_RESULT_OK 0
-#define LZMA_RESULT_DATA_ERROR 1
+7) Destroy LZMA Encoder Object
+ LzmaEnc_Destroy(enc, &g_Alloc, &g_Alloc);
-If you use callback function for input data and you return some
-error code, LZMA Decoder also returns that code.
+If callback function return some error code, LzmaEnc_Encode also returns that code.
-LZMA Defines
-------------
+Single-call RAM->RAM Compression
+--------------------------------
-_LZMA_IN_CB - Use callback for input data
+Single-call RAM->RAM Compression is similar to Compression with callbacks,
+but you provide pointers to buffers instead of pointers to stream callbacks:
-_LZMA_OUT_READ - Use read function for output data
+HRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,
+ CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark,
+ ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);
-_LZMA_LOC_OPT - Enable local speed optimizations inside code.
- _LZMA_LOC_OPT is only for LzmaDecodeSize.c (size-optimized version).
- _LZMA_LOC_OPT doesn't affect LzmaDecode.c (speed-optimized version)
- and LzmaStateDecode.c
+Return code:
+ SZ_OK - OK
+ SZ_ERROR_MEM - Memory allocation error
+ SZ_ERROR_PARAM - Incorrect paramater
+ SZ_ERROR_OUTPUT_EOF - output buffer overflow
+ SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version)
-_LZMA_PROB32 - It can increase speed on some 32-bit CPUs,
- but memory usage will be doubled in that case
-_LZMA_UINT32_IS_ULONG - Define it if int is 16-bit on your compiler
- and long is 32-bit.
-_LZMA_SYSTEM_SIZE_T - Define it if you want to use system's size_t.
- You can use it to enable 64-bit sizes supporting
+LZMA Defines
+------------
+
+_LZMA_SIZE_OPT - Enable some optimizations in LZMA Decoder to get smaller executable code.
+
+_LZMA_PROB32 - It can increase the speed on some 32-bit CPUs, but memory usage for
+ some structures will be doubled in that case.
+_LZMA_UINT32_IS_ULONG - Define it if int is 16-bit on your compiler and long is 32-bit.
+
+_LZMA_NO_SYSTEM_SIZE_T - Define it if you don't want to use size_t type.
C++ LZMA Encoder/Decoder
~~~~~~~~~~~~~~~~~~~~~~~~
C++ LZMA code use COM-like interfaces. So if you want to use it,
you can study basics of COM/OLE.
+C++ LZMA code is just wrapper over ANSI-C code.
-By default, LZMA Encoder contains all Match Finders.
-But for compressing it's enough to have just one of them.
-So for reducing size of compressing code you can define:
- #define COMPRESS_MF_BT
- #define COMPRESS_MF_BT4
-and it will use only bt4 match finder.
+C++ Notes
+~~~~~~~~~~~~~~~~~~~~~~~~
+If you use some C++ code folders in 7-Zip (for example, C++ code for .7z handling),
+you must check that you correctly work with "new" operator.
+7-Zip can be compiled with MSVC 6.0 that doesn't throw "exception" from "new" operator.
+So 7-Zip uses "CPP\Common\NewHandler.cpp" that redefines "new" operator:
+operator new(size_t size)
+{
+ void *p = ::malloc(size);
+ if (p == 0)
+ throw CNewException();
+ return p;
+}
+If you use MSCV that throws exception for "new" operator, you can compile without
+"NewHandler.cpp". So standard exception will be used. Actually some code of
+7-Zip catches any exception in internal code and converts it to HRESULT code.
+So you don't need to catch CNewException, if you call COM interfaces of 7-Zip.
---
http://www.7-zip.org
+http://www.7-zip.org/sdk.html
http://www.7-zip.org/support.html
and to fit the cifs vfs by
Steve French sfrench@us.ibm.com */
+#include "compiler.h"
+
#ifndef USE_HOSTCC
#include <common.h>
-#include <linux/string.h>
-#else
-#include <string.h>
-#endif /* USE_HOSTCC */
#include <watchdog.h>
-#include <linux/types.h>
+#endif /* USE_HOSTCC */
#include <u-boot/md5.h>
static void
#endif
#ifdef CONFIG_SYS_64BIT_VSPRINTF
+#include <div64.h>
# define NUM_TYPE long long
#else
# define NUM_TYPE long
-#endif
-#define noinline __attribute__((noinline))
-
#define do_div(n, base) ({ \
unsigned int __res; \
__res = ((unsigned NUM_TYPE) n) % base; \
n = ((unsigned NUM_TYPE) n) / base; \
__res; \
})
+#endif
+#define noinline __attribute__((noinline))
+
const char hex_asc[] = "0123456789abcdef";
#define hex_asc_lo(x) hex_asc[((x) & 0x0f)]
#include <common.h>
#include <watchdog.h>
#include <command.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <timestamp.h>
#include <version.h>
#include <malloc.h>
show_boot_progress(0x27);
- devices_init ();
+ stdio_init ();
jumptable_init ();
# MA 02111-1307 USA
#
+CROSS_COMPILE ?= i386-linux-
+
PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__
#include <common.h>
#include <pci.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <i8042.h>
#include <asm/ptrace.h>
#include <asm/realmode.h>
{
u16 pos;
- static device_t vga_dev;
- static device_t kbd_dev;
+ static struct stdio_dev vga_dev;
+ static struct stdio_dev kbd_dev;
vidmem = (char *) 0xb8000;
vidport = 0x3d4;
vga_dev.tstc = NULL; /* 'tstc' function */
vga_dev.getc = NULL; /* 'getc' function */
- if (device_register(&vga_dev) == 0) {
+ if (stdio_register(&vga_dev) == 0) {
return 1;
}
kbd_dev.tstc = i8042_tstc; /* 'tstc' function */
kbd_dev.getc = i8042_getc; /* 'getc' function */
- if (device_register(&kbd_dev) == 0) {
+ if (stdio_register(&kbd_dev) == 0) {
return 1;
}
return 0;
#include <watchdog.h>
#include <command.h>
#include <malloc.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <asm/immap.h>
#endif
/** leave this here (after malloc(), environment and PCI are working) **/
- /* Initialize devices */
- devices_init ();
+ /* Initialize stdio devices */
+ stdio_init ();
/* Initialize the jump table for applications */
jumptable_init ();
# MA 02111-1307 USA
#
+CROSS_COMPILE ?= m68k-elf-
+
PLATFORM_CPPFLAGS += -DCONFIG_M68K -D__M68K__
PLATFORM_LDFLAGS += -n
gd = (gd_t *) CONFIG_SYS_GBL_DATA_OFFSET;
#if defined(CONFIG_CMD_FLASH)
ulong flash_size = 0;
-#endif
-#if defined(CONFIG_CMD_NET)
- char *s, *e;
- int i;
#endif
asm ("nop"); /* FIXME gd is not initialize - wait */
memset ((void *)gd, 0, CONFIG_SYS_GBL_DATA_SIZE);
# MA 02111-1307 USA
#
+CROSS_COMPILE ?= mb-
+
PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__
#include <common.h>
#include <command.h>
#include <malloc.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <timestamp.h>
#include <version.h>
#include <net.h>
#endif
/** leave this here (after malloc(), environment and PCI are working) **/
- /* Initialize devices */
- devices_init ();
+ /* Initialize stdio devices */
+ stdio_init ();
jumptable_init ();
# MA 02111-1307 USA
#
+CROSS_COMPILE ?= mips_4KC-
+
PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
#
*/
#include <common.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <watchdog.h>
#include <net.h>
#ifdef CONFIG_STATUS_LED
bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
WATCHDOG_RESET ();
- devices_init();
+ stdio_init();
jumptable_init();
console_init_r();
/*
# MA 02111-1307 USA
#
+CROSS_COMPILE ?= nios-elf-
+
PLATFORM_CPPFLAGS += -m32 -DCONFIG_NIOS -D__NIOS__ -ffixed-g7 -gstabs
*/
#include <common.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <watchdog.h>
#include <net.h>
#ifdef CONFIG_STATUS_LED
bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
WATCHDOG_RESET ();
- devices_init();
+ stdio_init();
jumptable_init();
console_init_r();
# MA 02111-1307 USA
#
+CROSS_COMPILE ?= nios2-elf-
+
PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__
PLATFORM_CPPFLAGS += -ffixed-r15 -G0
#include <watchdog.h>
#include <command.h>
#include <malloc.h>
-#include <devices.h>
+#include <stdio_dev.h>
#ifdef CONFIG_8xx
#include <mpc8xx.h>
#endif
#endif
/** leave this here (after malloc(), environment and PCI are working) **/
- /* Initialize devices */
- devices_init ();
+ /* Initialize stdio devices */
+ stdio_init ();
/* Initialize the jump table for applications */
jumptable_init ();
# MA 02111-1307 USA
#
+CROSS_COMPILE ?= ppc_8xx-
+
PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__
PLATFORM_LDFLAGS += -n
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
- * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved.
+ * Copyright Freescale Semiconductor, Inc. 2004, 2006.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <common.h>
#include <command.h>
#include <malloc.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <timestamp.h>
#include <version.h>
#include <watchdog.h>
sh_flash_init, /* Flash memory(NOR) init*/
INIT_FUNC_NAND_INIT/* Flash memory (NAND) init */
INIT_FUNC_PCI_INIT /* PCI init */
- devices_init,
+ stdio_init,
console_init_r,
interrupt_init,
#ifdef BOARD_LATE_INIT
# MA 02111-1307 USA
#
+CROSS_COMPILE ?= sh4-linux-
+
PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
PLATFORM_LDFLAGS += -e $(TEXT_BASE) --defsym reloc_dst=$(TEXT_BASE)
#include <common.h>
#include <command.h>
#include <malloc.h>
-#include <devices.h>
+#include <stdio_dev.h>
#include <config.h>
#if defined(CONFIG_CMD_IDE)
#include <ide.h>
pci_init();
#endif
- /* Initialize devices */
- devices_init();
+ /* Initialize stdio devices */
+ stdio_init();
/* Initialize the jump table for applications */
jumptable_init();
# MA 02111-1307 USA
#
+CROSS_COMPILE ?= sparc-elf-
+
PLATFORM_CPPFLAGS += -DCONFIG_SPARC -D__sparc__
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
- ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
+ ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
# from cpu directory
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
- ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
+ ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
# from cpu directory
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
- ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
+ ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
/*
- * (C) Copyright 2008
+ * (C) Copyright 2008-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
#include <asm/io.h>
#include <asm/processor.h>
+/*
+ * This code can configure those two Crucial SODIMM's:
+ *
+ * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
+ * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
+ *
+ */
+
+#define TEST_ADDR 0x10000000
+#define TEST_MAGIC 0x11223344
+
static void wait_init_complete(void)
{
u32 val;
} while (!(val & 0x80000000));
}
-phys_size_t initdram(int board_type)
+static void ddr_start(void)
+{
+ mtsdram(SDRAM_MCOPT2, 0x28000000);
+ wait_init_complete();
+}
+
+static void ddr_init_common(void)
{
/*
* Reset the DDR-SDRAM controller.
* enabled. This will only work for the same memory
* configuration as used here:
*
- * Crucial CT6464AC667.8FB - 512MB SO-DIMM
- *
*/
mtsdram(SDRAM_MCOPT2, 0x00000000);
- mtsdram(SDRAM_MCOPT1, 0x05122000);
mtsdram(SDRAM_MODT0, 0x01000000);
- mtsdram(SDRAM_CODT, 0x02800021);
mtsdram(SDRAM_WRDTR, 0x82000823);
mtsdram(SDRAM_CLKTR, 0x40000000);
mtsdram(SDRAM_MB0CF, 0x00000201);
- mtsdram(SDRAM_MB1CF, 0x00000201);
mtsdram(SDRAM_RTR, 0x06180000);
mtsdram(SDRAM_SDTR1, 0x80201000);
mtsdram(SDRAM_SDTR2, 0x42103243);
mtsdram(SDRAM_INITPLR13, 0x80810040);
mtsdram(SDRAM_INITPLR14, 0x00000000);
mtsdram(SDRAM_INITPLR15, 0x00000000);
-
- mtsdram(SDRAM_MCOPT2, 0x28000000);
-
- wait_init_complete();
+ mtsdram(SDRAM_RDCC, 0x40000000);
+ mtsdram(SDRAM_RQDC, 0x80000038);
+ mtsdram(SDRAM_RFDC, 0x00000257);
mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */
mtdcr(SDRAM_R1BAS, 0x0400F800); /* MQ0_B1BAS */
+}
- mtsdram(SDRAM_RDCC, 0x40000000);
- mtsdram(SDRAM_RQDC, 0x80000038);
- mtsdram(SDRAM_RFDC, 0x00000257);
+phys_size_t initdram(int board_type)
+{
+ /*
+ * First try init for this module:
+ *
+ * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
+ */
+
+ ddr_init_common();
+
+ /*
+ * Crucial CT6464AC667.8FB - 512MB SO-DIMM
+ */
+ mtdcr(SDRAM_R0BAS, 0x0000F800);
+ mtdcr(SDRAM_R1BAS, 0x0400F800);
+ mtsdram(SDRAM_MCOPT1, 0x05122000);
+ mtsdram(SDRAM_CODT, 0x02800021);
+ mtsdram(SDRAM_MB1CF, 0x00000201);
+
+ ddr_start();
+
+ /*
+ * Now test if the dual-ranked module is really installed
+ * by checking an address in the upper 256MByte region
+ */
+ out_be32((void *)TEST_ADDR, TEST_MAGIC);
+ if (in_be32((void *)TEST_ADDR) != TEST_MAGIC) {
+ /*
+ * The test failed, so we assume that the single
+ * ranked module is installed:
+ *
+ * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
+ */
+
+ ddr_init_common();
+
+ mtdcr(SDRAM_R0BAS, 0x0000F000);
+ mtsdram(SDRAM_MCOPT1, 0x05322000);
+ mtsdram(SDRAM_CODT, 0x00800021);
+
+ ddr_start();
+ }
return CONFIG_SYS_MBYTES_SDRAM << 20;
}
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
- ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
+ ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
- ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
+ ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
LIB = $(obj)libnet.a
-COBJS-y += net.o
-COBJS-y += tftp.o
COBJS-y += bootp.o
-COBJS-y += rarp.o
+COBJS-$(CONFIG_CMD_DNS) += dns.o
COBJS-y += eth.o
+COBJS-y += net.o
COBJS-y += nfs.o
+COBJS-y += rarp.o
COBJS-$(CONFIG_CMD_SNTP) += sntp.o
+COBJS-y += tftp.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
NetCopyIP(&tmp_ip, &bp->bp_siaddr);
if (tmp_ip != 0)
NetCopyIP(&NetServerIP, &bp->bp_siaddr);
- memcpy (NetServerEther, ((Ethernet_t *)NetRxPkt)->et_src, 6);
+ memcpy (NetServerEther, ((Ethernet_t *)NetRxPacket)->et_src, 6);
#endif
if (strlen(bp->bp_file) > 0)
copy_filename (BootFile, bp->bp_file, sizeof(BootFile));
--- /dev/null
+/*
+ * DNS support driver
+ *
+ * Copyright (c) 2008 Pieter Voorthuijsen <pieter.voorthuijsen@prodrive.nl>
+ * Copyright (c) 2009 Robin Getz <rgetz@blackfin.uclinux.org>
+ *
+ * This is a simple DNS implementation for U-Boot. It will use the first IP
+ * in the DNS response as NetServerIP. This can then be used for any other
+ * network related activities.
+ *
+ * The packet handling is partly based on TADNS, original copyrights
+ * follow below.
+ *
+ */
+
+/*
+ * Copyright (c) 2004-2005 Sergey Lyubka <valenok@gmail.com>
+ *
+ * "THE BEER-WARE LICENSE" (Revision 42):
+ * Sergey Lyubka wrote this file. As long as you retain this notice you
+ * can do whatever you want with this stuff. If we meet some day, and you think
+ * this stuff is worth it, you can buy me a beer in return.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+
+#include "dns.h"
+
+char *NetDNSResolve; /* The host to resolve */
+char *NetDNSenvvar; /* The envvar to store the answer in */
+
+static int DnsOurPort;
+
+static void
+DnsSend(void)
+{
+ struct header *header;
+ int n, name_len;
+ uchar *p, *pkt;
+ const char *s;
+ const char *name;
+ enum dns_query_type qtype = DNS_A_RECORD;
+
+ name = NetDNSResolve;
+ pkt = p = (uchar *)(NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE);
+
+ /* Prepare DNS packet header */
+ header = (struct header *) pkt;
+ header->tid = 1;
+ header->flags = htons(0x100); /* standard query */
+ header->nqueries = htons(1); /* Just one query */
+ header->nanswers = 0;
+ header->nauth = 0;
+ header->nother = 0;
+
+ /* Encode DNS name */
+ name_len = strlen(name);
+ p = (uchar *) &header->data; /* For encoding host name into packet */
+
+ do {
+ s = strchr(name, '.');
+ if (!s)
+ s = name + name_len;
+
+ n = s - name; /* Chunk length */
+ *p++ = n; /* Copy length */
+ memcpy(p, name, n); /* Copy chunk */
+ p += n;
+
+ if (*s == '.')
+ n++;
+
+ name += n;
+ name_len -= n;
+ } while (*s != '\0');
+
+ *p++ = 0; /* Mark end of host name */
+ *p++ = 0; /* Some servers require double null */
+ *p++ = (unsigned char) qtype; /* Query Type */
+
+ *p++ = 0;
+ *p++ = 1; /* Class: inet, 0x0001 */
+
+ n = p - pkt; /* Total packet length */
+ debug("Packet size %d\n", n);
+
+ DnsOurPort = random_port();
+
+ NetSendUDPPacket(NetServerEther, NetOurDNSIP, DNS_SERVICE_PORT,
+ DnsOurPort, n);
+ debug("DNS packet sent\n");
+}
+
+static void
+DnsTimeout(void)
+{
+ puts("Timeout\n");
+ NetState = NETLOOP_FAIL;
+}
+
+static void
+DnsHandler(uchar *pkt, unsigned dest, unsigned src, unsigned len)
+{
+ struct header *header;
+ const unsigned char *p, *e, *s;
+ u16 type, i;
+ int found, stop, dlen;
+ char IPStr[22];
+ IPaddr_t IPAddress;
+ short tmp;
+
+
+ debug("%s\n", __func__);
+ if (dest != DnsOurPort)
+ return;
+
+ for (i = 0; i < len; i += 4)
+ debug("0x%p - 0x%.2x 0x%.2x 0x%.2x 0x%.2x\n",
+ pkt+i, pkt[i], pkt[i+1], pkt[i+2], pkt[i+3]);
+
+ /* We sent 1 query. We want to see more that 1 answer. */
+ header = (struct header *) pkt;
+ if (ntohs(header->nqueries) != 1)
+ return;
+
+ /* Received 0 answers */
+ if (header->nanswers == 0) {
+ puts("DNS server returned no answers\n");
+ NetState = NETLOOP_SUCCESS;
+ return;
+ }
+
+ /* Skip host name */
+ s = &header->data[0];
+ e = pkt + len;
+ for (p = s; p < e && *p != '\0'; p++)
+ continue;
+
+ /* We sent query class 1, query type 1 */
+ tmp = p[1] | (p[2] << 8);
+ if (&p[5] > e || ntohs(tmp) != DNS_A_RECORD) {
+ puts("DNS response was not A record\n");
+ NetState = NETLOOP_SUCCESS;
+ return;
+ }
+
+ /* Go to the first answer section */
+ p += 5;
+
+ /* Loop through the answers, we want A type answer */
+ for (found = stop = 0; !stop && &p[12] < e; ) {
+
+ /* Skip possible name in CNAME answer */
+ if (*p != 0xc0) {
+ while (*p && &p[12] < e)
+ p++;
+ p--;
+ }
+ debug("Name (Offset in header): %d\n", p[1]);
+
+ tmp = p[2] | (p[3] << 8);
+ type = ntohs(tmp);
+ debug("type = %d\n", type);
+ if (type == DNS_CNAME_RECORD) {
+ /* CNAME answer. shift to the next section */
+ debug("Found canonical name\n");
+ tmp = p[10] | (p[11] << 8);
+ dlen = ntohs(tmp);
+ debug("dlen = %d\n", dlen);
+ p += 12 + dlen;
+ } else if (type == DNS_A_RECORD) {
+ debug("Found A-record\n");
+ found = stop = 1;
+ } else {
+ debug("Unknown type\n");
+ stop = 1;
+ }
+ }
+
+ if (found && &p[12] < e) {
+
+ tmp = p[10] | (p[11] << 8);
+ dlen = ntohs(tmp);
+ p += 12;
+ memcpy(&IPAddress, p, 4);
+
+ if (p + dlen <= e) {
+ ip_to_string(IPAddress, IPStr);
+ printf("%s\n", IPStr);
+ if (NetDNSenvvar)
+ setenv(NetDNSenvvar, IPStr);
+ } else
+ puts("server responded with invalid IP number\n");
+ }
+
+ NetState = NETLOOP_SUCCESS;
+}
+
+void
+DnsStart(void)
+{
+ debug("%s\n", __func__);
+
+ NetSetTimeout(DNS_TIMEOUT, DnsTimeout);
+ NetSetHandler(DnsHandler);
+
+ DnsSend();
+}
--- /dev/null
+/*
+ * (C) Masami Komiya <mkomiya@sonare.it> 2005
+ * Copyright 2009, Robin Getz <rgetz@blackfin.uclinux.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#ifndef __DNS_H__
+#define __DNS_H__
+
+#define DNS_SERVICE_PORT 53
+#define DNS_TIMEOUT 10000UL
+
+/* http://en.wikipedia.org/wiki/List_of_DNS_record_types */
+enum dns_query_type {
+ DNS_A_RECORD = 0x01,
+ DNS_CNAME_RECORD = 0x05,
+ DNS_MX_RECORD = 0x0f,
+};
+
+/*
+ * DNS network packet
+ */
+struct header {
+ uint16_t tid; /* Transaction ID */
+ uint16_t flags; /* Flags */
+ uint16_t nqueries; /* Questions */
+ uint16_t nanswers; /* Answers */
+ uint16_t nauth; /* Authority PRs */
+ uint16_t nother; /* Other PRs */
+ unsigned char data[1]; /* Data, variable length */
+};
+
+extern void DnsStart(void); /* Begin DNS */
+
+#endif
}
#elif defined(CONFIG_CMD_NET) && !defined(CONFIG_NET_MULTI)
+#warning Ethernet driver is deprecated. Please update to use CONFIG_NET_MULTI
+
extern int at91rm9200_miiphy_initialize(bd_t *bis);
extern int mcf52x2_miiphy_initialize(bd_t *bis);
extern int ns7520_miiphy_initialize(bd_t *bis);
#if defined(CONFIG_CDP_VERSION)
#include <timestamp.h>
#endif
+#if defined(CONFIG_CMD_DNS)
+#include "dns.h"
+#endif
#if defined(CONFIG_CMD_NET)
{ 0, 0, 0, 0, 0, 0 };
IPaddr_t NetOurIP; /* Our IP addr (0 = unknown) */
IPaddr_t NetServerIP; /* Server IP addr (0 = unknown) */
-volatile uchar *NetRxPkt; /* Current receive packet */
-int NetRxPktLen; /* Current rx packet length */
+volatile uchar *NetRxPacket; /* Current receive packet */
+int NetRxPacketLen; /* Current rx packet length */
unsigned NetIPID; /* IP packet ID */
uchar NetBcastAddr[6] = /* Ethernet bcast address */
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
NetServerIP = getenv_IPaddr ("serverip");
NetOurNativeVLAN = getenv_VLAN("nvlan");
NetOurVLAN = getenv_VLAN("vlan");
+#if defined(CONFIG_CMD_DNS)
+ NetOurDNSIP = getenv_IPaddr("dnsip");
+#endif
env_changed_id = env_id;
}
#if defined(CONFIG_CMD_DHCP)
case DHCP:
BootpTry = 0;
+ NetOurIP = 0;
DhcpRequest(); /* Basically same as BOOTP */
break;
#endif
case BOOTP:
BootpTry = 0;
+ NetOurIP = 0;
BootpRequest ();
break;
case RARP:
RarpTry = 0;
+ NetOurIP = 0;
RarpRequest ();
break;
#if defined(CONFIG_CMD_PING)
case SNTP:
SntpStart();
break;
+#endif
+#if defined(CONFIG_CMD_DNS)
+ case DNS:
+ DnsStart();
+ break;
#endif
default:
break;
printf("packet received\n");
#endif
- NetRxPkt = inpkt;
- NetRxPktLen = len;
+ NetRxPacket = inpkt;
+ NetRxPacketLen = len;
et = (Ethernet_t *)inpkt;
/* too small packet? */
/* are we waiting for a reply */
if (!NetArpWaitPacketIP || !NetArpWaitPacketMAC)
break;
+
+#ifdef CONFIG_KEEP_SERVERADDR
+ if (NetServerIP == NetArpWaitPacketIP) {
+ char buf[20];
+ sprintf(buf, "%pM", arp->ar_data);
+ setenv("serveraddr", buf);
+ }
+#endif
+
#ifdef ET_DEBUG
printf("Got ARP REPLY, set server/gtwy eth addr (%pM)\n",
arp->ar_data);
}
goto common;
#endif
+#if defined(CONFIG_CMD_DNS)
+ case DNS:
+ if (NetOurDNSIP == 0) {
+ puts("*** ERROR: DNS server address not given\n");
+ return 1;
+ }
+ goto common;
+#endif
#if defined(CONFIG_CMD_NFS)
case NFS:
#endif
#endif
+#if defined(CONFIG_CMD_NFS) || defined(CONFIG_CMD_SNTP) || defined(CONFIG_CMD_DNS)
+/*
+ * make port a little random, but use something trivial to compute
+ */
+unsigned int random_port(void)
+{
+ return 1024 + (get_timer(0) % 0x8000);;
+}
+#endif
+
void ip_to_string (IPaddr_t x, char *s)
{
x = ntohl (x);
int fpu_status(void)
{
- if (mfspr(ccr0) & CCR0_DAPUIB)
+ if (mfspr(SPRN_CCR0) & CCR0_DAPUIB)
return 0; /* Disabled */
else
return 1; /* Enabled */
void fpu_disable(void)
{
- mtspr(ccr0, mfspr(ccr0) | CCR0_DAPUIB);
+ mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) | CCR0_DAPUIB);
mtmsr(mfmsr() & ~MSR_FP);
}
void fpu_enable(void)
{
- mtspr(ccr0, mfspr(ccr0) & ~CCR0_DAPUIB);
+ mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) & ~CCR0_DAPUIB);
mtmsr(mfmsr() | MSR_FP);
}
*/
#include <common.h>
-#include <console.h>
+#include <stdio_dev.h>
#include <watchdog.h>
#include <post.h>
@rm -f $@
@for f in $(SRCS); do \
g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \
- $(CC) -M $(HOST_CFLAGS) $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \
+ $(CC) -M $(HOSTCFLAGS) $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \
done
#########################################################################
# -multiply_defined suppress option to turn off this error.
#
-HOST_CFLAGS = -Wall
+HOSTCFLAGS = -Wall
HOST_LDFLAGS =
ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc)
-HOST_CFLAGS += -traditional-cpp
+HOSTCFLAGS += -traditional-cpp
HOST_LDFLAGS += -multiply_defined suppress
else
-HOST_CFLAGS += -pedantic
+HOSTCFLAGS += -pedantic
endif
ifeq ($(HOSTOS),cygwin)
-HOST_CFLAGS += -ansi
+HOSTCFLAGS += -ansi
endif
#
BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX)
BIN_FILES-y += mkimage$(SFX)
BIN_FILES-$(CONFIG_ENV_IS_EMBEDDED) += envcrc$(SFX)
+BIN_FILES-$(CONFIG_ENV_IS_IN_DATAFLASH) += envcrc$(SFX)
BIN_FILES-$(CONFIG_ENV_IS_IN_EEPROM) += envcrc$(SFX)
BIN_FILES-$(CONFIG_ENV_IS_IN_FLASH) += envcrc$(SFX)
+BIN_FILES-$(CONFIG_ENV_IS_IN_ONENAND) += envcrc$(SFX)
+BIN_FILES-$(CONFIG_ENV_IS_IN_NAND) += envcrc$(SFX)
BIN_FILES-$(CONFIG_ENV_IS_IN_NVRAM) += envcrc$(SFX)
+BIN_FILES-$(CONFIG_ENV_IS_IN_SPI_FLASH) += envcrc$(SFX)
BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
BIN_FILES-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX)
BIN_FILES-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX)
-I $(SRCTREE)/tools \
-DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC \
-D__KERNEL_STRICT_NAMES
-CFLAGS = $(HOST_CFLAGS) $(CPPFLAGS) -O
+CFLAGS = $(HOSTCFLAGS) $(CPPFLAGS) -O
# No -pedantic switch to avoid libfdt compilation warnings
FIT_CFLAGS = -Wall $(CPPFLAGS) -O
$(MAKE) \
HOSTOS=$(HOSTOS) \
HOSTARCH=$(HOSTARCH) \
- HOST_CFLAGS="$(HOST_CFLAGS)" \
+ HOSTCFLAGS="$(HOSTCFLAGS)" \
HOST_LDFLAGS="$(HOST_LDFLAGS)" \
-C $$dir || exit 1 ; \
done
-#include <stdio.h>
-#include <stdlib.h>
-
-#if defined(__linux__)
-#include <stdint.h>
-#else
-#ifdef __CYGWIN__
-#include "elf.h"
-#else
-#include <inttypes.h>
-#endif
-#endif
+#include "compiler.h"
typedef struct bitmap_s { /* bitmap description */
uint16_t width;
# Use native tools and options
#
CPPFLAGS = -I$(BFD_ROOT_DIR)/include
-CFLAGS = $(HOST_CFLAGS) -O $(CPPFLAGS)
+CFLAGS = $(HOSTCFLAGS) -O $(CPPFLAGS)
CC = $(HOSTCC)
MAKEDEPEND = makedepend
| INCLUDES
|*************************************************************************/
+#include "os_support.h"
#include <stddef.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <errno.h>
-extern int errno;
-
/*************************************************************************
| DEFINES
|*************************************************************************/
include $(TOPDIR)/config.mk
-HOST_CFLAGS = -Wall -pedantic
+HOSTCFLAGS = -Wall -pedantic
# Generated executable files
BIN_FILES-y += imls
-I $(SRCTREE)/libfdt \
-I $(SRCTREE)/tools \
-DUSE_HOSTCC -D__KERNEL_STRICT_NAMES
-CFLAGS = $(HOST_CFLAGS) $(CPPFLAGS) -O
+CFLAGS = $(HOSTCFLAGS) $(CPPFLAGS) -O
# No -pedantic switch to avoid libfdt compilation warnings
FIT_CFLAGS = -Wall $(CPPFLAGS) -O
#define MAP_SHARED 0x01 /* Share changes */
#define MAP_PRIVATE 0x02 /* Changes are private */
-/* Return value of `mmap' in case of an error */
-#define MAP_FAILED ((void *) -1)
-
/* Windows 64-bit access macros */
#define LODWORD(x) ((DWORD)((DWORDLONG)(x)))
#define HIDWORD(x) ((DWORD)(((DWORDLONG)(x) >> 32) & 0xffffffff))
#include "mkimage.h"
#include <image.h>
-extern int errno;
-
-#ifndef MAP_FAILED
-#define MAP_FAILED (void *)(-1)
-#endif
-
extern unsigned long crc32 (unsigned long crc, const char *buf, unsigned int len);
static void copy_file (int, const char *, int);
static void usage (void);
*/
memcpy (hdr, ptr, sizeof(image_header_t));
- if (ntohl(hdr->ih_magic) != IH_MAGIC) {
+ if (be32_to_cpu(hdr->ih_magic) != IH_MAGIC) {
fprintf (stderr,
"%s: Bad Magic Number: \"%s\" is no valid image\n",
cmdname, imagefile);
data = (char *)hdr;
len = sizeof(image_header_t);
- checksum = ntohl(hdr->ih_hcrc);
- hdr->ih_hcrc = htonl(0); /* clear for re-calculation */
+ checksum = be32_to_cpu(hdr->ih_hcrc);
+ hdr->ih_hcrc = cpu_to_be32(0); /* clear for re-calculation */
if (crc32 (0, data, len) != checksum) {
fprintf (stderr,
data = ptr + sizeof(image_header_t);
len = image_size - sizeof(image_header_t) ;
- if (crc32 (0, data, len) != ntohl(hdr->ih_dcrc)) {
+ if (crc32 (0, data, len) != be32_to_cpu(hdr->ih_dcrc)) {
fprintf (stderr,
"%s: ERROR: \"%s\" has corrupted data!\n",
cmdname, imagefile);
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
-#ifndef __WIN32__
-#include <netinet/in.h> /* for host / network byte order conversions */
-#endif
-#ifdef __MINGW32__
-#include <stdint.h>
-#else
-#include <sys/mman.h>
-#endif
#include <sys/stat.h>
#include <time.h>
#include <unistd.h>
#define MKIMAGE_DEFAULT_DTC_OPTIONS "-I dts -O dtb -p 500"
#define MKIMAGE_MAX_DTC_CMDLINE_LEN 512
#define MKIMAGE_DTC "dtc" /* assume dtc is in $PATH */
-
-#if defined(__BEOS__) || defined(__NetBSD__) || defined(__APPLE__)
-#include <inttypes.h>
-#endif
-
-#ifdef __WIN32__
-typedef unsigned int __u32;
-
-#define SWAP_LONG(x) \
- ((__u32)( \
- (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \
- (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \
- (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \
- (((__u32)(x) & (__u32)0xff000000UL) >> 24) ))
-typedef unsigned char uint8_t;
-typedef unsigned short uint16_t;
-typedef unsigned int uint32_t;
-
-#define ntohl(a) SWAP_LONG(a)
-#define htonl(a) SWAP_LONG(a)
-#endif /* __WIN32__ */
-
-#ifndef O_BINARY /* should be define'd on __WIN32__ */
-#define O_BINARY 0
-#endif
/*
* Include additional files required for supporting different operating systems
*/
+#include "compiler.h"
#ifdef __MINGW32__
#include "mingw_support.c"
#endif
#ifndef __OS_SUPPORT_H_
#define __OS_SUPPORT_H_
+#include "compiler.h"
+
/*
* Include additional files required for supporting different operating systems
*/
#include <fcntl.h>
#include <errno.h>
#include <string.h>
-#ifndef __MINGW32__
-#include <sys/mman.h>
-#endif
#include <sys/stat.h>
#include "sha1.h"
#include <config.h>
#undef __ASSEMBLY__
-#ifndef O_BINARY /* should be define'd on __WIN32__ */
-#define O_BINARY 0
-#endif
-
-#ifndef MAP_FAILED
-#define MAP_FAILED (-1)
-#endif
-
-extern int errno;
-
extern void sha1_csum (unsigned char *input, int ilen, unsigned char output[20]);
int main (int argc, char **argv)
projects / karo-tx-uboot.git / commitdiff