Merge git://www.denx.de/git/u-boot-sunxi

diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index 22561231cb8d2d1f18cf39e69d042e7d45b65582..e5a0e21e3696782bdd46f06015d67fe6561862dd 100644 (file)
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -451,6 +451,9 @@ cpu_init_f (void)
 #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
 
        gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+       /* Clear initial global data */
+       memset((void *)gd, 0, sizeof(gd_t));
 }
 
 /*

diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 451c33e1a199ad7ce98ee82b0140116c1e8b5d03..4bf493ed4532688bd5c8f40cd80e04b1cea4bc4e 100644 (file)
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -2,9 +2,9 @@
  * sh_eth.c - Driver for Renesas ethernet controler.
  *
  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
- * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
+ * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
- * Copyright (C) 2013  Renesas Electronics Corporation
+ * Copyright (C) 2013, 2014 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -83,6 +83,8 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len)
        else
                port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
 
+       flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
+
        /* Restart the transmitter if disabled */
        if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
                sh_eth_write(eth, EDTRR_TRNS, EDTRR);
@@ -133,6 +135,10 @@ int sh_eth_recv(struct eth_device *dev)
                        port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
                else
                        port_info->rx_desc_cur->rd0 = RD_RACT;
+
+               flush_cache_wback(port_info->rx_desc_cur,
+                                 sizeof(struct rx_desc_s));
+
                /* Point to the next descriptor */
                port_info->rx_desc_cur++;
                if (port_info->rx_desc_cur >=
@@ -181,27 +187,27 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 {
        int port = eth->port, i, ret = 0;
-       u32 tmp_addr;
+       u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
        struct sh_eth_info *port_info = &eth->port_info[port];
        struct tx_desc_s *cur_tx_desc;
 
        /*
-        * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
+        * Allocate rx descriptors. They must be aligned to size of struct
+        * tx_desc_s.
         */
-       port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
-                                                sizeof(struct tx_desc_s) +
-                                                TX_DESC_SIZE - 1);
-       if (!port_info->tx_desc_malloc) {
-               printf(SHETHER_NAME ": malloc failed\n");
+       port_info->tx_desc_alloc =
+               memalign(sizeof(struct tx_desc_s), alloc_desc_size);
+       if (!port_info->tx_desc_alloc) {
+               printf(SHETHER_NAME ": memalign failed\n");
                ret = -ENOMEM;
                goto err;
        }
 
-       tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
-                         ~(TX_DESC_SIZE - 1));
-       flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
+       flush_cache_wback((u32)port_info->tx_desc_alloc, alloc_desc_size);
+
        /* Make sure we use a P2 address (non-cacheable) */
-       port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
+       port_info->tx_desc_base =
+               (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
        port_info->tx_desc_cur = port_info->tx_desc_base;
 
        /* Initialize all descriptors */
@@ -232,47 +238,44 @@ err:
 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 {
        int port = eth->port, i , ret = 0;
+       u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
        struct sh_eth_info *port_info = &eth->port_info[port];
        struct rx_desc_s *cur_rx_desc;
-       u32 tmp_addr;
        u8 *rx_buf;
 
        /*
-        * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
+        * Allocate rx descriptors. They must be aligned to size of struct
+        * rx_desc_s.
         */
-       port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
-                                                sizeof(struct rx_desc_s) +
-                                                RX_DESC_SIZE - 1);
-       if (!port_info->rx_desc_malloc) {
-               printf(SHETHER_NAME ": malloc failed\n");
+       port_info->rx_desc_alloc =
+               memalign(sizeof(struct rx_desc_s), alloc_desc_size);
+       if (!port_info->rx_desc_alloc) {
+               printf(SHETHER_NAME ": memalign failed\n");
                ret = -ENOMEM;
                goto err;
        }
 
-       tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
-                         ~(RX_DESC_SIZE - 1));
-       flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
+       flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
+
        /* Make sure we use a P2 address (non-cacheable) */
-       port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
+       port_info->rx_desc_base =
+               (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
 
        port_info->rx_desc_cur = port_info->rx_desc_base;
 
        /*
-        * Allocate rx data buffers. They must be 32 bytes aligned  and in
-        * P2 area
+        * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
+        * aligned and in P2 area.
         */
-       port_info->rx_buf_malloc = malloc(
-               NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1);
-       if (!port_info->rx_buf_malloc) {
-               printf(SHETHER_NAME ": malloc failed\n");
+       port_info->rx_buf_alloc =
+               memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
+       if (!port_info->rx_buf_alloc) {
+               printf(SHETHER_NAME ": alloc failed\n");
                ret = -ENOMEM;
-               goto err_buf_malloc;
+               goto err_buf_alloc;
        }
 
-       tmp_addr = (u32)(((int)port_info->rx_buf_malloc
-                         + (RX_BUF_ALIGNE_SIZE - 1)) &
-                         ~(RX_BUF_ALIGNE_SIZE - 1));
-       port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
+       port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
 
        /* Initialize all descriptors */
        for (cur_rx_desc = port_info->rx_desc_base,
@@ -297,9 +300,9 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 
        return ret;
 
-err_buf_malloc:
-       free(port_info->rx_desc_malloc);
-       port_info->rx_desc_malloc = NULL;
+err_buf_alloc:
+       free(port_info->rx_desc_alloc);
+       port_info->rx_desc_alloc = NULL;
 
 err:
        return ret;
@@ -310,9 +313,9 @@ static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
        int port = eth->port;
        struct sh_eth_info *port_info = &eth->port_info[port];
 
-       if (port_info->tx_desc_malloc) {
-               free(port_info->tx_desc_malloc);
-               port_info->tx_desc_malloc = NULL;
+       if (port_info->tx_desc_alloc) {
+               free(port_info->tx_desc_alloc);
+               port_info->tx_desc_alloc = NULL;
        }
 }
 
@@ -321,14 +324,14 @@ static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
        int port = eth->port;
        struct sh_eth_info *port_info = &eth->port_info[port];
 
-       if (port_info->rx_desc_malloc) {
-               free(port_info->rx_desc_malloc);
-               port_info->rx_desc_malloc = NULL;
+       if (port_info->rx_desc_alloc) {
+               free(port_info->rx_desc_alloc);
+               port_info->rx_desc_alloc = NULL;
        }
 
-       if (port_info->rx_buf_malloc) {
-               free(port_info->rx_buf_malloc);
-               port_info->rx_buf_malloc = NULL;
+       if (port_info->rx_buf_alloc) {
+               free(port_info->rx_buf_alloc);
+               port_info->rx_buf_alloc = NULL;
        }
 }
 
@@ -414,7 +417,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
        sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
-       defined(CONFIG_R8A7794)
+       defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
        sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
 #endif
        /* Configure phy */
@@ -440,7 +443,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
                sh_eth_write(eth, 1, RTRATE);
 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
-               defined(CONFIG_R8A7791) || defined(CONFIG_R8A7794)
+               defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
+               defined(CONFIG_R8A7794)
                val = ECMR_RTM;
 #endif
        } else if (phy->speed == 10) {

diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index e325a39aac04fdecf919cdf8918a40776de2d874..5cb520c63ec76c4d95bf5954cfc606868c9e0244 100644 (file)
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -51,8 +51,6 @@
 /* The size of the tx descriptor is determined by how much padding is used.
    4, 20, or 52 bytes of padding can be used */
 #define TX_DESC_PADDING        (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
-/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
-#define TX_DESC_SIZE   (12 + TX_DESC_PADDING)
 
 /* Tx descriptor. We always use 3 bytes of padding */
 struct tx_desc_s {
@@ -68,8 +66,6 @@ struct tx_desc_s {
 /* The size of the rx descriptor is determined by how much padding is used.
    4, 20, or 52 bytes of padding can be used */
 #define RX_DESC_PADDING        (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
-/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
-#define RX_DESC_SIZE           (12 + RX_DESC_PADDING)
 /* aligned cache line size */
 #define RX_BUF_ALIGNE_SIZE     (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
 
@@ -82,13 +78,13 @@ struct rx_desc_s {
 };
 
 struct sh_eth_info {
-       struct tx_desc_s *tx_desc_malloc;
+       struct tx_desc_s *tx_desc_alloc;
        struct tx_desc_s *tx_desc_base;
        struct tx_desc_s *tx_desc_cur;
-       struct rx_desc_s *rx_desc_malloc;
+       struct rx_desc_s *rx_desc_alloc;
        struct rx_desc_s *rx_desc_base;
        struct rx_desc_s *rx_desc_cur;
-       u8 *rx_buf_malloc;
+       u8 *rx_buf_alloc;
        u8 *rx_buf_base;
        u8 mac_addr[6];
        u8 phy_addr;
@@ -359,7 +355,7 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 #define SH_ETH_TYPE_GETHER
 #define BASE_IO_ADDR   0xE9A00000
 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
-       defined(CONFIG_R8A7794)
+       defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 #define SH_ETH_TYPE_ETHER
 #define BASE_IO_ADDR   0xEE700200
 #elif defined(CONFIG_R7S72100)
@@ -571,7 +567,7 @@ enum FELIC_MODE_BIT {
 #ifdef CONFIG_CPU_SH7724
        ECMR_RTM = 0x00000010,
 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
-       defined(CONFIG_R8A7794)
+       defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
        ECMR_RTM = 0x00000004,
 #endif
 

diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index fe8cde4dedb5ffe3ea9c33779841038cbc9e90d6..53406e585548e5699c1e850edcc67f048bde30aa 100644 (file)
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -227,7 +227,7 @@ struct uart_port {
 # define SCIF_ORER 0x0001              /* Overrun error bit */
 # define SCSCR_INIT(port)      0x38    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
-       defined(CONFIG_R8A7794)
+       defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 # define SCIF_ORER     0x0001
 # define SCSCR_INIT(port)      0x32    /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
 #else
@@ -304,7 +304,8 @@ struct uart_port {
 /* SH7763 SCIF2 support */
 # define SCIF2_RFDC_MASK 0x001f
 # define SCIF2_TXROOM_MAX 16
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+       defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 # define SCIF_RFDC_MASK        0x003f
 #else
@@ -589,7 +590,7 @@ SCIF_FNS(SCSPTR,                        0,  0, 0, 0)
 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 #endif
 #if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
-       defined(CONFIG_R8A7794)
+       defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 SCIF_FNS(DL,                           0,  0, 0x30, 16)
 SCIF_FNS(CKS,                          0,  0, 0x34, 16)
 #endif
@@ -734,7 +735,8 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk)
 #define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
 #elif defined(__H8300H__) || defined(__H8300S__)
 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+       defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */
 #else /* Generic SH */