(i.e. setenv videomode 317; saveenv; reset;)
- "videomode=bootargs" all the video parameters are parsed
- from the bootargs. (See drivers/videomodes.c)
+ from the bootargs. (See drivers/video/videomodes.c)
CONFIG_VIDEO_SED13806
CONFIG_FSL_I2C
Define this option if you want to use Freescale's I2C driver in
- drivers/fsl_i2c.c.
+ drivers/i2c/fsl_i2c.c.
- SPI Support: CONFIG_SPI
};
/*-------------------------------------------------------------------------+
- | pci_init_board (Called from pci_init() in drivers/pci.c)
+ | pci_init_board (Called from pci_init() in drivers/pci/pci.c)
|
| Init the PCI part of the SolidCard III
|
* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* !!!!! !!!!!
* !!!!! Next type definition was coming from original !!!!!
- * !!!!! status LED driver drivers/status_led.c and !!!!!
- * !!!!! should exported for using here. !!!!!
+ * !!!!! status LED driver drivers/misc/status_led.c !!!!!
+ * !!!!! and should be exported for using it here. !!!!!
* !!!!! !!!!!
* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
+
extern int usb_cpu_init(void);
#ifdef CONFIG_PS2MULT
#include <command.h>
#include <miiphy.h>
-#ifdef CONFIG_TERSE_MII
-/*
- * Display values from last command.
- */
-uint last_op;
-uint last_addr;
-uint last_data;
-uint last_reg;
-
-/*
- * MII device/info/read/write
- *
- * Syntax:
- * mii device {devname}
- * mii info {addr}
- * mii read {addr} {reg}
- * mii write {addr} {reg} {data}
- */
-int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- char op;
- unsigned char addr, reg;
- unsigned short data;
- int rcode = 0;
- char *devname;
-
- if (argc < 2) {
- printf ("Usage:\n%s\n", cmdtp->usage);
- return 1;
- }
-
-#if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2)
- mii_init ();
-#endif
-
- /*
- * We use the last specified parameters, unless new ones are
- * entered.
- */
- op = last_op;
- addr = last_addr;
- data = last_data;
- reg = last_reg;
-
- if ((flag & CMD_FLAG_REPEAT) == 0) {
- op = argv[1][0];
- if (argc >= 3)
- addr = simple_strtoul (argv[2], NULL, 16);
- if (argc >= 4)
- reg = simple_strtoul (argv[3], NULL, 16);
- if (argc >= 5)
- data = simple_strtoul (argv[4], NULL, 16);
- }
-
- /* use current device */
- devname = miiphy_get_current_dev();
-
- /*
- * check device/read/write/list.
- */
- if (op == 'i') {
- unsigned char j, start, end;
- unsigned int oui;
- unsigned char model;
- unsigned char rev;
-
- /*
- * Look for any and all PHYs. Valid addresses are 0..31.
- */
- if (argc >= 3) {
- start = addr; end = addr + 1;
- } else {
- start = 0; end = 31;
- }
-
- for (j = start; j < end; j++) {
- if (miiphy_info (devname, j, &oui, &model, &rev) == 0) {
- printf ("PHY 0x%02X: "
- "OUI = 0x%04X, "
- "Model = 0x%02X, "
- "Rev = 0x%02X, "
- "%3dbase%s, %s\n",
- j, oui, model, rev,
- miiphy_speed (devname, j),
- miiphy_is_1000base_x (devname, j)
- ? "X" : "T",
- (miiphy_duplex (devname, j) == FULL)
- ? "FDX" : "HDX");
- }
- }
- } else if (op == 'r') {
- if (miiphy_read (devname, addr, reg, &data) != 0) {
- puts ("Error reading from the PHY\n");
- rcode = 1;
- } else {
- printf ("%04X\n", data & 0x0000FFFF);
- }
- } else if (op == 'w') {
- if (miiphy_write (devname, addr, reg, data) != 0) {
- puts ("Error writing to the PHY\n");
- rcode = 1;
- }
- } else if (op == 'd') {
- if (argc == 2)
- miiphy_listdev ();
- else
- miiphy_set_current_dev (argv[2]);
- } else {
- printf ("Usage:\n%s\n", cmdtp->usage);
- return 1;
- }
-
- /*
- * Save the parameters for repeats.
- */
- last_op = op;
- last_addr = addr;
- last_data = data;
- last_reg = reg;
-
- return rcode;
-}
-
-/***************************************************/
-
-U_BOOT_CMD(
- mii, 5, 1, do_mii,
- "mii - MII utility commands\n",
- "device - list available devices\n"
- "mii device <devname> - set current device\n"
- "mii info <addr> - display MII PHY info\n"
- "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
- "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
-);
-
-#else /* ! CONFIG_TERSE_MII ================================================= */
-
typedef struct _MII_reg_desc_t {
ushort regno;
char * name;
int rcode = 0;
char *devname;
+ if (argc < 2) {
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
#if defined(CONFIG_8xx) || defined(CONFIG_MCF532x)
mii_init ();
#endif
"mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
"Addr and/or reg may be ranges, e.g. 2-7.\n"
);
-
-#endif /* CONFIG_TERSE_MII */
size_t start, size_t len,
size_t * retlen, u_char * buf);
-/* info for NAND chips, defined in drivers/nand/nand.c */
+/* info for NAND chips, defined in drivers/mtd/nand/nand.c */
extern nand_info_t nand_info[];
/* references to names in env_common.c */
static unsigned char num_lock = 0;
static unsigned char caps_lock = 0;
static unsigned char scroll_lock = 0;
+static unsigned char ctrl = 0;
static unsigned char leds __attribute__ ((aligned (0x4)));
/* test if a character is in the queue */
static int usb_kbd_testc(void)
{
+#ifdef CFG_USB_EVENT_POLL
+ usb_event_poll();
+#endif
if(usb_in_pointer==usb_out_pointer)
return(0); /* no data */
else
else /* non shifted */
keycode=usb_kbd_numkey[scancode-0x1e];
}
+
+ if (ctrl)
+ keycode = scancode - 0x3;
+
if(pressed==1) {
if(scancode==NUM_LOCK) {
num_lock=~num_lock;
return 1;
}
res=0;
+
+ switch (new[0]) {
+ case 0x0: /* No combo key pressed */
+ ctrl = 0;
+ break;
+ case 0x01: /* Left Ctrl pressed */
+ case 0x10: /* Right Ctrl pressed */
+ ctrl = 1;
+ break;
+ }
+
for (i = 2; i < 8; i++) {
if (old[i] > 3 && memscan(&new[2], old[i], 6) == &new[8]) {
res|=usb_kbd_translate(old[i],new[0],0);
}
/*
- * drivers/pci.c skips every host bridge but the 405GP since it could
+ * drivers/pci/pci.c skips every host bridge but the 405GP since it could
* be set as an Adapter.
*
* I (Andrew May) don't know what we should do here, but I don't want
* Startup Code (reset vector)
*
* do important init only if we don't start from RAM!
- * - relocate armboot to ram
+ * - relocate armboot to RAM
* - setup stack
* - jump to second stage
*/
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
-#endif
+#endif /* CONFIG_USE_IRQ */
/****************************************************************************/
/****************************************************************************/
reset:
- mrs r0,cpsr /* set the cpu to SVC32 mode */
+ mrs r0,cpsr /* set the CPU to SVC32 mode */
bic r0,r0,#0x1f /* (superviser mode, M=10011) */
orr r0,r0,#0x13
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
- * not when booting from ram!
+ * not when booting from RAM!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit /* we do sys-critical inits */
-#endif
+#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end addreee [r2] */
ble copy_loop
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
+#endif /* !CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
stack_setup:
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
+#endif /* CONFIG_USE_IRQ */
sub sp, r0, #12 /* leave 3 words for abort-stack */
clear_bss:
#undef OSCR
#undef OWER
#undef OIER
-#endif
+#endif /* CONFIG_PXA250 || CONFIG_CPU_MONAHANS */
#ifdef CONFIG_PXA250
#undef RCSR
#undef CCCR
-#endif
+#endif /* CONFIG_PXA250 */
/* Interrupt-Controller base address */
IC_BASE: .word 0x40d00000
#ifdef CONFIG_CPU_MONAHANS
# ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO
# error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!"
-# endif
+# endif /* !CFG_MONAHANS_RUN_MODE_OSC_RATIO */
# ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO
# define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
-# endif
-#else /* ! CONFIG_CPU_MONAHANS */
+# endif /* !CFG_MONAHANS_TURBO_RUN_MODE_RATIO */
+#else /* !CONFIG_CPU_MONAHANS */
#ifdef CFG_CPUSPEED
CC_BASE: .word 0x41300000
#define CCCR 0x00
cpuspeed: .word CFG_CPUSPEED
-#else
+#else /* !CFG_CPUSPEED */
#error "You have to define CFG_CPUSPEED!!"
-#endif
+#endif /* CFG_CPUSPEED */
#endif /* CONFIG_CPU_MONAHANS */
/* takes care the CP15 update has taken place */
ldr r0, IC_BASE
mov r1, #0x00
str r1, [r0, #ICMR]
-#else
+#else /* CONFIG_CPU_MONAHANS */
/* Step 1 - Enable CP6 permission */
mrc p15, 0, r1, c15, c1, 0 @ read CPAR
orr r1, r1, #0x40
ldr r1, =CKENB
ldr r2, =(CKENB_6_IRQ)
str r2, [r1]
-#endif
+#endif /* !CONFIG_CPU_MONAHANS */
/* set clock speed */
#ifdef CONFIG_CPU_MONAHANS
ldr r0, =ACCR
ldr r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
str r1, [r0]
-#else /* ! CONFIG_CPU_MONAHANS */
+#else /* !CONFIG_CPU_MONAHANS */
#ifdef CFG_CPUSPEED
ldr r0, CC_BASE
ldr r1, cpuspeed
bl do_fiq /* effiction fiq_save_user_regs */
irq_restore_user_regs
-#else
+#else /* !CONFIG_USE_IRQ */
.align 5
irq:
bad_save_user_regs
bl do_fiq
-#endif
+#endif /* CONFIG_USE_IRQ */
/****************************************************************************/
/* */
int usb_cpu_init_fail(void)
{
+ UHCHR |= UHCHR_FHR;
+ udelay(11);
+ UHCHR &= ~UHCHR_FHR;
+
+ UHCCOMS |= 1;
+ udelay(10);
+
+#if defined(CONFIG_CPU_MONAHANS)
+ UHCHR |= UHCHR_SSEP0;
+#endif
+#if defined(CONFIG_PXA27X)
+ UHCHR |= UHCHR_SSEP2;
+#endif
+ UHCHR |= UHCHR_SSEP1;
+ UHCHR |= UHCHR_SSE;
+
return 0;
}
Notes on the the generic USB-OHCI driver
========================================
-This driver (drivers/usb_ohci.[ch]) is the result of the merge of
+This driver (drivers/usb/usb_ohci.[ch]) is the result of the merge of
various existing OHCI drivers that were basically identical beside
cpu/board dependant initalization. This initalization has been moved
into cpu/board directories and are called via the hooks below.
board/modnet50/flash.c .. flash routines
board/modnet50/modnet50.c .. some board init stuff
-drivers/netarm_eth.c .. ethernet driver for the NET+50 CPU
-drivers/netarm_eth.h .. header for ethernet driver
+drivers/net/netarm_eth.c .. ethernet driver for the NET+50 CPU
+drivers/net/netarm_eth.h .. header for ethernet driver
include/configs/modnet50.h .. configuration file for ModNET50
nand write.jffs2 addr ofs|partition size
Like `write', but blocks that are marked bad are skipped and the
- is written to the next block instead. This allows writing writing
+ data is written to the next block instead. This allows writing
a JFFS2 image, as long as the image is short enough to fit even
after skipping the bad blocks. Compact images, such as those
produced by mkfs.jffs2 should work well, but loading an image copied
/*
- * drivers/nand/nand_util.c
+ * drivers/mtd/nand/nand_util.c
*
* Copyright (C) 2006 by Weiss-Electronic GmbH.
* All rights reserved.
}
dp83902a_recv(&pbuf[0], len);
- /*Just pass it to the upper layer*/
+ /* Just pass it to the upper layer */
NetReceive(&pbuf[0], len);
}
}
void eth_halt() {
-
PRINTK("### eth_halt\n");
if(initialized)
dp83902a_stop();
}
int eth_rx() {
-dp83902a_poll();
-return 1;
+ dp83902a_poll();
+ return 1;
}
int eth_send(volatile void *packet, int length) {
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-# File: drivers/sk98lin/Makefile
+# File: drivers/net/sk98lin/Makefile
#
# Makefile for the SysKonnect SK-98xx device driver.
#
* MA 02111-1307 USA
*
*
- * Derived in part from the SL811 HCD driver "u-boot/drivers/sl811_usb.c"
+ * Derived in part from the SL811 HCD driver "u-boot/drivers/usb/sl811_usb.c"
* (original copyright message follows):
*
* (C) Copyright 2004
* bodonoghue@CodeHermit.ie
*
* References
- * DasUBoot/drivers/usbdcore_omap1510.c, for design and implementation ideas.
+ * DasUBoot/drivers/usb/usbdcore_omap1510.c, for design and implementation
+ * ideas.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
/*****************************************************************************/
/* Cursor definition: */
-/* CONFIG_CONSOLE_CURSOR: Uses a timer function (see drivers/i8042.c) to */
-/* let the cursor blink. Uses the macros CURSOR_OFF */
-/* and CURSOR_ON. */
+/* CONFIG_CONSOLE_CURSOR: Uses a timer function (see drivers/input/i8042.c) */
+/* to let the cursor blink. Uses the macros */
+/* CURSOR_OFF and CURSOR_ON. */
/* CONFIG_VIDEO_SW_CURSOR: Draws a cursor after the last character. No */
/* blinking is provided. Uses the macros CURSOR_SET */
/* and CURSOR_OFF. */
#define CURSOR_OFF console_cursor(0);
#define CURSOR_SET
#ifndef CONFIG_I8042_KBD
-#warning Cursor drawing on/off needs timer function s.a. drivers/i8042.c
+#warning Cursor drawing on/off needs timer function s.a. drivers/input/i8042.c
#endif
#else
#ifdef CONFIG_CONSOLE_TIME
int read_jffs2_nand(size_t start, size_t len,
size_t * retlen, u_char * buf, int nanddev);
#else
-/* info for NAND chips, defined in drivers/nand/nand.c */
+/* info for NAND chips, defined in drivers/mtd/nand/nand.c */
extern nand_info_t nand_info[];
#endif
#define CONFIG_VGA_AS_SINGLE_DEVICE
/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
#define CFG_ISA_IO 0xE8000000
-/* see also drivers/videomodes.c */
+/* see also drivers/video/videomodes.c */
#define CFG_DEFAULT_VIDEO_MODE 0x303
#endif
# define CFG_ENV_SECT_SIZE 0x20000
#endif
-/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
keep reset. */
#undef CFG_FLASH_CFI
#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */
-/* drivers/nand/nand.c */
+/* drivers/mtd/nand/nand.c */
#define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */
#define CFG_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_VGA_AS_SINGLE_DEVICE
/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
#define CFG_ISA_IO 0xE8000000
-/* see also drivers/videomodes.c */
+/* see also drivers/video/videomodes.c */
#define CFG_DEFAULT_VIDEO_MODE 0x303
#endif
* FLASH driver setup
*/
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
/*
* Move up the U-Boot & monitor area if more flash is fitted.
* If this U-Boot is to be run on Integrators with varying flash sizes,
- * drivers/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG
+ * drivers/mtd/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG
* register and dynamically assign CFG_ENV_ADDR & CFG_MONITOR_BASE
* - CFG_MONITOR_BASE is set to indicate that the environment is not
* embedded in the boot monitor(s) area
* FLASH driver setup
*/
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
* CFI FLASH driver setup
*/
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
* FLASH driver setup
*/
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
#define NAND_ECC_HW3_256 2
/* Hardware ECC 3 byte ECC per 512 Byte data */
#define NAND_ECC_HW3_512 3
-/* Hardware ECC 3 byte ECC per 512 Byte data */
+/* Hardware ECC 6 byte ECC per 512 Byte data */
#define NAND_ECC_HW6_512 4
/* Hardware ECC 8 byte ECC per 512 Byte data */
#define NAND_ECC_HW8_512 6
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
-# from drivers/nand directory
+# from drivers/mtd/nand directory
$(obj)nand_ecc.c:
@rm -f $(obj)nand_ecc.c
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
-# from drivers/nand directory
+# from drivers/mtd/nand directory
$(obj)nand_ecc.c:
@rm -f $(obj)nand_ecc.c
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
-# from drivers/nand directory
+# from drivers/mtd/nand directory
$(obj)nand_ecc.c:
@rm -f $(obj)nand_ecc.c
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
nand_command(mtd, block, 0, CFG_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
/*
- * Read on byte
+ * Read one byte
*/
if (this->read_byte(mtd) != 0xff)
return 1;
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
$(STRIP) $@
-$(obj)mkimage$(SFX): $(obj)mkimage.o $(obj)crc32.o $(obj)sha1.o
+$(obj)mkimage$(SFX): $(obj)mkimage.o $(obj)crc32.o
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
$(STRIP) $@
projects / karo-tx-uboot.git / commitdiff