This option is enabled by default for U-Boot.
-endmenu # General setup
-
menuconfig EXPERT
bool "Configure standard U-Boot features (expert users)"
help
environments which can tolerate a "non-standard" U-Boot.
Only use this if you really know what you are doing.
+endmenu # General setup
+
menu "Boot images"
config SPL_BUILD
ARM MARVELL KIRKWOOD
M: Prafulla Wadaskar <prafulla@marvell.com>
+M: Luka Perkov <luka.perkov@sartura.hr>
S: Maintained
T: git git://git.denx.de/u-boot-marvell.git
F: arch/arm/cpu/arm926ejs/kirkwood/
CONFIG_A003399_NOR_WORKAROUND
Enables a workaround for IFC erratum A003399. It is only
- requred during NOR boot.
+ required during NOR boot.
CONFIG_A008044_WORKAROUND
Enables a workaround for T1040/T1042 erratum A008044. It is only
- requred during NAND boot and valid for Rev 1.0 SoC revision
+ required during NAND boot and valid for Rev 1.0 SoC revision
CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
time of U-boot entry and is required to be re-initialized.
CONFIG_DEEP_SLEEP
- Inidcates this SoC supports deep sleep feature. If deep sleep is
+ Indicates this SoC supports deep sleep feature. If deep sleep is
supported, core will start to execute uboot when wakes up.
- Generic CPU options:
CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only]
- When transferring memsize parameter to linux, some versions
+ When transferring memsize parameter to Linux, some versions
expect it to be in bytes, others in MB.
Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
CONFIG_LCD_ALIGNMENT
- Normally the LCD is page-aligned (tyically 4KB). If this is
+ Normally the LCD is page-aligned (typically 4KB). If this is
defined then the LCD will be aligned to this value instead.
For ARM it is sometimes useful to use MMU_SECTION_SIZE
here, since it is cheaper to change data cache settings on
can be displayed via the splashscreen support or the
bmp command.
-- Do compresssing for memory range:
+- Do compressing for memory range:
CONFIG_CMD_ZIP
If this option is set, it would use zlib deflate method
- define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
- define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
- define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
- If thoses defines are not set, default value is 100000
+ If those defines are not set, default value is 100000
for speed, and 0 for slave.
- drivers/i2c/rcar_i2c.c:
- CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
- CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
- CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
- - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses
+ - CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses
- drivers/i2c/omap24xx_i2c.c
- activate this driver with CONFIG_SYS_I2C_OMAP24XX
additional defines:
CONFIG_SYS_NUM_I2C_BUSES
- Hold the number of i2c busses you want to use. If you
+ Hold the number of i2c buses you want to use. If you
don't use/have i2c muxes on your i2c bus, this
is equal to CONFIG_SYS_NUM_I2C_ADAPTERS, and you can
omit this define.
define.
CONFIG_SYS_I2C_BUSES
- hold a list of busses you want to use, only used if
+ hold a list of buses you want to use, only used if
CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
CONFIG_SYS_NUM_I2C_BUSES = 9:
CONFIG_SYS_FPGA_WAIT_INIT
- Maximum time to wait for the INIT_B line to deassert
- after PROB_B has been deasserted during a Virtex II
+ Maximum time to wait for the INIT_B line to de-assert
+ after PROB_B has been de-asserted during a Virtex II
FPGA configuration sequence. The default time is 500
ms.
CONFIG_SYS_FPGA_WAIT_BUSY
- Maximum time to wait for BUSY to deassert during
+ Maximum time to wait for BUSY to de-assert during
Virtex II FPGA configuration. The default is 5 ms.
CONFIG_SYS_FPGA_WAIT_CONFIG
of the backslashes before semicolons and special
symbols.
-- Commandline Editing and History:
+- Command Line Editing and History:
CONFIG_CMDLINE_EDITING
Enable editing and History functions for interactive
- commandline input operations
+ command line input operations
- Default Environment:
CONFIG_EXTRA_ENV_SETTINGS
CONFIG_DELAY_ENVIRONMENT
Normally the environment is loaded when the board is
- intialised so that it is available to U-Boot. This inhibits
+ initialised so that it is available to U-Boot. This inhibits
that so that the environment is not available until
explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL
this is instead controlled by the value of
Define this option to use dual flash support where two flash
memories can be connected with a given cs line.
- currently Xilinx Zynq qspi support these type of connections.
+ Currently Xilinx Zynq qspi supports these type of connections.
CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
enable the W#/Vpp signal to disable writing to the status
CONFIG_SYS_NAND_HW_ECC_OOBFIRST
Define this if you need to first read the OOB and then the
- data. This is used for example on davinci plattforms.
+ data. This is used, for example, on davinci platforms.
CONFIG_SPL_OMAP3_ID_NAND
Support for an OMAP3-specific set of functions to return the
This feature allocates regions with increasing addresses
within the region. calloc() is supported, but realloc()
is not available. free() is supported but does nothing.
- The memory will be freed (or in fact just forgotton) when
+ The memory will be freed (or in fact just forgotten) when
U-Boot relocates itself.
Pre-relocation malloc() is only supported on ARM and sandbox
The format of the list is:
type_attribute = [s|d|x|b|i|m]
- access_atribute = [a|r|o|c]
- attributes = type_attribute[access_atribute]
+ access_attribute = [a|r|o|c]
+ attributes = type_attribute[access_attribute]
entry = variable_name[:attributes]
list = entry[,list]
- CONFIG_ENV_FLAGS_LIST_DEFAULT
Define this to a list (string) to define the ".flags"
- envirnoment variable in the default or embedded environment.
+ environment variable in the default or embedded environment.
- CONFIG_ENV_FLAGS_LIST_STATIC
Define this to a list (string) to define validation that
- CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
This is set by OMAP boards for the max time that reset should
be asserted. See doc/README.omap-reset-time for details on how
- the value can be calulated on a given board.
+ the value can be calculated on a given board.
- CONFIG_USE_STDINT
If stdint.h is available with your toolchain you can define this
provision.
BE CAREFUL! The first access to the environment happens quite early
-in U-Boot initalization (when we try to get the setting of for the
+in U-Boot initialization (when we try to get the setting of for the
console baudrate). You *MUST* have mapped your NVRAM area then, or
U-Boot will hang.
table, or the whole device D if has no partition
table.
- "D:auto": first partition in device D with bootable flag set.
- If none, first valid paratition in device D. If no
+ If none, first valid partition in device D. If no
partition table then means device D.
- FAT_ENV_FILE:
It's a string of the FAT file name. This file use to store the
- envrionment.
+ environment.
- CONFIG_FAT_WRITE:
- This should be defined. Otherwise it cannot save the envrionment file.
+ This should be defined. Otherwise it cannot save the environment file.
- CONFIG_ENV_IS_IN_MMC:
if CONFIG_SYS_FDC_HW_INIT is defined, then the function
fdc_hw_init() is called at the beginning of the FDC
setup. fdc_hw_init() must be provided by the board
- source code. It is used to make hardware dependant
+ source code. It is used to make hardware-dependent
initializations.
- CONFIG_IDE_AHB:
When software is doing ATA command and data transfer to
IDE devices through IDE-AHB controller, some additional
registers accessing to these kind of IDE-AHB controller
- is requierd.
+ is required.
- CONFIG_SYS_IMMR: Physical address of the Internal Memory.
DO NOT CHANGE unless you know exactly what you're
required.
- CONFIG_PCI_ENUM_ONLY
- Only scan through and get the devices on the busses.
+ Only scan through and get the devices on the buses.
Don't do any setup work, presumably because someone or
something has already done it, and we don't need to do it
a second time. Useful for platforms that are pre-booted
npe_ucode - set load address for the NPE microcode
- silent_linux - If set then linux will be told to boot silently, by
+ silent_linux - If set then Linux will be told to boot silently, by
changing the console to be empty. If "yes" it will be
made silent. If "no" it will not be made silent. If
unset, then it will be made silent if the U-Boot console
---------------------------------------------
For some environment variables, the behavior of u-boot needs to change
-when their values are changed. This functionailty allows functions to
+when their values are changed. This functionality allows functions to
be associated with arbitrary variables. On creation, overwrite, or
deletion, the callback will provide the opportunity for some side
effect to happen or for the change to be rejected.
with the same list format above. Any association in ".callbacks" will
override any association in the static list. You can define
CONFIG_ENV_CALLBACK_LIST_DEFAULT to a list (string) to define the
-".callbacks" envirnoment variable in the default or embedded environment.
+".callbacks" environment variable in the default or embedded environment.
Command Line Parsing:
* Initialized global data (data segment) is read-only. Do not attempt
to write it.
-* Do not use any uninitialized global data (or implicitely initialized
+* Do not use any uninitialized global data (or implicitly initialized
as zero data - BSS segment) at all - this is undefined, initiali-
zation is performed later (when relocating to RAM).
that.
Having only the stack as writable memory limits means we cannot use
-normal global data to share information beween the code. But it
+normal global data to share information between the code. But it
turned out that the implementation of U-Boot can be greatly
simplified by making a global data structure (gd_t) available to all
functions. We could pass a pointer to this data as argument to _all_
In the reset configuration, U-Boot starts at the reset entry point
(on most PowerPC systems at address 0x00000100). Because of the reset
-configuration for CS0# this is a mirror of the onboard Flash memory.
+configuration for CS0# this is a mirror of the on board Flash memory.
To be able to re-map memory U-Boot then jumps to its link address.
To be able to implement the initialization code in C, a (small!)
initial stack is set up in the internal Dual Ported RAM (in case CPUs
Source files originating from a different project (for example the
MTD subsystem) are generally exempt from these guidelines and are not
-reformated to ease subsequent migration to newer versions of those
+reformatted to ease subsequent migration to newer versions of those
sources.
Please note that U-Boot is implemented in C (and to some small parts in
# SPDX-License-Identifier: GPL-2.0+
obj-y = generic.o timer.o reset.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y += relocate.o
+endif
(cpurev & 0xF0) >> 4, (cpurev & 0x0F),
((cpurev & 0x8000) ? " unknown" : ""),
strmhz(buf, imx_get_armclk()));
- printf("Reset cause: %s\n\n", get_reset_cause());
+ printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
#endif
--- /dev/null
+/*
+ * relocate - i.MX25-specific vector relocation
+ *
+ * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * The i.MX25 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0xFFFF0000),
+ * thus only the low address (0x00000000) is useable; but that is
+ * in ROM, so let's avoid relocating the vectors.
+ */
+ .section .text.relocate_vectors,"ax",%progbits
+
+ENTRY(relocate_vectors)
+
+ bx lr
+
+ENDPROC(relocate_vectors)
save_omap_boot_params();
#endif
watchdog_disable();
- timer_init();
set_uart_mux_conf();
setup_clocks_for_console();
uart_soft_reset();
#include <asm/arch/hardware.h>
#include <asm/arch/psc_defs.h>
+#define MAX_PCI_PORTS 2
+enum pci_mode {
+ ENDPOINT,
+ LEGACY_ENDPOINT,
+ ROOTCOMPLEX,
+};
+
+#define DEVCFG_MODE_MASK (BIT(2) | BIT(1))
+#define DEVCFG_MODE_SHIFT 1
+
void chip_configuration_unlock(void)
{
__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
}
#endif
+/* Function to set up PCIe mode */
+static void config_pcie_mode(int pcie_port, enum pci_mode mode)
+{
+ u32 val = __raw_readl(KS2_DEVCFG);
+
+ if (pcie_port >= MAX_PCI_PORTS)
+ return;
+
+ /**
+ * each pci port has two bits for mode and it starts at
+ * bit 1. So use port number to get the right bit position.
+ */
+ pcie_port <<= 1;
+ val &= ~(DEVCFG_MODE_MASK << pcie_port);
+ val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
+ __raw_writel(val, KS2_DEVCFG);
+}
+
int arch_cpu_init(void)
{
chip_configuration_unlock();
msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
+
+ /* Initialize the PCIe-0 to work as Root Complex */
+ config_pcie_mode(0, ROOTCOMPLEX);
#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
+ /* Initialize the PCIe-1 to work as Root Complex */
+ config_pcie_mode(1, ROOTCOMPLEX);
#endif
#ifdef CONFIG_SOC_K2L
osr_init();
*/
#include <common.h>
+#include <ahci.h>
#include <spl.h>
#include <asm/omap_common.h>
#include <asm/arch/omap.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <watchdog.h>
+#include <scsi.h>
DECLARE_GLOBAL_DATA_PTR;
image_entry((u32 *)&gd->arch.omap_boot_params);
}
#endif
+
+#ifdef CONFIG_SCSI_AHCI_PLAT
+void arch_preboot_os(void)
+{
+ ahci_reset(DWC_AHSATA_BASE);
+}
+#endif
init_sata(0);
scsi_scan(1);
}
+
+void scsi_bus_reset(void)
+{
+ ahci_reset(DWC_AHSATA_BASE);
+ ahci_init(DWC_AHSATA_BASE);
+}
writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
&timer_base->tclr);
- /* reset time, capture current incrementer value time */
- gd->arch.lastinc = readl(&timer_base->tcrr) /
- (TIMER_CLOCK / CONFIG_SYS_HZ);
- gd->arch.tbl = 0; /* start "advancing" time stamp from 0 */
-
return 0;
}
*regs = &emif_regs_elpida_380_mhz_1cs;
else if (omap4_rev == OMAP4430_ES2_0)
*regs = &emif_regs_elpida_200_mhz_2cs;
- else if (omap4_rev == OMAP4430_ES2_3)
- *regs = &emif_regs_elpida_400_mhz_1cs;
else if (omap4_rev < OMAP4470_ES1_0)
*regs = &emif_regs_elpida_400_mhz_2cs;
else
if (omap_rev == OMAP4430_ES1_0)
*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
- else if (omap_rev == OMAP4430_ES2_3)
- *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
else if (omap_rev < OMAP4460_ES1_0)
*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
else
#include <config.h>
#include <version.h>
-/* Save the parameter pass in by previous boot loader */
-.global save_boot_params
-save_boot_params:
- /* no parameter to save */
- bx lr
-
-
/* Set up the platform, once the cpu has been initialized */
.globl lowlevel_init
lowlevel_init:
orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
mcr p15, 0, r0, c1, c0, 0
+#ifdef CONFIG_DEBUG_LL
+ bl setup_lowlevel_debug
+#endif
+
/*
* Now we are using the page table embedded in the Boot ROM.
* It is not handy since it is not a straight mapped table for sLD3.
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
clkrst_init.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
--- /dev/null
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <asm/arch/sg-regs.h>
+
+#define UART_CLK 36864000
+#include <asm/arch/debug-uart.S>
+
+ENTRY(setup_lowlevel_debug)
+ init_debug_uart r0, r1, r2
+
+ /* UART Port 0 */
+ set_pinsel 85, 1, r0, r1
+ set_pinsel 88, 1, r0, r1
+
+ ldr r0, =SG_IECTRL
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ mov pc, lr
+ENDPROC(setup_lowlevel_debug)
void sbc_init(void)
{
+ u32 tmp;
+
+ /* system bus output enable */
+ tmp = readl(PC0CTRL);
+ tmp &= 0xfffffcff;
+ writel(tmp, PC0CTRL);
+
/* XECS1: sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o
--- /dev/null
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <asm/arch/sc-regs.h>
+#include <asm/arch/sg-regs.h>
+
+#define UART_CLK 73728000
+#include <asm/arch/debug-uart.S>
+
+ENTRY(setup_lowlevel_debug)
+ ldr r0, =SC_CLKCTRL
+ ldr r1, [r0]
+ orr r1, r1, #SC_CLKCTRL_CLK_PERI
+ str r1, [r0]
+
+ init_debug_uart r0, r1, r2
+
+ /* UART Port 0 */
+ set_pinsel 127, 0, r0, r1
+ set_pinsel 128, 0, r0, r1
+
+ ldr r0, =SG_LOADPINCTRL
+ mov r1, #1
+ str r1, [r0]
+
+ ldr r0, =SG_IECTRL
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ mov pc, lr
+ENDPROC(setup_lowlevel_debug)
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
clkrst_init.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
--- /dev/null
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <asm/arch/sg-regs.h>
+
+#define UART_CLK 80000000
+#include <asm/arch/debug-uart.S>
+
+ENTRY(setup_lowlevel_debug)
+ init_debug_uart r0, r1, r2
+
+ /* UART Port 0 */
+ set_pinsel 70, 3, r0, r1
+ set_pinsel 71, 3, r0, r1
+
+ ldr r0, =SG_IECTRL
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ mov pc, lr
+ENDPROC(setup_lowlevel_debug)
void sbc_init(void)
{
+ u32 tmp;
+
+ /* system bus output enable */
+ tmp = readl(PC0CTRL);
+ tmp &= 0xfffffcff;
+ writel(tmp, PC0CTRL);
+
#if !defined(CONFIG_SPL_BUILD)
/* XECS0 : dummy */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
static const struct memory_bank memory_banks_boot_swap_off[] = {
- {0x04000000, 0x04000000},
+ {0x04000000, 0x02000000},
};
static const struct memory_bank memory_banks_boot_swap_on[] = {
- {0x00000000, 0x04000000},
- {0x04000000, 0x04000000},
+ {0x00000000, 0x02000000},
+ {0x04000000, 0x02000000},
};
#endif
int armv7_update_dt(void *fdt)
{
+ if (!armv7_boot_nonsec())
+ return 0;
#ifndef CONFIG_ARMV7_SECURE_BASE
/* secure code lives in RAM, keep it alive */
fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
spi@131b0000 {
spi-max-frequency = <1000000>;
spi-deactivate-delay = <100>;
- cros-ec@0 {
+ cros_ec: cros-ec@0 {
reg = <0>;
compatible = "google,cros-ec";
spi-max-frequency = <5000000>;
samsung,dc-value = <25>;
};
- cros-ec-keyb {
- compatible = "google,cros-ec-keyb";
- google,key-rows = <8>;
- google,key-columns = <13>;
- google,repeat-delay-ms = <240>;
- google,repeat-rate-ms = <30>;
- google,ghost-filter;
- /*
- * Keymap entries take the form of 0xRRCCKKKK where
- * RR=Row CC=Column KKKK=Key Code
- * The values below are for a US keyboard layout and
- * are taken from the Linux driver. Note that the
- * 102ND key is not used for US keyboards.
- */
- linux,keymap = <
- /* CAPSLCK F1 B F10 */
- 0x0001003a 0x0002003b 0x00030030 0x00040044
- /* N = R_ALT ESC */
- 0x00060031 0x0008000d 0x000a0064 0x01010001
- /* F4 G F7 H */
- 0x0102003e 0x01030022 0x01040041 0x01060023
- /* ' F9 BKSPACE L_CTRL */
- 0x01080028 0x01090043 0x010b000e 0x0200001d
- /* TAB F3 T F6 */
- 0x0201000f 0x0202003d 0x02030014 0x02040040
- /* ] Y 102ND [ */
- 0x0205001b 0x02060015 0x02070056 0x0208001a
- /* F8 GRAVE F2 5 */
- 0x02090042 0x03010029 0x0302003c 0x03030006
- /* F5 6 - \ */
- 0x0304003f 0x03060007 0x0308000c 0x030b002b
- /* R_CTRL A D F */
- 0x04000061 0x0401001e 0x04020020 0x04030021
- /* S K J ; */
- 0x0404001f 0x04050025 0x04060024 0x04080027
- /* L ENTER Z C */
- 0x04090026 0x040b001c 0x0501002c 0x0502002e
- /* V X , M */
- 0x0503002f 0x0504002d 0x05050033 0x05060032
- /* L_SHIFT / . SPACE */
- 0x0507002a 0x05080035 0x05090034 0x050B0039
- /* 1 3 4 2 */
- 0x06010002 0x06020004 0x06030005 0x06040003
- /* 8 7 0 9 */
- 0x06050009 0x06060008 0x0608000b 0x0609000a
- /* L_ALT DOWN RIGHT Q */
- 0x060a0038 0x060b006c 0x060c006a 0x07010010
- /* E R W I */
- 0x07020012 0x07030013 0x07040011 0x07050017
- /* U R_SHIFT P O */
- 0x07060016 0x07070036 0x07080019 0x07090018
- /* UP LEFT */
- 0x070b0067 0x070c0069>;
- };
-
fimd@14400000 {
samsung,vl-freq = <60>;
samsung,vl-col = <1366>;
};
};
+
+#include "cros-ec-keyboard.dtsi"
pmic = "/i2c@12ca0000";
};
- cros-ec-keyb {
- compatible = "google,cros-ec-keyb";
- google,key-rows = <8>;
- google,key-columns = <13>;
- google,repeat-delay-ms = <240>;
- google,repeat-rate-ms = <30>;
- google,ghost-filter;
- /*
- * Keymap entries take the form of 0xRRCCKKKK where
- * RR=Row CC=Column KKKK=Key Code
- * The values below are for a US keyboard layout and
- * are taken from the Linux driver. Note that the
- * 102ND key is not used for US keyboards.
- */
- linux,keymap = <
- /* CAPSLCK F1 B F10 */
- 0x0001003a 0x0002003b 0x00030030 0x00040044
- /* N = R_ALT ESC */
- 0x00060031 0x0008000d 0x000a0064 0x01010001
- /* F4 G F7 H */
- 0x0102003e 0x01030022 0x01040041 0x01060023
- /* ' F9 BKSPACE L_CTRL */
- 0x01080028 0x01090043 0x010b000e 0x0200001d
- /* TAB F3 T F6 */
- 0x0201000f 0x0202003d 0x02030014 0x02040040
- /* ] Y 102ND [ */
- 0x0205001b 0x02060015 0x02070056 0x0208001a
- /* F8 GRAVE F2 5 */
- 0x02090042 0x03010029 0x0302003c 0x03030006
- /* F5 6 - \ */
- 0x0304003f 0x03060007 0x0308000c 0x030b002b
- /* R_CTRL A D F */
- 0x04000061 0x0401001e 0x04020020 0x04030021
- /* S K J ; */
- 0x0404001f 0x04050025 0x04060024 0x04080027
- /* L ENTER Z C */
- 0x04090026 0x040b001c 0x0501002c 0x0502002e
- /* V X , M */
- 0x0503002f 0x0504002d 0x05050033 0x05060032
- /* L_SHIFT / . SPACE */
- 0x0507002a 0x05080035 0x05090034 0x050B0039
- /* 1 3 4 2 */
- 0x06010002 0x06020004 0x06030005 0x06040003
- /* 8 7 0 9 */
- 0x06050009 0x06060008 0x0608000b 0x0609000a
- /* L_ALT DOWN RIGHT Q */
- 0x060a0038 0x060b006c 0x060c006a 0x07010010
- /* E R W I */
- 0x07020012 0x07030013 0x07040011 0x07050017
- /* U R_SHIFT P O */
- 0x07060016 0x07070036 0x07080019 0x07090018
- /* UP LEFT */
- 0x070b0067 0x070c0069>;
- };
-
dmc {
mem-manuf = "samsung";
mem-type = "ddr3";
spi@12d40000 { /* spi2 */
spi-max-frequency = <4000000>;
spi-deactivate-delay = <200>;
- cros-ec@0 {
+ cros_ec: cros-ec@0 {
reg = <0>;
compatible = "google,cros-ec";
spi-half-duplex;
samsung,dual-lcd-enabled = <0>;
};
};
+
+#include "cros-ec-keyboard.dtsi"
spi@12d40000 { /* spi2 */
spi-max-frequency = <4000000>;
spi-deactivate-delay = <200>;
- cros-ec@0 {
+ cros_ec: cros-ec@0 {
reg = <0>;
compatible = "google,cros-ec";
spi-half-duplex;
samsung,dual-lcd-enabled = <0>;
};
};
+
+#include "cros-ec-keyboard.dtsi"
#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
+#define KS2_DEVCFG (KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
/* PSC */
#define KS2_PSC_BASE 0x02350000
extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;
extern const struct emif_regs emif_regs_elpida_400_mhz_1cs;
extern const struct emif_regs emif_regs_elpida_400_mhz_2cs;
+extern const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2;
+extern const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2;
+extern const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2;
struct omap_sysinfo {
char *board_string;
};
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/serial_reg.h>
+
+#if !defined(CONFIG_DEBUG_SEMIHOSTING)
+#include CONFIG_DEBUG_LL_INCLUDE
+#endif
+
+#define BAUDRATE 115200
+#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
+#define DIVISOR DIV_ROUND(UART_CLK, 16 * BAUDRATE)
+
+ .macro init_debug_uart, ra, rb, rc
+ addruart \ra, \rb, \rc
+ mov \rb, #UART_LCR_WLEN8
+ strb \rb, [\ra, #0x11]
+ ldr \rb, =DIVISOR
+ str \rb, [\ra, #0x24]
+ .endm
#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
+#define PC0CTRL 0x598000c0
#define ROM_BOOT_ROMRSV2 0x59801208
#ifndef __ASSEMBLY__
int armv7_init_nonsec(void);
int armv7_update_dt(void *fdt);
+bool armv7_boot_nonsec(void);
/* defined in assembly file */
unsigned int _nonsec_init(void);
}
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
-static bool boot_nonsec(void)
+bool armv7_boot_nonsec(void)
{
char *s = getenv("bootm_boot_mode");
#ifdef CONFIG_ARMV7_BOOT_SEC_DEFAULT
if (!fake) {
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
- if (boot_nonsec()) {
+ if (armv7_boot_nonsec()) {
armv7_init_nonsec();
secure_ram_addr(_do_nonsec_entry)(kernel_entry,
0, machid, r2);
NOR
===
-The Beaglebone White can be equiped with a "memory cape" that in turn can
+The Beaglebone White can be equipped with a "memory cape" that in turn can
have a NOR module plugged into it. In this case it is then possible to
-program and boot from NOR. Note that due to how U-Boot is architectured we
+program and boot from NOR. Note that due to how U-Boot is designed we
must build a specific version of U-Boot that knows we have NOR flash. This
build is named 'am335x_evm_nor'. Further, we have a 'am335x_evm_norboot'
build that will assume that the environment is on NOR rather than NAND. In
In this case the additional data is written to another partition of the
NAND. In this example we assume that the uImage and device tree to be are
-already located on the NAND somewhere (such as fileystem or mtd partition)
+already located on the NAND somewhere (such as filesystem or mtd partition)
along with a Falcon Mode aware MLO written to the correct locations for
booting and mtdparts have been configured correctly for the board:
else
*regs = &emif_regs_elpida_400_mhz_1cs;
}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs
+ **dmm_lisa_regs)
+{
+ u32 omap_rev = omap_revision();
+
+ if (omap_rev == OMAP4430_ES1_0)
+ *dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
+ else if (omap_rev == OMAP4430_ES2_3)
+ *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+ else if (omap_rev < OMAP4460_ES1_0)
+ *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+ else
+ *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
+}
+
#endif
/**
return 0;
}
-#elif defined(CONFIG_ARC700)
+#elif defined(CONFIG_ARC)
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (control)
gd->fdt_blob = blob;
else
- set_working_fdt_addr(blob);
+ set_working_fdt_addr((void *)blob);
if (argc >= 2) {
int len;
return;
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ if (to > from) {
+ from += len;
+ to += len;
+ }
while (len > 0) {
size_t tail = (len > chunksz) ? chunksz : len;
WATCHDOG_RESET();
+ if (to > from) {
+ to -= tail;
+ from -= tail;
+ }
memmove(to, from, tail);
- to += tail;
- from += tail;
+ if (to < from) {
+ to += tail;
+ from += tail;
+ }
len -= tail;
}
#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */
err = mmc_load_image_raw_sector(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
#endif
- } else {
+ }
+
+ switch(boot_mode){
+ case MMCSD_MODE_RAW:
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+ case MMCSD_MODE_FS:
+#endif
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+ case MMCSD_MODE_EMMCBOOT:
+#endif
+ /* Boot mode is ok. Nothing to do. */
+ break;
+ case MMCSD_MODE_UNDEFINED:
+ default:
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- puts("spl: wrong MMC boot mode\n");
+ puts("spl: wrong MMC boot mode\n");
#endif
- hang();
+ hang();
}
if (err)
#include <spl.h>
#include <asm/u-boot.h>
#include <sata.h>
+#include <scsi.h>
#include <fat.h>
#include <version.h>
#include <image.h>
p_mbr->signature = MSDOS_MBR_SIGNATURE;
p_mbr->partition_record[0].sys_ind = EFI_PMBR_OSTYPE_EFI_GPT;
p_mbr->partition_record[0].start_sect = 1;
- p_mbr->partition_record[0].nr_sects = (u32) dev_desc->lba;
+ p_mbr->partition_record[0].nr_sects = (u32) dev_desc->lba - 1;
/* Write MBR sector to the MMC device */
if (dev_desc->block_write(dev_desc->dev, 0, 1, p_mbr) != 1) {
-CROS_EC Keyboard
+ChromeOS EC Keyboard
-The CROS_EC (Matrix Keyboard Protocol) allows communcation with a secondary
-micro used for keyboard, and possible other features.
+Google's ChromeOS EC Keyboard is a simple matrix keyboard implemented on
+a separate EC (Embedded Controller) device. It provides a message for reading
+key scans from the EC. These are then converted into keycodes for processing
+by the kernel.
-The CROS_EC keyboard uses this protocol to receive key scans and produce input
-in U-Boot.
+This binding is based on matrix-keymap.txt and extends/modifies it as follows:
-Required properties :
-- compatible : "google,cros-ec-keyb"
-- google,key-rows : Number of key rows
-- google,key-columns : Number of key columns
+Required properties:
+- compatible: "google,cros-ec-keyb"
-Optional properties, in addition to those specified by the shared
-matrix-keyboard bindings:
+Optional properties:
+- google,needs-ghost-filter: True to enable a ghost filter for the matrix
+keyboard. This is recommended if the EC does not have its own logic or
+hardware for this.
-- linux,fn-keymap: a second keymap, same specification as the
- matrix-keyboard-controller spec but to be used when the KEY_FN modifier
- key is pressed.
-- google,repeat-delay-ms : delay in milliseconds before repeat starts
-- google,repeat-rate-ms : delay between each subsequent key press
-- google,ghost-filter : enable ghost filtering for this device
-Example, taken from daisy:
+Example:
cros-ec-keyb {
compatible = "google,cros-ec-keyb";
- google,key-rows = <8>;
- google,key-columns = <13>;
- google,ghost-filter;
- google,repeat-delay-ms = <240>;
- google,repeat-rate-ms = <30>;
+ keypad,num-rows = <8>;
+ keypad,num-columns = <13>;
+ google,needs-ghost-filter;
/*
- * Keymap entries take the form of 0xRRCCKKKK where
- * RR=Row CC=Column KKKK=Key Code
- * The values below are for a US keyboard layout and
- * are taken from the Linux driver. Note that the
- * 102ND key is not used for US keyboards.
- */
+ * Keymap entries take the form of 0xRRCCKKKK where
+ * RR=Row CC=Column KKKK=Key Code
+ * The values below are for a US keyboard layout and
+ * are taken from the Linux driver. Note that the
+ * 102ND key is not used for US keyboards.
+ */
linux,keymap = <
/* CAPSLCK F1 B F10 */
- 0x0001003a 0x0002003c 0x00030030 0x00040044
+ 0x0001003a 0x0002003b 0x00030030 0x00040044
/* N = R_ALT ESC */
0x00060031 0x0008000d 0x000a0064 0x01010001
/* F4 G F7 H */
Build U-Boot sandbox and run it:
- make sandbox_config
+ make sandbox_defconfig
make
- ./u-boot
+ ./u-boot -d u-boot.dtb
(type 'reset' to exit U-Boot)
alias hs Heiko Schocher <hs@denx.de>
alias ijc Ian Campbell <ijc+uboot@hellion.org.uk>
alias iwamatsu Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-alias jagan Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
+alias jagan Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
alias jasonjin Jason Jin <jason.jin@freescale.com>
alias jhersh Joe Hershberger <joe.hershberger@gmail.com>
alias jwrdegoede Hans de Goede <hdegoede@redhat.com>
alias kimphill Kim Phillips <kim.phillips@freescale.com>
+alias luka Luka Perkov <luka.perkov@sartura.hr>
alias lukma Lukasz Majewski <l.majewski@samsung.com>
alias macpaul Macpaul Lin <macpaul@andestech.com>
alias marex Marek Vasut <marex@denx.de>
alias at91 uboot, abiessmann
alias davinci ti
alias imx uboot, sbabic
-alias kirkwood uboot, prafulla
+alias kirkwood uboot, prafulla, luka
alias omap ti
alias pxa uboot, marex
alias rmobile uboot, iwamatsu
alias mmc uboot, panto
alias nand uboot, scottwood
alias net uboot, jhersh
-alias spi uboot, jagan
+alias spi uboot, jagan
alias ubi uboot, hs
alias usb uboot, marex
alias video uboot, ag
}
#endif
+int ahci_reset(u32 base)
+{
+ int i = 1000;
+ u32 host_ctl_reg = base + HOST_CTL;
+ u32 tmp = readl(host_ctl_reg); /* global controller reset */
+
+ if ((tmp & HOST_RESET) == 0)
+ writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
+
+ /*
+ * reset must complete within 1 second, or
+ * the hardware should be considered fried.
+ */
+ do {
+ udelay(1000);
+ tmp = readl(host_ctl_reg);
+ i--;
+ } while ((i > 0) && (tmp & HOST_RESET));
+
+ if (i == 0) {
+ printf("controller reset failed (0x%x)\n", tmp);
+ return -1;
+ }
+
+ return 0;
+}
+
static int ahci_host_init(struct ahci_probe_ent *probe_ent)
{
#ifndef CONFIG_SCSI_AHCI_PLAT
cap_save &= ((1 << 28) | (1 << 17));
cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
- /* global controller reset */
- tmp = readl(mmio + HOST_CTL);
- if ((tmp & HOST_RESET) == 0)
- writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
-
- /* reset must complete within 1 second, or
- * the hardware should be considered fried.
- */
- i = 1000;
- do {
- udelay(1000);
- tmp = readl(mmio + HOST_CTL);
- if (!i--) {
- debug("controller reset failed (0x%x)\n", tmp);
- return -1;
- }
- } while (tmp & HOST_RESET);
+ ret = ahci_reset(probe_ent->mmio_base);
+ if (ret)
+ return ret;
writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
writel(cap_save, mmio + HOST_CAP);
}
-void scsi_bus_reset(void)
+__weak void scsi_bus_reset(void)
{
/*Not implement*/
}
-
void scsi_print_error(ccb * pccb)
{
/*The ahci error info can be read in the ahci driver*/
return ret;
}
-struct i2c_parms {
- void *base;
- void *idle_bus_data;
- int (*idle_bus_fn)(void *p);
-};
-
-struct sram_data {
- unsigned curr_i2c_bus;
- struct i2c_parms i2c_data[3];
-};
-
static void * const i2c_bases[] = {
#if defined(CONFIG_MX25)
(void *)IMX_I2C_BASE,
#endif
};
+struct i2c_parms {
+ void *base;
+ void *idle_bus_data;
+ int (*idle_bus_fn)(void *p);
+};
+
+struct sram_data {
+ unsigned curr_i2c_bus;
+ struct i2c_parms i2c_data[ARRAY_SIZE(i2c_bases)];
+};
+
void *i2c_get_base(struct i2c_adapter *adap)
{
return i2c_bases[adap->hwadapnr];
enum {
KBC_MAX_KEYS = 8, /* Maximum keys held down at once */
+ KBC_REPEAT_RATE_MS = 30,
+ KBC_REPEAT_DELAY_MS = 240,
};
static struct keyb {
struct key_matrix matrix; /* The key matrix layer */
int key_rows; /* Number of keyboard rows */
int key_cols; /* Number of keyboard columns */
- unsigned int repeat_delay_ms; /* Time before autorepeat starts */
- unsigned int repeat_rate_ms; /* Autorepeat rate in ms */
int ghost_filter; /* 1 to enable ghost filter, else 0 */
int inited; /* 1 if keyboard is ready */
} config;
* Get keyboard rows and columns - at present we are limited to
* 8 columns by the protocol (one byte per row scan)
*/
- config->key_rows = fdtdec_get_int(blob, node, "google,key-rows", 0);
- config->key_cols = fdtdec_get_int(blob, node, "google,key-columns", 0);
+ config->key_rows = fdtdec_get_int(blob, node, "keypad,num-rows", 0);
+ config->key_cols = fdtdec_get_int(blob, node, "keypad,num-columns", 0);
if (!config->key_rows || !config->key_cols ||
config->key_rows * config->key_cols / 8
> CROS_EC_KEYSCAN_COLS) {
config->key_rows, config->key_cols);
return -1;
}
- config->repeat_delay_ms = fdtdec_get_int(blob, node,
- "google,repeat-delay-ms", 0);
- config->repeat_rate_ms = fdtdec_get_int(blob, node,
- "google,repeat-rate-ms", 0);
config->ghost_filter = fdtdec_get_bool(blob, node,
"google,ghost-filter");
return 0;
}
if (cros_ec_keyb_decode_fdt(blob, node, &config))
return -1;
- input_set_delays(&config.input, config.repeat_delay_ms,
- config.repeat_rate_ms);
+ input_set_delays(&config.input, KBC_REPEAT_DELAY_MS,
+ KBC_REPEAT_RATE_MS);
if (key_matrix_init(&config.matrix, config.key_rows,
config.key_cols, config.ghost_filter)) {
debug("%s: cannot init key matrix\n", __func__);
*/
#include <common.h>
+#include <linux/err.h>
#include <dm.h>
#include <i2c.h>
#include <i2c_eeprom.h>
/*
* Marvell MMC/SD/SDIO driver
*
- * (C) Copyright 2012
+ * (C) Copyright 2012-2014
* Marvell Semiconductor <www.marvell.com>
* Written-by: Maen Suleiman, Gerald Kerma
*
#define MVEBU_TARGET_DRAM 0
+#define TIMEOUT_DELAY 5*CONFIG_SYS_HZ /* wait 5 seconds */
+
static void mvebu_mmc_write(u32 offs, u32 val)
{
writel(val, CONFIG_SYS_MMC_BASE + (offs));
static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
- int timeout = 10;
+ ulong start;
ushort waittype = 0;
ushort resptype = 0;
ushort xfertype = 0;
ushort resp_indx = 0;
- debug("cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
- cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
-
- udelay(10*1000);
+ debug("%s: cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
+ DRIVER_NAME, cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME,
cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE));
- /* Checking if card is busy */
- while ((mvebu_mmc_read(SDIO_HW_STATE) & CARD_BUSY)) {
- if (timeout == 0) {
- printf("%s: card busy!\n", DRIVER_NAME);
- return -1;
- }
- timeout--;
- udelay(1000);
+ /*
+ * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
+ * register is sometimes not set before a while when some
+ * "unusual" data block sizes are used (such as with the SWITCH
+ * command), even despite the fact that the XFER_DONE interrupt
+ * was raised. And if another data transfer starts before
+ * this bit comes to good sense (which eventually happens by
+ * itself) then the new transfer simply fails with a timeout.
+ */
+ if (!(mvebu_mmc_read(SDIO_HW_STATE) & CMD_FIFO_EMPTY)) {
+ ushort hw_state, count = 0;
+
+ start = get_timer(0);
+ do {
+ hw_state = mvebu_mmc_read(SDIO_HW_STATE);
+ if ((get_timer(0) - start) > TIMEOUT_DELAY) {
+ printf("%s : FIFO_EMPTY bit missing\n",
+ DRIVER_NAME);
+ break;
+ }
+ count++;
+ } while (!(hw_state & CMD_FIFO_EMPTY));
+ debug("%s *** wait for FIFO_EMPTY bit (hw=0x%04x, count=%d, jiffies=%ld)\n",
+ DRIVER_NAME, hw_state, count, (get_timer(0) - (start)));
}
- /* Set up for a data transfer if we have one */
- if (data) {
- int err = mvebu_mmc_setup_data(data);
-
- if (err)
- return err;
- }
+ /* Clear status */
+ mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
+ mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
resptype = SDIO_CMD_INDEX(cmd->cmdidx);
}
if (data) {
+ int err = mvebu_mmc_setup_data(data);
+
+ if (err) {
+ debug("%s: command DATA error :%x\n",
+ DRIVER_NAME, err);
+ return err;
+ }
+
resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
if (data->flags & MMC_DATA_READ) {
/* Setting Xfer mode */
mvebu_mmc_write(SDIO_XFER_MODE, xfertype);
- mvebu_mmc_write(SDIO_NOR_INTR_STATUS, ~SDIO_NOR_CARD_INT);
- mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
-
/* Sending command */
mvebu_mmc_write(SDIO_CMD, resptype);
- mvebu_mmc_write(SDIO_NOR_INTR_EN, SDIO_POLL_MASK);
- mvebu_mmc_write(SDIO_ERR_INTR_EN, SDIO_POLL_MASK);
-
- /* Waiting for completion */
- timeout = 1000000;
+ start = get_timer(0);
while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) {
if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
DRIVER_NAME, cmd->cmdidx,
mvebu_mmc_read(SDIO_ERR_INTR_STATUS));
if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
- (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
+ (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) {
+ debug("%s: command READ timed out\n",
+ DRIVER_NAME);
return TIMEOUT;
+ }
+ debug("%s: command READ error\n", DRIVER_NAME);
return COMM_ERR;
}
- timeout--;
- udelay(1);
- if (timeout <= 0) {
- printf("%s: command timed out\n", DRIVER_NAME);
+ if ((get_timer(0) - start) > TIMEOUT_DELAY) {
+ debug("%s: command timed out\n", DRIVER_NAME);
return TIMEOUT;
}
}
- if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
- (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
- return TIMEOUT;
/* Handling response */
if (cmd->resp_type & MMC_RSP_136) {
cmd->response[1] = ((response[0] & 0xfc00) >> 10);
cmd->response[2] = 0;
cmd->response[3] = 0;
+ } else {
+ cmd->response[0] = 0;
+ cmd->response[1] = 0;
+ cmd->response[2] = 0;
+ cmd->response[3] = 0;
}
debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);
debug("[0x%x] ", cmd->response[3]);
debug("\n");
+ if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
+ (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
+ return TIMEOUT;
+
return 0;
}
if (m > MVEBU_MMC_BASE_DIV_MAX)
m = MVEBU_MMC_BASE_DIV_MAX;
mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
+ debug("%s: clock (%d) div : %d\n", DRIVER_NAME, clock, m);
}
-
- udelay(10*1000);
}
static void mvebu_mmc_set_bus(unsigned int bus)
"high-speed" : "");
mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
- udelay(10*1000);
}
static void mvebu_mmc_set_ios(struct mmc *mmc)
static int mvebu_mmc_initialize(struct mmc *mmc)
{
- debug("%s: mvebu_mmc_initialize", DRIVER_NAME);
+ debug("%s: mvebu_mmc_initialize\n", DRIVER_NAME);
/*
* Setting host parameters
/* SW reset */
mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
- udelay(10*1000);
-
return 0;
}
uint32_t error_loc[ELM_MAX_ERROR_COUNT];
enum bch_level bch_type;
uint32_t i, ecc_flag = 0;
- uint8_t count, err = 0;
+ uint8_t count;
uint32_t byte_pos, bit_pos;
+ int err = 0;
/* check calculated ecc */
for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
int ret = -1;
int firsttime;
__u32 root_cluster = 0;
+ __u32 read_blk;
int rootdir_size = 0;
- int j;
+ int buffer_blk_cnt;
+ int do_read;
+ __u8 *dir_ptr;
if (read_bootsectandvi(&bs, &volinfo, &mydata->fatsize)) {
debug("Error: reading boot sector\n");
isdir = 1;
}
- j = 0;
+ buffer_blk_cnt = 0;
+ firsttime = 1;
while (1) {
int i;
- if (j == 0) {
- debug("FAT read sect=%d, clust_size=%d, DIRENTSPERBLOCK=%zd\n",
- cursect, mydata->clust_size, DIRENTSPERBLOCK);
+ if (mydata->fatsize == 32 || firsttime) {
+ dir_ptr = do_fat_read_at_block;
+ firsttime = 0;
+ } else {
+ /**
+ * FAT16 sector buffer modification:
+ * Each loop, the second buffered block is moved to
+ * the buffer begin, and two next sectors are read
+ * next to the previously moved one. So the sector
+ * buffer keeps always 3 sectors for fat16.
+ * And the current sector is the buffer second sector
+ * beside the "firsttime" read, when it is the first one.
+ *
+ * PREFETCH_BLOCKS is 2 for FAT16 == loop[0:1]
+ * n = computed root dir sector
+ * loop | cursect-1 | cursect | cursect+1 |
+ * 0 | sector n+0 | sector n+1 | none |
+ * 1 | none | sector n+0 | sector n+1 |
+ * 0 | sector n+1 | sector n+2 | sector n+3 |
+ * 1 | sector n+3 | ...
+ */
+ dir_ptr = (do_fat_read_at_block + mydata->sect_size);
+ memcpy(do_fat_read_at_block, dir_ptr, mydata->sect_size);
+ }
+
+ do_read = 1;
+
+ if (mydata->fatsize == 32 && buffer_blk_cnt)
+ do_read = 0;
+
+ if (do_read) {
+ read_blk = (mydata->fatsize == 32) ?
+ mydata->clust_size : PREFETCH_BLOCKS;
+
+ debug("FAT read(sect=%d, cnt:%d), clust_size=%d, DIRENTSPERBLOCK=%zd\n",
+ cursect, read_blk, mydata->clust_size, DIRENTSPERBLOCK);
- if (disk_read(cursect,
- (mydata->fatsize == 32) ?
- (mydata->clust_size) :
- PREFETCH_BLOCKS,
- do_fat_read_at_block) < 0) {
+ if (disk_read(cursect, read_blk, dir_ptr) < 0) {
debug("Error: reading rootdir block\n");
goto exit;
}
- dentptr = (dir_entry *) do_fat_read_at_block;
+ dentptr = (dir_entry *)dir_ptr;
}
for (i = 0; i < DIRENTSPERBLOCK; i++) {
get_vfatname(mydata,
root_cluster,
- do_fat_read_at_block,
+ dir_ptr,
dentptr, l_name);
if (dols == LS_ROOT) {
goto rootdir_done; /* We got a match */
}
- debug("END LOOP: j=%d clust_size=%d\n", j,
+ debug("END LOOP: buffer_blk_cnt=%d clust_size=%d\n", buffer_blk_cnt,
mydata->clust_size);
/*
* root directory clusters when a cluster has been
* completely processed.
*/
- ++j;
+ ++buffer_blk_cnt;
int rootdir_end = 0;
if (mydata->fatsize == 32) {
- if (j == mydata->clust_size) {
+ if (buffer_blk_cnt == mydata->clust_size) {
int nxtsect = 0;
int nxt_clust = 0;
root_cluster = nxt_clust;
cursect = nxtsect;
- j = 0;
+ buffer_blk_cnt = 0;
}
} else {
- if (j == PREFETCH_BLOCKS)
- j = 0;
+ if (buffer_blk_cnt == PREFETCH_BLOCKS)
+ buffer_blk_cnt = 0;
rootdir_end = (++cursect - mydata->rootdir_sect >=
rootdir_size);
};
int ahci_init(u32 base);
+int ahci_reset(u32 base);
#endif
#define AXP221_DCDC4_CTRL 0x24
#define AXP221_DCDC5_CTRL 0x25
#define AXP221_ALDO1_CTRL 0x28
-#define AXP221_ALDO2_CTRL 0x28
+#define AXP221_ALDO2_CTRL 0x29
#define AXP221_ALDO3_CTRL 0x2a
int axp221_set_dcdc1(unsigned int mvolt);
/* Enhance our eMMC support / experience. */
#define CONFIG_CMD_GPT
#define CONFIG_EFI_PARTITION
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
#ifdef CONFIG_NAND
#define NANDARGS \
/* Enhance our eMMC support / experience. */
#define CONFIG_CMD_GPT
#define CONFIG_EFI_PARTITION
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
/* Enhance our eMMC support / experience. */
#define CONFIG_CMD_GPT
#define CONFIG_EFI_PARTITION
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
/* CPSW Ethernet */
+#define CONFIG_CMD_NFS
#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
#define CONFIG_CMD_DHCP
#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
#ifndef __CONFIG_H
#define __CONFIG_H
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
+
/*
* High Level Configuration Options
*/
#define CONFIG_CMD_GPIO
#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
#define CONFIG_OMAP_COMMON
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SDRC /* The chip has SDRC controller */
#define CONFIG_HSMMC2_8BIT
#define CONFIG_SUPPORT_EMMC_BOOT
+/* SATA Boot related defines */
+#define CONFIG_SPL_SATA_SUPPORT
+#define CONFIG_SPL_SATA_BOOT_DEVICE 0
+#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1
+
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
/* USB UHH support options */
#define CONFIG_CMD_USB
#define CONFIG_USB_HOST
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
-#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
#endif
/*
#undef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (64 << 10)
-#define CONFIG_ENV_OFFSET (256 << 10)
+#define CONFIG_ENV_OFFSET (512 << 10)
#define CONFIG_ENV_SECT_SIZE (64 << 10)
#define CONFIG_SYS_NO_FLASH
#endif
/*
* U-Boot general configuration
*/
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
+#define CONFIG_OF_LIBFDT
/*
* Linux Information
#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
+#define CONFIG_SYS_GENERIC_BOARD
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
/* Enhance our eMMC support / experience. */
#define CONFIG_CMD_GPT
#define CONFIG_EFI_PARTITION
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
#define CONFIG_HSMMC2_8BIT
/* CPSW Ethernet */
/* Enhance our eMMC support / experience. */
#define CONFIG_CMD_GPT
#define CONFIG_EFI_PARTITION
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
#define CONFIG_HSMMC2_8BIT
#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
#endif
/*
#define CMD_INHIBIT (1 << 0)
#define CMD_TXACTIVE (1 << 8)
#define CMD_RXACTIVE (1 << 9)
+#define CMD_FIFO_EMPTY (1 << 13)
#define CMD_AUTOCMD12ACTIVE (1 << 14)
#define CMD_BUS_BUSY (CMD_AUTOCMD12ACTIVE | \
CMD_RXACTIVE | \
exit 1
fi
-version_string=$($gas --version | head -1 | sed -e 's/.*) *\([0-9.]*\).*/\1/' )
+version_string=$($gas --version | head -1 | \
+ sed -e 's/(.*)//; s/[^0-9.]*\([0-9.]*\).*/\1/')
MAJOR=$(echo $version_string | cut -d . -f 1)
MINOR=$(echo $version_string | cut -d . -f 2)
projects / karo-tx-uboot.git / commitdiff