am33xx: elm: fix clearing of irqstatus bits

The irqstatus bits are cleared by writing a '1' to the irqstatus
register. Change bogus RMW register access to a simple write of the
bitmask to be cleared.

diff --git a/arch/arm/cpu/armv7/am33xx/elm.c b/arch/arm/cpu/armv7/am33xx/elm.c
index b0b05f4c8593ae233ebc86bacc5d433bd7303349..21f3473a2888f7187e95b1a2859c8177a685da14 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/elm.c
+++ b/arch/arm/cpu/armv7/am33xx/elm.c
@@ -111,8 +111,7 @@ int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
        /* wait for processing to complete */
        while (!(readl(&elm_cfg->irqstatus) & (0x1 << poly)));
        /* clear status */
        /* wait for processing to complete */
        while (!(readl(&elm_cfg->irqstatus) & (0x1 << poly)));
        /* clear status */

-       writel((readl(&elm_cfg->irqstatus) & ~(0x1 << poly)),
-               &elm_cfg->irqstatus);
+       writel(0x1 << poly, &elm_cfg->irqstatus);

 
        /* check if correctable */
        location_status = readl(&elm_cfg->error_location[poly].location_status);
 
        /* check if correctable */
        location_status = readl(&elm_cfg->error_location[poly].location_status);