ARM: cpu: Add ARMv7 barrier operations support

This enables ARMv7 barrier operations support when
march=armv7-a is enabled.

Using CP15 barriers causes U-Boot bootm command crash when
transferring control to the loaded image on Renesas R8A7794 Cortex A7 CPU.
Using ARMv7 barrier operations instead of the deprecated CP15 barriers
helps to avoid these issues.

Signed-off-by: Valentine Barshak <valentine.barshak+renesas@cogentembedded.com>
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 8ebe9b0303c9916adbfbc3c08094c38a7b49a196..d048301b5d7923e536db55cd32e11089dae2a230 100644 (file)
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -68,7 +68,7 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
                }
        }
        /* DSB to make sure the operation is complete */
-       CP15DSB;
+       DSB;
 }
 
 static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
@@ -96,7 +96,7 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
                }
        }
        /* DSB to make sure the operation is complete */
-       CP15DSB;
+       DSB;
 }
 
 static void v7_maint_dcache_level_setway(u32 level, u32 operation)
@@ -215,7 +215,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
        }
 
        /* DSB to make sure the operation is complete */
-       CP15DSB;
+       DSB;
 }
 
 /* Invalidate TLB */
@@ -228,11 +228,11 @@ static void v7_inval_tlb(void)
                "mcr p15, 0, %0, c8, c6, 0\n"
                /* Invalidate entire instruction TLB */
                "mcr p15, 0, %0, c8, c5, 0\n"
-               /* Full system DSB - make sure that the invalidation is complete */
-               "mcr     p15, 0, %0, c7, c10, 4\n"
-               /* Full system ISB - make sure the instruction stream sees it */
-               "mcr     p15, 0, %0, c7, c5, 4\n"
                : : "r" (0));
+       /* Full system DSB - make sure that the invalidation is complete */
+       DSB;
+       /* Full system ISB - make sure the instruction stream sees it */
+       ISB;
 }
 
 void invalidate_dcache_all(void)
@@ -335,19 +335,23 @@ void arm_init_domains(void)
 /* Invalidate entire I-cache and branch predictor array */
 void invalidate_icache_all(void)
 {
-       /*
-        * Invalidate all instruction caches to PoU.
-        * Also flushes branch target cache.
-        */
        asm volatile (
+               /*
+                * Invalidate all instruction caches to PoU.
+                * Also flushes branch target cache.
+                */
                "mcr p15, 0, %0, c7, c5, 0\n"
+
                /* Invalidate entire branch predictor array */
                "mcr p15, 0, %0, c7, c5, 6\n"
-               /* Full system DSB - make sure that the invalidation is complete */
-               "mcr     p15, 0, %0, c7, c10, 4\n"
-               /* ISB - make sure the instruction stream sees it */
-               "mcr     p15, 0, %0, c7, c5, 4\n"
+
                : : "r" (0));
+
+       /* Full system DSB - make sure that the invalidation is complete */
+       DSB;
+
+       /* ISB - make sure the instruction stream sees it */
+       ISB;
 }
 #else
 void invalidate_icache_all(void)

diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 58d8b161215a6229fb0e9661a0687a49440ed70a..cbe7dc1a5c641701cea2051c9c5bee3072015179 100644 (file)
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -70,6 +70,16 @@
 #define CP15DSB        asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
 #define CP15DMB        asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
 
+#ifdef __ARM_ARCH_7A__
+#define ISB    asm volatile ("isb" : : : "memory")
+#define DSB    asm volatile ("dsb" : : : "memory")
+#define DMB    asm volatile ("dmb" : : : "memory")
+#else
+#define ISB    CP15ISB
+#define DSB    CP15DSB
+#define DMB    CP15DMB
+#endif
+
 /*
  * Workaround for ARM errata # 798870
  * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been