2 * Copyright (c) 2013 Xilinx Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/arch/clk.h>
14 #define SLCR_LOCK_MAGIC 0x767B
15 #define SLCR_UNLOCK_MAGIC 0xDF0D
17 #define SLCR_IDCODE_MASK 0x1F000
18 #define SLCR_IDCODE_SHIFT 12
20 static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
22 void zynq_slcr_lock(void)
25 writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
30 void zynq_slcr_unlock(void)
33 writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
38 /* Reset the entire system */
39 void zynq_slcr_cpu_reset(void)
42 * Unlock the SLCR then reset the system.
43 * Note that this seems to require raw i/o
44 * functions or there's a lockup?
49 * Clear 0x0F000000 bits of reboot status register to workaround
50 * the FSBL not loading the bitstream after soft-reboot
51 * This is a temporary solution until we know more.
53 clrbits_le32(&slcr_base->reboot_status, 0xF000000);
55 writel(1, &slcr_base->pss_rst_ctrl);
58 /* Setup clk for network */
59 void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
66 printf("Non existing GEM id %d\n", gem_id);
70 ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
75 /* Configure GEM_RCLK_CTRL */
76 writel(1, &slcr_base->gem1_rclk_ctrl);
78 /* Configure GEM_RCLK_CTRL */
79 writel(1, &slcr_base->gem0_rclk_ctrl);
86 void zynq_slcr_devcfg_disable(void)
90 /* Disable AXI interface by asserting FPGA resets */
91 writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
93 /* Set Level Shifters DT618760 */
94 writel(0xA, &slcr_base->lvl_shftr_en);
99 void zynq_slcr_devcfg_enable(void)
103 /* Set Level Shifters DT618760 */
104 writel(0xF, &slcr_base->lvl_shftr_en);
106 /* Enable AXI interface by de-asserting FPGA resets */
107 writel(0x0, &slcr_base->fpga_rst_ctrl);
112 u32 zynq_slcr_get_boot_mode(void)
114 /* Get the bootmode register value */
115 return readl(&slcr_base->boot_mode);
118 u32 zynq_slcr_get_idcode(void)
120 return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>