2 * Copyright (c) 2013 Xilinx Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/arch/clk.h>
14 #define SLCR_LOCK_MAGIC 0x767B
15 #define SLCR_UNLOCK_MAGIC 0xDF0D
17 #define SLCR_IDCODE_MASK 0x1F000
18 #define SLCR_IDCODE_SHIFT 12
20 static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
22 void zynq_slcr_lock(void)
25 writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
28 void zynq_slcr_unlock(void)
31 writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
34 /* Reset the entire system */
35 void zynq_slcr_cpu_reset(void)
38 * Unlock the SLCR then reset the system.
39 * Note that this seems to require raw i/o
40 * functions or there's a lockup?
45 * Clear 0x0F000000 bits of reboot status register to workaround
46 * the FSBL not loading the bitstream after soft-reboot
47 * This is a temporary solution until we know more.
49 clrbits_le32(&slcr_base->reboot_status, 0xF000000);
51 writel(1, &slcr_base->pss_rst_ctrl);
54 /* Setup clk for network */
55 void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
62 printf("Non existing GEM id %d\n", gem_id);
66 ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
71 /* Configure GEM_RCLK_CTRL */
72 writel(1, &slcr_base->gem1_rclk_ctrl);
74 /* Configure GEM_RCLK_CTRL */
75 writel(1, &slcr_base->gem0_rclk_ctrl);
82 void zynq_slcr_devcfg_disable(void)
86 /* Disable AXI interface */
87 writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
89 /* Set Level Shifters DT618760 */
90 writel(0xA, &slcr_base->lvl_shftr_en);
95 void zynq_slcr_devcfg_enable(void)
99 /* Set Level Shifters DT618760 */
100 writel(0xF, &slcr_base->lvl_shftr_en);
102 /* Disable AXI interface */
103 writel(0x0, &slcr_base->fpga_rst_ctrl);
108 u32 zynq_slcr_get_boot_mode(void)
110 /* Get the bootmode register value */
111 return readl(&slcr_base->boot_mode);
114 u32 zynq_slcr_get_idcode(void)
116 return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>