cpu/mpc8xxx/ddr/ctrl_regs.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  11  * Based on code from spd_sdram.c
  12  * Author: James Yang [at freescale.com]
  13  */
  14
  15 #include <common.h>
  16 #include <asm/fsl_ddr_sdram.h>
  17
  18 #include "ddr.h"
  19
  20 extern unsigned int picos_to_mclk(unsigned int picos);
  21 /*
  22  * Determine Rtt value.
  23  *
  24  * This should likely be either board or controller specific.
  25  *
  26  * Rtt(nominal):
  27  *      0 = Rtt disabled
  28  *      1 = 75 ohm
  29  *      2 = 150 ohm
  30  *      3 = 50 ohm
  31  *
  32  * FIXME: Apparently 8641 needs a value of 2
  33  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  34  *
  35  * FIXME: There was some effort down this line earlier:
  36  *
  37  *      unsigned int i;
  38  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  39  *              if (popts->dimmslot[i].num_valid_cs
  40  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  41  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  42  *                      rtt = 2;
  43  *                      break;
  44  *              }
  45  *      }
  46  */
  47 static inline int fsl_ddr_get_rtt(void)
  48 {
  49         int rtt;
  50
  51 #if defined(CONFIG_FSL_DDR1)
  52         rtt = 0;
  53 #elif defined(CONFIG_FSL_DDR2)
  54         rtt = 3;
  55 #else
  56 #error "Need Rtt value for DDR3"
  57 #endif
  58
  59         return rtt;
  60 }
  61
  62 /* Chip Select Configuration (CSn_CONFIG) */
  63 static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr,
  64                                const memctl_options_t *popts,
  65                                const dimm_params_t *dimm_params)
  66 {
  67         unsigned int cs_n_en = 0; /* Chip Select enable */
  68         unsigned int intlv_en = 0; /* Memory controller interleave enable */
  69         unsigned int intlv_ctl = 0; /* Interleaving control */
  70         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
  71         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
  72         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
  73         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
  74         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
  75         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
  76
  77         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
  78         if ((((i&1) == 0)
  79             && (dimm_params[i/2].n_ranks == 1))
  80             || (dimm_params[i/2].n_ranks == 2)) {
  81                 unsigned int n_banks_per_sdram_device;
  82                 cs_n_en = 1;
  83                 if (i == 0) {
  84                         /* These fields only available in CS0_CONFIG */
  85                         intlv_en = popts->memctl_interleaving;
  86                         intlv_ctl = popts->memctl_interleaving_mode;
  87                 }
  88                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
  89                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
  90                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
  91                 n_banks_per_sdram_device
  92                         = dimm_params[i/2].n_banks_per_sdram_device;
  93                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
  94                 row_bits_cs_n = dimm_params[i/2].n_row_addr - 12;
  95                 col_bits_cs_n = dimm_params[i/2].n_col_addr - 8;
  96         }
  97
  98         ddr->cs[i].config = (0
  99                 | ((cs_n_en & 0x1) << 31)
 100                 | ((intlv_en & 0x3) << 29)
 101                 | ((intlv_ctl & 0xf) << 24)
 102                 | ((ap_n_en & 0x1) << 23)
 103
 104                 /* XXX: some implementation only have 1 bit starting at left */
 105                 | ((odt_rd_cfg & 0x7) << 20)
 106
 107                 /* XXX: Some implementation only have 1 bit starting at left */
 108                 | ((odt_wr_cfg & 0x7) << 16)
 109
 110                 | ((ba_bits_cs_n & 0x3) << 14)
 111                 | ((row_bits_cs_n & 0x7) << 8)
 112                 | ((col_bits_cs_n & 0x7) << 0)
 113                 );
 114 }
 115
 116 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 117 /* FIXME: 8572 */
 118 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 119 {
 120         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 121
 122         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 123 }
 124
 125 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 126
 127 #if defined(CONFIG_FSL_DDR2)
 128 /*
 129  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 130  *
 131  * Avoid writing for DDR I.  The new PQ38 DDR controller
 132  * dreams up non-zero default values to be backwards compatible.
 133  */
 134 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
 135 {
 136         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 137         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 138         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 139         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 140         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 141
 142         /* Active powerdown exit timing (tXARD and tXARDS). */
 143         unsigned char act_pd_exit_mclk;
 144         /* Precharge powerdown exit timing (tXP). */
 145         unsigned char pre_pd_exit_mclk;
 146         /* Precharge powerdown exit timing (tAXPD). */
 147         unsigned char taxpd_mclk;
 148         /* Mode register set cycle time (tMRD). */
 149         unsigned char tmrd_mclk;
 150
 151         /* (tXARD and tXARDS). Empirical? */
 152         act_pd_exit_mclk = 2;
 153
 154         /* XXX:  tXARD = 2, tXARDS = 7 - AL. * Empirical? */
 155         pre_pd_exit_mclk = 6;
 156
 157         /* FIXME:  tXP = 2 on Micron 667 MHz DIMM */
 158         taxpd_mclk = 8;
 159
 160         tmrd_mclk = 2;
 161
 162         ddr->timing_cfg_0 = (0
 163                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 164                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 165                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 166                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 167                 | ((act_pd_exit_mclk & 0x7) << 20)  /* ACT_PD_EXIT */
 168                 | ((pre_pd_exit_mclk & 0x7) << 16)  /* PRE_PD_EXIT */
 169                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 170                 | ((tmrd_mclk & 0xf) << 0)      /* MRS_CYC */
 171                 );
 172         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 173 }
 174 #endif  /* defined(CONFIG_FSL_DDR2) */
 175
 176 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 177 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 178                                const common_timing_params_t *common_dimm)
 179 {
 180         /* Extended Activate to precharge interval (tRAS) */
 181         unsigned int ext_acttopre = 0;
 182         unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
 183         unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
 184         unsigned int cntl_adj = 0; /* Control Adjust */
 185
 186         ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
 187         ddr->timing_cfg_3 = (0
 188                 | ((ext_acttopre & 0x1) << 24)
 189                 | ((ext_refrec & 0x7) << 16)
 190                 | ((ext_caslat & 0x1) << 12)
 191                 | ((cntl_adj & 0x7) << 0)
 192                 );
 193 }
 194
 195 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 196 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 197                                const common_timing_params_t *common_dimm,
 198                                unsigned int cas_latency)
 199 {
 200         /* Precharge-to-activate interval (tRP) */
 201         unsigned char pretoact_mclk;
 202         /* Activate to precharge interval (tRAS) */
 203         unsigned char acttopre_mclk;
 204         /*  Activate to read/write interval (tRCD) */
 205         unsigned char acttorw_mclk;
 206         /* CASLAT */
 207         unsigned char caslat_ctrl;
 208         /*  Refresh recovery time (tRFC) ; trfc_low */
 209         unsigned char refrec_ctrl;
 210         /* Last data to precharge minimum interval (tWR) */
 211         unsigned char wrrec_mclk;
 212         /* Activate-to-activate interval (tRRD) */
 213         unsigned char acttoact_mclk;
 214         /* Last write data pair to read command issue interval (tWTR) */
 215         unsigned char wrtord_mclk;
 216
 217         pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
 218         acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
 219         acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
 220
 221         /*
 222          * Translate CAS Latency to a DDR controller field value:
 223          *
 224          *      CAS Lat DDR I   DDR II  Ctrl
 225          *      Clocks  SPD Bit SPD Bit Value
 226          *      ------- ------- ------- -----
 227          *      1.0     0               0001
 228          *      1.5     1               0010
 229          *      2.0     2       2       0011
 230          *      2.5     3               0100
 231          *      3.0     4       3       0101
 232          *      3.5     5               0110
 233          *      4.0             4       0111
 234          *      4.5                     1000
 235          *      5.0             5       1001
 236          */
 237 #if defined(CONFIG_FSL_DDR1)
 238         caslat_ctrl = (cas_latency + 1) & 0x07;
 239 #elif defined(CONFIG_FSL_DDR2)
 240         caslat_ctrl = 2 * cas_latency - 1;
 241 #else
 242 #error "Need CAS Latency help for DDR3 in fsl_ddr_sdram.c"
 243 #endif
 244
 245         refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
 246         wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
 247         acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
 248         wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
 249
 250         ddr->timing_cfg_1 = (0
 251                 | ((pretoact_mclk & 0x07) << 28)
 252                 | ((acttopre_mclk & 0x0F) << 24)
 253                 | ((acttorw_mclk & 0x7) << 20)
 254                 | ((caslat_ctrl & 0xF) << 16)
 255                 | ((refrec_ctrl & 0xF) << 12)
 256                 | ((wrrec_mclk & 0x07) << 8)
 257                 | ((acttoact_mclk & 0x07) << 4)
 258                 | ((wrtord_mclk & 0x07) << 0)
 259                 );
 260 }
 261
 262 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 263 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 264                                const memctl_options_t *popts,
 265                                const common_timing_params_t *common_dimm,
 266                                unsigned int cas_latency,
 267                                unsigned int additive_latency)
 268 {
 269         /* Additive latency */
 270         unsigned char add_lat_mclk;
 271         /* CAS-to-preamble override */
 272         unsigned short cpo;
 273         /* Write latency */
 274         unsigned char wr_lat;
 275         /*  Read to precharge (tRTP) */
 276         unsigned char rd_to_pre;
 277         /* Write command to write data strobe timing adjustment */
 278         unsigned char wr_data_delay;
 279         /* Minimum CKE pulse width (tCKE) */
 280         unsigned char cke_pls;
 281         /* Window for four activates (tFAW) */
 282         unsigned short four_act;
 283
 284         /* FIXME add check that this must be less than acttorw_mclk */
 285         add_lat_mclk = additive_latency;
 286         cpo = popts->cpo_override;
 287
 288 #if defined(CONFIG_FSL_DDR1)
 289         /*
 290          * This is a lie.  It should really be 1, but if it is
 291          * set to 1, bits overlap into the old controller's
 292          * otherwise unused ACSM field.  If we leave it 0, then
 293          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 294          */
 295         wr_lat = 0;
 296 #elif defined(CONFIG_FSL_DDR2)
 297         wr_lat = cas_latency + additive_latency - 1;
 298 #else
 299 #error "Fix WR_LAT for DDR3"
 300 #endif
 301
 302         rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
 303         wr_data_delay = popts->write_data_delay;
 304         cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
 305         four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
 306
 307         ddr->timing_cfg_2 = (0
 308                 | ((add_lat_mclk & 0x7) << 28)
 309                 | ((cpo & 0x1f) << 23)
 310                 | ((wr_lat & 0x7) << 19)
 311                 | ((rd_to_pre & 0x7) << 13)
 312                 | ((wr_data_delay & 0x7) << 10)
 313                 | ((cke_pls & 0x7) << 6)
 314                 | ((four_act & 0x1f) << 0)
 315                 );
 316 }
 317
 318 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 319 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 320                                const memctl_options_t *popts,
 321                                const common_timing_params_t *common_dimm)
 322 {
 323         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 324         unsigned int sren;              /* Self refresh enable (during sleep) */
 325         unsigned int ecc_en;            /* ECC enable. */
 326         unsigned int rd_en;             /* Registered DIMM enable */
 327         unsigned int sdram_type;        /* Type of SDRAM */
 328         unsigned int dyn_pwr;           /* Dynamic power management mode */
 329         unsigned int dbw;               /* DRAM dta bus width */
 330         unsigned int eight_be;          /* 8-beat burst enable */
 331         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 332         unsigned int threeT_en;         /* Enable 3T timing */
 333         unsigned int twoT_en;           /* Enable 2T timing */
 334         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 335         unsigned int x32_en = 0;        /* x32 enable */
 336         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 337         unsigned int hse;               /* Global half strength override */
 338         unsigned int mem_halt = 0;      /* memory controller halt */
 339         unsigned int bi = 0;            /* Bypass initialization */
 340
 341         mem_en = 1;
 342         sren = popts->self_refresh_in_sleep;
 343         if (common_dimm->all_DIMMs_ECC_capable) {
 344                 /* Allow setting of ECC only if all DIMMs are ECC. */
 345                 ecc_en = popts->ECC_mode;
 346         } else {
 347                 ecc_en = 0;
 348         }
 349
 350         rd_en = (common_dimm->all_DIMMs_registered
 351                  && !common_dimm->all_DIMMs_unbuffered);
 352
 353         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 354
 355         dyn_pwr = popts->dynamic_power;
 356         dbw = popts->data_bus_width;
 357         eight_be = 0;           /* always 0 for DDR2 */
 358         threeT_en = popts->threeT_en;
 359         twoT_en = popts->twoT_en;
 360         ba_intlv_ctl = popts->ba_intlv_ctl;
 361         hse = popts->half_strength_driver_enable;
 362
 363         ddr->ddr_sdram_cfg = (0
 364                         | ((mem_en & 0x1) << 31)
 365                         | ((sren & 0x1) << 30)
 366                         | ((ecc_en & 0x1) << 29)
 367                         | ((rd_en & 0x1) << 28)
 368                         | ((sdram_type & 0x7) << 24)
 369                         | ((dyn_pwr & 0x1) << 21)
 370                         | ((dbw & 0x3) << 19)
 371                         | ((eight_be & 0x1) << 18)
 372                         | ((ncap & 0x1) << 17)
 373                         | ((threeT_en & 0x1) << 16)
 374                         | ((twoT_en & 0x1) << 15)
 375                         | ((ba_intlv_ctl & 0x7F) << 8)
 376                         | ((x32_en & 0x1) << 5)
 377                         | ((pchb8 & 0x1) << 4)
 378                         | ((hse & 0x1) << 3)
 379                         | ((mem_halt & 0x1) << 1)
 380                         | ((bi & 0x1) << 0)
 381                         );
 382 }
 383
 384 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 385 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 386                                const memctl_options_t *popts)
 387 {
 388         unsigned int frc_sr = 0;        /* Force self refresh */
 389         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 390         unsigned int dll_rst_dis;       /* DLL reset disable */
 391         unsigned int dqs_cfg;           /* DQS configuration */
 392         unsigned int odt_cfg;           /* ODT configuration */
 393         unsigned int num_pr;            /* Number of posted refreshes */
 394         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 395         unsigned int ap_en;             /* Address Parity Enable */
 396         unsigned int d_init;            /* DRAM data initialization */
 397         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 398         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 399
 400         dll_rst_dis = 1;        /* Make this configurable */
 401         dqs_cfg = popts->DQS_config;
 402         if (popts->cs_local_opts[0].odt_rd_cfg
 403             || popts->cs_local_opts[0].odt_wr_cfg) {
 404                 /* FIXME */
 405                 odt_cfg = 2;
 406         } else {
 407                 odt_cfg = 0;
 408         }
 409
 410         num_pr = 1;     /* Make this configurable */
 411
 412         /*
 413          * 8572 manual says
 414          *     {TIMING_CFG_1[PRETOACT]
 415          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 416          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 417          *      << DDR_SDRAM_INTERVAL[REFINT]
 418          */
 419
 420         obc_cfg = 0;    /* Make this configurable? */
 421         ap_en = 0;      /* Make this configurable? */
 422
 423 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 424         /* Use the DDR controller to auto initialize memory. */
 425         d_init = 1;
 426         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 427         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 428 #else
 429         /* Memory will be initialized via DMA, or not at all. */
 430         d_init = 0;
 431 #endif
 432
 433         ddr->ddr_sdram_cfg_2 = (0
 434                 | ((frc_sr & 0x1) << 31)
 435                 | ((sr_ie & 0x1) << 30)
 436                 | ((dll_rst_dis & 0x1) << 29)
 437                 | ((dqs_cfg & 0x3) << 26)
 438                 | ((odt_cfg & 0x3) << 21)
 439                 | ((num_pr & 0xf) << 12)
 440                 | ((obc_cfg & 0x1) << 6)
 441                 | ((ap_en & 0x1) << 5)
 442                 | ((d_init & 0x1) << 4)
 443                 | ((rcw_en & 0x1) << 2)
 444                 | ((md_en & 0x1) << 0)
 445                 );
 446 }
 447
 448 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 449 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr)
 450 {
 451         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 452         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 453
 454         ddr->ddr_sdram_mode_2 = (0
 455                                  | ((esdmode2 & 0xFFFF) << 16)
 456                                  | ((esdmode3 & 0xFFFF) << 0)
 457                                  );
 458 }
 459
 460 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
 461 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 462                                const memctl_options_t *popts,
 463                                const common_timing_params_t *common_dimm)
 464 {
 465         unsigned int refint;    /* Refresh interval */
 466         unsigned int bstopre;   /* Precharge interval */
 467
 468         refint = picos_to_mclk(common_dimm->refresh_rate_ps);
 469
 470         bstopre = popts->bstopre;
 471
 472         /* refint field used 0x3FFF in earlier controllers */
 473         ddr->ddr_sdram_interval = (0
 474                                    | ((refint & 0xFFFF) << 16)
 475                                    | ((bstopre & 0x3FFF) << 0)
 476                                    );
 477 }
 478
 479 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 480 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 481                                const memctl_options_t *popts,
 482                                const common_timing_params_t *common_dimm,
 483                                unsigned int cas_latency,
 484                                unsigned int additive_latency)
 485 {
 486         unsigned short esdmode;         /* Extended SDRAM mode */
 487         unsigned short sdmode;          /* SDRAM mode */
 488
 489         /*
 490          * FIXME: This ought to be pre-calculated in a
 491          * technology-specific routine,
 492          * e.g. compute_DDR2_mode_register(), and then the
 493          * sdmode and esdmode passed in as part of common_dimm.
 494          */
 495
 496         /* Extended Mode Register */
 497         unsigned int mrs = 0;           /* Mode Register Set */
 498         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
 499         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
 500         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
 501         unsigned int ocd = 0;           /* 0x0=OCD not supported,
 502                                            0x7=OCD default state */
 503         unsigned int rtt;
 504         unsigned int al;                /* Posted CAS# additive latency (AL) */
 505         unsigned int ods = 0;           /* Output Drive Strength:
 506                                                 0 = Full strength (18ohm)
 507                                                 1 = Reduced strength (4ohm) */
 508         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
 509                                                        1=Disable (Test/Debug) */
 510
 511         /* Mode Register (MR) */
 512         unsigned int mr;        /* Mode Register Definition */
 513         unsigned int pd;        /* Power-Down Mode */
 514         unsigned int wr;        /* Write Recovery */
 515         unsigned int dll_res;   /* DLL Reset */
 516         unsigned int mode;      /* Normal=0 or Test=1 */
 517         unsigned int caslat = 0;/* CAS# latency */
 518         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
 519         unsigned int bt;
 520         unsigned int bl;        /* BL: Burst Length */
 521
 522 #if defined(CONFIG_FSL_DDR2)
 523         const unsigned int mclk_ps = get_memory_clk_period_ps();
 524 #endif
 525
 526         rtt = fsl_ddr_get_rtt();
 527
 528         al = additive_latency;
 529
 530         esdmode = (0
 531                 | ((mrs & 0x3) << 14)
 532                 | ((outputs & 0x1) << 12)
 533                 | ((rdqs_en & 0x1) << 11)
 534                 | ((dqs_en & 0x1) << 10)
 535                 | ((ocd & 0x7) << 7)
 536                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 537                 | ((al & 0x7) << 3)
 538                 | ((rtt & 0x1) << 2)   /* rtt field is split */
 539                 | ((ods & 0x1) << 1)
 540                 | ((dll_en & 0x1) << 0)
 541                 );
 542
 543         mr = 0;          /* FIXME: CHECKME */
 544
 545         /*
 546          * 0 = Fast Exit (Normal)
 547          * 1 = Slow Exit (Low Power)
 548          */
 549         pd = 0;
 550
 551 #if defined(CONFIG_FSL_DDR1)
 552         wr = 0;       /* Historical */
 553 #elif defined(CONFIG_FSL_DDR2)
 554         wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
 555 #else
 556 #error "Write tWR_auto for DDR3"
 557 #endif
 558         dll_res = 0;
 559         mode = 0;
 560
 561 #if defined(CONFIG_FSL_DDR1)
 562         if (1 <= cas_latency && cas_latency <= 4) {
 563                 unsigned char mode_caslat_table[4] = {
 564                         0x5,    /* 1.5 clocks */
 565                         0x2,    /* 2.0 clocks */
 566                         0x6,    /* 2.5 clocks */
 567                         0x3     /* 3.0 clocks */
 568                 };
 569                 caslat = mode_caslat_table[cas_latency - 1];
 570         } else {
 571                 printf("Warning: unknown cas_latency %d\n", cas_latency);
 572         }
 573 #elif defined(CONFIG_FSL_DDR2)
 574         caslat = cas_latency;
 575 #else
 576 #error "Fix the mode CAS Latency for DDR3"
 577 #endif
 578         bt = 0;
 579
 580         switch (popts->burst_length) {
 581         case 4:
 582                 bl = 2;
 583                 break;
 584         case 8:
 585                 bl = 3;
 586                 break;
 587         default:
 588                 printf("Error: invalid burst length of %u specified. "
 589                         " Defaulting to 4 beats.\n",
 590                         popts->burst_length);
 591                 bl = 2;
 592                 break;
 593         }
 594
 595         sdmode = (0
 596                   | ((mr & 0x3) << 14)
 597                   | ((pd & 0x1) << 12)
 598                   | ((wr & 0x7) << 9)
 599                   | ((dll_res & 0x1) << 8)
 600                   | ((mode & 0x1) << 7)
 601                   | ((caslat & 0x7) << 4)
 602                   | ((bt & 0x1) << 3)
 603                   | ((bl & 0x7) << 0)
 604                   );
 605
 606         ddr->ddr_sdram_mode = (0
 607                                | ((esdmode & 0xFFFF) << 16)
 608                                | ((sdmode & 0xFFFF) << 0)
 609                                );
 610 }
 611
 612
 613 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
 614 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
 615 {
 616         unsigned int init_value;        /* Initialization value */
 617
 618         init_value = 0xDEADBEEF;
 619         ddr->ddr_data_init = init_value;
 620 }
 621
 622 /*
 623  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
 624  * The old controller on the 8540/60 doesn't have this register.
 625  * Hope it's OK to set it (to 0) anyway.
 626  */
 627 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
 628                                          const memctl_options_t *popts)
 629 {
 630         unsigned int clk_adjust;        /* Clock adjust */
 631
 632         clk_adjust = popts->clk_adjust;
 633         ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
 634 }
 635
 636 /* DDR Initialization Address (DDR_INIT_ADDR) */
 637 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
 638 {
 639         unsigned int init_addr = 0;     /* Initialization address */
 640
 641         ddr->ddr_init_addr = init_addr;
 642 }
 643
 644 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
 645 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
 646 {
 647         unsigned int uia = 0;   /* Use initialization address */
 648         unsigned int init_ext_addr = 0; /* Initialization address */
 649
 650         ddr->ddr_init_ext_addr = (0
 651                                   | ((uia & 0x1) << 31)
 652                                   | (init_ext_addr & 0xF)
 653                                   );
 654 }
 655
 656 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
 657 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
 658 {
 659         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
 660         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
 661         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
 662         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
 663         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
 664
 665         ddr->timing_cfg_4 = (0
 666                              | ((rwt & 0xf) << 28)
 667                              | ((wrt & 0xf) << 24)
 668                              | ((rrt & 0xf) << 20)
 669                              | ((wwt & 0xf) << 16)
 670                              | (dll_lock & 0x3)
 671                              );
 672 }
 673
 674 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
 675 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
 676 {
 677         unsigned int rodt_on = 0;       /* Read to ODT on */
 678         unsigned int rodt_off = 0;      /* Read to ODT off */
 679         unsigned int wodt_on = 0;       /* Write to ODT on */
 680         unsigned int wodt_off = 0;      /* Write to ODT off */
 681
 682         ddr->timing_cfg_5 = (0
 683                              | ((rodt_on & 0xf) << 24)
 684                              | ((rodt_off & 0xf) << 20)
 685                              | ((wodt_on & 0xf) << 12)
 686                              | ((wodt_off & 0xf) << 8)
 687                              );
 688 }
 689
 690 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
 691 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr)
 692 {
 693         unsigned int zq_en = 0; /* ZQ Calibration Enable */
 694         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
 695         /* Normal Operation Full Calibration Time (tZQoper) */
 696         unsigned int zqoper = 0;
 697         /* Normal Operation Short Calibration Time (tZQCS) */
 698         unsigned int zqcs = 0;
 699
 700         ddr->ddr_zq_cntl = (0
 701                             | ((zq_en & 0x1) << 31)
 702                             | ((zqinit & 0xF) << 24)
 703                             | ((zqoper & 0xF) << 16)
 704                             | ((zqcs & 0xF) << 8)
 705                             );
 706 }
 707
 708 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
 709 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr)
 710 {
 711         unsigned int wrlvl_en = 0; /* Write Leveling Enable */
 712         /*
 713          * First DQS pulse rising edge after margining mode
 714          * is programmed (tWL_MRD)
 715          */
 716         unsigned int wrlvl_mrd = 0;
 717         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
 718         unsigned int wrlvl_odten = 0;
 719         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
 720         unsigned int wrlvl_dqsen = 0;
 721         /* WRLVL_SMPL: Write leveling sample time */
 722         unsigned int wrlvl_smpl = 0;
 723         /* WRLVL_WLR: Write leveling repeition time */
 724         unsigned int wrlvl_wlr = 0;
 725         /* WRLVL_START: Write leveling start time */
 726         unsigned int wrlvl_start = 0;
 727
 728         ddr->ddr_wrlvl_cntl = (0
 729                                | ((wrlvl_en & 0x1) << 31)
 730                                | ((wrlvl_mrd & 0x7) << 24)
 731                                | ((wrlvl_odten & 0x7) << 20)
 732                                | ((wrlvl_dqsen & 0x7) << 16)
 733                                | ((wrlvl_smpl & 0xf) << 12)
 734                                | ((wrlvl_wlr & 0x7) << 8)
 735                                | ((wrlvl_start & 0xF) << 0)
 736                                );
 737 }
 738
 739 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
 740 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr)
 741 {
 742         unsigned int sr_it = 0; /* Self Refresh Idle Threshold */
 743
 744         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
 745 }
 746
 747 /* DDR Pre-Drive Conditioning Control (DDR_PD_CNTL) */
 748 static void set_ddr_pd_cntl(fsl_ddr_cfg_regs_t *ddr)
 749 {
 750         /* Termination value during pre-drive conditioning */
 751         unsigned int tvpd = 0;
 752         unsigned int pd_en = 0;         /* Pre-Drive Conditioning Enable */
 753         unsigned int pdar = 0;          /* Pre-Drive After Read */
 754         unsigned int pdaw = 0;          /* Pre-Drive After Write */
 755         unsigned int pd_on = 0;         /* Pre-Drive Conditioning On */
 756         unsigned int pd_off = 0;        /* Pre-Drive Conditioning Off */
 757
 758         ddr->ddr_pd_cntl = (0
 759                             | ((pd_en & 0x1) << 31)
 760                             | ((tvpd & 0x7) << 28)
 761                             | ((pdar & 0x7F) << 20)
 762                             | ((pdaw & 0x7F) << 12)
 763                             | ((pd_on & 0x1F) << 6)
 764                             | ((pd_off & 0x1F) << 0)
 765                             );
 766 }
 767
 768
 769 /* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */
 770 static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr)
 771 {
 772         unsigned int rcw0 = 0;  /* RCW0: Register Control Word 0 */
 773         unsigned int rcw1 = 0;  /* RCW1: Register Control Word 1 */
 774         unsigned int rcw2 = 0;  /* RCW2: Register Control Word 2 */
 775         unsigned int rcw3 = 0;  /* RCW3: Register Control Word 3 */
 776         unsigned int rcw4 = 0;  /* RCW4: Register Control Word 4 */
 777         unsigned int rcw5 = 0;  /* RCW5: Register Control Word 5 */
 778         unsigned int rcw6 = 0;  /* RCW6: Register Control Word 6 */
 779         unsigned int rcw7 = 0;  /* RCW7: Register Control Word 7 */
 780
 781         ddr->ddr_sdram_rcw_1 = (0
 782                                 | ((rcw0 & 0xF) << 28)
 783                                 | ((rcw1 & 0xF) << 24)
 784                                 | ((rcw2 & 0xF) << 20)
 785                                 | ((rcw3 & 0xF) << 16)
 786                                 | ((rcw4 & 0xF) << 12)
 787                                 | ((rcw5 & 0xF) << 8)
 788                                 | ((rcw6 & 0xF) << 4)
 789                                 | ((rcw7 & 0xF) << 0)
 790                                 );
 791 }
 792
 793 /* DDR SDRAM Register Control Word 2 (DDR_SDRAM_RCW_2) */
 794 static void set_ddr_sdram_rcw_2(fsl_ddr_cfg_regs_t *ddr)
 795 {
 796         unsigned int rcw8 = 0;  /* RCW0: Register Control Word 8 */
 797         unsigned int rcw9 = 0;  /* RCW1: Register Control Word 9 */
 798         unsigned int rcw10 = 0; /* RCW2: Register Control Word 10 */
 799         unsigned int rcw11 = 0; /* RCW3: Register Control Word 11 */
 800         unsigned int rcw12 = 0; /* RCW4: Register Control Word 12 */
 801         unsigned int rcw13 = 0; /* RCW5: Register Control Word 13 */
 802         unsigned int rcw14 = 0; /* RCW6: Register Control Word 14 */
 803         unsigned int rcw15 = 0; /* RCW7: Register Control Word 15 */
 804
 805         ddr->ddr_sdram_rcw_2 = (0
 806                                 | ((rcw8 & 0xF) << 28)
 807                                 | ((rcw9 & 0xF) << 24)
 808                                 | ((rcw10 & 0xF) << 20)
 809                                 | ((rcw11 & 0xF) << 16)
 810                                 | ((rcw12 & 0xF) << 12)
 811                                 | ((rcw13 & 0xF) << 8)
 812                                 | ((rcw14 & 0xF) << 4)
 813                                 | ((rcw15 & 0xF) << 0)
 814                                 );
 815 }
 816
 817 unsigned int
 818 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 819 {
 820         unsigned int res = 0;
 821
 822         /*
 823          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
 824          * not set at the same time.
 825          */
 826         if (ddr->ddr_sdram_cfg & 0x10000000
 827             && ddr->ddr_sdram_cfg & 0x00008000) {
 828                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
 829                                 " should not be set at the same time.\n");
 830                 res++;
 831         }
 832
 833         return res;
 834 }
 835
 836 unsigned int
 837 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 838                                fsl_ddr_cfg_regs_t *ddr,
 839                                const common_timing_params_t *common_dimm,
 840                                const dimm_params_t *dimm_params,
 841                                unsigned int dbw_cap_adj)
 842 {
 843         unsigned int i;
 844         unsigned int cas_latency;
 845         unsigned int additive_latency;
 846
 847         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
 848
 849         if (common_dimm == NULL) {
 850                 printf("Error: subset DIMM params struct null pointer\n");
 851                 return 1;
 852         }
 853
 854         /*
 855          * Process overrides first.
 856          *
 857          * FIXME: somehow add dereated caslat to this
 858          */
 859         cas_latency = (popts->cas_latency_override)
 860                 ? popts->cas_latency_override_value
 861                 : common_dimm->lowest_common_SPD_caslat;
 862
 863         additive_latency = (popts->additive_latency_override)
 864                 ? popts->additive_latency_override_value
 865                 : common_dimm->additive_latency;
 866
 867         /* Chip Select Memory Bounds (CSn_BNDS) */
 868         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 869                 phys_size_t sa = 0;
 870                 phys_size_t ea = 0;
 871
 872                 if (popts->ba_intlv_ctl && (i > 0) &&
 873                         ((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) {
 874                         /* Don't set up boundaries for other CS
 875                          * other than CS0, if bank interleaving
 876                          * is enabled and not CS2+CS3 interleaved.
 877                          */
 878                         break;
 879                 }
 880
 881                 if (dimm_params[i/2].n_ranks == 0) {
 882                         debug("Skipping setup of CS%u "
 883                                 "because n_ranks on DIMM %u is 0\n", i, i/2);
 884                         continue;
 885                 }
 886                 if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
 887                         /*
 888                          * This works superbank 2CS
 889                          * There are 2 memory controllers configured
 890                          * identically, memory is interleaved between them,
 891                          * and each controller uses rank interleaving within
 892                          * itself. Therefore the starting and ending address
 893                          * on each controller is twice the amount present on
 894                          * each controller.
 895                          */
 896                         unsigned long long rank_density
 897                                         = dimm_params[0].capacity;
 898                         ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
 899                 }
 900                 else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
 901                         /*
 902                          * If memory interleaving between controllers is NOT
 903                          * enabled, the starting address for each memory
 904                          * controller is distinct.  However, because rank
 905                          * interleaving is enabled, the starting and ending
 906                          * addresses of the total memory on that memory
 907                          * controller needs to be programmed into its
 908                          * respective CS0_BNDS.
 909                          */
 910                         unsigned long long rank_density
 911                                                 = dimm_params[i/2].rank_density;
 912                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
 913                         case FSL_DDR_CS0_CS1_CS2_CS3:
 914                                 /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
 915                                  * needs to be set.
 916                                  */
 917                                 sa = common_dimm->base_address;
 918                                 ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
 919                                 break;
 920                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 921                                 /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
 922                                  * and CS2_CNDS need to be set.
 923                                  */
 924                                 if (!(i&1)) {
 925                                         sa = dimm_params[i/2].base_address;
 926                                         ea = sa + (i * (rank_density >>
 927                                                 dbw_cap_adj)) - 1;
 928                                 }
 929                                 break;
 930                         case FSL_DDR_CS0_CS1:
 931                                 /* CS0+CS1 interleaving, CS0_CNDS needs
 932                                  * to be set
 933                                  */
 934                                 sa = common_dimm->base_address;
 935                                 ea = sa + (2 * (rank_density >> dbw_cap_adj))-1;
 936                                 break;
 937                         case FSL_DDR_CS2_CS3:
 938                                 /* CS2+CS3 interleaving*/
 939                                 if (i == 2) {
 940                                         sa = dimm_params[i/2].base_address;
 941                                         ea = sa + (2 * (rank_density >>
 942                                                 dbw_cap_adj)) - 1;
 943                                 }
 944                                 break;
 945                         default:  /* No bank(chip-select) interleaving */
 946                                 break;
 947                         }
 948                 }
 949                 else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
 950                         /*
 951                          * Only the rank on CS0 of each memory controller may
 952                          * be used if memory controller interleaving is used
 953                          * without rank interleaving within each memory
 954                          * controller.  However, the ending address programmed
 955                          * into each CS0 must be the sum of the amount of
 956                          * memory in the two CS0 ranks.
 957                          */
 958                         if (i == 0) {
 959                                 unsigned long long rank_density
 960                                                 = dimm_params[0].rank_density;
 961                                 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
 962                         }
 963
 964                 }
 965                 else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
 966                         /*
 967                          * No rank interleaving and no memory controller
 968                          * interleaving.
 969                          */
 970                         unsigned long long rank_density
 971                                                 = dimm_params[i/2].rank_density;
 972                         sa = dimm_params[i/2].base_address;
 973                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
 974                         if (i&1) {
 975                                 if ((dimm_params[i/2].n_ranks == 1)) {
 976                                         /* Odd chip select, single-rank dimm */
 977                                         sa = 0;
 978                                         ea = 0;
 979                                 } else {
 980                                         /* Odd chip select, dual-rank DIMM */
 981                                         sa += rank_density >> dbw_cap_adj;
 982                                         ea += rank_density >> dbw_cap_adj;
 983                                 }
 984                         }
 985                 }
 986
 987                 sa >>= 24;
 988                 ea >>= 24;
 989
 990                 ddr->cs[i].bnds = (0
 991                         | ((sa & 0xFFF) << 16)  /* starting address MSB */
 992                         | ((ea & 0xFFF) << 0)   /* ending address MSB */
 993                         );
 994
 995                 set_csn_config(i, ddr, popts, dimm_params);
 996                 set_csn_config_2(i, ddr);
 997         }
 998
 999 #if defined(CONFIG_FSL_DDR2)
1000         set_timing_cfg_0(ddr);
1001 #endif
1002
1003         set_timing_cfg_3(ddr, common_dimm);
1004         set_timing_cfg_1(ddr, common_dimm, cas_latency);
1005         set_timing_cfg_2(ddr, popts, common_dimm,
1006                                 cas_latency, additive_latency);
1007
1008         set_ddr_sdram_cfg(ddr, popts, common_dimm);
1009
1010         set_ddr_sdram_cfg_2(ddr, popts);
1011         set_ddr_sdram_mode(ddr, popts, common_dimm,
1012                                 cas_latency, additive_latency);
1013         set_ddr_sdram_mode_2(ddr);
1014         set_ddr_sdram_interval(ddr, popts, common_dimm);
1015         set_ddr_data_init(ddr);
1016         set_ddr_sdram_clk_cntl(ddr, popts);
1017         set_ddr_init_addr(ddr);
1018         set_ddr_init_ext_addr(ddr);
1019         set_timing_cfg_4(ddr);
1020         set_timing_cfg_5(ddr);
1021
1022         set_ddr_zq_cntl(ddr);
1023         set_ddr_wrlvl_cntl(ddr);
1024
1025         set_ddr_pd_cntl(ddr);
1026         set_ddr_sr_cntr(ddr);
1027
1028         set_ddr_sdram_rcw_1(ddr);
1029         set_ddr_sdram_rcw_2(ddr);
1030
1031         return check_fsl_memctl_config_regs(ddr);
1032 }