2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
30 #include <linux/log2.h>
33 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 /* Rough estimate of the typical request size, performing a flush,
38 * set-context and then emitting the batch.
40 #define LEGACY_REQUEST_SIZE 200
42 int __intel_ring_space(int head, int tail, int size)
44 int space = head - tail;
47 return space - I915_RING_FREE_SPACE;
50 void intel_ring_update_space(struct intel_ring *ring)
52 if (ring->last_retired_head != -1) {
53 ring->head = ring->last_retired_head;
54 ring->last_retired_head = -1;
57 ring->space = __intel_ring_space(ring->head & HEAD_ADDR,
58 ring->tail, ring->size);
62 gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
64 struct intel_ring *ring = req->ring;
70 if (mode & EMIT_INVALIDATE)
73 ret = intel_ring_begin(req, 2);
77 intel_ring_emit(ring, cmd);
78 intel_ring_emit(ring, MI_NOOP);
79 intel_ring_advance(ring);
85 gen4_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
87 struct intel_ring *ring = req->ring;
94 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
95 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
96 * also flushed at 2d versus 3d pipeline switches.
100 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
101 * MI_READ_FLUSH is set, and is always flushed on 965.
103 * I915_GEM_DOMAIN_COMMAND may not exist?
105 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
106 * invalidated when MI_EXE_FLUSH is set.
108 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
109 * invalidated with every MI_FLUSH.
113 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
114 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
115 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
116 * are flushed at any MI_FLUSH.
120 if (mode & EMIT_INVALIDATE) {
122 if (IS_G4X(req->i915) || IS_GEN5(req->i915))
123 cmd |= MI_INVALIDATE_ISP;
126 ret = intel_ring_begin(req, 2);
130 intel_ring_emit(ring, cmd);
131 intel_ring_emit(ring, MI_NOOP);
132 intel_ring_advance(ring);
138 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
139 * implementing two workarounds on gen6. From section 1.4.7.1
140 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
142 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
143 * produced by non-pipelined state commands), software needs to first
144 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
147 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
148 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
150 * And the workaround for these two requires this workaround first:
152 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
153 * BEFORE the pipe-control with a post-sync op and no write-cache
156 * And this last workaround is tricky because of the requirements on
157 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
160 * "1 of the following must also be set:
161 * - Render Target Cache Flush Enable ([12] of DW1)
162 * - Depth Cache Flush Enable ([0] of DW1)
163 * - Stall at Pixel Scoreboard ([1] of DW1)
164 * - Depth Stall ([13] of DW1)
165 * - Post-Sync Operation ([13] of DW1)
166 * - Notify Enable ([8] of DW1)"
168 * The cache flushes require the workaround flush that triggered this
169 * one, so we can't use it. Depth stall would trigger the same.
170 * Post-sync nonzero is what triggered this second workaround, so we
171 * can't use that one either. Notify enable is IRQs, which aren't
172 * really our business. That leaves only stall at scoreboard.
175 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
177 struct intel_ring *ring = req->ring;
179 req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
182 ret = intel_ring_begin(req, 6);
186 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
187 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
188 PIPE_CONTROL_STALL_AT_SCOREBOARD);
189 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
190 intel_ring_emit(ring, 0); /* low dword */
191 intel_ring_emit(ring, 0); /* high dword */
192 intel_ring_emit(ring, MI_NOOP);
193 intel_ring_advance(ring);
195 ret = intel_ring_begin(req, 6);
199 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
200 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
201 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
202 intel_ring_emit(ring, 0);
203 intel_ring_emit(ring, 0);
204 intel_ring_emit(ring, MI_NOOP);
205 intel_ring_advance(ring);
211 gen6_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
213 struct intel_ring *ring = req->ring;
215 req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
219 /* Force SNB workarounds for PIPE_CONTROL flushes */
220 ret = intel_emit_post_sync_nonzero_flush(req);
224 /* Just flush everything. Experiments have shown that reducing the
225 * number of bits based on the write domains has little performance
228 if (mode & EMIT_FLUSH) {
229 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
230 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
232 * Ensure that any following seqno writes only happen
233 * when the render cache is indeed flushed.
235 flags |= PIPE_CONTROL_CS_STALL;
237 if (mode & EMIT_INVALIDATE) {
238 flags |= PIPE_CONTROL_TLB_INVALIDATE;
239 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
240 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
241 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
243 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
245 * TLB invalidate requires a post-sync write.
247 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
250 ret = intel_ring_begin(req, 4);
254 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
255 intel_ring_emit(ring, flags);
256 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
257 intel_ring_emit(ring, 0);
258 intel_ring_advance(ring);
264 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
266 struct intel_ring *ring = req->ring;
269 ret = intel_ring_begin(req, 4);
273 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(ring,
275 PIPE_CONTROL_CS_STALL |
276 PIPE_CONTROL_STALL_AT_SCOREBOARD);
277 intel_ring_emit(ring, 0);
278 intel_ring_emit(ring, 0);
279 intel_ring_advance(ring);
285 gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
287 struct intel_ring *ring = req->ring;
289 req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
294 * Ensure that any following seqno writes only happen when the render
295 * cache is indeed flushed.
297 * Workaround: 4th PIPE_CONTROL command (except the ones with only
298 * read-cache invalidate bits set) must have the CS_STALL bit set. We
299 * don't try to be clever and just set it unconditionally.
301 flags |= PIPE_CONTROL_CS_STALL;
303 /* Just flush everything. Experiments have shown that reducing the
304 * number of bits based on the write domains has little performance
307 if (mode & EMIT_FLUSH) {
308 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
309 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
310 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
311 flags |= PIPE_CONTROL_FLUSH_ENABLE;
313 if (mode & EMIT_INVALIDATE) {
314 flags |= PIPE_CONTROL_TLB_INVALIDATE;
315 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
316 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
317 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
318 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
319 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
320 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
322 * TLB invalidate requires a post-sync write.
324 flags |= PIPE_CONTROL_QW_WRITE;
325 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
327 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
329 /* Workaround: we must issue a pipe_control with CS-stall bit
330 * set before a pipe_control command that has the state cache
331 * invalidate bit set. */
332 gen7_render_ring_cs_stall_wa(req);
335 ret = intel_ring_begin(req, 4);
339 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
340 intel_ring_emit(ring, flags);
341 intel_ring_emit(ring, scratch_addr);
342 intel_ring_emit(ring, 0);
343 intel_ring_advance(ring);
349 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
350 u32 flags, u32 scratch_addr)
352 struct intel_ring *ring = req->ring;
355 ret = intel_ring_begin(req, 6);
359 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
360 intel_ring_emit(ring, flags);
361 intel_ring_emit(ring, scratch_addr);
362 intel_ring_emit(ring, 0);
363 intel_ring_emit(ring, 0);
364 intel_ring_emit(ring, 0);
365 intel_ring_advance(ring);
371 gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
373 u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
377 flags |= PIPE_CONTROL_CS_STALL;
379 if (mode & EMIT_FLUSH) {
380 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
381 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
382 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
383 flags |= PIPE_CONTROL_FLUSH_ENABLE;
385 if (mode & EMIT_INVALIDATE) {
386 flags |= PIPE_CONTROL_TLB_INVALIDATE;
387 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
388 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
389 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
390 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
391 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
392 flags |= PIPE_CONTROL_QW_WRITE;
393 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
395 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
396 ret = gen8_emit_pipe_control(req,
397 PIPE_CONTROL_CS_STALL |
398 PIPE_CONTROL_STALL_AT_SCOREBOARD,
404 return gen8_emit_pipe_control(req, flags, scratch_addr);
407 u64 intel_engine_get_active_head(struct intel_engine_cs *engine)
409 struct drm_i915_private *dev_priv = engine->i915;
412 if (INTEL_GEN(dev_priv) >= 8)
413 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
414 RING_ACTHD_UDW(engine->mmio_base));
415 else if (INTEL_GEN(dev_priv) >= 4)
416 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
418 acthd = I915_READ(ACTHD);
423 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
425 struct drm_i915_private *dev_priv = engine->i915;
428 addr = dev_priv->status_page_dmah->busaddr;
429 if (INTEL_GEN(dev_priv) >= 4)
430 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
431 I915_WRITE(HWS_PGA, addr);
434 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
436 struct drm_i915_private *dev_priv = engine->i915;
439 /* The ring status page addresses are no longer next to the rest of
440 * the ring registers as of gen7.
442 if (IS_GEN7(dev_priv)) {
443 switch (engine->id) {
445 mmio = RENDER_HWS_PGA_GEN7;
448 mmio = BLT_HWS_PGA_GEN7;
451 * VCS2 actually doesn't exist on Gen7. Only shut up
452 * gcc switch check warning
456 mmio = BSD_HWS_PGA_GEN7;
459 mmio = VEBOX_HWS_PGA_GEN7;
462 } else if (IS_GEN6(dev_priv)) {
463 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
465 /* XXX: gen8 returns to sanity */
466 mmio = RING_HWS_PGA(engine->mmio_base);
469 I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
473 * Flush the TLB for this page
475 * FIXME: These two bits have disappeared on gen8, so a question
476 * arises: do we still need this and if so how should we go about
477 * invalidating the TLB?
479 if (IS_GEN(dev_priv, 6, 7)) {
480 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
482 /* ring should be idle before issuing a sync flush*/
483 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
486 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
488 if (intel_wait_for_register(dev_priv,
489 reg, INSTPM_SYNC_FLUSH, 0,
491 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
496 static bool stop_ring(struct intel_engine_cs *engine)
498 struct drm_i915_private *dev_priv = engine->i915;
500 if (!IS_GEN2(dev_priv)) {
501 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
502 if (intel_wait_for_register(dev_priv,
503 RING_MI_MODE(engine->mmio_base),
507 DRM_ERROR("%s : timed out trying to stop ring\n",
509 /* Sometimes we observe that the idle flag is not
510 * set even though the ring is empty. So double
511 * check before giving up.
513 if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
518 I915_WRITE_CTL(engine, 0);
519 I915_WRITE_HEAD(engine, 0);
520 I915_WRITE_TAIL(engine, 0);
522 if (!IS_GEN2(dev_priv)) {
523 (void)I915_READ_CTL(engine);
524 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
527 return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
530 static int init_ring_common(struct intel_engine_cs *engine)
532 struct drm_i915_private *dev_priv = engine->i915;
533 struct intel_ring *ring = engine->buffer;
534 struct drm_i915_gem_object *obj = ring->obj;
537 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
539 if (!stop_ring(engine)) {
540 /* G45 ring initialization often fails to reset head to zero */
541 DRM_DEBUG_KMS("%s head not reset to zero "
542 "ctl %08x head %08x tail %08x start %08x\n",
544 I915_READ_CTL(engine),
545 I915_READ_HEAD(engine),
546 I915_READ_TAIL(engine),
547 I915_READ_START(engine));
549 if (!stop_ring(engine)) {
550 DRM_ERROR("failed to set %s head to zero "
551 "ctl %08x head %08x tail %08x start %08x\n",
553 I915_READ_CTL(engine),
554 I915_READ_HEAD(engine),
555 I915_READ_TAIL(engine),
556 I915_READ_START(engine));
562 if (I915_NEED_GFX_HWS(dev_priv))
563 intel_ring_setup_status_page(engine);
565 ring_setup_phys_status_page(engine);
567 /* Enforce ordering by reading HEAD register back */
568 I915_READ_HEAD(engine);
570 /* Initialize the ring. This must happen _after_ we've cleared the ring
571 * registers with the above sequence (the readback of the HEAD registers
572 * also enforces ordering), otherwise the hw might lose the new ring
573 * register values. */
574 I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
576 /* WaClearRingBufHeadRegAtInit:ctg,elk */
577 if (I915_READ_HEAD(engine))
578 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
579 engine->name, I915_READ_HEAD(engine));
580 I915_WRITE_HEAD(engine, 0);
581 (void)I915_READ_HEAD(engine);
583 I915_WRITE_CTL(engine,
584 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
587 /* If the head is still not zero, the ring is dead */
588 if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
589 I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
590 (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
591 DRM_ERROR("%s initialization failed "
592 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
594 I915_READ_CTL(engine),
595 I915_READ_CTL(engine) & RING_VALID,
596 I915_READ_HEAD(engine), I915_READ_TAIL(engine),
597 I915_READ_START(engine),
598 (unsigned long)i915_gem_obj_ggtt_offset(obj));
603 ring->last_retired_head = -1;
604 ring->head = I915_READ_HEAD(engine);
605 ring->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
606 intel_ring_update_space(ring);
608 intel_engine_init_hangcheck(engine);
611 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
616 void intel_fini_pipe_control(struct intel_engine_cs *engine)
618 if (engine->scratch.obj == NULL)
621 i915_gem_object_ggtt_unpin(engine->scratch.obj);
622 i915_gem_object_put(engine->scratch.obj);
623 engine->scratch.obj = NULL;
626 int intel_init_pipe_control(struct intel_engine_cs *engine, int size)
628 struct drm_i915_gem_object *obj;
631 WARN_ON(engine->scratch.obj);
633 obj = i915_gem_object_create_stolen(&engine->i915->drm, size);
635 obj = i915_gem_object_create(&engine->i915->drm, size);
637 DRM_ERROR("Failed to allocate scratch page\n");
642 ret = i915_gem_object_ggtt_pin(obj, NULL, 0, 4096, PIN_HIGH);
646 engine->scratch.obj = obj;
647 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
648 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
649 engine->name, engine->scratch.gtt_offset);
653 i915_gem_object_put(engine->scratch.obj);
658 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
660 struct intel_ring *ring = req->ring;
661 struct i915_workarounds *w = &req->i915->workarounds;
667 ret = req->engine->emit_flush(req, EMIT_BARRIER);
671 ret = intel_ring_begin(req, (w->count * 2 + 2));
675 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
676 for (i = 0; i < w->count; i++) {
677 intel_ring_emit_reg(ring, w->reg[i].addr);
678 intel_ring_emit(ring, w->reg[i].value);
680 intel_ring_emit(ring, MI_NOOP);
682 intel_ring_advance(ring);
684 ret = req->engine->emit_flush(req, EMIT_BARRIER);
688 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
693 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
697 ret = intel_ring_workarounds_emit(req);
701 ret = i915_gem_render_state_init(req);
708 static int wa_add(struct drm_i915_private *dev_priv,
710 const u32 mask, const u32 val)
712 const u32 idx = dev_priv->workarounds.count;
714 if (WARN_ON(idx >= I915_MAX_WA_REGS))
717 dev_priv->workarounds.reg[idx].addr = addr;
718 dev_priv->workarounds.reg[idx].value = val;
719 dev_priv->workarounds.reg[idx].mask = mask;
721 dev_priv->workarounds.count++;
726 #define WA_REG(addr, mask, val) do { \
727 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
732 #define WA_SET_BIT_MASKED(addr, mask) \
733 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
735 #define WA_CLR_BIT_MASKED(addr, mask) \
736 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
738 #define WA_SET_FIELD_MASKED(addr, mask, value) \
739 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
741 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
742 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
744 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
746 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
749 struct drm_i915_private *dev_priv = engine->i915;
750 struct i915_workarounds *wa = &dev_priv->workarounds;
751 const uint32_t index = wa->hw_whitelist_count[engine->id];
753 if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
756 WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
757 i915_mmio_reg_offset(reg));
758 wa->hw_whitelist_count[engine->id]++;
763 static int gen8_init_workarounds(struct intel_engine_cs *engine)
765 struct drm_i915_private *dev_priv = engine->i915;
767 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
769 /* WaDisableAsyncFlipPerfMode:bdw,chv */
770 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
772 /* WaDisablePartialInstShootdown:bdw,chv */
773 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
774 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
776 /* Use Force Non-Coherent whenever executing a 3D context. This is a
777 * workaround for for a possible hang in the unlikely event a TLB
778 * invalidation occurs during a PSD flush.
780 /* WaForceEnableNonCoherent:bdw,chv */
781 /* WaHdcDisableFetchWhenMasked:bdw,chv */
782 WA_SET_BIT_MASKED(HDC_CHICKEN0,
783 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
784 HDC_FORCE_NON_COHERENT);
786 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
787 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
788 * polygons in the same 8x4 pixel/sample area to be processed without
789 * stalling waiting for the earlier ones to write to Hierarchical Z
792 * This optimization is off by default for BDW and CHV; turn it on.
794 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
796 /* Wa4x4STCOptimizationDisable:bdw,chv */
797 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
800 * BSpec recommends 8x4 when MSAA is used,
801 * however in practice 16x4 seems fastest.
803 * Note that PS/WM thread counts depend on the WIZ hashing
804 * disable bit, which we don't touch here, but it's good
805 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
807 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
808 GEN6_WIZ_HASHING_MASK,
809 GEN6_WIZ_HASHING_16x4);
814 static int bdw_init_workarounds(struct intel_engine_cs *engine)
816 struct drm_i915_private *dev_priv = engine->i915;
819 ret = gen8_init_workarounds(engine);
823 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
824 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
826 /* WaDisableDopClockGating:bdw */
827 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
828 DOP_CLOCK_GATING_DISABLE);
830 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
831 GEN8_SAMPLER_POWER_BYPASS_DIS);
833 WA_SET_BIT_MASKED(HDC_CHICKEN0,
834 /* WaForceContextSaveRestoreNonCoherent:bdw */
835 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
836 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
837 (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
842 static int chv_init_workarounds(struct intel_engine_cs *engine)
844 struct drm_i915_private *dev_priv = engine->i915;
847 ret = gen8_init_workarounds(engine);
851 /* WaDisableThreadStallDopClockGating:chv */
852 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
854 /* Improve HiZ throughput on CHV. */
855 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
860 static int gen9_init_workarounds(struct intel_engine_cs *engine)
862 struct drm_i915_private *dev_priv = engine->i915;
865 /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */
866 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
868 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
869 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
870 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
872 /* WaDisableKillLogic:bxt,skl,kbl */
873 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
876 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
877 /* WaDisablePartialInstShootdown:skl,bxt,kbl */
878 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
879 FLOW_CONTROL_ENABLE |
880 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
882 /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
883 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
884 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
886 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
887 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
888 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
889 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
890 GEN9_DG_MIRROR_FIX_ENABLE);
892 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
893 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
894 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
895 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
896 GEN9_RHWO_OPTIMIZATION_DISABLE);
898 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
899 * but we do that in per ctx batchbuffer as there is an issue
900 * with this register not getting restored on ctx restore
904 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
905 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
906 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
907 GEN9_ENABLE_YV12_BUGFIX |
908 GEN9_ENABLE_GPGPU_PREEMPTION);
910 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
911 /* WaDisablePartialResolveInVc:skl,bxt,kbl */
912 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
913 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
915 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
916 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
917 GEN9_CCS_TLB_PREFETCH_ENABLE);
919 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
920 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) ||
921 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
922 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
923 PIXEL_MASK_CAMMING_DISABLE);
925 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
926 WA_SET_BIT_MASKED(HDC_CHICKEN0,
927 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
928 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
930 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
931 * both tied to WaForceContextSaveRestoreNonCoherent
932 * in some hsds for skl. We keep the tie for all gen9. The
933 * documentation is a bit hazy and so we want to get common behaviour,
934 * even though there is no clear evidence we would need both on kbl/bxt.
935 * This area has been source of system hangs so we play it safe
936 * and mimic the skl regardless of what bspec says.
938 * Use Force Non-Coherent whenever executing a 3D context. This
939 * is a workaround for a possible hang in the unlikely event
940 * a TLB invalidation occurs during a PSD flush.
943 /* WaForceEnableNonCoherent:skl,bxt,kbl */
944 WA_SET_BIT_MASKED(HDC_CHICKEN0,
945 HDC_FORCE_NON_COHERENT);
947 /* WaDisableHDCInvalidation:skl,bxt,kbl */
948 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
949 BDW_DISABLE_HDC_INVALIDATION);
951 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
952 if (IS_SKYLAKE(dev_priv) ||
953 IS_KABYLAKE(dev_priv) ||
954 IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
955 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
956 GEN8_SAMPLER_POWER_BYPASS_DIS);
958 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
959 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
961 /* WaOCLCoherentLineFlush:skl,bxt,kbl */
962 I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
963 GEN8_LQSC_FLUSH_COHERENT_LINES));
965 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
966 ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
970 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
971 ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
975 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
976 ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
983 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
985 struct drm_i915_private *dev_priv = engine->i915;
986 u8 vals[3] = { 0, 0, 0 };
989 for (i = 0; i < 3; i++) {
993 * Only consider slices where one, and only one, subslice has 7
996 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1000 * subslice_7eu[i] != 0 (because of the check above) and
1001 * ss_max == 4 (maximum number of subslices possible per slice)
1005 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1009 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1012 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1013 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1014 GEN9_IZ_HASHING_MASK(2) |
1015 GEN9_IZ_HASHING_MASK(1) |
1016 GEN9_IZ_HASHING_MASK(0),
1017 GEN9_IZ_HASHING(2, vals[2]) |
1018 GEN9_IZ_HASHING(1, vals[1]) |
1019 GEN9_IZ_HASHING(0, vals[0]));
1024 static int skl_init_workarounds(struct intel_engine_cs *engine)
1026 struct drm_i915_private *dev_priv = engine->i915;
1029 ret = gen9_init_workarounds(engine);
1034 * Actual WA is to disable percontext preemption granularity control
1035 * until D0 which is the default case so this is equivalent to
1036 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1038 if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) {
1039 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1040 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1043 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) {
1044 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1045 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1046 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1049 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1050 * involving this register should also be added to WA batch as required.
1052 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0))
1053 /* WaDisableLSQCROPERFforOCL:skl */
1054 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1055 GEN8_LQSC_RO_PERF_DIS);
1057 /* WaEnableGapsTsvCreditFix:skl */
1058 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
1059 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1060 GEN9_GAPS_TSV_CREDIT_DISABLE));
1063 /* WaDisablePowerCompilerClockGating:skl */
1064 if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
1065 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1066 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1068 /* WaBarrierPerformanceFixDisable:skl */
1069 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
1070 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1071 HDC_FENCE_DEST_SLM_DISABLE |
1072 HDC_BARRIER_PERFORMANCE_DISABLE);
1074 /* WaDisableSbeCacheDispatchPortSharing:skl */
1075 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
1077 GEN7_HALF_SLICE_CHICKEN1,
1078 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1080 /* WaDisableGafsUnitClkGating:skl */
1081 WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1083 /* WaInPlaceDecompressionHang:skl */
1084 if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
1085 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
1086 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1088 /* WaDisableLSQCROPERFforOCL:skl */
1089 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1093 return skl_tune_iz_hashing(engine);
1096 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1098 struct drm_i915_private *dev_priv = engine->i915;
1101 ret = gen9_init_workarounds(engine);
1105 /* WaStoreMultiplePTEenable:bxt */
1106 /* This is a requirement according to Hardware specification */
1107 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1108 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1110 /* WaSetClckGatingDisableMedia:bxt */
1111 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
1112 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1113 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1116 /* WaDisableThreadStallDopClockGating:bxt */
1117 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1118 STALL_DOP_GATING_DISABLE);
1120 /* WaDisablePooledEuLoadBalancingFix:bxt */
1121 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
1122 WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
1123 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
1126 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1127 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
1129 GEN7_HALF_SLICE_CHICKEN1,
1130 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1133 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1134 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1135 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1136 /* WaDisableLSQCROPERFforOCL:bxt */
1137 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
1138 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1142 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1147 /* WaProgramL3SqcReg1DefaultForPerf:bxt */
1148 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
1149 I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
1150 L3_HIGH_PRIO_CREDITS(2));
1152 /* WaInsertDummyPushConstPs:bxt */
1153 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
1154 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1155 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1157 /* WaInPlaceDecompressionHang:bxt */
1158 if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
1159 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
1160 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1165 static int kbl_init_workarounds(struct intel_engine_cs *engine)
1167 struct drm_i915_private *dev_priv = engine->i915;
1170 ret = gen9_init_workarounds(engine);
1174 /* WaEnableGapsTsvCreditFix:kbl */
1175 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1176 GEN9_GAPS_TSV_CREDIT_DISABLE));
1178 /* WaDisableDynamicCreditSharing:kbl */
1179 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1180 WA_SET_BIT(GAMT_CHKN_BIT_REG,
1181 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
1183 /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1184 if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
1185 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1186 HDC_FENCE_DEST_SLM_DISABLE);
1188 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1189 * involving this register should also be added to WA batch as required.
1191 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
1192 /* WaDisableLSQCROPERFforOCL:kbl */
1193 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1194 GEN8_LQSC_RO_PERF_DIS);
1196 /* WaInsertDummyPushConstPs:kbl */
1197 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1198 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1199 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1201 /* WaDisableGafsUnitClkGating:kbl */
1202 WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1204 /* WaDisableSbeCacheDispatchPortSharing:kbl */
1206 GEN7_HALF_SLICE_CHICKEN1,
1207 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1209 /* WaInPlaceDecompressionHang:kbl */
1210 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
1211 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1213 /* WaDisableLSQCROPERFforOCL:kbl */
1214 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1221 int init_workarounds_ring(struct intel_engine_cs *engine)
1223 struct drm_i915_private *dev_priv = engine->i915;
1225 WARN_ON(engine->id != RCS);
1227 dev_priv->workarounds.count = 0;
1228 dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1230 if (IS_BROADWELL(dev_priv))
1231 return bdw_init_workarounds(engine);
1233 if (IS_CHERRYVIEW(dev_priv))
1234 return chv_init_workarounds(engine);
1236 if (IS_SKYLAKE(dev_priv))
1237 return skl_init_workarounds(engine);
1239 if (IS_BROXTON(dev_priv))
1240 return bxt_init_workarounds(engine);
1242 if (IS_KABYLAKE(dev_priv))
1243 return kbl_init_workarounds(engine);
1248 static int init_render_ring(struct intel_engine_cs *engine)
1250 struct drm_i915_private *dev_priv = engine->i915;
1251 int ret = init_ring_common(engine);
1255 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1256 if (IS_GEN(dev_priv, 4, 6))
1257 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1259 /* We need to disable the AsyncFlip performance optimisations in order
1260 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1261 * programmed to '1' on all products.
1263 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1265 if (IS_GEN(dev_priv, 6, 7))
1266 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1268 /* Required for the hardware to program scanline values for waiting */
1269 /* WaEnableFlushTlbInvalidationMode:snb */
1270 if (IS_GEN6(dev_priv))
1271 I915_WRITE(GFX_MODE,
1272 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1274 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1275 if (IS_GEN7(dev_priv))
1276 I915_WRITE(GFX_MODE_GEN7,
1277 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1278 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1280 if (IS_GEN6(dev_priv)) {
1281 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1282 * "If this bit is set, STCunit will have LRA as replacement
1283 * policy. [...] This bit must be reset. LRA replacement
1284 * policy is not supported."
1286 I915_WRITE(CACHE_MODE_0,
1287 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1290 if (IS_GEN(dev_priv, 6, 7))
1291 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1293 if (INTEL_INFO(dev_priv)->gen >= 6)
1294 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1296 return init_workarounds_ring(engine);
1299 static void render_ring_cleanup(struct intel_engine_cs *engine)
1301 struct drm_i915_private *dev_priv = engine->i915;
1303 if (dev_priv->semaphore_obj) {
1304 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1305 i915_gem_object_put(dev_priv->semaphore_obj);
1306 dev_priv->semaphore_obj = NULL;
1309 intel_fini_pipe_control(engine);
1312 static int gen8_rcs_signal(struct drm_i915_gem_request *req)
1314 struct intel_ring *ring = req->ring;
1315 struct drm_i915_private *dev_priv = req->i915;
1316 struct intel_engine_cs *waiter;
1317 enum intel_engine_id id;
1320 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1321 ret = intel_ring_begin(req, (num_rings-1) * 8);
1325 for_each_engine_id(waiter, dev_priv, id) {
1326 u64 gtt_offset = req->engine->semaphore.signal_ggtt[id];
1327 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1330 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1331 intel_ring_emit(ring,
1332 PIPE_CONTROL_GLOBAL_GTT_IVB |
1333 PIPE_CONTROL_QW_WRITE |
1334 PIPE_CONTROL_CS_STALL);
1335 intel_ring_emit(ring, lower_32_bits(gtt_offset));
1336 intel_ring_emit(ring, upper_32_bits(gtt_offset));
1337 intel_ring_emit(ring, req->fence.seqno);
1338 intel_ring_emit(ring, 0);
1339 intel_ring_emit(ring,
1340 MI_SEMAPHORE_SIGNAL |
1341 MI_SEMAPHORE_TARGET(waiter->hw_id));
1342 intel_ring_emit(ring, 0);
1344 intel_ring_advance(ring);
1349 static int gen8_xcs_signal(struct drm_i915_gem_request *req)
1351 struct intel_ring *ring = req->ring;
1352 struct drm_i915_private *dev_priv = req->i915;
1353 struct intel_engine_cs *waiter;
1354 enum intel_engine_id id;
1357 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1358 ret = intel_ring_begin(req, (num_rings-1) * 6);
1362 for_each_engine_id(waiter, dev_priv, id) {
1363 u64 gtt_offset = req->engine->semaphore.signal_ggtt[id];
1364 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1367 intel_ring_emit(ring,
1368 (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
1369 intel_ring_emit(ring,
1370 lower_32_bits(gtt_offset) |
1371 MI_FLUSH_DW_USE_GTT);
1372 intel_ring_emit(ring, upper_32_bits(gtt_offset));
1373 intel_ring_emit(ring, req->fence.seqno);
1374 intel_ring_emit(ring,
1375 MI_SEMAPHORE_SIGNAL |
1376 MI_SEMAPHORE_TARGET(waiter->hw_id));
1377 intel_ring_emit(ring, 0);
1379 intel_ring_advance(ring);
1384 static int gen6_signal(struct drm_i915_gem_request *req)
1386 struct intel_ring *ring = req->ring;
1387 struct drm_i915_private *dev_priv = req->i915;
1388 struct intel_engine_cs *useless;
1389 enum intel_engine_id id;
1392 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1393 ret = intel_ring_begin(req, round_up((num_rings-1) * 3, 2));
1397 for_each_engine_id(useless, dev_priv, id) {
1398 i915_reg_t mbox_reg = req->engine->semaphore.mbox.signal[id];
1400 if (i915_mmio_reg_valid(mbox_reg)) {
1401 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1402 intel_ring_emit_reg(ring, mbox_reg);
1403 intel_ring_emit(ring, req->fence.seqno);
1407 /* If num_dwords was rounded, make sure the tail pointer is correct */
1408 if (num_rings % 2 == 0)
1409 intel_ring_emit(ring, MI_NOOP);
1410 intel_ring_advance(ring);
1415 static void i9xx_submit_request(struct drm_i915_gem_request *request)
1417 struct drm_i915_private *dev_priv = request->i915;
1419 I915_WRITE_TAIL(request->engine,
1420 intel_ring_offset(request->ring, request->tail));
1423 static int i9xx_emit_request(struct drm_i915_gem_request *req)
1425 struct intel_ring *ring = req->ring;
1428 ret = intel_ring_begin(req, 4);
1432 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1433 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1434 intel_ring_emit(ring, req->fence.seqno);
1435 intel_ring_emit(ring, MI_USER_INTERRUPT);
1436 intel_ring_advance(ring);
1438 req->tail = ring->tail;
1444 * gen6_sema_emit_request - Update the semaphore mailbox registers
1446 * @request - request to write to the ring
1448 * Update the mailbox registers in the *other* rings with the current seqno.
1449 * This acts like a signal in the canonical semaphore.
1451 static int gen6_sema_emit_request(struct drm_i915_gem_request *req)
1455 ret = req->engine->semaphore.signal(req);
1459 return i9xx_emit_request(req);
1462 static int gen8_render_emit_request(struct drm_i915_gem_request *req)
1464 struct intel_engine_cs *engine = req->engine;
1465 struct intel_ring *ring = req->ring;
1468 if (engine->semaphore.signal) {
1469 ret = engine->semaphore.signal(req);
1474 ret = intel_ring_begin(req, 8);
1478 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1479 intel_ring_emit(ring, (PIPE_CONTROL_GLOBAL_GTT_IVB |
1480 PIPE_CONTROL_CS_STALL |
1481 PIPE_CONTROL_QW_WRITE));
1482 intel_ring_emit(ring, intel_hws_seqno_address(engine));
1483 intel_ring_emit(ring, 0);
1484 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1485 /* We're thrashing one dword of HWS. */
1486 intel_ring_emit(ring, 0);
1487 intel_ring_emit(ring, MI_USER_INTERRUPT);
1488 intel_ring_emit(ring, MI_NOOP);
1489 intel_ring_advance(ring);
1491 req->tail = ring->tail;
1497 * intel_ring_sync - sync the waiter to the signaller on seqno
1499 * @waiter - ring that is waiting
1500 * @signaller - ring which has, or will signal
1501 * @seqno - seqno which the waiter will block on
1505 gen8_ring_sync_to(struct drm_i915_gem_request *req,
1506 struct drm_i915_gem_request *signal)
1508 struct intel_ring *ring = req->ring;
1509 struct drm_i915_private *dev_priv = req->i915;
1510 u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id);
1511 struct i915_hw_ppgtt *ppgtt;
1514 ret = intel_ring_begin(req, 4);
1518 intel_ring_emit(ring,
1520 MI_SEMAPHORE_GLOBAL_GTT |
1521 MI_SEMAPHORE_SAD_GTE_SDD);
1522 intel_ring_emit(ring, signal->fence.seqno);
1523 intel_ring_emit(ring, lower_32_bits(offset));
1524 intel_ring_emit(ring, upper_32_bits(offset));
1525 intel_ring_advance(ring);
1527 /* When the !RCS engines idle waiting upon a semaphore, they lose their
1528 * pagetables and we must reload them before executing the batch.
1529 * We do this on the i915_switch_context() following the wait and
1530 * before the dispatch.
1532 ppgtt = req->ctx->ppgtt;
1533 if (ppgtt && req->engine->id != RCS)
1534 ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine);
1539 gen6_ring_sync_to(struct drm_i915_gem_request *req,
1540 struct drm_i915_gem_request *signal)
1542 struct intel_ring *ring = req->ring;
1543 u32 dw1 = MI_SEMAPHORE_MBOX |
1544 MI_SEMAPHORE_COMPARE |
1545 MI_SEMAPHORE_REGISTER;
1546 u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->id];
1549 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1551 ret = intel_ring_begin(req, 4);
1555 intel_ring_emit(ring, dw1 | wait_mbox);
1556 /* Throughout all of the GEM code, seqno passed implies our current
1557 * seqno is >= the last seqno executed. However for hardware the
1558 * comparison is strictly greater than.
1560 intel_ring_emit(ring, signal->fence.seqno - 1);
1561 intel_ring_emit(ring, 0);
1562 intel_ring_emit(ring, MI_NOOP);
1563 intel_ring_advance(ring);
1569 gen5_seqno_barrier(struct intel_engine_cs *engine)
1571 /* MI_STORE are internally buffered by the GPU and not flushed
1572 * either by MI_FLUSH or SyncFlush or any other combination of
1575 * "Only the submission of the store operation is guaranteed.
1576 * The write result will be complete (coherent) some time later
1577 * (this is practically a finite period but there is no guaranteed
1580 * Empirically, we observe that we need a delay of at least 75us to
1581 * be sure that the seqno write is visible by the CPU.
1583 usleep_range(125, 250);
1587 gen6_seqno_barrier(struct intel_engine_cs *engine)
1589 struct drm_i915_private *dev_priv = engine->i915;
1591 /* Workaround to force correct ordering between irq and seqno writes on
1592 * ivb (and maybe also on snb) by reading from a CS register (like
1593 * ACTHD) before reading the status page.
1595 * Note that this effectively stalls the read by the time it takes to
1596 * do a memory transaction, which more or less ensures that the write
1597 * from the GPU has sufficient time to invalidate the CPU cacheline.
1598 * Alternatively we could delay the interrupt from the CS ring to give
1599 * the write time to land, but that would incur a delay after every
1600 * batch i.e. much more frequent than a delay when waiting for the
1601 * interrupt (with the same net latency).
1603 * Also note that to prevent whole machine hangs on gen7, we have to
1604 * take the spinlock to guard against concurrent cacheline access.
1606 spin_lock_irq(&dev_priv->uncore.lock);
1607 POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
1608 spin_unlock_irq(&dev_priv->uncore.lock);
1612 gen5_irq_enable(struct intel_engine_cs *engine)
1614 gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask);
1618 gen5_irq_disable(struct intel_engine_cs *engine)
1620 gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask);
1624 i9xx_irq_enable(struct intel_engine_cs *engine)
1626 struct drm_i915_private *dev_priv = engine->i915;
1628 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1629 I915_WRITE(IMR, dev_priv->irq_mask);
1630 POSTING_READ_FW(RING_IMR(engine->mmio_base));
1634 i9xx_irq_disable(struct intel_engine_cs *engine)
1636 struct drm_i915_private *dev_priv = engine->i915;
1638 dev_priv->irq_mask |= engine->irq_enable_mask;
1639 I915_WRITE(IMR, dev_priv->irq_mask);
1643 i8xx_irq_enable(struct intel_engine_cs *engine)
1645 struct drm_i915_private *dev_priv = engine->i915;
1647 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1648 I915_WRITE16(IMR, dev_priv->irq_mask);
1649 POSTING_READ16(RING_IMR(engine->mmio_base));
1653 i8xx_irq_disable(struct intel_engine_cs *engine)
1655 struct drm_i915_private *dev_priv = engine->i915;
1657 dev_priv->irq_mask |= engine->irq_enable_mask;
1658 I915_WRITE16(IMR, dev_priv->irq_mask);
1662 bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode)
1664 struct intel_ring *ring = req->ring;
1667 ret = intel_ring_begin(req, 2);
1671 intel_ring_emit(ring, MI_FLUSH);
1672 intel_ring_emit(ring, MI_NOOP);
1673 intel_ring_advance(ring);
1678 gen6_irq_enable(struct intel_engine_cs *engine)
1680 struct drm_i915_private *dev_priv = engine->i915;
1682 I915_WRITE_IMR(engine,
1683 ~(engine->irq_enable_mask |
1684 engine->irq_keep_mask));
1685 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1689 gen6_irq_disable(struct intel_engine_cs *engine)
1691 struct drm_i915_private *dev_priv = engine->i915;
1693 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1694 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1698 hsw_vebox_irq_enable(struct intel_engine_cs *engine)
1700 struct drm_i915_private *dev_priv = engine->i915;
1702 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1703 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1707 hsw_vebox_irq_disable(struct intel_engine_cs *engine)
1709 struct drm_i915_private *dev_priv = engine->i915;
1711 I915_WRITE_IMR(engine, ~0);
1712 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1716 gen8_irq_enable(struct intel_engine_cs *engine)
1718 struct drm_i915_private *dev_priv = engine->i915;
1720 I915_WRITE_IMR(engine,
1721 ~(engine->irq_enable_mask |
1722 engine->irq_keep_mask));
1723 POSTING_READ_FW(RING_IMR(engine->mmio_base));
1727 gen8_irq_disable(struct intel_engine_cs *engine)
1729 struct drm_i915_private *dev_priv = engine->i915;
1731 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1735 i965_emit_bb_start(struct drm_i915_gem_request *req,
1736 u64 offset, u32 length,
1737 unsigned int dispatch_flags)
1739 struct intel_ring *ring = req->ring;
1742 ret = intel_ring_begin(req, 2);
1746 intel_ring_emit(ring,
1747 MI_BATCH_BUFFER_START |
1749 (dispatch_flags & I915_DISPATCH_SECURE ?
1750 0 : MI_BATCH_NON_SECURE_I965));
1751 intel_ring_emit(ring, offset);
1752 intel_ring_advance(ring);
1757 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1758 #define I830_BATCH_LIMIT (256*1024)
1759 #define I830_TLB_ENTRIES (2)
1760 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1762 i830_emit_bb_start(struct drm_i915_gem_request *req,
1763 u64 offset, u32 len,
1764 unsigned int dispatch_flags)
1766 struct intel_ring *ring = req->ring;
1767 u32 cs_offset = req->engine->scratch.gtt_offset;
1770 ret = intel_ring_begin(req, 6);
1774 /* Evict the invalid PTE TLBs */
1775 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1776 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1777 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1778 intel_ring_emit(ring, cs_offset);
1779 intel_ring_emit(ring, 0xdeadbeef);
1780 intel_ring_emit(ring, MI_NOOP);
1781 intel_ring_advance(ring);
1783 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1784 if (len > I830_BATCH_LIMIT)
1787 ret = intel_ring_begin(req, 6 + 2);
1791 /* Blit the batch (which has now all relocs applied) to the
1792 * stable batch scratch bo area (so that the CS never
1793 * stumbles over its tlb invalidation bug) ...
1795 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1796 intel_ring_emit(ring,
1797 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1798 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1799 intel_ring_emit(ring, cs_offset);
1800 intel_ring_emit(ring, 4096);
1801 intel_ring_emit(ring, offset);
1803 intel_ring_emit(ring, MI_FLUSH);
1804 intel_ring_emit(ring, MI_NOOP);
1805 intel_ring_advance(ring);
1807 /* ... and execute it. */
1811 ret = intel_ring_begin(req, 2);
1815 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1816 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1817 0 : MI_BATCH_NON_SECURE));
1818 intel_ring_advance(ring);
1824 i915_emit_bb_start(struct drm_i915_gem_request *req,
1825 u64 offset, u32 len,
1826 unsigned int dispatch_flags)
1828 struct intel_ring *ring = req->ring;
1831 ret = intel_ring_begin(req, 2);
1835 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1836 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1837 0 : MI_BATCH_NON_SECURE));
1838 intel_ring_advance(ring);
1843 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
1845 struct drm_i915_private *dev_priv = engine->i915;
1847 if (!dev_priv->status_page_dmah)
1850 drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah);
1851 engine->status_page.page_addr = NULL;
1854 static void cleanup_status_page(struct intel_engine_cs *engine)
1856 struct drm_i915_gem_object *obj;
1858 obj = engine->status_page.obj;
1862 kunmap(sg_page(obj->pages->sgl));
1863 i915_gem_object_ggtt_unpin(obj);
1864 i915_gem_object_put(obj);
1865 engine->status_page.obj = NULL;
1868 static int init_status_page(struct intel_engine_cs *engine)
1870 struct drm_i915_gem_object *obj = engine->status_page.obj;
1876 obj = i915_gem_object_create(&engine->i915->drm, 4096);
1878 DRM_ERROR("Failed to allocate status page\n");
1879 return PTR_ERR(obj);
1882 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1887 if (!HAS_LLC(engine->i915))
1888 /* On g33, we cannot place HWS above 256MiB, so
1889 * restrict its pinning to the low mappable arena.
1890 * Though this restriction is not documented for
1891 * gen4, gen5, or byt, they also behave similarly
1892 * and hang if the HWS is placed at the top of the
1893 * GTT. To generalise, it appears that all !llc
1894 * platforms have issues with us placing the HWS
1895 * above the mappable region (even though we never
1898 flags |= PIN_MAPPABLE;
1899 ret = i915_gem_object_ggtt_pin(obj, NULL, 0, 4096, flags);
1902 i915_gem_object_put(obj);
1906 engine->status_page.obj = obj;
1909 engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1910 engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1911 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
1913 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1914 engine->name, engine->status_page.gfx_addr);
1919 static int init_phys_status_page(struct intel_engine_cs *engine)
1921 struct drm_i915_private *dev_priv = engine->i915;
1923 if (!dev_priv->status_page_dmah) {
1924 dev_priv->status_page_dmah =
1925 drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE);
1926 if (!dev_priv->status_page_dmah)
1930 engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1931 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
1936 int intel_ring_pin(struct intel_ring *ring)
1938 struct drm_i915_private *dev_priv = ring->engine->i915;
1939 struct drm_i915_gem_object *obj = ring->obj;
1940 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
1941 unsigned flags = PIN_OFFSET_BIAS | 4096;
1945 if (HAS_LLC(dev_priv) && !obj->stolen) {
1946 ret = i915_gem_object_ggtt_pin(obj, NULL, 0, PAGE_SIZE, flags);
1950 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1954 addr = i915_gem_object_pin_map(obj);
1956 ret = PTR_ERR(addr);
1960 ret = i915_gem_object_ggtt_pin(obj, NULL, 0, PAGE_SIZE,
1961 flags | PIN_MAPPABLE);
1965 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1969 /* Access through the GTT requires the device to be awake. */
1970 assert_rpm_wakelock_held(dev_priv);
1972 addr = (void __force *)
1973 i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj));
1975 ret = PTR_ERR(addr);
1981 ring->vma = i915_gem_obj_to_ggtt(obj);
1985 i915_gem_object_ggtt_unpin(obj);
1989 void intel_ring_unpin(struct intel_ring *ring)
1991 GEM_BUG_ON(!ring->vma);
1992 GEM_BUG_ON(!ring->vaddr);
1994 if (HAS_LLC(ring->engine->i915) && !ring->obj->stolen)
1995 i915_gem_object_unpin_map(ring->obj);
1997 i915_vma_unpin_iomap(ring->vma);
2000 i915_gem_object_ggtt_unpin(ring->obj);
2004 static void intel_destroy_ringbuffer_obj(struct intel_ring *ring)
2006 i915_gem_object_put(ring->obj);
2010 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2011 struct intel_ring *ring)
2013 struct drm_i915_gem_object *obj;
2017 obj = i915_gem_object_create_stolen(dev, ring->size);
2019 obj = i915_gem_object_create(dev, ring->size);
2021 return PTR_ERR(obj);
2023 /* mark ring buffers as read-only from GPU side by default */
2032 intel_engine_create_ring(struct intel_engine_cs *engine, int size)
2034 struct intel_ring *ring;
2037 GEM_BUG_ON(!is_power_of_2(size));
2039 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2041 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2043 return ERR_PTR(-ENOMEM);
2046 ring->engine = engine;
2047 list_add(&ring->link, &engine->buffers);
2049 INIT_LIST_HEAD(&ring->request_list);
2052 /* Workaround an erratum on the i830 which causes a hang if
2053 * the TAIL pointer points to within the last 2 cachelines
2056 ring->effective_size = size;
2057 if (IS_I830(engine->i915) || IS_845G(engine->i915))
2058 ring->effective_size -= 2 * CACHELINE_BYTES;
2060 ring->last_retired_head = -1;
2061 intel_ring_update_space(ring);
2063 ret = intel_alloc_ringbuffer_obj(&engine->i915->drm, ring);
2065 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2067 list_del(&ring->link);
2069 return ERR_PTR(ret);
2076 intel_ring_free(struct intel_ring *ring)
2078 intel_destroy_ringbuffer_obj(ring);
2079 list_del(&ring->link);
2083 static int intel_ring_context_pin(struct i915_gem_context *ctx,
2084 struct intel_engine_cs *engine)
2086 struct intel_context *ce = &ctx->engine[engine->id];
2089 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
2091 if (ce->pin_count++)
2095 ret = i915_gem_object_ggtt_pin(ce->state, NULL, 0,
2096 ctx->ggtt_alignment, 0);
2101 /* The kernel context is only used as a placeholder for flushing the
2102 * active context. It is never used for submitting user rendering and
2103 * as such never requires the golden render context, and so we can skip
2104 * emitting it when we switch to the kernel context. This is required
2105 * as during eviction we cannot allocate and pin the renderstate in
2106 * order to initialise the context.
2108 if (ctx == ctx->i915->kernel_context)
2109 ce->initialised = true;
2111 i915_gem_context_get(ctx);
2119 static void intel_ring_context_unpin(struct i915_gem_context *ctx,
2120 struct intel_engine_cs *engine)
2122 struct intel_context *ce = &ctx->engine[engine->id];
2124 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
2126 if (--ce->pin_count)
2130 i915_gem_object_ggtt_unpin(ce->state);
2132 i915_gem_context_put(ctx);
2135 static int intel_init_ring_buffer(struct intel_engine_cs *engine)
2137 struct drm_i915_private *dev_priv = engine->i915;
2138 struct intel_ring *ring;
2141 WARN_ON(engine->buffer);
2143 intel_engine_setup_common(engine);
2145 memset(engine->semaphore.sync_seqno, 0,
2146 sizeof(engine->semaphore.sync_seqno));
2148 ret = intel_engine_init_common(engine);
2152 /* We may need to do things with the shrinker which
2153 * require us to immediately switch back to the default
2154 * context. This can cause a problem as pinning the
2155 * default context also requires GTT space which may not
2156 * be available. To avoid this we always pin the default
2159 ret = intel_ring_context_pin(dev_priv->kernel_context, engine);
2163 ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE);
2165 ret = PTR_ERR(ring);
2168 engine->buffer = ring;
2170 if (I915_NEED_GFX_HWS(dev_priv)) {
2171 ret = init_status_page(engine);
2175 WARN_ON(engine->id != RCS);
2176 ret = init_phys_status_page(engine);
2181 ret = intel_ring_pin(ring);
2183 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2185 intel_destroy_ringbuffer_obj(ring);
2192 intel_engine_cleanup(engine);
2196 void intel_engine_cleanup(struct intel_engine_cs *engine)
2198 struct drm_i915_private *dev_priv;
2200 if (!intel_engine_initialized(engine))
2203 dev_priv = engine->i915;
2205 if (engine->buffer) {
2206 WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2208 intel_ring_unpin(engine->buffer);
2209 intel_ring_free(engine->buffer);
2210 engine->buffer = NULL;
2213 if (engine->cleanup)
2214 engine->cleanup(engine);
2216 if (I915_NEED_GFX_HWS(dev_priv)) {
2217 cleanup_status_page(engine);
2219 WARN_ON(engine->id != RCS);
2220 cleanup_phys_status_page(engine);
2223 intel_engine_cleanup_common(engine);
2225 intel_ring_context_unpin(dev_priv->kernel_context, engine);
2227 engine->i915 = NULL;
2230 int intel_engine_idle(struct intel_engine_cs *engine)
2232 struct drm_i915_gem_request *req;
2234 /* Wait upon the last request to be completed */
2235 if (list_empty(&engine->request_list))
2238 req = list_entry(engine->request_list.prev,
2239 struct drm_i915_gem_request,
2242 /* Make sure we do not trigger any retires */
2243 return i915_wait_request(req,
2244 req->i915->mm.interruptible,
2248 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2252 /* Flush enough space to reduce the likelihood of waiting after
2253 * we start building the request - in which case we will just
2254 * have to repeat work.
2256 request->reserved_space += LEGACY_REQUEST_SIZE;
2258 request->ring = request->engine->buffer;
2260 ret = intel_ring_begin(request, 0);
2264 request->reserved_space -= LEGACY_REQUEST_SIZE;
2268 static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2270 struct intel_ring *ring = req->ring;
2271 struct drm_i915_gem_request *target;
2274 intel_ring_update_space(ring);
2275 if (ring->space >= bytes)
2279 * Space is reserved in the ringbuffer for finalising the request,
2280 * as that cannot be allowed to fail. During request finalisation,
2281 * reserved_space is set to 0 to stop the overallocation and the
2282 * assumption is that then we never need to wait (which has the
2283 * risk of failing with EINTR).
2285 * See also i915_gem_request_alloc() and i915_add_request().
2287 GEM_BUG_ON(!req->reserved_space);
2289 list_for_each_entry(target, &ring->request_list, ring_link) {
2292 /* Would completion of this request free enough space? */
2293 space = __intel_ring_space(target->postfix, ring->tail,
2299 if (WARN_ON(&target->ring_link == &ring->request_list))
2302 ret = i915_wait_request(target, true, NULL, NO_WAITBOOST);
2306 if (i915_reset_in_progress(&target->i915->gpu_error))
2309 i915_gem_request_retire_upto(target);
2311 intel_ring_update_space(ring);
2312 GEM_BUG_ON(ring->space < bytes);
2316 int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
2318 struct intel_ring *ring = req->ring;
2319 int remain_actual = ring->size - ring->tail;
2320 int remain_usable = ring->effective_size - ring->tail;
2321 int bytes = num_dwords * sizeof(u32);
2322 int total_bytes, wait_bytes;
2323 bool need_wrap = false;
2325 total_bytes = bytes + req->reserved_space;
2327 if (unlikely(bytes > remain_usable)) {
2329 * Not enough space for the basic request. So need to flush
2330 * out the remainder and then wait for base + reserved.
2332 wait_bytes = remain_actual + total_bytes;
2334 } else if (unlikely(total_bytes > remain_usable)) {
2336 * The base request will fit but the reserved space
2337 * falls off the end. So we don't need an immediate wrap
2338 * and only need to effectively wait for the reserved
2339 * size space from the start of ringbuffer.
2341 wait_bytes = remain_actual + req->reserved_space;
2343 /* No wrapping required, just waiting. */
2344 wait_bytes = total_bytes;
2347 if (wait_bytes > ring->space) {
2348 int ret = wait_for_space(req, wait_bytes);
2353 if (unlikely(need_wrap)) {
2354 GEM_BUG_ON(remain_actual > ring->space);
2355 GEM_BUG_ON(ring->tail + remain_actual > ring->size);
2357 /* Fill the tail with MI_NOOP */
2358 memset(ring->vaddr + ring->tail, 0, remain_actual);
2360 ring->space -= remain_actual;
2363 ring->space -= bytes;
2364 GEM_BUG_ON(ring->space < 0);
2368 /* Align the ring tail to a cacheline boundary */
2369 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2371 struct intel_ring *ring = req->ring;
2373 (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2376 if (num_dwords == 0)
2379 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2380 ret = intel_ring_begin(req, num_dwords);
2384 while (num_dwords--)
2385 intel_ring_emit(ring, MI_NOOP);
2387 intel_ring_advance(ring);
2392 void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno)
2394 struct drm_i915_private *dev_priv = engine->i915;
2396 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2397 * so long as the semaphore value in the register/page is greater
2398 * than the sync value), so whenever we reset the seqno,
2399 * so long as we reset the tracking semaphore value to 0, it will
2400 * always be before the next request's seqno. If we don't reset
2401 * the semaphore value, then when the seqno moves backwards all
2402 * future waits will complete instantly (causing rendering corruption).
2404 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
2405 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2406 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
2407 if (HAS_VEBOX(dev_priv))
2408 I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
2410 if (dev_priv->semaphore_obj) {
2411 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2412 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2413 void *semaphores = kmap(page);
2414 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2415 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2418 memset(engine->semaphore.sync_seqno, 0,
2419 sizeof(engine->semaphore.sync_seqno));
2421 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
2422 if (engine->irq_seqno_barrier)
2423 engine->irq_seqno_barrier(engine);
2424 engine->last_submitted_seqno = seqno;
2426 engine->hangcheck.seqno = seqno;
2428 /* After manually advancing the seqno, fake the interrupt in case
2429 * there are any waiters for that seqno.
2432 intel_engine_wakeup(engine);
2436 static void gen6_bsd_submit_request(struct drm_i915_gem_request *request)
2438 struct drm_i915_private *dev_priv = request->i915;
2440 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2442 /* Every tail move must follow the sequence below */
2444 /* Disable notification that the ring is IDLE. The GT
2445 * will then assume that it is busy and bring it out of rc6.
2447 I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
2448 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2450 /* Clear the context id. Here be magic! */
2451 I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0);
2453 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2454 if (intel_wait_for_register_fw(dev_priv,
2455 GEN6_BSD_SLEEP_PSMI_CONTROL,
2456 GEN6_BSD_SLEEP_INDICATOR,
2459 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2461 /* Now that the ring is fully powered up, update the tail */
2462 i9xx_submit_request(request);
2464 /* Let the ring send IDLE messages to the GT again,
2465 * and so let it sleep to conserve power when idle.
2467 I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
2468 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2470 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2473 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode)
2475 struct intel_ring *ring = req->ring;
2479 ret = intel_ring_begin(req, 4);
2484 if (INTEL_GEN(req->i915) >= 8)
2487 /* We always require a command barrier so that subsequent
2488 * commands, such as breadcrumb interrupts, are strictly ordered
2489 * wrt the contents of the write cache being flushed to memory
2490 * (and thus being coherent from the CPU).
2492 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2495 * Bspec vol 1c.5 - video engine command streamer:
2496 * "If ENABLED, all TLBs will be invalidated once the flush
2497 * operation is complete. This bit is only valid when the
2498 * Post-Sync Operation field is a value of 1h or 3h."
2500 if (mode & EMIT_INVALIDATE)
2501 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2503 intel_ring_emit(ring, cmd);
2504 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2505 if (INTEL_GEN(req->i915) >= 8) {
2506 intel_ring_emit(ring, 0); /* upper addr */
2507 intel_ring_emit(ring, 0); /* value */
2509 intel_ring_emit(ring, 0);
2510 intel_ring_emit(ring, MI_NOOP);
2512 intel_ring_advance(ring);
2517 gen8_emit_bb_start(struct drm_i915_gem_request *req,
2518 u64 offset, u32 len,
2519 unsigned int dispatch_flags)
2521 struct intel_ring *ring = req->ring;
2522 bool ppgtt = USES_PPGTT(req->i915) &&
2523 !(dispatch_flags & I915_DISPATCH_SECURE);
2526 ret = intel_ring_begin(req, 4);
2530 /* FIXME(BDW): Address space and security selectors. */
2531 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2532 (dispatch_flags & I915_DISPATCH_RS ?
2533 MI_BATCH_RESOURCE_STREAMER : 0));
2534 intel_ring_emit(ring, lower_32_bits(offset));
2535 intel_ring_emit(ring, upper_32_bits(offset));
2536 intel_ring_emit(ring, MI_NOOP);
2537 intel_ring_advance(ring);
2543 hsw_emit_bb_start(struct drm_i915_gem_request *req,
2544 u64 offset, u32 len,
2545 unsigned int dispatch_flags)
2547 struct intel_ring *ring = req->ring;
2550 ret = intel_ring_begin(req, 2);
2554 intel_ring_emit(ring,
2555 MI_BATCH_BUFFER_START |
2556 (dispatch_flags & I915_DISPATCH_SECURE ?
2557 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2558 (dispatch_flags & I915_DISPATCH_RS ?
2559 MI_BATCH_RESOURCE_STREAMER : 0));
2560 /* bit0-7 is the length on GEN6+ */
2561 intel_ring_emit(ring, offset);
2562 intel_ring_advance(ring);
2568 gen6_emit_bb_start(struct drm_i915_gem_request *req,
2569 u64 offset, u32 len,
2570 unsigned int dispatch_flags)
2572 struct intel_ring *ring = req->ring;
2575 ret = intel_ring_begin(req, 2);
2579 intel_ring_emit(ring,
2580 MI_BATCH_BUFFER_START |
2581 (dispatch_flags & I915_DISPATCH_SECURE ?
2582 0 : MI_BATCH_NON_SECURE_I965));
2583 /* bit0-7 is the length on GEN6+ */
2584 intel_ring_emit(ring, offset);
2585 intel_ring_advance(ring);
2590 /* Blitter support (SandyBridge+) */
2592 static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode)
2594 struct intel_ring *ring = req->ring;
2598 ret = intel_ring_begin(req, 4);
2603 if (INTEL_GEN(req->i915) >= 8)
2606 /* We always require a command barrier so that subsequent
2607 * commands, such as breadcrumb interrupts, are strictly ordered
2608 * wrt the contents of the write cache being flushed to memory
2609 * (and thus being coherent from the CPU).
2611 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2614 * Bspec vol 1c.3 - blitter engine command streamer:
2615 * "If ENABLED, all TLBs will be invalidated once the flush
2616 * operation is complete. This bit is only valid when the
2617 * Post-Sync Operation field is a value of 1h or 3h."
2619 if (mode & EMIT_INVALIDATE)
2620 cmd |= MI_INVALIDATE_TLB;
2621 intel_ring_emit(ring, cmd);
2622 intel_ring_emit(ring,
2623 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2624 if (INTEL_GEN(req->i915) >= 8) {
2625 intel_ring_emit(ring, 0); /* upper addr */
2626 intel_ring_emit(ring, 0); /* value */
2628 intel_ring_emit(ring, 0);
2629 intel_ring_emit(ring, MI_NOOP);
2631 intel_ring_advance(ring);
2636 static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
2637 struct intel_engine_cs *engine)
2639 struct drm_i915_gem_object *obj;
2642 if (!i915.semaphores)
2645 if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore_obj) {
2646 obj = i915_gem_object_create(&dev_priv->drm, 4096);
2648 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2649 i915.semaphores = 0;
2651 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2652 ret = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
2654 i915_gem_object_put(obj);
2655 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2656 i915.semaphores = 0;
2658 dev_priv->semaphore_obj = obj;
2663 if (!i915.semaphores)
2666 if (INTEL_GEN(dev_priv) >= 8) {
2667 u64 offset = i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj);
2669 engine->semaphore.sync_to = gen8_ring_sync_to;
2670 engine->semaphore.signal = gen8_xcs_signal;
2672 for (i = 0; i < I915_NUM_ENGINES; i++) {
2675 if (i != engine->id)
2676 ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i);
2678 ring_offset = MI_SEMAPHORE_SYNC_INVALID;
2680 engine->semaphore.signal_ggtt[i] = ring_offset;
2682 } else if (INTEL_GEN(dev_priv) >= 6) {
2683 engine->semaphore.sync_to = gen6_ring_sync_to;
2684 engine->semaphore.signal = gen6_signal;
2687 * The current semaphore is only applied on pre-gen8
2688 * platform. And there is no VCS2 ring on the pre-gen8
2689 * platform. So the semaphore between RCS and VCS2 is
2690 * initialized as INVALID. Gen8 will initialize the
2691 * sema between VCS2 and RCS later.
2693 for (i = 0; i < I915_NUM_ENGINES; i++) {
2694 static const struct {
2696 i915_reg_t mbox_reg;
2697 } sem_data[I915_NUM_ENGINES][I915_NUM_ENGINES] = {
2699 [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC },
2700 [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC },
2701 [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
2704 [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC },
2705 [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC },
2706 [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
2709 [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC },
2710 [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC },
2711 [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
2714 [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
2715 [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
2716 [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
2720 i915_reg_t mbox_reg;
2722 if (i == engine->id || i == VCS2) {
2723 wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
2724 mbox_reg = GEN6_NOSYNC;
2726 wait_mbox = sem_data[engine->id][i].wait_mbox;
2727 mbox_reg = sem_data[engine->id][i].mbox_reg;
2730 engine->semaphore.mbox.wait[i] = wait_mbox;
2731 engine->semaphore.mbox.signal[i] = mbox_reg;
2736 static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
2737 struct intel_engine_cs *engine)
2739 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift;
2741 if (INTEL_GEN(dev_priv) >= 8) {
2742 engine->irq_enable = gen8_irq_enable;
2743 engine->irq_disable = gen8_irq_disable;
2744 engine->irq_seqno_barrier = gen6_seqno_barrier;
2745 } else if (INTEL_GEN(dev_priv) >= 6) {
2746 engine->irq_enable = gen6_irq_enable;
2747 engine->irq_disable = gen6_irq_disable;
2748 engine->irq_seqno_barrier = gen6_seqno_barrier;
2749 } else if (INTEL_GEN(dev_priv) >= 5) {
2750 engine->irq_enable = gen5_irq_enable;
2751 engine->irq_disable = gen5_irq_disable;
2752 engine->irq_seqno_barrier = gen5_seqno_barrier;
2753 } else if (INTEL_GEN(dev_priv) >= 3) {
2754 engine->irq_enable = i9xx_irq_enable;
2755 engine->irq_disable = i9xx_irq_disable;
2757 engine->irq_enable = i8xx_irq_enable;
2758 engine->irq_disable = i8xx_irq_disable;
2762 static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
2763 struct intel_engine_cs *engine)
2765 intel_ring_init_irq(dev_priv, engine);
2766 intel_ring_init_semaphores(dev_priv, engine);
2768 engine->init_hw = init_ring_common;
2770 engine->emit_request = i9xx_emit_request;
2771 if (i915.semaphores)
2772 engine->emit_request = gen6_sema_emit_request;
2773 engine->submit_request = i9xx_submit_request;
2775 if (INTEL_GEN(dev_priv) >= 8)
2776 engine->emit_bb_start = gen8_emit_bb_start;
2777 else if (INTEL_GEN(dev_priv) >= 6)
2778 engine->emit_bb_start = gen6_emit_bb_start;
2779 else if (INTEL_GEN(dev_priv) >= 4)
2780 engine->emit_bb_start = i965_emit_bb_start;
2781 else if (IS_I830(dev_priv) || IS_845G(dev_priv))
2782 engine->emit_bb_start = i830_emit_bb_start;
2784 engine->emit_bb_start = i915_emit_bb_start;
2787 int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
2789 struct drm_i915_private *dev_priv = engine->i915;
2792 intel_ring_default_vfuncs(dev_priv, engine);
2794 if (HAS_L3_DPF(dev_priv))
2795 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2797 if (INTEL_GEN(dev_priv) >= 8) {
2798 engine->init_context = intel_rcs_ctx_init;
2799 engine->emit_request = gen8_render_emit_request;
2800 engine->emit_flush = gen8_render_ring_flush;
2801 if (i915.semaphores)
2802 engine->semaphore.signal = gen8_rcs_signal;
2803 } else if (INTEL_GEN(dev_priv) >= 6) {
2804 engine->init_context = intel_rcs_ctx_init;
2805 engine->emit_flush = gen7_render_ring_flush;
2806 if (IS_GEN6(dev_priv))
2807 engine->emit_flush = gen6_render_ring_flush;
2808 } else if (IS_GEN5(dev_priv)) {
2809 engine->emit_flush = gen4_render_ring_flush;
2811 if (INTEL_GEN(dev_priv) < 4)
2812 engine->emit_flush = gen2_render_ring_flush;
2814 engine->emit_flush = gen4_render_ring_flush;
2815 engine->irq_enable_mask = I915_USER_INTERRUPT;
2818 if (IS_HASWELL(dev_priv))
2819 engine->emit_bb_start = hsw_emit_bb_start;
2821 engine->init_hw = init_render_ring;
2822 engine->cleanup = render_ring_cleanup;
2824 ret = intel_init_ring_buffer(engine);
2828 if (INTEL_GEN(dev_priv) >= 6) {
2829 ret = intel_init_pipe_control(engine, 4096);
2832 } else if (HAS_BROKEN_CS_TLB(dev_priv)) {
2833 ret = intel_init_pipe_control(engine, I830_WA_SIZE);
2841 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
2843 struct drm_i915_private *dev_priv = engine->i915;
2845 intel_ring_default_vfuncs(dev_priv, engine);
2847 if (INTEL_GEN(dev_priv) >= 6) {
2848 /* gen6 bsd needs a special wa for tail updates */
2849 if (IS_GEN6(dev_priv))
2850 engine->submit_request = gen6_bsd_submit_request;
2851 engine->emit_flush = gen6_bsd_ring_flush;
2852 if (INTEL_GEN(dev_priv) < 8)
2853 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2855 engine->mmio_base = BSD_RING_BASE;
2856 engine->emit_flush = bsd_ring_flush;
2857 if (IS_GEN5(dev_priv))
2858 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2860 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2863 return intel_init_ring_buffer(engine);
2867 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2869 int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine)
2871 struct drm_i915_private *dev_priv = engine->i915;
2873 intel_ring_default_vfuncs(dev_priv, engine);
2875 engine->emit_flush = gen6_bsd_ring_flush;
2877 return intel_init_ring_buffer(engine);
2880 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
2882 struct drm_i915_private *dev_priv = engine->i915;
2884 intel_ring_default_vfuncs(dev_priv, engine);
2886 engine->emit_flush = gen6_ring_flush;
2887 if (INTEL_GEN(dev_priv) < 8)
2888 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2890 return intel_init_ring_buffer(engine);
2893 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
2895 struct drm_i915_private *dev_priv = engine->i915;
2897 intel_ring_default_vfuncs(dev_priv, engine);
2899 engine->emit_flush = gen6_ring_flush;
2901 if (INTEL_GEN(dev_priv) < 8) {
2902 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2903 engine->irq_enable = hsw_vebox_irq_enable;
2904 engine->irq_disable = hsw_vebox_irq_disable;
2907 return intel_init_ring_buffer(engine);