2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 intel_ring_initialized(struct intel_engine_cs *ring)
39 struct drm_device *dev = ring->dev;
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
50 return ring->buffer && ring->buffer->obj;
53 int __intel_ring_space(int head, int tail, int size)
55 int space = head - (tail + I915_RING_FREE_SPACE);
61 int intel_ring_space(struct intel_ringbuffer *ringbuf)
63 return __intel_ring_space(ringbuf->head & HEAD_ADDR,
64 ringbuf->tail, ringbuf->size);
67 bool intel_ring_stopped(struct intel_engine_cs *ring)
69 struct drm_i915_private *dev_priv = ring->dev->dev_private;
70 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
73 void __intel_ring_advance(struct intel_engine_cs *ring)
75 struct intel_ringbuffer *ringbuf = ring->buffer;
76 ringbuf->tail &= ringbuf->size - 1;
77 if (intel_ring_stopped(ring))
79 ring->write_tail(ring, ringbuf->tail);
83 gen2_render_ring_flush(struct intel_engine_cs *ring,
84 u32 invalidate_domains,
91 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
92 cmd |= MI_NO_WRITE_FLUSH;
94 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
97 ret = intel_ring_begin(ring, 2);
101 intel_ring_emit(ring, cmd);
102 intel_ring_emit(ring, MI_NOOP);
103 intel_ring_advance(ring);
109 gen4_render_ring_flush(struct intel_engine_cs *ring,
110 u32 invalidate_domains,
113 struct drm_device *dev = ring->dev;
120 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
121 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
122 * also flushed at 2d versus 3d pipeline switches.
126 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
127 * MI_READ_FLUSH is set, and is always flushed on 965.
129 * I915_GEM_DOMAIN_COMMAND may not exist?
131 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
132 * invalidated when MI_EXE_FLUSH is set.
134 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
135 * invalidated with every MI_FLUSH.
139 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
140 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
141 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
142 * are flushed at any MI_FLUSH.
145 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
146 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
147 cmd &= ~MI_NO_WRITE_FLUSH;
148 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
151 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
152 (IS_G4X(dev) || IS_GEN5(dev)))
153 cmd |= MI_INVALIDATE_ISP;
155 ret = intel_ring_begin(ring, 2);
159 intel_ring_emit(ring, cmd);
160 intel_ring_emit(ring, MI_NOOP);
161 intel_ring_advance(ring);
167 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
168 * implementing two workarounds on gen6. From section 1.4.7.1
169 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
171 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
172 * produced by non-pipelined state commands), software needs to first
173 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
176 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
177 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
179 * And the workaround for these two requires this workaround first:
181 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
182 * BEFORE the pipe-control with a post-sync op and no write-cache
185 * And this last workaround is tricky because of the requirements on
186 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
189 * "1 of the following must also be set:
190 * - Render Target Cache Flush Enable ([12] of DW1)
191 * - Depth Cache Flush Enable ([0] of DW1)
192 * - Stall at Pixel Scoreboard ([1] of DW1)
193 * - Depth Stall ([13] of DW1)
194 * - Post-Sync Operation ([13] of DW1)
195 * - Notify Enable ([8] of DW1)"
197 * The cache flushes require the workaround flush that triggered this
198 * one, so we can't use it. Depth stall would trigger the same.
199 * Post-sync nonzero is what triggered this second workaround, so we
200 * can't use that one either. Notify enable is IRQs, which aren't
201 * really our business. That leaves only stall at scoreboard.
204 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
206 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
210 ret = intel_ring_begin(ring, 6);
214 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
215 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
216 PIPE_CONTROL_STALL_AT_SCOREBOARD);
217 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
218 intel_ring_emit(ring, 0); /* low dword */
219 intel_ring_emit(ring, 0); /* high dword */
220 intel_ring_emit(ring, MI_NOOP);
221 intel_ring_advance(ring);
223 ret = intel_ring_begin(ring, 6);
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
229 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
230 intel_ring_emit(ring, 0);
231 intel_ring_emit(ring, 0);
232 intel_ring_emit(ring, MI_NOOP);
233 intel_ring_advance(ring);
239 gen6_render_ring_flush(struct intel_engine_cs *ring,
240 u32 invalidate_domains, u32 flush_domains)
243 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
246 /* Force SNB workarounds for PIPE_CONTROL flushes */
247 ret = intel_emit_post_sync_nonzero_flush(ring);
251 /* Just flush everything. Experiments have shown that reducing the
252 * number of bits based on the write domains has little performance
256 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
257 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
259 * Ensure that any following seqno writes only happen
260 * when the render cache is indeed flushed.
262 flags |= PIPE_CONTROL_CS_STALL;
264 if (invalidate_domains) {
265 flags |= PIPE_CONTROL_TLB_INVALIDATE;
266 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
267 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
268 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
269 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
270 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
272 * TLB invalidate requires a post-sync write.
274 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
277 ret = intel_ring_begin(ring, 4);
281 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
282 intel_ring_emit(ring, flags);
283 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
284 intel_ring_emit(ring, 0);
285 intel_ring_advance(ring);
291 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
295 ret = intel_ring_begin(ring, 4);
299 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
300 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
301 PIPE_CONTROL_STALL_AT_SCOREBOARD);
302 intel_ring_emit(ring, 0);
303 intel_ring_emit(ring, 0);
304 intel_ring_advance(ring);
309 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
313 if (!ring->fbc_dirty)
316 ret = intel_ring_begin(ring, 6);
319 /* WaFbcNukeOn3DBlt:ivb/hsw */
320 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
321 intel_ring_emit(ring, MSG_FBC_REND_STATE);
322 intel_ring_emit(ring, value);
323 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
324 intel_ring_emit(ring, MSG_FBC_REND_STATE);
325 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
326 intel_ring_advance(ring);
328 ring->fbc_dirty = false;
333 gen7_render_ring_flush(struct intel_engine_cs *ring,
334 u32 invalidate_domains, u32 flush_domains)
337 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
341 * Ensure that any following seqno writes only happen when the render
342 * cache is indeed flushed.
344 * Workaround: 4th PIPE_CONTROL command (except the ones with only
345 * read-cache invalidate bits set) must have the CS_STALL bit set. We
346 * don't try to be clever and just set it unconditionally.
348 flags |= PIPE_CONTROL_CS_STALL;
350 /* Just flush everything. Experiments have shown that reducing the
351 * number of bits based on the write domains has little performance
355 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
356 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
358 if (invalidate_domains) {
359 flags |= PIPE_CONTROL_TLB_INVALIDATE;
360 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
361 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
362 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
363 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
364 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
366 * TLB invalidate requires a post-sync write.
368 flags |= PIPE_CONTROL_QW_WRITE;
369 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
371 /* Workaround: we must issue a pipe_control with CS-stall bit
372 * set before a pipe_control command that has the state cache
373 * invalidate bit set. */
374 gen7_render_ring_cs_stall_wa(ring);
377 ret = intel_ring_begin(ring, 4);
381 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
382 intel_ring_emit(ring, flags);
383 intel_ring_emit(ring, scratch_addr);
384 intel_ring_emit(ring, 0);
385 intel_ring_advance(ring);
387 if (!invalidate_domains && flush_domains)
388 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
394 gen8_emit_pipe_control(struct intel_engine_cs *ring,
395 u32 flags, u32 scratch_addr)
399 ret = intel_ring_begin(ring, 6);
403 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
404 intel_ring_emit(ring, flags);
405 intel_ring_emit(ring, scratch_addr);
406 intel_ring_emit(ring, 0);
407 intel_ring_emit(ring, 0);
408 intel_ring_emit(ring, 0);
409 intel_ring_advance(ring);
415 gen8_render_ring_flush(struct intel_engine_cs *ring,
416 u32 invalidate_domains, u32 flush_domains)
419 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
422 flags |= PIPE_CONTROL_CS_STALL;
425 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
426 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
428 if (invalidate_domains) {
429 flags |= PIPE_CONTROL_TLB_INVALIDATE;
430 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
431 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
432 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
433 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
434 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
435 flags |= PIPE_CONTROL_QW_WRITE;
436 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
438 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
439 ret = gen8_emit_pipe_control(ring,
440 PIPE_CONTROL_CS_STALL |
441 PIPE_CONTROL_STALL_AT_SCOREBOARD,
447 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
451 if (!invalidate_domains && flush_domains)
452 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
457 static void ring_write_tail(struct intel_engine_cs *ring,
460 struct drm_i915_private *dev_priv = ring->dev->dev_private;
461 I915_WRITE_TAIL(ring, value);
464 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
466 struct drm_i915_private *dev_priv = ring->dev->dev_private;
469 if (INTEL_INFO(ring->dev)->gen >= 8)
470 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
471 RING_ACTHD_UDW(ring->mmio_base));
472 else if (INTEL_INFO(ring->dev)->gen >= 4)
473 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
475 acthd = I915_READ(ACTHD);
480 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
482 struct drm_i915_private *dev_priv = ring->dev->dev_private;
485 addr = dev_priv->status_page_dmah->busaddr;
486 if (INTEL_INFO(ring->dev)->gen >= 4)
487 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
488 I915_WRITE(HWS_PGA, addr);
491 static bool stop_ring(struct intel_engine_cs *ring)
493 struct drm_i915_private *dev_priv = to_i915(ring->dev);
495 if (!IS_GEN2(ring->dev)) {
496 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
497 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
498 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
499 /* Sometimes we observe that the idle flag is not
500 * set even though the ring is empty. So double
501 * check before giving up.
503 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
508 I915_WRITE_CTL(ring, 0);
509 I915_WRITE_HEAD(ring, 0);
510 ring->write_tail(ring, 0);
512 if (!IS_GEN2(ring->dev)) {
513 (void)I915_READ_CTL(ring);
514 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
517 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
520 static int init_ring_common(struct intel_engine_cs *ring)
522 struct drm_device *dev = ring->dev;
523 struct drm_i915_private *dev_priv = dev->dev_private;
524 struct intel_ringbuffer *ringbuf = ring->buffer;
525 struct drm_i915_gem_object *obj = ringbuf->obj;
528 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
530 if (!stop_ring(ring)) {
531 /* G45 ring initialization often fails to reset head to zero */
532 DRM_DEBUG_KMS("%s head not reset to zero "
533 "ctl %08x head %08x tail %08x start %08x\n",
536 I915_READ_HEAD(ring),
537 I915_READ_TAIL(ring),
538 I915_READ_START(ring));
540 if (!stop_ring(ring)) {
541 DRM_ERROR("failed to set %s head to zero "
542 "ctl %08x head %08x tail %08x start %08x\n",
545 I915_READ_HEAD(ring),
546 I915_READ_TAIL(ring),
547 I915_READ_START(ring));
553 if (I915_NEED_GFX_HWS(dev))
554 intel_ring_setup_status_page(ring);
556 ring_setup_phys_status_page(ring);
558 /* Enforce ordering by reading HEAD register back */
559 I915_READ_HEAD(ring);
561 /* Initialize the ring. This must happen _after_ we've cleared the ring
562 * registers with the above sequence (the readback of the HEAD registers
563 * also enforces ordering), otherwise the hw might lose the new ring
564 * register values. */
565 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
567 /* WaClearRingBufHeadRegAtInit:ctg,elk */
568 if (I915_READ_HEAD(ring))
569 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
570 ring->name, I915_READ_HEAD(ring));
571 I915_WRITE_HEAD(ring, 0);
572 (void)I915_READ_HEAD(ring);
575 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
578 /* If the head is still not zero, the ring is dead */
579 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
580 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
581 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
582 DRM_ERROR("%s initialization failed "
583 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
585 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
586 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
587 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
592 ringbuf->head = I915_READ_HEAD(ring);
593 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
594 ringbuf->space = intel_ring_space(ringbuf);
595 ringbuf->last_retired_head = -1;
597 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
600 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
606 intel_fini_pipe_control(struct intel_engine_cs *ring)
608 struct drm_device *dev = ring->dev;
610 if (ring->scratch.obj == NULL)
613 if (INTEL_INFO(dev)->gen >= 5) {
614 kunmap(sg_page(ring->scratch.obj->pages->sgl));
615 i915_gem_object_ggtt_unpin(ring->scratch.obj);
618 drm_gem_object_unreference(&ring->scratch.obj->base);
619 ring->scratch.obj = NULL;
623 intel_init_pipe_control(struct intel_engine_cs *ring)
627 if (ring->scratch.obj)
630 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
631 if (ring->scratch.obj == NULL) {
632 DRM_ERROR("Failed to allocate seqno page\n");
637 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
641 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
645 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
646 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
647 if (ring->scratch.cpu_page == NULL) {
652 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
653 ring->name, ring->scratch.gtt_offset);
657 i915_gem_object_ggtt_unpin(ring->scratch.obj);
659 drm_gem_object_unreference(&ring->scratch.obj->base);
664 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
665 struct intel_context *ctx)
668 struct drm_device *dev = ring->dev;
669 struct drm_i915_private *dev_priv = dev->dev_private;
670 struct i915_workarounds *w = &dev_priv->workarounds;
672 if (WARN_ON(w->count == 0))
675 ring->gpu_caches_dirty = true;
676 ret = intel_ring_flush_all_caches(ring);
680 ret = intel_ring_begin(ring, (w->count * 2 + 2));
684 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
685 for (i = 0; i < w->count; i++) {
686 intel_ring_emit(ring, w->reg[i].addr);
687 intel_ring_emit(ring, w->reg[i].value);
689 intel_ring_emit(ring, MI_NOOP);
691 intel_ring_advance(ring);
693 ring->gpu_caches_dirty = true;
694 ret = intel_ring_flush_all_caches(ring);
698 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
703 static int wa_add(struct drm_i915_private *dev_priv,
704 const u32 addr, const u32 mask, const u32 val)
706 const u32 idx = dev_priv->workarounds.count;
708 if (WARN_ON(idx >= I915_MAX_WA_REGS))
711 dev_priv->workarounds.reg[idx].addr = addr;
712 dev_priv->workarounds.reg[idx].value = val;
713 dev_priv->workarounds.reg[idx].mask = mask;
715 dev_priv->workarounds.count++;
720 #define WA_REG(addr, mask, val) { \
721 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
726 #define WA_SET_BIT_MASKED(addr, mask) \
727 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
729 #define WA_CLR_BIT_MASKED(addr, mask) \
730 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
732 #define WA_SET_FIELD_MASKED(addr, mask, value) \
733 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
735 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
736 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
738 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
740 static int bdw_init_workarounds(struct intel_engine_cs *ring)
742 struct drm_device *dev = ring->dev;
743 struct drm_i915_private *dev_priv = dev->dev_private;
745 /* WaDisablePartialInstShootdown:bdw */
746 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
747 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
748 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
749 STALL_DOP_GATING_DISABLE);
751 /* WaDisableDopClockGating:bdw */
752 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
753 DOP_CLOCK_GATING_DISABLE);
755 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
756 GEN8_SAMPLER_POWER_BYPASS_DIS);
758 /* Use Force Non-Coherent whenever executing a 3D context. This is a
759 * workaround for for a possible hang in the unlikely event a TLB
760 * invalidation occurs during a PSD flush.
762 /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
763 WA_SET_BIT_MASKED(HDC_CHICKEN0,
764 HDC_FORCE_NON_COHERENT |
765 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
767 /* Wa4x4STCOptimizationDisable:bdw */
768 WA_SET_BIT_MASKED(CACHE_MODE_1,
769 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
772 * BSpec recommends 8x4 when MSAA is used,
773 * however in practice 16x4 seems fastest.
775 * Note that PS/WM thread counts depend on the WIZ hashing
776 * disable bit, which we don't touch here, but it's good
777 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
779 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
780 GEN6_WIZ_HASHING_MASK,
781 GEN6_WIZ_HASHING_16x4);
786 static int chv_init_workarounds(struct intel_engine_cs *ring)
788 struct drm_device *dev = ring->dev;
789 struct drm_i915_private *dev_priv = dev->dev_private;
791 /* WaDisablePartialInstShootdown:chv */
792 /* WaDisableThreadStallDopClockGating:chv */
793 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
794 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
795 STALL_DOP_GATING_DISABLE);
797 /* Use Force Non-Coherent whenever executing a 3D context. This is a
798 * workaround for a possible hang in the unlikely event a TLB
799 * invalidation occurs during a PSD flush.
801 /* WaForceEnableNonCoherent:chv */
802 /* WaHdcDisableFetchWhenMasked:chv */
803 WA_SET_BIT_MASKED(HDC_CHICKEN0,
804 HDC_FORCE_NON_COHERENT |
805 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
810 int init_workarounds_ring(struct intel_engine_cs *ring)
812 struct drm_device *dev = ring->dev;
813 struct drm_i915_private *dev_priv = dev->dev_private;
815 WARN_ON(ring->id != RCS);
817 dev_priv->workarounds.count = 0;
819 if (IS_BROADWELL(dev))
820 return bdw_init_workarounds(ring);
822 if (IS_CHERRYVIEW(dev))
823 return chv_init_workarounds(ring);
828 static int init_render_ring(struct intel_engine_cs *ring)
830 struct drm_device *dev = ring->dev;
831 struct drm_i915_private *dev_priv = dev->dev_private;
832 int ret = init_ring_common(ring);
836 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
837 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
838 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
840 /* We need to disable the AsyncFlip performance optimisations in order
841 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
842 * programmed to '1' on all products.
844 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
846 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
847 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
849 /* Required for the hardware to program scanline values for waiting */
850 /* WaEnableFlushTlbInvalidationMode:snb */
851 if (INTEL_INFO(dev)->gen == 6)
853 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
855 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
857 I915_WRITE(GFX_MODE_GEN7,
858 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
859 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
861 if (INTEL_INFO(dev)->gen >= 5) {
862 ret = intel_init_pipe_control(ring);
868 /* From the Sandybridge PRM, volume 1 part 3, page 24:
869 * "If this bit is set, STCunit will have LRA as replacement
870 * policy. [...] This bit must be reset. LRA replacement
871 * policy is not supported."
873 I915_WRITE(CACHE_MODE_0,
874 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
877 if (INTEL_INFO(dev)->gen >= 6)
878 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
881 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
883 return init_workarounds_ring(ring);
886 static void render_ring_cleanup(struct intel_engine_cs *ring)
888 struct drm_device *dev = ring->dev;
889 struct drm_i915_private *dev_priv = dev->dev_private;
891 if (dev_priv->semaphore_obj) {
892 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
893 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
894 dev_priv->semaphore_obj = NULL;
897 intel_fini_pipe_control(ring);
900 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
901 unsigned int num_dwords)
903 #define MBOX_UPDATE_DWORDS 8
904 struct drm_device *dev = signaller->dev;
905 struct drm_i915_private *dev_priv = dev->dev_private;
906 struct intel_engine_cs *waiter;
907 int i, ret, num_rings;
909 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
910 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
911 #undef MBOX_UPDATE_DWORDS
913 ret = intel_ring_begin(signaller, num_dwords);
917 for_each_ring(waiter, dev_priv, i) {
918 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
919 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
922 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
923 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
924 PIPE_CONTROL_QW_WRITE |
925 PIPE_CONTROL_FLUSH_ENABLE);
926 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
927 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
928 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
929 intel_ring_emit(signaller, 0);
930 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
931 MI_SEMAPHORE_TARGET(waiter->id));
932 intel_ring_emit(signaller, 0);
938 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
939 unsigned int num_dwords)
941 #define MBOX_UPDATE_DWORDS 6
942 struct drm_device *dev = signaller->dev;
943 struct drm_i915_private *dev_priv = dev->dev_private;
944 struct intel_engine_cs *waiter;
945 int i, ret, num_rings;
947 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
948 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
949 #undef MBOX_UPDATE_DWORDS
951 ret = intel_ring_begin(signaller, num_dwords);
955 for_each_ring(waiter, dev_priv, i) {
956 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
957 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
960 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
961 MI_FLUSH_DW_OP_STOREDW);
962 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
963 MI_FLUSH_DW_USE_GTT);
964 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
965 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
966 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
967 MI_SEMAPHORE_TARGET(waiter->id));
968 intel_ring_emit(signaller, 0);
974 static int gen6_signal(struct intel_engine_cs *signaller,
975 unsigned int num_dwords)
977 struct drm_device *dev = signaller->dev;
978 struct drm_i915_private *dev_priv = dev->dev_private;
979 struct intel_engine_cs *useless;
980 int i, ret, num_rings;
982 #define MBOX_UPDATE_DWORDS 3
983 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
984 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
985 #undef MBOX_UPDATE_DWORDS
987 ret = intel_ring_begin(signaller, num_dwords);
991 for_each_ring(useless, dev_priv, i) {
992 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
993 if (mbox_reg != GEN6_NOSYNC) {
994 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
995 intel_ring_emit(signaller, mbox_reg);
996 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
1000 /* If num_dwords was rounded, make sure the tail pointer is correct */
1001 if (num_rings % 2 == 0)
1002 intel_ring_emit(signaller, MI_NOOP);
1008 * gen6_add_request - Update the semaphore mailbox registers
1010 * @ring - ring that is adding a request
1011 * @seqno - return seqno stuck into the ring
1013 * Update the mailbox registers in the *other* rings with the current seqno.
1014 * This acts like a signal in the canonical semaphore.
1017 gen6_add_request(struct intel_engine_cs *ring)
1021 if (ring->semaphore.signal)
1022 ret = ring->semaphore.signal(ring, 4);
1024 ret = intel_ring_begin(ring, 4);
1029 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1030 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1031 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1032 intel_ring_emit(ring, MI_USER_INTERRUPT);
1033 __intel_ring_advance(ring);
1038 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1041 struct drm_i915_private *dev_priv = dev->dev_private;
1042 return dev_priv->last_seqno < seqno;
1046 * intel_ring_sync - sync the waiter to the signaller on seqno
1048 * @waiter - ring that is waiting
1049 * @signaller - ring which has, or will signal
1050 * @seqno - seqno which the waiter will block on
1054 gen8_ring_sync(struct intel_engine_cs *waiter,
1055 struct intel_engine_cs *signaller,
1058 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1061 ret = intel_ring_begin(waiter, 4);
1065 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1066 MI_SEMAPHORE_GLOBAL_GTT |
1068 MI_SEMAPHORE_SAD_GTE_SDD);
1069 intel_ring_emit(waiter, seqno);
1070 intel_ring_emit(waiter,
1071 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1072 intel_ring_emit(waiter,
1073 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1074 intel_ring_advance(waiter);
1079 gen6_ring_sync(struct intel_engine_cs *waiter,
1080 struct intel_engine_cs *signaller,
1083 u32 dw1 = MI_SEMAPHORE_MBOX |
1084 MI_SEMAPHORE_COMPARE |
1085 MI_SEMAPHORE_REGISTER;
1086 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1089 /* Throughout all of the GEM code, seqno passed implies our current
1090 * seqno is >= the last seqno executed. However for hardware the
1091 * comparison is strictly greater than.
1095 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1097 ret = intel_ring_begin(waiter, 4);
1101 /* If seqno wrap happened, omit the wait with no-ops */
1102 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1103 intel_ring_emit(waiter, dw1 | wait_mbox);
1104 intel_ring_emit(waiter, seqno);
1105 intel_ring_emit(waiter, 0);
1106 intel_ring_emit(waiter, MI_NOOP);
1108 intel_ring_emit(waiter, MI_NOOP);
1109 intel_ring_emit(waiter, MI_NOOP);
1110 intel_ring_emit(waiter, MI_NOOP);
1111 intel_ring_emit(waiter, MI_NOOP);
1113 intel_ring_advance(waiter);
1118 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1120 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1121 PIPE_CONTROL_DEPTH_STALL); \
1122 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1123 intel_ring_emit(ring__, 0); \
1124 intel_ring_emit(ring__, 0); \
1128 pc_render_add_request(struct intel_engine_cs *ring)
1130 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1133 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1134 * incoherent with writes to memory, i.e. completely fubar,
1135 * so we need to use PIPE_NOTIFY instead.
1137 * However, we also need to workaround the qword write
1138 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1139 * memory before requesting an interrupt.
1141 ret = intel_ring_begin(ring, 32);
1145 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1146 PIPE_CONTROL_WRITE_FLUSH |
1147 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1148 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1149 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1150 intel_ring_emit(ring, 0);
1151 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1152 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1153 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1154 scratch_addr += 2 * CACHELINE_BYTES;
1155 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1156 scratch_addr += 2 * CACHELINE_BYTES;
1157 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1158 scratch_addr += 2 * CACHELINE_BYTES;
1159 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1160 scratch_addr += 2 * CACHELINE_BYTES;
1161 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1163 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1164 PIPE_CONTROL_WRITE_FLUSH |
1165 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1166 PIPE_CONTROL_NOTIFY);
1167 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1168 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1169 intel_ring_emit(ring, 0);
1170 __intel_ring_advance(ring);
1176 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1178 /* Workaround to force correct ordering between irq and seqno writes on
1179 * ivb (and maybe also on snb) by reading from a CS register (like
1180 * ACTHD) before reading the status page. */
1181 if (!lazy_coherency) {
1182 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1183 POSTING_READ(RING_ACTHD(ring->mmio_base));
1186 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1190 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1192 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1196 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1198 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1202 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1204 return ring->scratch.cpu_page[0];
1208 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1210 ring->scratch.cpu_page[0] = seqno;
1214 gen5_ring_get_irq(struct intel_engine_cs *ring)
1216 struct drm_device *dev = ring->dev;
1217 struct drm_i915_private *dev_priv = dev->dev_private;
1218 unsigned long flags;
1220 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1223 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1224 if (ring->irq_refcount++ == 0)
1225 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1226 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1232 gen5_ring_put_irq(struct intel_engine_cs *ring)
1234 struct drm_device *dev = ring->dev;
1235 struct drm_i915_private *dev_priv = dev->dev_private;
1236 unsigned long flags;
1238 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1239 if (--ring->irq_refcount == 0)
1240 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1241 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1245 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1247 struct drm_device *dev = ring->dev;
1248 struct drm_i915_private *dev_priv = dev->dev_private;
1249 unsigned long flags;
1251 if (!intel_irqs_enabled(dev_priv))
1254 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1255 if (ring->irq_refcount++ == 0) {
1256 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1257 I915_WRITE(IMR, dev_priv->irq_mask);
1260 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1266 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1268 struct drm_device *dev = ring->dev;
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270 unsigned long flags;
1272 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1273 if (--ring->irq_refcount == 0) {
1274 dev_priv->irq_mask |= ring->irq_enable_mask;
1275 I915_WRITE(IMR, dev_priv->irq_mask);
1278 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1282 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1284 struct drm_device *dev = ring->dev;
1285 struct drm_i915_private *dev_priv = dev->dev_private;
1286 unsigned long flags;
1288 if (!intel_irqs_enabled(dev_priv))
1291 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1292 if (ring->irq_refcount++ == 0) {
1293 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1294 I915_WRITE16(IMR, dev_priv->irq_mask);
1295 POSTING_READ16(IMR);
1297 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1303 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1305 struct drm_device *dev = ring->dev;
1306 struct drm_i915_private *dev_priv = dev->dev_private;
1307 unsigned long flags;
1309 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1310 if (--ring->irq_refcount == 0) {
1311 dev_priv->irq_mask |= ring->irq_enable_mask;
1312 I915_WRITE16(IMR, dev_priv->irq_mask);
1313 POSTING_READ16(IMR);
1315 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1318 void intel_ring_setup_status_page(struct intel_engine_cs *ring)
1320 struct drm_device *dev = ring->dev;
1321 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1324 /* The ring status page addresses are no longer next to the rest of
1325 * the ring registers as of gen7.
1330 mmio = RENDER_HWS_PGA_GEN7;
1333 mmio = BLT_HWS_PGA_GEN7;
1336 * VCS2 actually doesn't exist on Gen7. Only shut up
1337 * gcc switch check warning
1341 mmio = BSD_HWS_PGA_GEN7;
1344 mmio = VEBOX_HWS_PGA_GEN7;
1347 } else if (IS_GEN6(ring->dev)) {
1348 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1350 /* XXX: gen8 returns to sanity */
1351 mmio = RING_HWS_PGA(ring->mmio_base);
1354 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1358 * Flush the TLB for this page
1360 * FIXME: These two bits have disappeared on gen8, so a question
1361 * arises: do we still need this and if so how should we go about
1362 * invalidating the TLB?
1364 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1365 u32 reg = RING_INSTPM(ring->mmio_base);
1367 /* ring should be idle before issuing a sync flush*/
1368 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1371 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1372 INSTPM_SYNC_FLUSH));
1373 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1375 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1381 bsd_ring_flush(struct intel_engine_cs *ring,
1382 u32 invalidate_domains,
1387 ret = intel_ring_begin(ring, 2);
1391 intel_ring_emit(ring, MI_FLUSH);
1392 intel_ring_emit(ring, MI_NOOP);
1393 intel_ring_advance(ring);
1398 i9xx_add_request(struct intel_engine_cs *ring)
1402 ret = intel_ring_begin(ring, 4);
1406 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1407 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1408 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1409 intel_ring_emit(ring, MI_USER_INTERRUPT);
1410 __intel_ring_advance(ring);
1416 gen6_ring_get_irq(struct intel_engine_cs *ring)
1418 struct drm_device *dev = ring->dev;
1419 struct drm_i915_private *dev_priv = dev->dev_private;
1420 unsigned long flags;
1422 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1425 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1426 if (ring->irq_refcount++ == 0) {
1427 if (HAS_L3_DPF(dev) && ring->id == RCS)
1428 I915_WRITE_IMR(ring,
1429 ~(ring->irq_enable_mask |
1430 GT_PARITY_ERROR(dev)));
1432 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1433 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1435 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1441 gen6_ring_put_irq(struct intel_engine_cs *ring)
1443 struct drm_device *dev = ring->dev;
1444 struct drm_i915_private *dev_priv = dev->dev_private;
1445 unsigned long flags;
1447 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1448 if (--ring->irq_refcount == 0) {
1449 if (HAS_L3_DPF(dev) && ring->id == RCS)
1450 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1452 I915_WRITE_IMR(ring, ~0);
1453 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1455 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1459 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1461 struct drm_device *dev = ring->dev;
1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463 unsigned long flags;
1465 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1468 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1469 if (ring->irq_refcount++ == 0) {
1470 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1471 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1473 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1479 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1481 struct drm_device *dev = ring->dev;
1482 struct drm_i915_private *dev_priv = dev->dev_private;
1483 unsigned long flags;
1485 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1486 if (--ring->irq_refcount == 0) {
1487 I915_WRITE_IMR(ring, ~0);
1488 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1490 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1494 gen8_ring_get_irq(struct intel_engine_cs *ring)
1496 struct drm_device *dev = ring->dev;
1497 struct drm_i915_private *dev_priv = dev->dev_private;
1498 unsigned long flags;
1500 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1503 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1504 if (ring->irq_refcount++ == 0) {
1505 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1506 I915_WRITE_IMR(ring,
1507 ~(ring->irq_enable_mask |
1508 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1510 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1512 POSTING_READ(RING_IMR(ring->mmio_base));
1514 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1520 gen8_ring_put_irq(struct intel_engine_cs *ring)
1522 struct drm_device *dev = ring->dev;
1523 struct drm_i915_private *dev_priv = dev->dev_private;
1524 unsigned long flags;
1526 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1527 if (--ring->irq_refcount == 0) {
1528 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1529 I915_WRITE_IMR(ring,
1530 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1532 I915_WRITE_IMR(ring, ~0);
1534 POSTING_READ(RING_IMR(ring->mmio_base));
1536 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1540 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1541 u64 offset, u32 length,
1546 ret = intel_ring_begin(ring, 2);
1550 intel_ring_emit(ring,
1551 MI_BATCH_BUFFER_START |
1553 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1554 intel_ring_emit(ring, offset);
1555 intel_ring_advance(ring);
1560 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1561 #define I830_BATCH_LIMIT (256*1024)
1562 #define I830_TLB_ENTRIES (2)
1563 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1565 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1566 u64 offset, u32 len,
1569 u32 cs_offset = ring->scratch.gtt_offset;
1572 ret = intel_ring_begin(ring, 6);
1576 /* Evict the invalid PTE TLBs */
1577 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1578 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1579 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1580 intel_ring_emit(ring, cs_offset);
1581 intel_ring_emit(ring, 0xdeadbeef);
1582 intel_ring_emit(ring, MI_NOOP);
1583 intel_ring_advance(ring);
1585 if ((flags & I915_DISPATCH_PINNED) == 0) {
1586 if (len > I830_BATCH_LIMIT)
1589 ret = intel_ring_begin(ring, 6 + 2);
1593 /* Blit the batch (which has now all relocs applied) to the
1594 * stable batch scratch bo area (so that the CS never
1595 * stumbles over its tlb invalidation bug) ...
1597 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1598 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1599 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1600 intel_ring_emit(ring, cs_offset);
1601 intel_ring_emit(ring, 4096);
1602 intel_ring_emit(ring, offset);
1604 intel_ring_emit(ring, MI_FLUSH);
1605 intel_ring_emit(ring, MI_NOOP);
1606 intel_ring_advance(ring);
1608 /* ... and execute it. */
1612 ret = intel_ring_begin(ring, 4);
1616 intel_ring_emit(ring, MI_BATCH_BUFFER);
1617 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1618 intel_ring_emit(ring, offset + len - 8);
1619 intel_ring_emit(ring, MI_NOOP);
1620 intel_ring_advance(ring);
1626 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1627 u64 offset, u32 len,
1632 ret = intel_ring_begin(ring, 2);
1636 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1637 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1638 intel_ring_advance(ring);
1643 static void cleanup_status_page(struct intel_engine_cs *ring)
1645 struct drm_i915_gem_object *obj;
1647 obj = ring->status_page.obj;
1651 kunmap(sg_page(obj->pages->sgl));
1652 i915_gem_object_ggtt_unpin(obj);
1653 drm_gem_object_unreference(&obj->base);
1654 ring->status_page.obj = NULL;
1657 static int init_status_page(struct intel_engine_cs *ring)
1659 struct drm_i915_gem_object *obj;
1661 if ((obj = ring->status_page.obj) == NULL) {
1665 obj = i915_gem_alloc_object(ring->dev, 4096);
1667 DRM_ERROR("Failed to allocate status page\n");
1671 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1676 if (!HAS_LLC(ring->dev))
1677 /* On g33, we cannot place HWS above 256MiB, so
1678 * restrict its pinning to the low mappable arena.
1679 * Though this restriction is not documented for
1680 * gen4, gen5, or byt, they also behave similarly
1681 * and hang if the HWS is placed at the top of the
1682 * GTT. To generalise, it appears that all !llc
1683 * platforms have issues with us placing the HWS
1684 * above the mappable region (even though we never
1687 flags |= PIN_MAPPABLE;
1688 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1691 drm_gem_object_unreference(&obj->base);
1695 ring->status_page.obj = obj;
1698 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1699 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1700 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1702 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1703 ring->name, ring->status_page.gfx_addr);
1708 static int init_phys_status_page(struct intel_engine_cs *ring)
1710 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1712 if (!dev_priv->status_page_dmah) {
1713 dev_priv->status_page_dmah =
1714 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1715 if (!dev_priv->status_page_dmah)
1719 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1720 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1725 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1727 iounmap(ringbuf->virtual_start);
1728 ringbuf->virtual_start = NULL;
1729 i915_gem_object_ggtt_unpin(ringbuf->obj);
1732 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1733 struct intel_ringbuffer *ringbuf)
1735 struct drm_i915_private *dev_priv = to_i915(dev);
1736 struct drm_i915_gem_object *obj = ringbuf->obj;
1739 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1743 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1745 i915_gem_object_ggtt_unpin(obj);
1749 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1750 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1751 if (ringbuf->virtual_start == NULL) {
1752 i915_gem_object_ggtt_unpin(obj);
1759 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1761 drm_gem_object_unreference(&ringbuf->obj->base);
1762 ringbuf->obj = NULL;
1765 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1766 struct intel_ringbuffer *ringbuf)
1768 struct drm_i915_gem_object *obj;
1772 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1774 obj = i915_gem_alloc_object(dev, ringbuf->size);
1778 /* mark ring buffers as read-only from GPU side by default */
1786 static int intel_init_ring_buffer(struct drm_device *dev,
1787 struct intel_engine_cs *ring)
1789 struct intel_ringbuffer *ringbuf = ring->buffer;
1792 if (ringbuf == NULL) {
1793 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1796 ring->buffer = ringbuf;
1800 INIT_LIST_HEAD(&ring->active_list);
1801 INIT_LIST_HEAD(&ring->request_list);
1802 INIT_LIST_HEAD(&ring->execlist_queue);
1803 ringbuf->size = 32 * PAGE_SIZE;
1804 ringbuf->ring = ring;
1805 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1807 init_waitqueue_head(&ring->irq_queue);
1809 if (I915_NEED_GFX_HWS(dev)) {
1810 ret = init_status_page(ring);
1814 BUG_ON(ring->id != RCS);
1815 ret = init_phys_status_page(ring);
1820 if (ringbuf->obj == NULL) {
1821 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1823 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1828 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1830 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1832 intel_destroy_ringbuffer_obj(ringbuf);
1837 /* Workaround an erratum on the i830 which causes a hang if
1838 * the TAIL pointer points to within the last 2 cachelines
1841 ringbuf->effective_size = ringbuf->size;
1842 if (IS_I830(dev) || IS_845G(dev))
1843 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
1845 ret = i915_cmd_parser_init_ring(ring);
1849 ret = ring->init(ring);
1857 ring->buffer = NULL;
1861 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
1863 struct drm_i915_private *dev_priv;
1864 struct intel_ringbuffer *ringbuf;
1866 if (!intel_ring_initialized(ring))
1869 dev_priv = to_i915(ring->dev);
1870 ringbuf = ring->buffer;
1872 intel_stop_ring_buffer(ring);
1873 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
1875 intel_unpin_ringbuffer_obj(ringbuf);
1876 intel_destroy_ringbuffer_obj(ringbuf);
1877 ring->preallocated_lazy_request = NULL;
1878 ring->outstanding_lazy_seqno = 0;
1881 ring->cleanup(ring);
1883 cleanup_status_page(ring);
1885 i915_cmd_parser_fini_ring(ring);
1888 ring->buffer = NULL;
1891 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
1893 struct intel_ringbuffer *ringbuf = ring->buffer;
1894 struct drm_i915_gem_request *request;
1898 if (ringbuf->last_retired_head != -1) {
1899 ringbuf->head = ringbuf->last_retired_head;
1900 ringbuf->last_retired_head = -1;
1902 ringbuf->space = intel_ring_space(ringbuf);
1903 if (ringbuf->space >= n)
1907 list_for_each_entry(request, &ring->request_list, list) {
1908 if (__intel_ring_space(request->tail, ringbuf->tail,
1909 ringbuf->size) >= n) {
1910 seqno = request->seqno;
1918 ret = i915_wait_seqno(ring, seqno);
1922 i915_gem_retire_requests_ring(ring);
1923 ringbuf->head = ringbuf->last_retired_head;
1924 ringbuf->last_retired_head = -1;
1926 ringbuf->space = intel_ring_space(ringbuf);
1930 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
1932 struct drm_device *dev = ring->dev;
1933 struct drm_i915_private *dev_priv = dev->dev_private;
1934 struct intel_ringbuffer *ringbuf = ring->buffer;
1938 ret = intel_ring_wait_request(ring, n);
1942 /* force the tail write in case we have been skipping them */
1943 __intel_ring_advance(ring);
1945 /* With GEM the hangcheck timer should kick us out of the loop,
1946 * leaving it early runs the risk of corrupting GEM state (due
1947 * to running on almost untested codepaths). But on resume
1948 * timers don't work yet, so prevent a complete hang in that
1949 * case by choosing an insanely large timeout. */
1950 end = jiffies + 60 * HZ;
1952 trace_i915_ring_wait_begin(ring);
1954 ringbuf->head = I915_READ_HEAD(ring);
1955 ringbuf->space = intel_ring_space(ringbuf);
1956 if (ringbuf->space >= n) {
1963 if (dev_priv->mm.interruptible && signal_pending(current)) {
1968 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1969 dev_priv->mm.interruptible);
1973 if (time_after(jiffies, end)) {
1978 trace_i915_ring_wait_end(ring);
1982 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
1984 uint32_t __iomem *virt;
1985 struct intel_ringbuffer *ringbuf = ring->buffer;
1986 int rem = ringbuf->size - ringbuf->tail;
1988 if (ringbuf->space < rem) {
1989 int ret = ring_wait_for_space(ring, rem);
1994 virt = ringbuf->virtual_start + ringbuf->tail;
1997 iowrite32(MI_NOOP, virt++);
2000 ringbuf->space = intel_ring_space(ringbuf);
2005 int intel_ring_idle(struct intel_engine_cs *ring)
2010 /* We need to add any requests required to flush the objects and ring */
2011 if (ring->outstanding_lazy_seqno) {
2012 ret = i915_add_request(ring, NULL);
2017 /* Wait upon the last request to be completed */
2018 if (list_empty(&ring->request_list))
2021 seqno = list_entry(ring->request_list.prev,
2022 struct drm_i915_gem_request,
2025 return i915_wait_seqno(ring, seqno);
2029 intel_ring_alloc_seqno(struct intel_engine_cs *ring)
2031 if (ring->outstanding_lazy_seqno)
2034 if (ring->preallocated_lazy_request == NULL) {
2035 struct drm_i915_gem_request *request;
2037 request = kmalloc(sizeof(*request), GFP_KERNEL);
2038 if (request == NULL)
2041 ring->preallocated_lazy_request = request;
2044 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
2047 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2050 struct intel_ringbuffer *ringbuf = ring->buffer;
2053 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2054 ret = intel_wrap_ring_buffer(ring);
2059 if (unlikely(ringbuf->space < bytes)) {
2060 ret = ring_wait_for_space(ring, bytes);
2068 int intel_ring_begin(struct intel_engine_cs *ring,
2071 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2074 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2075 dev_priv->mm.interruptible);
2079 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2083 /* Preallocate the olr before touching the ring */
2084 ret = intel_ring_alloc_seqno(ring);
2088 ring->buffer->space -= num_dwords * sizeof(uint32_t);
2092 /* Align the ring tail to a cacheline boundary */
2093 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2095 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2098 if (num_dwords == 0)
2101 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2102 ret = intel_ring_begin(ring, num_dwords);
2106 while (num_dwords--)
2107 intel_ring_emit(ring, MI_NOOP);
2109 intel_ring_advance(ring);
2114 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2116 struct drm_device *dev = ring->dev;
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2119 BUG_ON(ring->outstanding_lazy_seqno);
2121 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2122 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2123 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2125 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2128 ring->set_seqno(ring, seqno);
2129 ring->hangcheck.seqno = seqno;
2132 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2135 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2137 /* Every tail move must follow the sequence below */
2139 /* Disable notification that the ring is IDLE. The GT
2140 * will then assume that it is busy and bring it out of rc6.
2142 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2143 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2145 /* Clear the context id. Here be magic! */
2146 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2148 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2149 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2150 GEN6_BSD_SLEEP_INDICATOR) == 0,
2152 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2154 /* Now that the ring is fully powered up, update the tail */
2155 I915_WRITE_TAIL(ring, value);
2156 POSTING_READ(RING_TAIL(ring->mmio_base));
2158 /* Let the ring send IDLE messages to the GT again,
2159 * and so let it sleep to conserve power when idle.
2161 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2162 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2165 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2166 u32 invalidate, u32 flush)
2171 ret = intel_ring_begin(ring, 4);
2176 if (INTEL_INFO(ring->dev)->gen >= 8)
2179 * Bspec vol 1c.5 - video engine command streamer:
2180 * "If ENABLED, all TLBs will be invalidated once the flush
2181 * operation is complete. This bit is only valid when the
2182 * Post-Sync Operation field is a value of 1h or 3h."
2184 if (invalidate & I915_GEM_GPU_DOMAINS)
2185 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2186 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2187 intel_ring_emit(ring, cmd);
2188 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2189 if (INTEL_INFO(ring->dev)->gen >= 8) {
2190 intel_ring_emit(ring, 0); /* upper addr */
2191 intel_ring_emit(ring, 0); /* value */
2193 intel_ring_emit(ring, 0);
2194 intel_ring_emit(ring, MI_NOOP);
2196 intel_ring_advance(ring);
2201 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2202 u64 offset, u32 len,
2205 bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
2208 ret = intel_ring_begin(ring, 4);
2212 /* FIXME(BDW): Address space and security selectors. */
2213 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2214 intel_ring_emit(ring, lower_32_bits(offset));
2215 intel_ring_emit(ring, upper_32_bits(offset));
2216 intel_ring_emit(ring, MI_NOOP);
2217 intel_ring_advance(ring);
2223 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2224 u64 offset, u32 len,
2229 ret = intel_ring_begin(ring, 2);
2233 intel_ring_emit(ring,
2234 MI_BATCH_BUFFER_START |
2235 (flags & I915_DISPATCH_SECURE ?
2236 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2237 /* bit0-7 is the length on GEN6+ */
2238 intel_ring_emit(ring, offset);
2239 intel_ring_advance(ring);
2245 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2246 u64 offset, u32 len,
2251 ret = intel_ring_begin(ring, 2);
2255 intel_ring_emit(ring,
2256 MI_BATCH_BUFFER_START |
2257 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
2258 /* bit0-7 is the length on GEN6+ */
2259 intel_ring_emit(ring, offset);
2260 intel_ring_advance(ring);
2265 /* Blitter support (SandyBridge+) */
2267 static int gen6_ring_flush(struct intel_engine_cs *ring,
2268 u32 invalidate, u32 flush)
2270 struct drm_device *dev = ring->dev;
2271 struct drm_i915_private *dev_priv = dev->dev_private;
2275 ret = intel_ring_begin(ring, 4);
2280 if (INTEL_INFO(ring->dev)->gen >= 8)
2283 * Bspec vol 1c.3 - blitter engine command streamer:
2284 * "If ENABLED, all TLBs will be invalidated once the flush
2285 * operation is complete. This bit is only valid when the
2286 * Post-Sync Operation field is a value of 1h or 3h."
2288 if (invalidate & I915_GEM_DOMAIN_RENDER)
2289 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
2290 MI_FLUSH_DW_OP_STOREDW;
2291 intel_ring_emit(ring, cmd);
2292 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2293 if (INTEL_INFO(ring->dev)->gen >= 8) {
2294 intel_ring_emit(ring, 0); /* upper addr */
2295 intel_ring_emit(ring, 0); /* value */
2297 intel_ring_emit(ring, 0);
2298 intel_ring_emit(ring, MI_NOOP);
2300 intel_ring_advance(ring);
2302 if (!invalidate && flush) {
2304 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2305 else if (IS_BROADWELL(dev))
2306 dev_priv->fbc.need_sw_cache_clean = true;
2312 int intel_init_render_ring_buffer(struct drm_device *dev)
2314 struct drm_i915_private *dev_priv = dev->dev_private;
2315 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2316 struct drm_i915_gem_object *obj;
2319 ring->name = "render ring";
2321 ring->mmio_base = RENDER_RING_BASE;
2323 if (INTEL_INFO(dev)->gen >= 8) {
2324 if (i915_semaphore_is_enabled(dev)) {
2325 obj = i915_gem_alloc_object(dev, 4096);
2327 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2328 i915.semaphores = 0;
2330 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2331 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2333 drm_gem_object_unreference(&obj->base);
2334 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2335 i915.semaphores = 0;
2337 dev_priv->semaphore_obj = obj;
2341 ring->init_context = intel_ring_workarounds_emit;
2342 ring->add_request = gen6_add_request;
2343 ring->flush = gen8_render_ring_flush;
2344 ring->irq_get = gen8_ring_get_irq;
2345 ring->irq_put = gen8_ring_put_irq;
2346 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2347 ring->get_seqno = gen6_ring_get_seqno;
2348 ring->set_seqno = ring_set_seqno;
2349 if (i915_semaphore_is_enabled(dev)) {
2350 WARN_ON(!dev_priv->semaphore_obj);
2351 ring->semaphore.sync_to = gen8_ring_sync;
2352 ring->semaphore.signal = gen8_rcs_signal;
2353 GEN8_RING_SEMAPHORE_INIT;
2355 } else if (INTEL_INFO(dev)->gen >= 6) {
2356 ring->add_request = gen6_add_request;
2357 ring->flush = gen7_render_ring_flush;
2358 if (INTEL_INFO(dev)->gen == 6)
2359 ring->flush = gen6_render_ring_flush;
2360 ring->irq_get = gen6_ring_get_irq;
2361 ring->irq_put = gen6_ring_put_irq;
2362 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2363 ring->get_seqno = gen6_ring_get_seqno;
2364 ring->set_seqno = ring_set_seqno;
2365 if (i915_semaphore_is_enabled(dev)) {
2366 ring->semaphore.sync_to = gen6_ring_sync;
2367 ring->semaphore.signal = gen6_signal;
2369 * The current semaphore is only applied on pre-gen8
2370 * platform. And there is no VCS2 ring on the pre-gen8
2371 * platform. So the semaphore between RCS and VCS2 is
2372 * initialized as INVALID. Gen8 will initialize the
2373 * sema between VCS2 and RCS later.
2375 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2376 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2377 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2378 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2379 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2380 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2381 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2382 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2383 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2384 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2386 } else if (IS_GEN5(dev)) {
2387 ring->add_request = pc_render_add_request;
2388 ring->flush = gen4_render_ring_flush;
2389 ring->get_seqno = pc_render_get_seqno;
2390 ring->set_seqno = pc_render_set_seqno;
2391 ring->irq_get = gen5_ring_get_irq;
2392 ring->irq_put = gen5_ring_put_irq;
2393 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2394 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2396 ring->add_request = i9xx_add_request;
2397 if (INTEL_INFO(dev)->gen < 4)
2398 ring->flush = gen2_render_ring_flush;
2400 ring->flush = gen4_render_ring_flush;
2401 ring->get_seqno = ring_get_seqno;
2402 ring->set_seqno = ring_set_seqno;
2404 ring->irq_get = i8xx_ring_get_irq;
2405 ring->irq_put = i8xx_ring_put_irq;
2407 ring->irq_get = i9xx_ring_get_irq;
2408 ring->irq_put = i9xx_ring_put_irq;
2410 ring->irq_enable_mask = I915_USER_INTERRUPT;
2412 ring->write_tail = ring_write_tail;
2414 if (IS_HASWELL(dev))
2415 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2416 else if (IS_GEN8(dev))
2417 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2418 else if (INTEL_INFO(dev)->gen >= 6)
2419 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2420 else if (INTEL_INFO(dev)->gen >= 4)
2421 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2422 else if (IS_I830(dev) || IS_845G(dev))
2423 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2425 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2426 ring->init = init_render_ring;
2427 ring->cleanup = render_ring_cleanup;
2429 /* Workaround batchbuffer to combat CS tlb bug. */
2430 if (HAS_BROKEN_CS_TLB(dev)) {
2431 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2433 DRM_ERROR("Failed to allocate batch bo\n");
2437 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2439 drm_gem_object_unreference(&obj->base);
2440 DRM_ERROR("Failed to ping batch bo\n");
2444 ring->scratch.obj = obj;
2445 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2448 return intel_init_ring_buffer(dev, ring);
2451 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2453 struct drm_i915_private *dev_priv = dev->dev_private;
2454 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2456 ring->name = "bsd ring";
2459 ring->write_tail = ring_write_tail;
2460 if (INTEL_INFO(dev)->gen >= 6) {
2461 ring->mmio_base = GEN6_BSD_RING_BASE;
2462 /* gen6 bsd needs a special wa for tail updates */
2464 ring->write_tail = gen6_bsd_ring_write_tail;
2465 ring->flush = gen6_bsd_ring_flush;
2466 ring->add_request = gen6_add_request;
2467 ring->get_seqno = gen6_ring_get_seqno;
2468 ring->set_seqno = ring_set_seqno;
2469 if (INTEL_INFO(dev)->gen >= 8) {
2470 ring->irq_enable_mask =
2471 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2472 ring->irq_get = gen8_ring_get_irq;
2473 ring->irq_put = gen8_ring_put_irq;
2474 ring->dispatch_execbuffer =
2475 gen8_ring_dispatch_execbuffer;
2476 if (i915_semaphore_is_enabled(dev)) {
2477 ring->semaphore.sync_to = gen8_ring_sync;
2478 ring->semaphore.signal = gen8_xcs_signal;
2479 GEN8_RING_SEMAPHORE_INIT;
2482 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2483 ring->irq_get = gen6_ring_get_irq;
2484 ring->irq_put = gen6_ring_put_irq;
2485 ring->dispatch_execbuffer =
2486 gen6_ring_dispatch_execbuffer;
2487 if (i915_semaphore_is_enabled(dev)) {
2488 ring->semaphore.sync_to = gen6_ring_sync;
2489 ring->semaphore.signal = gen6_signal;
2490 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2491 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2492 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2493 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2494 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2495 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2496 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2497 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2498 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2499 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2503 ring->mmio_base = BSD_RING_BASE;
2504 ring->flush = bsd_ring_flush;
2505 ring->add_request = i9xx_add_request;
2506 ring->get_seqno = ring_get_seqno;
2507 ring->set_seqno = ring_set_seqno;
2509 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2510 ring->irq_get = gen5_ring_get_irq;
2511 ring->irq_put = gen5_ring_put_irq;
2513 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2514 ring->irq_get = i9xx_ring_get_irq;
2515 ring->irq_put = i9xx_ring_put_irq;
2517 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2519 ring->init = init_ring_common;
2521 return intel_init_ring_buffer(dev, ring);
2525 * Initialize the second BSD ring for Broadwell GT3.
2526 * It is noted that this only exists on Broadwell GT3.
2528 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2530 struct drm_i915_private *dev_priv = dev->dev_private;
2531 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2533 if ((INTEL_INFO(dev)->gen != 8)) {
2534 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2538 ring->name = "bsd2 ring";
2541 ring->write_tail = ring_write_tail;
2542 ring->mmio_base = GEN8_BSD2_RING_BASE;
2543 ring->flush = gen6_bsd_ring_flush;
2544 ring->add_request = gen6_add_request;
2545 ring->get_seqno = gen6_ring_get_seqno;
2546 ring->set_seqno = ring_set_seqno;
2547 ring->irq_enable_mask =
2548 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2549 ring->irq_get = gen8_ring_get_irq;
2550 ring->irq_put = gen8_ring_put_irq;
2551 ring->dispatch_execbuffer =
2552 gen8_ring_dispatch_execbuffer;
2553 if (i915_semaphore_is_enabled(dev)) {
2554 ring->semaphore.sync_to = gen8_ring_sync;
2555 ring->semaphore.signal = gen8_xcs_signal;
2556 GEN8_RING_SEMAPHORE_INIT;
2558 ring->init = init_ring_common;
2560 return intel_init_ring_buffer(dev, ring);
2563 int intel_init_blt_ring_buffer(struct drm_device *dev)
2565 struct drm_i915_private *dev_priv = dev->dev_private;
2566 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2568 ring->name = "blitter ring";
2571 ring->mmio_base = BLT_RING_BASE;
2572 ring->write_tail = ring_write_tail;
2573 ring->flush = gen6_ring_flush;
2574 ring->add_request = gen6_add_request;
2575 ring->get_seqno = gen6_ring_get_seqno;
2576 ring->set_seqno = ring_set_seqno;
2577 if (INTEL_INFO(dev)->gen >= 8) {
2578 ring->irq_enable_mask =
2579 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2580 ring->irq_get = gen8_ring_get_irq;
2581 ring->irq_put = gen8_ring_put_irq;
2582 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2583 if (i915_semaphore_is_enabled(dev)) {
2584 ring->semaphore.sync_to = gen8_ring_sync;
2585 ring->semaphore.signal = gen8_xcs_signal;
2586 GEN8_RING_SEMAPHORE_INIT;
2589 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2590 ring->irq_get = gen6_ring_get_irq;
2591 ring->irq_put = gen6_ring_put_irq;
2592 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2593 if (i915_semaphore_is_enabled(dev)) {
2594 ring->semaphore.signal = gen6_signal;
2595 ring->semaphore.sync_to = gen6_ring_sync;
2597 * The current semaphore is only applied on pre-gen8
2598 * platform. And there is no VCS2 ring on the pre-gen8
2599 * platform. So the semaphore between BCS and VCS2 is
2600 * initialized as INVALID. Gen8 will initialize the
2601 * sema between BCS and VCS2 later.
2603 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2604 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2605 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2606 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2607 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2608 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2609 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2610 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2611 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2612 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2615 ring->init = init_ring_common;
2617 return intel_init_ring_buffer(dev, ring);
2620 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2622 struct drm_i915_private *dev_priv = dev->dev_private;
2623 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2625 ring->name = "video enhancement ring";
2628 ring->mmio_base = VEBOX_RING_BASE;
2629 ring->write_tail = ring_write_tail;
2630 ring->flush = gen6_ring_flush;
2631 ring->add_request = gen6_add_request;
2632 ring->get_seqno = gen6_ring_get_seqno;
2633 ring->set_seqno = ring_set_seqno;
2635 if (INTEL_INFO(dev)->gen >= 8) {
2636 ring->irq_enable_mask =
2637 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2638 ring->irq_get = gen8_ring_get_irq;
2639 ring->irq_put = gen8_ring_put_irq;
2640 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2641 if (i915_semaphore_is_enabled(dev)) {
2642 ring->semaphore.sync_to = gen8_ring_sync;
2643 ring->semaphore.signal = gen8_xcs_signal;
2644 GEN8_RING_SEMAPHORE_INIT;
2647 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2648 ring->irq_get = hsw_vebox_get_irq;
2649 ring->irq_put = hsw_vebox_put_irq;
2650 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2651 if (i915_semaphore_is_enabled(dev)) {
2652 ring->semaphore.sync_to = gen6_ring_sync;
2653 ring->semaphore.signal = gen6_signal;
2654 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2655 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2656 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2657 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2658 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2659 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2660 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2661 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2662 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2663 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2666 ring->init = init_ring_common;
2668 return intel_init_ring_buffer(dev, ring);
2672 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2676 if (!ring->gpu_caches_dirty)
2679 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2683 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2685 ring->gpu_caches_dirty = false;
2690 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2692 uint32_t flush_domains;
2696 if (ring->gpu_caches_dirty)
2697 flush_domains = I915_GEM_GPU_DOMAINS;
2699 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2703 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2705 ring->gpu_caches_dirty = false;
2710 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2714 if (!intel_ring_initialized(ring))
2717 ret = intel_ring_idle(ring);
2718 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2719 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",