2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
61 u32 val = t4_read_reg(adapter, reg);
63 if (!!(val & mask) == polarity) {
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
161 if (is_t4(adap->params.chip))
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter *adap)
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F)
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
204 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
209 for ( ; nflit; nflit--, mbox_addr += 8)
210 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
214 * Handle a FW assertion reported in a mailbox.
216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
218 struct fw_debug_cmd asrt;
220 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
221 dev_alert(adap->pdev_dev,
222 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
223 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
224 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
227 static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg)
229 dev_err(adap->pdev_dev,
230 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
231 (unsigned long long)t4_read_reg64(adap, data_reg),
232 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
233 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
234 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
235 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
236 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
237 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
238 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
242 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
244 * @mbox: index of the mailbox to use
245 * @cmd: the command to write
246 * @size: command length in bytes
247 * @rpl: where to optionally store the reply
248 * @sleep_ok: if true we may sleep while awaiting command completion
249 * @timeout: time to wait for command to finish before timing out
251 * Sends the given command to FW through the selected mailbox and waits
252 * for the FW to execute the command. If @rpl is not %NULL it is used to
253 * store the FW's reply to the command. The command and its optional
254 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
255 * to respond. @sleep_ok determines whether we may sleep while awaiting
256 * the response. If sleeping is allowed we use progressive backoff
259 * The return value is 0 on success or a negative errno on failure. A
260 * failure can happen either because we are not able to execute the
261 * command or FW executes it but signals an error. In the latter case
262 * the return value is the error code indicated by FW (negated).
264 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
265 int size, void *rpl, bool sleep_ok, int timeout)
267 static const int delay[] = {
268 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
273 int i, ms, delay_idx;
274 const __be64 *p = cmd;
275 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
276 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
278 if ((size & 15) || size > MBOX_LEN)
282 * If the device is off-line, as in EEH, commands will time out.
283 * Fail them early so we don't waste time waiting.
285 if (adap->pdev->error_state != pci_channel_io_normal)
288 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
289 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
290 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
292 if (v != MBOX_OWNER_DRV)
293 return v ? -EBUSY : -ETIMEDOUT;
295 for (i = 0; i < size; i += 8)
296 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
298 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
299 t4_read_reg(adap, ctl_reg); /* flush write */
304 for (i = 0; i < timeout; i += ms) {
306 ms = delay[delay_idx]; /* last element may repeat */
307 if (delay_idx < ARRAY_SIZE(delay) - 1)
313 v = t4_read_reg(adap, ctl_reg);
314 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
315 if (!(v & MBMSGVALID_F)) {
316 t4_write_reg(adap, ctl_reg, 0);
320 res = t4_read_reg64(adap, data_reg);
321 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
322 fw_asrt(adap, data_reg);
323 res = FW_CMD_RETVAL_V(EIO);
325 get_mbox_rpl(adap, rpl, size / 8, data_reg);
328 if (FW_CMD_RETVAL_G((int)res))
329 dump_mbox(adap, mbox, data_reg);
330 t4_write_reg(adap, ctl_reg, 0);
331 return -FW_CMD_RETVAL_G((int)res);
335 dump_mbox(adap, mbox, data_reg);
336 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
337 *(const u8 *)cmd, mbox);
338 t4_report_fw_error(adap);
342 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
343 void *rpl, bool sleep_ok)
345 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
349 static int t4_edc_err_read(struct adapter *adap, int idx)
351 u32 edc_ecc_err_addr_reg;
354 if (is_t4(adap->params.chip)) {
355 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
358 if (idx != 0 && idx != 1) {
359 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
363 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
364 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
367 "edc%d err addr 0x%x: 0x%x.\n",
368 idx, edc_ecc_err_addr_reg,
369 t4_read_reg(adap, edc_ecc_err_addr_reg));
371 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
373 (unsigned long long)t4_read_reg64(adap, rdata_reg),
374 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
375 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
376 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
377 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
378 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
379 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
380 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
381 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
387 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
389 * @win: PCI-E Memory Window to use
390 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
391 * @addr: address within indicated memory type
392 * @len: amount of memory to transfer
393 * @hbuf: host memory buffer
394 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
396 * Reads/writes an [almost] arbitrary memory region in the firmware: the
397 * firmware memory address and host buffer must be aligned on 32-bit
398 * boudaries; the length may be arbitrary. The memory is transferred as
399 * a raw byte sequence from/to the firmware's memory. If this memory
400 * contains data structures which contain multi-byte integers, it's the
401 * caller's responsibility to perform appropriate byte order conversions.
403 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
404 u32 len, void *hbuf, int dir)
406 u32 pos, offset, resid, memoffset;
407 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
410 /* Argument sanity checks ...
412 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
416 /* It's convenient to be able to handle lengths which aren't a
417 * multiple of 32-bits because we often end up transferring files to
418 * the firmware. So we'll handle that by normalizing the length here
419 * and then handling any residual transfer at the end.
424 /* Offset into the region of memory which is being accessed
427 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
428 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
430 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
431 if (mtype != MEM_MC1)
432 memoffset = (mtype * (edc_size * 1024 * 1024));
434 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
435 MA_EXT_MEMORY0_BAR_A));
436 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
439 /* Determine the PCIE_MEM_ACCESS_OFFSET */
440 addr = addr + memoffset;
442 /* Each PCI-E Memory Window is programmed with a window size -- or
443 * "aperture" -- which controls the granularity of its mapping onto
444 * adapter memory. We need to grab that aperture in order to know
445 * how to use the specified window. The window is also programmed
446 * with the base address of the Memory Window in BAR0's address
447 * space. For T4 this is an absolute PCI-E Bus Address. For T5
448 * the address is relative to BAR0.
450 mem_reg = t4_read_reg(adap,
451 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
453 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
454 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
455 if (is_t4(adap->params.chip))
456 mem_base -= adap->t4_bar0;
457 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
459 /* Calculate our initial PCI-E Memory Window Position and Offset into
462 pos = addr & ~(mem_aperture-1);
465 /* Set up initial PCI-E Memory Window to cover the start of our
466 * transfer. (Read it back to ensure that changes propagate before we
467 * attempt to use the new value.)
470 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
473 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
475 /* Transfer data to/from the adapter as long as there's an integral
476 * number of 32-bit transfers to complete.
478 * A note on Endianness issues:
480 * The "register" reads and writes below from/to the PCI-E Memory
481 * Window invoke the standard adapter Big-Endian to PCI-E Link
482 * Little-Endian "swizzel." As a result, if we have the following
483 * data in adapter memory:
485 * Memory: ... | b0 | b1 | b2 | b3 | ...
486 * Address: i+0 i+1 i+2 i+3
488 * Then a read of the adapter memory via the PCI-E Memory Window
493 * [ b3 | b2 | b1 | b0 ]
495 * If this value is stored into local memory on a Little-Endian system
496 * it will show up correctly in local memory as:
498 * ( ..., b0, b1, b2, b3, ... )
500 * But on a Big-Endian system, the store will show up in memory
501 * incorrectly swizzled as:
503 * ( ..., b3, b2, b1, b0, ... )
505 * So we need to account for this in the reads and writes to the
506 * PCI-E Memory Window below by undoing the register read/write
510 if (dir == T4_MEMORY_READ)
511 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
514 t4_write_reg(adap, mem_base + offset,
515 (__force u32)cpu_to_le32(*buf++));
516 offset += sizeof(__be32);
517 len -= sizeof(__be32);
519 /* If we've reached the end of our current window aperture,
520 * move the PCI-E Memory Window on to the next. Note that
521 * doing this here after "len" may be 0 allows us to set up
522 * the PCI-E Memory Window for a possible final residual
525 if (offset == mem_aperture) {
529 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
532 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
537 /* If the original transfer had a length which wasn't a multiple of
538 * 32-bits, now's where we need to finish off the transfer of the
539 * residual amount. The PCI-E Memory Window has already been moved
540 * above (if necessary) to cover this final transfer.
550 if (dir == T4_MEMORY_READ) {
551 last.word = le32_to_cpu(
552 (__force __le32)t4_read_reg(adap,
554 for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
555 bp[i] = last.byte[i];
558 for (i = resid; i < 4; i++)
560 t4_write_reg(adap, mem_base + offset,
561 (__force u32)cpu_to_le32(last.word));
568 /* Return the specified PCI-E Configuration Space register from our Physical
569 * Function. We try first via a Firmware LDST Command since we prefer to let
570 * the firmware own all of these registers, but if that fails we go for it
571 * directly ourselves.
573 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
575 u32 val, ldst_addrspace;
577 /* If fw_attach != 0, construct and send the Firmware LDST Command to
578 * retrieve the specified PCI-E Configuration Space register.
580 struct fw_ldst_cmd ldst_cmd;
583 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
584 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
585 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
589 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
590 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
591 ldst_cmd.u.pcie.ctrl_to_fn =
592 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
593 ldst_cmd.u.pcie.r = reg;
595 /* If the LDST Command succeeds, return the result, otherwise
596 * fall through to reading it directly ourselves ...
598 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
601 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
603 /* Read the desired Configuration Space register via the PCI-E
604 * Backdoor mechanism.
606 t4_hw_pci_read_cfg4(adap, reg, &val);
610 /* Get the window based on base passed to it.
611 * Window aperture is currently unhandled, but there is no use case for it
614 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
619 if (is_t4(adap->params.chip)) {
622 /* Truncation intentional: we only read the bottom 32-bits of
623 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
624 * mechanism to read BAR0 instead of using
625 * pci_resource_start() because we could be operating from
626 * within a Virtual Machine which is trapping our accesses to
627 * our Configuration Space and we need to set up the PCI-E
628 * Memory Window decoders with the actual addresses which will
629 * be coming across the PCI-E link.
631 bar0 = t4_read_pcie_cfg4(adap, pci_base);
633 adap->t4_bar0 = bar0;
635 ret = bar0 + memwin_base;
637 /* For T5, only relative offset inside the PCIe BAR is passed */
643 /* Get the default utility window (win0) used by everyone */
644 u32 t4_get_util_window(struct adapter *adap)
646 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
647 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
650 /* Set up memory window for accessing adapter memory ranges. (Read
651 * back MA register to ensure that changes propagate before we attempt
652 * to use the new values.)
654 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
657 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
658 memwin_base | BIR_V(0) |
659 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
661 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
665 * t4_get_regs_len - return the size of the chips register set
666 * @adapter: the adapter
668 * Returns the size of the chip's BAR0 register space.
670 unsigned int t4_get_regs_len(struct adapter *adapter)
672 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
674 switch (chip_version) {
676 return T4_REGMAP_SIZE;
680 return T5_REGMAP_SIZE;
683 dev_err(adapter->pdev_dev,
684 "Unsupported chip version %d\n", chip_version);
689 * t4_get_regs - read chip registers into provided buffer
691 * @buf: register buffer
692 * @buf_size: size (in bytes) of register buffer
694 * If the provided register buffer isn't large enough for the chip's
695 * full register range, the register dump will be truncated to the
696 * register buffer's size.
698 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
700 static const unsigned int t4_reg_ranges[] = {
1158 static const unsigned int t5_reg_ranges[] = {
1933 static const unsigned int t6_reg_ranges[] = {
2504 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2505 const unsigned int *reg_ranges;
2506 int reg_ranges_size, range;
2507 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2509 /* Select the right set of register ranges to dump depending on the
2510 * adapter chip type.
2512 switch (chip_version) {
2514 reg_ranges = t4_reg_ranges;
2515 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2519 reg_ranges = t5_reg_ranges;
2520 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2524 reg_ranges = t6_reg_ranges;
2525 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2529 dev_err(adap->pdev_dev,
2530 "Unsupported chip version %d\n", chip_version);
2534 /* Clear the register buffer and insert the appropriate register
2535 * values selected by the above register ranges.
2537 memset(buf, 0, buf_size);
2538 for (range = 0; range < reg_ranges_size; range += 2) {
2539 unsigned int reg = reg_ranges[range];
2540 unsigned int last_reg = reg_ranges[range + 1];
2541 u32 *bufp = (u32 *)((char *)buf + reg);
2543 /* Iterate across the register range filling in the register
2544 * buffer but don't write past the end of the register buffer.
2546 while (reg <= last_reg && bufp < buf_end) {
2547 *bufp++ = t4_read_reg(adap, reg);
2553 #define EEPROM_STAT_ADDR 0x7bfc
2554 #define VPD_BASE 0x400
2555 #define VPD_BASE_OLD 0
2556 #define VPD_LEN 1024
2557 #define CHELSIO_VPD_UNIQUE_ID 0x82
2560 * t4_seeprom_wp - enable/disable EEPROM write protection
2561 * @adapter: the adapter
2562 * @enable: whether to enable or disable write protection
2564 * Enables or disables write protection on the serial EEPROM.
2566 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2568 unsigned int v = enable ? 0xc : 0;
2569 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2570 return ret < 0 ? ret : 0;
2574 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2575 * @adapter: adapter to read
2576 * @p: where to store the parameters
2578 * Reads card parameters stored in VPD EEPROM.
2580 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2582 int i, ret = 0, addr;
2585 unsigned int vpdr_len, kw_offset, id_len;
2587 vpd = vmalloc(VPD_LEN);
2591 /* Card information normally starts at VPD_BASE but early cards had
2594 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2598 /* The VPD shall have a unique identifier specified by the PCI SIG.
2599 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2600 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2601 * is expected to automatically put this entry at the
2602 * beginning of the VPD.
2604 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2606 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2610 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2611 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2616 id_len = pci_vpd_lrdt_size(vpd);
2617 if (id_len > ID_LEN)
2620 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2622 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2627 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2628 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2629 if (vpdr_len + kw_offset > VPD_LEN) {
2630 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2635 #define FIND_VPD_KW(var, name) do { \
2636 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2638 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2642 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2645 FIND_VPD_KW(i, "RV");
2646 for (csum = 0; i >= 0; i--)
2650 dev_err(adapter->pdev_dev,
2651 "corrupted VPD EEPROM, actual csum %u\n", csum);
2656 FIND_VPD_KW(ec, "EC");
2657 FIND_VPD_KW(sn, "SN");
2658 FIND_VPD_KW(pn, "PN");
2659 FIND_VPD_KW(na, "NA");
2662 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2664 memcpy(p->ec, vpd + ec, EC_LEN);
2666 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2667 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2669 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2670 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2672 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2673 strim((char *)p->na);
2681 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2682 * @adapter: adapter to read
2683 * @p: where to store the parameters
2685 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2686 * Clock. This can only be called after a connection to the firmware
2689 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2691 u32 cclk_param, cclk_val;
2694 /* Grab the raw VPD parameters.
2696 ret = t4_get_raw_vpd_params(adapter, p);
2700 /* Ask firmware for the Core Clock since it knows how to translate the
2701 * Reference Clock ('V2') VPD field into a Core Clock value ...
2703 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2704 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2705 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2706 1, &cclk_param, &cclk_val);
2715 /* serial flash and firmware constants */
2717 SF_ATTEMPTS = 10, /* max retries for SF operations */
2719 /* flash command opcodes */
2720 SF_PROG_PAGE = 2, /* program page */
2721 SF_WR_DISABLE = 4, /* disable writes */
2722 SF_RD_STATUS = 5, /* read status register */
2723 SF_WR_ENABLE = 6, /* enable writes */
2724 SF_RD_DATA_FAST = 0xb, /* read flash */
2725 SF_RD_ID = 0x9f, /* read ID */
2726 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2728 FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2732 * sf1_read - read data from the serial flash
2733 * @adapter: the adapter
2734 * @byte_cnt: number of bytes to read
2735 * @cont: whether another operation will be chained
2736 * @lock: whether to lock SF for PL access only
2737 * @valp: where to store the read data
2739 * Reads up to 4 bytes of data from the serial flash. The location of
2740 * the read needs to be specified prior to calling this by issuing the
2741 * appropriate commands to the serial flash.
2743 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2744 int lock, u32 *valp)
2748 if (!byte_cnt || byte_cnt > 4)
2750 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2752 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2753 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2754 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2756 *valp = t4_read_reg(adapter, SF_DATA_A);
2761 * sf1_write - write data to the serial flash
2762 * @adapter: the adapter
2763 * @byte_cnt: number of bytes to write
2764 * @cont: whether another operation will be chained
2765 * @lock: whether to lock SF for PL access only
2766 * @val: value to write
2768 * Writes up to 4 bytes of data to the serial flash. The location of
2769 * the write needs to be specified prior to calling this by issuing the
2770 * appropriate commands to the serial flash.
2772 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2775 if (!byte_cnt || byte_cnt > 4)
2777 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2779 t4_write_reg(adapter, SF_DATA_A, val);
2780 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2781 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2782 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2786 * flash_wait_op - wait for a flash operation to complete
2787 * @adapter: the adapter
2788 * @attempts: max number of polls of the status register
2789 * @delay: delay between polls in ms
2791 * Wait for a flash operation to complete by polling the status register.
2793 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2799 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2800 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2804 if (--attempts == 0)
2812 * t4_read_flash - read words from serial flash
2813 * @adapter: the adapter
2814 * @addr: the start address for the read
2815 * @nwords: how many 32-bit words to read
2816 * @data: where to store the read data
2817 * @byte_oriented: whether to store data as bytes or as words
2819 * Read the specified number of 32-bit words from the serial flash.
2820 * If @byte_oriented is set the read data is stored as a byte array
2821 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2822 * natural endianness.
2824 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2825 unsigned int nwords, u32 *data, int byte_oriented)
2829 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2832 addr = swab32(addr) | SF_RD_DATA_FAST;
2834 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2835 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2838 for ( ; nwords; nwords--, data++) {
2839 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2841 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2845 *data = (__force __u32)(cpu_to_be32(*data));
2851 * t4_write_flash - write up to a page of data to the serial flash
2852 * @adapter: the adapter
2853 * @addr: the start address to write
2854 * @n: length of data to write in bytes
2855 * @data: the data to write
2857 * Writes up to a page of data (256 bytes) to the serial flash starting
2858 * at the given address. All the data must be written to the same page.
2860 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2861 unsigned int n, const u8 *data)
2865 unsigned int i, c, left, val, offset = addr & 0xff;
2867 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2870 val = swab32(addr) | SF_PROG_PAGE;
2872 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2873 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2876 for (left = n; left; left -= c) {
2878 for (val = 0, i = 0; i < c; ++i)
2879 val = (val << 8) + *data++;
2881 ret = sf1_write(adapter, c, c != left, 1, val);
2885 ret = flash_wait_op(adapter, 8, 1);
2889 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2891 /* Read the page to verify the write succeeded */
2892 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
2896 if (memcmp(data - n, (u8 *)buf + offset, n)) {
2897 dev_err(adapter->pdev_dev,
2898 "failed to correctly write the flash page at %#x\n",
2905 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2910 * t4_get_fw_version - read the firmware version
2911 * @adapter: the adapter
2912 * @vers: where to place the version
2914 * Reads the FW version from flash.
2916 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2918 return t4_read_flash(adapter, FLASH_FW_START +
2919 offsetof(struct fw_hdr, fw_ver), 1,
2924 * t4_get_tp_version - read the TP microcode version
2925 * @adapter: the adapter
2926 * @vers: where to place the version
2928 * Reads the TP microcode version from flash.
2930 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2932 return t4_read_flash(adapter, FLASH_FW_START +
2933 offsetof(struct fw_hdr, tp_microcode_ver),
2938 * t4_get_exprom_version - return the Expansion ROM version (if any)
2939 * @adapter: the adapter
2940 * @vers: where to place the version
2942 * Reads the Expansion ROM header from FLASH and returns the version
2943 * number (if present) through the @vers return value pointer. We return
2944 * this in the Firmware Version Format since it's convenient. Return
2945 * 0 on success, -ENOENT if no Expansion ROM is present.
2947 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
2949 struct exprom_header {
2950 unsigned char hdr_arr[16]; /* must start with 0x55aa */
2951 unsigned char hdr_ver[4]; /* Expansion ROM version */
2953 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2957 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
2958 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
2963 hdr = (struct exprom_header *)exprom_header_buf;
2964 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2967 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
2968 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
2969 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
2970 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
2975 * t4_check_fw_version - check if the FW is supported with this driver
2976 * @adap: the adapter
2978 * Checks if an adapter's FW is compatible with the driver. Returns 0
2979 * if there's exact match, a negative error if the version could not be
2980 * read or there's a major version mismatch
2982 int t4_check_fw_version(struct adapter *adap)
2984 int i, ret, major, minor, micro;
2985 int exp_major, exp_minor, exp_micro;
2986 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2988 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
2989 /* Try multiple times before returning error */
2990 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
2991 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
2996 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
2997 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
2998 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3000 switch (chip_version) {
3002 exp_major = T4FW_MIN_VERSION_MAJOR;
3003 exp_minor = T4FW_MIN_VERSION_MINOR;
3004 exp_micro = T4FW_MIN_VERSION_MICRO;
3007 exp_major = T5FW_MIN_VERSION_MAJOR;
3008 exp_minor = T5FW_MIN_VERSION_MINOR;
3009 exp_micro = T5FW_MIN_VERSION_MICRO;
3012 exp_major = T6FW_MIN_VERSION_MAJOR;
3013 exp_minor = T6FW_MIN_VERSION_MINOR;
3014 exp_micro = T6FW_MIN_VERSION_MICRO;
3017 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3022 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3023 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3024 dev_err(adap->pdev_dev,
3025 "Card has firmware version %u.%u.%u, minimum "
3026 "supported firmware is %u.%u.%u.\n", major, minor,
3027 micro, exp_major, exp_minor, exp_micro);
3033 /* Is the given firmware API compatible with the one the driver was compiled
3036 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3039 /* short circuit if it's the exact same firmware version */
3040 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3043 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3044 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3045 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3052 /* The firmware in the filesystem is usable, but should it be installed?
3053 * This routine explains itself in detail if it indicates the filesystem
3054 * firmware should be installed.
3056 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3061 if (!card_fw_usable) {
3062 reason = "incompatible or unusable";
3067 reason = "older than the version supported with this driver";
3074 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3075 "installing firmware %u.%u.%u.%u on card.\n",
3076 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3077 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3078 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3079 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3084 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3085 const u8 *fw_data, unsigned int fw_size,
3086 struct fw_hdr *card_fw, enum dev_state state,
3089 int ret, card_fw_usable, fs_fw_usable;
3090 const struct fw_hdr *fs_fw;
3091 const struct fw_hdr *drv_fw;
3093 drv_fw = &fw_info->fw_hdr;
3095 /* Read the header of the firmware on the card */
3096 ret = -t4_read_flash(adap, FLASH_FW_START,
3097 sizeof(*card_fw) / sizeof(uint32_t),
3098 (uint32_t *)card_fw, 1);
3100 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3102 dev_err(adap->pdev_dev,
3103 "Unable to read card's firmware header: %d\n", ret);
3107 if (fw_data != NULL) {
3108 fs_fw = (const void *)fw_data;
3109 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3115 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3116 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3117 /* Common case: the firmware on the card is an exact match and
3118 * the filesystem one is an exact match too, or the filesystem
3119 * one is absent/incompatible.
3121 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3122 should_install_fs_fw(adap, card_fw_usable,
3123 be32_to_cpu(fs_fw->fw_ver),
3124 be32_to_cpu(card_fw->fw_ver))) {
3125 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3128 dev_err(adap->pdev_dev,
3129 "failed to install firmware: %d\n", ret);
3133 /* Installed successfully, update the cached header too. */
3136 *reset = 0; /* already reset as part of load_fw */
3139 if (!card_fw_usable) {
3142 d = be32_to_cpu(drv_fw->fw_ver);
3143 c = be32_to_cpu(card_fw->fw_ver);
3144 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3146 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3148 "driver compiled with %d.%d.%d.%d, "
3149 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3151 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3152 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3153 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3154 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3155 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3156 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3161 /* We're using whatever's on the card and it's known to be good. */
3162 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3163 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3170 * t4_flash_erase_sectors - erase a range of flash sectors
3171 * @adapter: the adapter
3172 * @start: the first sector to erase
3173 * @end: the last sector to erase
3175 * Erases the sectors in the given inclusive range.
3177 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3181 if (end >= adapter->params.sf_nsec)
3184 while (start <= end) {
3185 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3186 (ret = sf1_write(adapter, 4, 0, 1,
3187 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3188 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3189 dev_err(adapter->pdev_dev,
3190 "erase of flash sector %d failed, error %d\n",
3196 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3201 * t4_flash_cfg_addr - return the address of the flash configuration file
3202 * @adapter: the adapter
3204 * Return the address within the flash where the Firmware Configuration
3207 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3209 if (adapter->params.sf_size == 0x100000)
3210 return FLASH_FPGA_CFG_START;
3212 return FLASH_CFG_START;
3215 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3216 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3217 * and emit an error message for mismatched firmware to save our caller the
3220 static bool t4_fw_matches_chip(const struct adapter *adap,
3221 const struct fw_hdr *hdr)
3223 /* The expression below will return FALSE for any unsupported adapter
3224 * which will keep us "honest" in the future ...
3226 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3227 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3228 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3231 dev_err(adap->pdev_dev,
3232 "FW image (%d) is not suitable for this adapter (%d)\n",
3233 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3238 * t4_load_fw - download firmware
3239 * @adap: the adapter
3240 * @fw_data: the firmware image to write
3243 * Write the supplied firmware image to the card's serial flash.
3245 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3250 u8 first_page[SF_PAGE_SIZE];
3251 const __be32 *p = (const __be32 *)fw_data;
3252 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3253 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3254 unsigned int fw_img_start = adap->params.sf_fw_start;
3255 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3258 dev_err(adap->pdev_dev, "FW image has no data\n");
3262 dev_err(adap->pdev_dev,
3263 "FW image size not multiple of 512 bytes\n");
3266 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3267 dev_err(adap->pdev_dev,
3268 "FW image size differs from size in FW header\n");
3271 if (size > FW_MAX_SIZE) {
3272 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3276 if (!t4_fw_matches_chip(adap, hdr))
3279 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3280 csum += be32_to_cpu(p[i]);
3282 if (csum != 0xffffffff) {
3283 dev_err(adap->pdev_dev,
3284 "corrupted firmware image, checksum %#x\n", csum);
3288 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3289 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3294 * We write the correct version at the end so the driver can see a bad
3295 * version if the FW write fails. Start by writing a copy of the
3296 * first page with a bad version.
3298 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3299 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3300 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3304 addr = fw_img_start;
3305 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3306 addr += SF_PAGE_SIZE;
3307 fw_data += SF_PAGE_SIZE;
3308 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3313 ret = t4_write_flash(adap,
3314 fw_img_start + offsetof(struct fw_hdr, fw_ver),
3315 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3318 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3321 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3326 * t4_phy_fw_ver - return current PHY firmware version
3327 * @adap: the adapter
3328 * @phy_fw_ver: return value buffer for PHY firmware version
3330 * Returns the current version of external PHY firmware on the
3333 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3338 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3339 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3340 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3341 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3342 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3351 * t4_load_phy_fw - download port PHY firmware
3352 * @adap: the adapter
3353 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3354 * @win_lock: the lock to use to guard the memory copy
3355 * @phy_fw_version: function to check PHY firmware versions
3356 * @phy_fw_data: the PHY firmware image to write
3357 * @phy_fw_size: image size
3359 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3360 * @phy_fw_version is supplied, then it will be used to determine if
3361 * it's necessary to perform the transfer by comparing the version
3362 * of any existing adapter PHY firmware with that of the passed in
3363 * PHY firmware image. If @win_lock is non-NULL then it will be used
3364 * around the call to t4_memory_rw() which transfers the PHY firmware
3367 * A negative error number will be returned if an error occurs. If
3368 * version number support is available and there's no need to upgrade
3369 * the firmware, 0 will be returned. If firmware is successfully
3370 * transferred to the adapter, 1 will be retured.
3372 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3373 * a result, a RESET of the adapter would cause that RAM to lose its
3374 * contents. Thus, loading PHY firmware on such adapters must happen
3375 * after any FW_RESET_CMDs ...
3377 int t4_load_phy_fw(struct adapter *adap,
3378 int win, spinlock_t *win_lock,
3379 int (*phy_fw_version)(const u8 *, size_t),
3380 const u8 *phy_fw_data, size_t phy_fw_size)
3382 unsigned long mtype = 0, maddr = 0;
3384 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3387 /* If we have version number support, then check to see if the adapter
3388 * already has up-to-date PHY firmware loaded.
3390 if (phy_fw_version) {
3391 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3392 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3396 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3397 CH_WARN(adap, "PHY Firmware already up-to-date, "
3398 "version %#x\n", cur_phy_fw_ver);
3403 /* Ask the firmware where it wants us to copy the PHY firmware image.
3404 * The size of the file requires a special version of the READ coommand
3405 * which will pass the file size via the values field in PARAMS_CMD and
3406 * retrieve the return value from firmware and place it in the same
3409 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3410 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3411 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3412 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3414 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3419 maddr = (val & 0xff) << 16;
3421 /* Copy the supplied PHY Firmware image to the adapter memory location
3422 * allocated by the adapter firmware.
3425 spin_lock_bh(win_lock);
3426 ret = t4_memory_rw(adap, win, mtype, maddr,
3427 phy_fw_size, (__be32 *)phy_fw_data,
3430 spin_unlock_bh(win_lock);
3434 /* Tell the firmware that the PHY firmware image has been written to
3435 * RAM and it can now start copying it over to the PHYs. The chip
3436 * firmware will RESET the affected PHYs as part of this operation
3437 * leaving them running the new PHY firmware image.
3439 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3440 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3441 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3442 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3443 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3444 ¶m, &val, 30000);
3446 /* If we have version number support, then check to see that the new
3447 * firmware got loaded properly.
3449 if (phy_fw_version) {
3450 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3454 if (cur_phy_fw_ver != new_phy_fw_vers) {
3455 CH_WARN(adap, "PHY Firmware did not update: "
3456 "version on adapter %#x, "
3457 "version flashed %#x\n",
3458 cur_phy_fw_ver, new_phy_fw_vers);
3467 * t4_fwcache - firmware cache operation
3468 * @adap: the adapter
3469 * @op : the operation (flush or flush and invalidate)
3471 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3473 struct fw_params_cmd c;
3475 memset(&c, 0, sizeof(c));
3477 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3478 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3479 FW_PARAMS_CMD_PFN_V(adap->pf) |
3480 FW_PARAMS_CMD_VFN_V(0));
3481 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3483 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3484 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3485 c.param[0].val = (__force __be32)op;
3487 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3490 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3491 unsigned int *pif_req_wrptr,
3492 unsigned int *pif_rsp_wrptr)
3495 u32 cfg, val, req, rsp;
3497 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3498 if (cfg & LADBGEN_F)
3499 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3501 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3502 req = POLADBGWRPTR_G(val);
3503 rsp = PILADBGWRPTR_G(val);
3505 *pif_req_wrptr = req;
3507 *pif_rsp_wrptr = rsp;
3509 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3510 for (j = 0; j < 6; j++) {
3511 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3512 PILADBGRDPTR_V(rsp));
3513 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3514 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3518 req = (req + 2) & POLADBGRDPTR_M;
3519 rsp = (rsp + 2) & PILADBGRDPTR_M;
3521 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3524 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3529 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3530 if (cfg & LADBGEN_F)
3531 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3533 for (i = 0; i < CIM_MALA_SIZE; i++) {
3534 for (j = 0; j < 5; j++) {
3536 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3537 PILADBGRDPTR_V(idx));
3538 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3539 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3542 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3545 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3549 for (i = 0; i < 8; i++) {
3550 u32 *p = la_buf + i;
3552 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3553 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3554 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3555 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3556 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3560 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3561 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
3565 * t4_link_l1cfg - apply link configuration to MAC/PHY
3566 * @phy: the PHY to setup
3567 * @mac: the MAC to setup
3568 * @lc: the requested link configuration
3570 * Set up a port's MAC and PHY according to a desired link configuration.
3571 * - If the PHY can auto-negotiate first decide what to advertise, then
3572 * enable/disable auto-negotiation as desired, and reset.
3573 * - If the PHY does not auto-negotiate just reset it.
3574 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3575 * otherwise do it later based on the outcome of auto-negotiation.
3577 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3578 struct link_config *lc)
3580 struct fw_port_cmd c;
3581 unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
3584 if (lc->requested_fc & PAUSE_RX)
3585 fc |= FW_PORT_CAP_FC_RX;
3586 if (lc->requested_fc & PAUSE_TX)
3587 fc |= FW_PORT_CAP_FC_TX;
3589 memset(&c, 0, sizeof(c));
3590 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3591 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3592 FW_PORT_CMD_PORTID_V(port));
3594 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3597 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3598 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3600 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3601 } else if (lc->autoneg == AUTONEG_DISABLE) {
3602 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
3603 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3605 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
3607 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3611 * t4_restart_aneg - restart autonegotiation
3612 * @adap: the adapter
3613 * @mbox: mbox to use for the FW command
3614 * @port: the port id
3616 * Restarts autonegotiation for the selected port.
3618 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3620 struct fw_port_cmd c;
3622 memset(&c, 0, sizeof(c));
3623 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3624 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3625 FW_PORT_CMD_PORTID_V(port));
3627 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3629 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3630 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3633 typedef void (*int_handler_t)(struct adapter *adap);
3636 unsigned int mask; /* bits to check in interrupt status */
3637 const char *msg; /* message to print or NULL */
3638 short stat_idx; /* stat counter to increment or -1 */
3639 unsigned short fatal; /* whether the condition reported is fatal */
3640 int_handler_t int_handler; /* platform-specific int handler */
3644 * t4_handle_intr_status - table driven interrupt handler
3645 * @adapter: the adapter that generated the interrupt
3646 * @reg: the interrupt status register to process
3647 * @acts: table of interrupt actions
3649 * A table driven interrupt handler that applies a set of masks to an
3650 * interrupt status word and performs the corresponding actions if the
3651 * interrupts described by the mask have occurred. The actions include
3652 * optionally emitting a warning or alert message. The table is terminated
3653 * by an entry specifying mask 0. Returns the number of fatal interrupt
3656 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3657 const struct intr_info *acts)
3660 unsigned int mask = 0;
3661 unsigned int status = t4_read_reg(adapter, reg);
3663 for ( ; acts->mask; ++acts) {
3664 if (!(status & acts->mask))
3668 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3669 status & acts->mask);
3670 } else if (acts->msg && printk_ratelimit())
3671 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3672 status & acts->mask);
3673 if (acts->int_handler)
3674 acts->int_handler(adapter);
3678 if (status) /* clear processed interrupts */
3679 t4_write_reg(adapter, reg, status);
3684 * Interrupt handler for the PCIE module.
3686 static void pcie_intr_handler(struct adapter *adapter)
3688 static const struct intr_info sysbus_intr_info[] = {
3689 { RNPP_F, "RXNP array parity error", -1, 1 },
3690 { RPCP_F, "RXPC array parity error", -1, 1 },
3691 { RCIP_F, "RXCIF array parity error", -1, 1 },
3692 { RCCP_F, "Rx completions control array parity error", -1, 1 },
3693 { RFTP_F, "RXFT array parity error", -1, 1 },
3696 static const struct intr_info pcie_port_intr_info[] = {
3697 { TPCP_F, "TXPC array parity error", -1, 1 },
3698 { TNPP_F, "TXNP array parity error", -1, 1 },
3699 { TFTP_F, "TXFT array parity error", -1, 1 },
3700 { TCAP_F, "TXCA array parity error", -1, 1 },
3701 { TCIP_F, "TXCIF array parity error", -1, 1 },
3702 { RCAP_F, "RXCA array parity error", -1, 1 },
3703 { OTDD_F, "outbound request TLP discarded", -1, 1 },
3704 { RDPE_F, "Rx data parity error", -1, 1 },
3705 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
3708 static const struct intr_info pcie_intr_info[] = {
3709 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
3710 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
3711 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
3712 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3713 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3714 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3715 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3716 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
3717 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
3718 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3719 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
3720 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3721 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3722 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
3723 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3724 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3725 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
3726 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3727 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3728 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3729 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3730 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
3731 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
3732 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3733 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
3734 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
3735 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
3736 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
3737 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
3738 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
3743 static struct intr_info t5_pcie_intr_info[] = {
3744 { MSTGRPPERR_F, "Master Response Read Queue parity error",
3746 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
3747 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
3748 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3749 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3750 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3751 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3752 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
3754 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
3756 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3757 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
3758 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3759 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3760 { DREQWRPERR_F, "PCI DMA channel write request parity error",
3762 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3763 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3764 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
3765 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3766 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3767 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3768 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3769 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
3770 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
3771 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3772 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
3774 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
3776 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
3777 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
3778 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3779 { READRSPERR_F, "Outbound read error", -1, 0 },
3785 if (is_t4(adapter->params.chip))
3786 fat = t4_handle_intr_status(adapter,
3787 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
3789 t4_handle_intr_status(adapter,
3790 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
3791 pcie_port_intr_info) +
3792 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3795 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3799 t4_fatal_err(adapter);
3803 * TP interrupt handler.
3805 static void tp_intr_handler(struct adapter *adapter)
3807 static const struct intr_info tp_intr_info[] = {
3808 { 0x3fffffff, "TP parity error", -1, 1 },
3809 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
3813 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
3814 t4_fatal_err(adapter);
3818 * SGE interrupt handler.
3820 static void sge_intr_handler(struct adapter *adapter)
3825 static const struct intr_info sge_intr_info[] = {
3826 { ERR_CPL_EXCEED_IQE_SIZE_F,
3827 "SGE received CPL exceeding IQE size", -1, 1 },
3828 { ERR_INVALID_CIDX_INC_F,
3829 "SGE GTS CIDX increment too large", -1, 0 },
3830 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
3831 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
3832 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
3833 "SGE IQID > 1023 received CPL for FL", -1, 0 },
3834 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
3836 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
3838 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
3840 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
3842 { ERR_ING_CTXT_PRIO_F,
3843 "SGE too many priority ingress contexts", -1, 0 },
3844 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
3845 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
3849 static struct intr_info t4t5_sge_intr_info[] = {
3850 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
3851 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
3852 { ERR_EGR_CTXT_PRIO_F,
3853 "SGE too many priority egress contexts", -1, 0 },
3857 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
3858 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
3860 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
3861 (unsigned long long)v);
3862 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
3863 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
3866 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
3867 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
3868 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
3869 t4t5_sge_intr_info);
3871 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
3872 if (err & ERROR_QID_VALID_F) {
3873 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
3875 if (err & UNCAPTURED_ERROR_F)
3876 dev_err(adapter->pdev_dev,
3877 "SGE UNCAPTURED_ERROR set (clearing)\n");
3878 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
3879 UNCAPTURED_ERROR_F);
3883 t4_fatal_err(adapter);
3886 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
3887 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
3888 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
3889 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
3892 * CIM interrupt handler.
3894 static void cim_intr_handler(struct adapter *adapter)
3896 static const struct intr_info cim_intr_info[] = {
3897 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
3898 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
3899 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
3900 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
3901 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
3902 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
3903 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
3906 static const struct intr_info cim_upintr_info[] = {
3907 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
3908 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
3909 { ILLWRINT_F, "CIM illegal write", -1, 1 },
3910 { ILLRDINT_F, "CIM illegal read", -1, 1 },
3911 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
3912 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
3913 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
3914 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
3915 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
3916 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
3917 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
3918 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
3919 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
3920 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
3921 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
3922 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
3923 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
3924 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
3925 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
3926 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
3927 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
3928 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
3929 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
3930 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
3931 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
3932 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
3933 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
3934 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
3940 if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
3941 t4_report_fw_error(adapter);
3943 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
3945 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
3948 t4_fatal_err(adapter);
3952 * ULP RX interrupt handler.
3954 static void ulprx_intr_handler(struct adapter *adapter)
3956 static const struct intr_info ulprx_intr_info[] = {
3957 { 0x1800000, "ULPRX context error", -1, 1 },
3958 { 0x7fffff, "ULPRX parity error", -1, 1 },
3962 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
3963 t4_fatal_err(adapter);
3967 * ULP TX interrupt handler.
3969 static void ulptx_intr_handler(struct adapter *adapter)
3971 static const struct intr_info ulptx_intr_info[] = {
3972 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
3974 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
3976 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
3978 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
3980 { 0xfffffff, "ULPTX parity error", -1, 1 },
3984 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
3985 t4_fatal_err(adapter);
3989 * PM TX interrupt handler.
3991 static void pmtx_intr_handler(struct adapter *adapter)
3993 static const struct intr_info pmtx_intr_info[] = {
3994 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
3995 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
3996 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
3997 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
3998 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
3999 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4000 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4002 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4003 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4007 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4008 t4_fatal_err(adapter);
4012 * PM RX interrupt handler.
4014 static void pmrx_intr_handler(struct adapter *adapter)
4016 static const struct intr_info pmrx_intr_info[] = {
4017 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4018 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4019 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4020 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4022 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4023 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4027 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4028 t4_fatal_err(adapter);
4032 * CPL switch interrupt handler.
4034 static void cplsw_intr_handler(struct adapter *adapter)
4036 static const struct intr_info cplsw_intr_info[] = {
4037 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4038 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4039 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4040 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4041 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4042 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4046 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4047 t4_fatal_err(adapter);
4051 * LE interrupt handler.
4053 static void le_intr_handler(struct adapter *adap)
4055 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4056 static const struct intr_info le_intr_info[] = {
4057 { LIPMISS_F, "LE LIP miss", -1, 0 },
4058 { LIP0_F, "LE 0 LIP error", -1, 0 },
4059 { PARITYERR_F, "LE parity error", -1, 1 },
4060 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4061 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4065 static struct intr_info t6_le_intr_info[] = {
4066 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4067 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4068 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4069 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4070 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4074 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4075 (chip <= CHELSIO_T5) ?
4076 le_intr_info : t6_le_intr_info))
4081 * MPS interrupt handler.
4083 static void mps_intr_handler(struct adapter *adapter)
4085 static const struct intr_info mps_rx_intr_info[] = {
4086 { 0xffffff, "MPS Rx parity error", -1, 1 },
4089 static const struct intr_info mps_tx_intr_info[] = {
4090 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4091 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4092 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4094 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4096 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4097 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4098 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4101 static const struct intr_info mps_trc_intr_info[] = {
4102 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4103 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4105 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4108 static const struct intr_info mps_stat_sram_intr_info[] = {
4109 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4112 static const struct intr_info mps_stat_tx_intr_info[] = {
4113 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4116 static const struct intr_info mps_stat_rx_intr_info[] = {
4117 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4120 static const struct intr_info mps_cls_intr_info[] = {
4121 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4122 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4123 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4129 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4131 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4133 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4134 mps_trc_intr_info) +
4135 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4136 mps_stat_sram_intr_info) +
4137 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4138 mps_stat_tx_intr_info) +
4139 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4140 mps_stat_rx_intr_info) +
4141 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4144 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4145 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4147 t4_fatal_err(adapter);
4150 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4154 * EDC/MC interrupt handler.
4156 static void mem_intr_handler(struct adapter *adapter, int idx)
4158 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4160 unsigned int addr, cnt_addr, v;
4162 if (idx <= MEM_EDC1) {
4163 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4164 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4165 } else if (idx == MEM_MC) {
4166 if (is_t4(adapter->params.chip)) {
4167 addr = MC_INT_CAUSE_A;
4168 cnt_addr = MC_ECC_STATUS_A;
4170 addr = MC_P_INT_CAUSE_A;
4171 cnt_addr = MC_P_ECC_STATUS_A;
4174 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4175 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4178 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4179 if (v & PERR_INT_CAUSE_F)
4180 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4182 if (v & ECC_CE_INT_CAUSE_F) {
4183 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4185 t4_edc_err_read(adapter, idx);
4187 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4188 if (printk_ratelimit())
4189 dev_warn(adapter->pdev_dev,
4190 "%u %s correctable ECC data error%s\n",
4191 cnt, name[idx], cnt > 1 ? "s" : "");
4193 if (v & ECC_UE_INT_CAUSE_F)
4194 dev_alert(adapter->pdev_dev,
4195 "%s uncorrectable ECC data error\n", name[idx]);
4197 t4_write_reg(adapter, addr, v);
4198 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4199 t4_fatal_err(adapter);
4203 * MA interrupt handler.
4205 static void ma_intr_handler(struct adapter *adap)
4207 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4209 if (status & MEM_PERR_INT_CAUSE_F) {
4210 dev_alert(adap->pdev_dev,
4211 "MA parity error, parity status %#x\n",
4212 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4213 if (is_t5(adap->params.chip))
4214 dev_alert(adap->pdev_dev,
4215 "MA parity error, parity status %#x\n",
4217 MA_PARITY_ERROR_STATUS2_A));
4219 if (status & MEM_WRAP_INT_CAUSE_F) {
4220 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4221 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4222 "client %u to address %#x\n",
4223 MEM_WRAP_CLIENT_NUM_G(v),
4224 MEM_WRAP_ADDRESS_G(v) << 4);
4226 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4231 * SMB interrupt handler.
4233 static void smb_intr_handler(struct adapter *adap)
4235 static const struct intr_info smb_intr_info[] = {
4236 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4237 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4238 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4242 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4247 * NC-SI interrupt handler.
4249 static void ncsi_intr_handler(struct adapter *adap)
4251 static const struct intr_info ncsi_intr_info[] = {
4252 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4253 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4254 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4255 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4259 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4264 * XGMAC interrupt handler.
4266 static void xgmac_intr_handler(struct adapter *adap, int port)
4268 u32 v, int_cause_reg;
4270 if (is_t4(adap->params.chip))
4271 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4273 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4275 v = t4_read_reg(adap, int_cause_reg);
4277 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4281 if (v & TXFIFO_PRTY_ERR_F)
4282 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4284 if (v & RXFIFO_PRTY_ERR_F)
4285 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4287 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4292 * PL interrupt handler.
4294 static void pl_intr_handler(struct adapter *adap)
4296 static const struct intr_info pl_intr_info[] = {
4297 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4298 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4302 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4306 #define PF_INTR_MASK (PFSW_F)
4307 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4308 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4309 CPL_SWITCH_F | SGE_F | ULP_TX_F)
4312 * t4_slow_intr_handler - control path interrupt handler
4313 * @adapter: the adapter
4315 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4316 * The designation 'slow' is because it involves register reads, while
4317 * data interrupts typically don't involve any MMIOs.
4319 int t4_slow_intr_handler(struct adapter *adapter)
4321 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4323 if (!(cause & GLBL_INTR_MASK))
4326 cim_intr_handler(adapter);
4328 mps_intr_handler(adapter);
4330 ncsi_intr_handler(adapter);
4332 pl_intr_handler(adapter);
4334 smb_intr_handler(adapter);
4335 if (cause & XGMAC0_F)
4336 xgmac_intr_handler(adapter, 0);
4337 if (cause & XGMAC1_F)
4338 xgmac_intr_handler(adapter, 1);
4339 if (cause & XGMAC_KR0_F)
4340 xgmac_intr_handler(adapter, 2);
4341 if (cause & XGMAC_KR1_F)
4342 xgmac_intr_handler(adapter, 3);
4344 pcie_intr_handler(adapter);
4346 mem_intr_handler(adapter, MEM_MC);
4347 if (is_t5(adapter->params.chip) && (cause & MC1_F))
4348 mem_intr_handler(adapter, MEM_MC1);
4350 mem_intr_handler(adapter, MEM_EDC0);
4352 mem_intr_handler(adapter, MEM_EDC1);
4354 le_intr_handler(adapter);
4356 tp_intr_handler(adapter);
4358 ma_intr_handler(adapter);
4359 if (cause & PM_TX_F)
4360 pmtx_intr_handler(adapter);
4361 if (cause & PM_RX_F)
4362 pmrx_intr_handler(adapter);
4363 if (cause & ULP_RX_F)
4364 ulprx_intr_handler(adapter);
4365 if (cause & CPL_SWITCH_F)
4366 cplsw_intr_handler(adapter);
4368 sge_intr_handler(adapter);
4369 if (cause & ULP_TX_F)
4370 ulptx_intr_handler(adapter);
4372 /* Clear the interrupts just processed for which we are the master. */
4373 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4374 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4379 * t4_intr_enable - enable interrupts
4380 * @adapter: the adapter whose interrupts should be enabled
4382 * Enable PF-specific interrupts for the calling function and the top-level
4383 * interrupt concentrator for global interrupts. Interrupts are already
4384 * enabled at each module, here we just enable the roots of the interrupt
4387 * Note: this function should be called only when the driver manages
4388 * non PF-specific interrupts from the various HW modules. Only one PCI
4389 * function at a time should be doing this.
4391 void t4_intr_enable(struct adapter *adapter)
4394 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4395 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4396 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4398 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4399 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4400 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4401 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4402 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4403 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4404 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4405 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4406 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4407 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4408 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4412 * t4_intr_disable - disable interrupts
4413 * @adapter: the adapter whose interrupts should be disabled
4415 * Disable interrupts. We only disable the top-level interrupt
4416 * concentrators. The caller must be a PCI function managing global
4419 void t4_intr_disable(struct adapter *adapter)
4421 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4422 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4423 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4425 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4426 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4430 * hash_mac_addr - return the hash value of a MAC address
4431 * @addr: the 48-bit Ethernet MAC address
4433 * Hashes a MAC address according to the hash function used by HW inexact
4434 * (hash) address matching.
4436 static int hash_mac_addr(const u8 *addr)
4438 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
4439 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
4447 * t4_config_rss_range - configure a portion of the RSS mapping table
4448 * @adapter: the adapter
4449 * @mbox: mbox to use for the FW command
4450 * @viid: virtual interface whose RSS subtable is to be written
4451 * @start: start entry in the table to write
4452 * @n: how many table entries to write
4453 * @rspq: values for the response queue lookup table
4454 * @nrspq: number of values in @rspq
4456 * Programs the selected part of the VI's RSS mapping table with the
4457 * provided values. If @nrspq < @n the supplied values are used repeatedly
4458 * until the full table range is populated.
4460 * The caller must ensure the values in @rspq are in the range allowed for
4463 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4464 int start, int n, const u16 *rspq, unsigned int nrspq)
4467 const u16 *rsp = rspq;
4468 const u16 *rsp_end = rspq + nrspq;
4469 struct fw_rss_ind_tbl_cmd cmd;
4471 memset(&cmd, 0, sizeof(cmd));
4472 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4473 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4474 FW_RSS_IND_TBL_CMD_VIID_V(viid));
4475 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4477 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4479 int nq = min(n, 32);
4480 __be32 *qp = &cmd.iq0_to_iq2;
4482 cmd.niqid = cpu_to_be16(nq);
4483 cmd.startidx = cpu_to_be16(start);
4491 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4492 if (++rsp >= rsp_end)
4494 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4495 if (++rsp >= rsp_end)
4497 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4498 if (++rsp >= rsp_end)
4501 *qp++ = cpu_to_be32(v);
4505 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4513 * t4_config_glbl_rss - configure the global RSS mode
4514 * @adapter: the adapter
4515 * @mbox: mbox to use for the FW command
4516 * @mode: global RSS mode
4517 * @flags: mode-specific flags
4519 * Sets the global RSS mode.
4521 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4524 struct fw_rss_glb_config_cmd c;
4526 memset(&c, 0, sizeof(c));
4527 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4528 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4529 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4530 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4531 c.u.manual.mode_pkd =
4532 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4533 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4534 c.u.basicvirtual.mode_pkd =
4535 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4536 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4539 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4543 * t4_config_vi_rss - configure per VI RSS settings
4544 * @adapter: the adapter
4545 * @mbox: mbox to use for the FW command
4548 * @defq: id of the default RSS queue for the VI.
4550 * Configures VI-specific RSS properties.
4552 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4553 unsigned int flags, unsigned int defq)
4555 struct fw_rss_vi_config_cmd c;
4557 memset(&c, 0, sizeof(c));
4558 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
4559 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4560 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
4561 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4562 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4563 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
4564 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4567 /* Read an RSS table row */
4568 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4570 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
4571 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
4576 * t4_read_rss - read the contents of the RSS mapping table
4577 * @adapter: the adapter
4578 * @map: holds the contents of the RSS mapping table
4580 * Reads the contents of the RSS hash->queue mapping table.
4582 int t4_read_rss(struct adapter *adapter, u16 *map)
4587 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4588 ret = rd_rss_row(adapter, i, &val);
4591 *map++ = LKPTBLQUEUE0_G(val);
4592 *map++ = LKPTBLQUEUE1_G(val);
4597 static unsigned int t4_use_ldst(struct adapter *adap)
4599 return (adap->flags & FW_OK) || !adap->use_bd;
4603 * t4_fw_tp_pio_rw - Access TP PIO through LDST
4604 * @adap: the adapter
4605 * @vals: where the indirect register values are stored/written
4606 * @nregs: how many indirect registers to read/write
4607 * @start_idx: index of first indirect register to read/write
4608 * @rw: Read (1) or Write (0)
4610 * Access TP PIO registers through LDST
4612 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4613 unsigned int start_index, unsigned int rw)
4616 int cmd = FW_LDST_ADDRSPC_TP_PIO;
4617 struct fw_ldst_cmd c;
4619 for (i = 0 ; i < nregs; i++) {
4620 memset(&c, 0, sizeof(c));
4621 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4623 (rw ? FW_CMD_READ_F :
4625 FW_LDST_CMD_ADDRSPACE_V(cmd));
4626 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4628 c.u.addrval.addr = cpu_to_be32(start_index + i);
4629 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
4630 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4632 vals[i] = be32_to_cpu(c.u.addrval.val);
4637 * t4_read_rss_key - read the global RSS key
4638 * @adap: the adapter
4639 * @key: 10-entry array holding the 320-bit RSS key
4641 * Reads the global 320-bit RSS key.
4643 void t4_read_rss_key(struct adapter *adap, u32 *key)
4645 if (t4_use_ldst(adap))
4646 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
4648 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4649 TP_RSS_SECRET_KEY0_A);
4653 * t4_write_rss_key - program one of the RSS keys
4654 * @adap: the adapter
4655 * @key: 10-entry array holding the 320-bit RSS key
4656 * @idx: which RSS key to write
4658 * Writes one of the RSS keys with the given 320-bit value. If @idx is
4659 * 0..15 the corresponding entry in the RSS key table is written,
4660 * otherwise the global RSS key is written.
4662 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
4664 u8 rss_key_addr_cnt = 16;
4665 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
4667 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4668 * allows access to key addresses 16-63 by using KeyWrAddrX
4669 * as index[5:4](upper 2) into key table
4671 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
4672 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
4673 rss_key_addr_cnt = 32;
4675 if (t4_use_ldst(adap))
4676 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
4678 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4679 TP_RSS_SECRET_KEY0_A);
4681 if (idx >= 0 && idx < rss_key_addr_cnt) {
4682 if (rss_key_addr_cnt > 16)
4683 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4684 KEYWRADDRX_V(idx >> 4) |
4685 T6_VFWRADDR_V(idx) | KEYWREN_F);
4687 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4688 KEYWRADDR_V(idx) | KEYWREN_F);
4693 * t4_read_rss_pf_config - read PF RSS Configuration Table
4694 * @adapter: the adapter
4695 * @index: the entry in the PF RSS table to read
4696 * @valp: where to store the returned value
4698 * Reads the PF RSS Configuration Table at the specified index and returns
4699 * the value found there.
4701 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4704 if (t4_use_ldst(adapter))
4705 t4_fw_tp_pio_rw(adapter, valp, 1,
4706 TP_RSS_PF0_CONFIG_A + index, 1);
4708 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4709 valp, 1, TP_RSS_PF0_CONFIG_A + index);
4713 * t4_read_rss_vf_config - read VF RSS Configuration Table
4714 * @adapter: the adapter
4715 * @index: the entry in the VF RSS table to read
4716 * @vfl: where to store the returned VFL
4717 * @vfh: where to store the returned VFH
4719 * Reads the VF RSS Configuration Table at the specified index and returns
4720 * the (VFL, VFH) values found there.
4722 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4725 u32 vrt, mask, data;
4727 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
4728 mask = VFWRADDR_V(VFWRADDR_M);
4729 data = VFWRADDR_V(index);
4731 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
4732 data = T6_VFWRADDR_V(index);
4735 /* Request that the index'th VF Table values be read into VFL/VFH.
4737 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
4738 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
4739 vrt |= data | VFRDEN_F;
4740 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
4742 /* Grab the VFL/VFH values ...
4744 if (t4_use_ldst(adapter)) {
4745 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
4746 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
4748 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4749 vfl, 1, TP_RSS_VFL_CONFIG_A);
4750 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4751 vfh, 1, TP_RSS_VFH_CONFIG_A);
4756 * t4_read_rss_pf_map - read PF RSS Map
4757 * @adapter: the adapter
4759 * Reads the PF RSS Map register and returns its value.
4761 u32 t4_read_rss_pf_map(struct adapter *adapter)
4765 if (t4_use_ldst(adapter))
4766 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
4768 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4769 &pfmap, 1, TP_RSS_PF_MAP_A);
4774 * t4_read_rss_pf_mask - read PF RSS Mask
4775 * @adapter: the adapter
4777 * Reads the PF RSS Mask register and returns its value.
4779 u32 t4_read_rss_pf_mask(struct adapter *adapter)
4783 if (t4_use_ldst(adapter))
4784 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
4786 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4787 &pfmask, 1, TP_RSS_PF_MSK_A);
4792 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
4793 * @adap: the adapter
4794 * @v4: holds the TCP/IP counter values
4795 * @v6: holds the TCP/IPv6 counter values
4797 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4798 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4800 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4801 struct tp_tcp_stats *v6)
4803 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
4805 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
4806 #define STAT(x) val[STAT_IDX(x)]
4807 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4810 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4811 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
4812 v4->tcp_out_rsts = STAT(OUT_RST);
4813 v4->tcp_in_segs = STAT64(IN_SEG);
4814 v4->tcp_out_segs = STAT64(OUT_SEG);
4815 v4->tcp_retrans_segs = STAT64(RXT_SEG);
4818 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4819 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
4820 v6->tcp_out_rsts = STAT(OUT_RST);
4821 v6->tcp_in_segs = STAT64(IN_SEG);
4822 v6->tcp_out_segs = STAT64(OUT_SEG);
4823 v6->tcp_retrans_segs = STAT64(RXT_SEG);
4831 * t4_tp_get_err_stats - read TP's error MIB counters
4832 * @adap: the adapter
4833 * @st: holds the counter values
4835 * Returns the values of TP's error counters.
4837 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
4839 int nchan = adap->params.arch.nchan;
4841 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4842 st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
4843 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4844 st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
4845 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4846 st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
4847 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4848 st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
4849 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4850 st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
4851 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4852 st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
4853 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4854 st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
4855 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4856 st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
4858 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4859 &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
4863 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
4864 * @adap: the adapter
4865 * @st: holds the counter values
4867 * Returns the values of TP's CPL counters.
4869 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
4871 int nchan = adap->params.arch.nchan;
4873 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
4874 nchan, TP_MIB_CPL_IN_REQ_0_A);
4875 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
4876 nchan, TP_MIB_CPL_OUT_RSP_0_A);
4881 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
4882 * @adap: the adapter
4883 * @st: holds the counter values
4885 * Returns the values of TP's RDMA counters.
4887 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
4889 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
4890 2, TP_MIB_RQE_DFR_PKT_A);
4894 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
4895 * @adap: the adapter
4896 * @idx: the port index
4897 * @st: holds the counter values
4899 * Returns the values of TP's FCoE counters for the selected port.
4901 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
4902 struct tp_fcoe_stats *st)
4906 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
4907 1, TP_MIB_FCOE_DDP_0_A + idx);
4908 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
4909 1, TP_MIB_FCOE_DROP_0_A + idx);
4910 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4911 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
4912 st->octets_ddp = ((u64)val[0] << 32) | val[1];
4916 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
4917 * @adap: the adapter
4918 * @st: holds the counter values
4920 * Returns the values of TP's counters for non-TCP directly-placed packets.
4922 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
4926 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
4928 st->frames = val[0];
4930 st->octets = ((u64)val[2] << 32) | val[3];
4934 * t4_read_mtu_tbl - returns the values in the HW path MTU table
4935 * @adap: the adapter
4936 * @mtus: where to store the MTU values
4937 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
4939 * Reads the HW path MTU table.
4941 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
4946 for (i = 0; i < NMTUS; ++i) {
4947 t4_write_reg(adap, TP_MTU_TABLE_A,
4948 MTUINDEX_V(0xff) | MTUVALUE_V(i));
4949 v = t4_read_reg(adap, TP_MTU_TABLE_A);
4950 mtus[i] = MTUVALUE_G(v);
4952 mtu_log[i] = MTUWIDTH_G(v);
4957 * t4_read_cong_tbl - reads the congestion control table
4958 * @adap: the adapter
4959 * @incr: where to store the alpha values
4961 * Reads the additive increments programmed into the HW congestion
4964 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
4966 unsigned int mtu, w;
4968 for (mtu = 0; mtu < NMTUS; ++mtu)
4969 for (w = 0; w < NCCTRL_WIN; ++w) {
4970 t4_write_reg(adap, TP_CCTRL_TABLE_A,
4971 ROWINDEX_V(0xffff) | (mtu << 5) | w);
4972 incr[mtu][w] = (u16)t4_read_reg(adap,
4973 TP_CCTRL_TABLE_A) & 0x1fff;
4978 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
4979 * @adap: the adapter
4980 * @addr: the indirect TP register address
4981 * @mask: specifies the field within the register to modify
4982 * @val: new value for the field
4984 * Sets a field of an indirect TP register to the given value.
4986 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
4987 unsigned int mask, unsigned int val)
4989 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
4990 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
4991 t4_write_reg(adap, TP_PIO_DATA_A, val);
4995 * init_cong_ctrl - initialize congestion control parameters
4996 * @a: the alpha values for congestion control
4997 * @b: the beta values for congestion control
4999 * Initialize the congestion control parameters.
5001 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5003 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5028 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5031 b[13] = b[14] = b[15] = b[16] = 3;
5032 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5033 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5038 /* The minimum additive increment value for the congestion control table */
5039 #define CC_MIN_INCR 2U
5042 * t4_load_mtus - write the MTU and congestion control HW tables
5043 * @adap: the adapter
5044 * @mtus: the values for the MTU table
5045 * @alpha: the values for the congestion control alpha parameter
5046 * @beta: the values for the congestion control beta parameter
5048 * Write the HW MTU table with the supplied MTUs and the high-speed
5049 * congestion control table with the supplied alpha, beta, and MTUs.
5050 * We write the two tables together because the additive increments
5051 * depend on the MTUs.
5053 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5054 const unsigned short *alpha, const unsigned short *beta)
5056 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5057 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5058 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5059 28672, 40960, 57344, 81920, 114688, 163840, 229376
5064 for (i = 0; i < NMTUS; ++i) {
5065 unsigned int mtu = mtus[i];
5066 unsigned int log2 = fls(mtu);
5068 if (!(mtu & ((1 << log2) >> 2))) /* round */
5070 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5071 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5073 for (w = 0; w < NCCTRL_WIN; ++w) {
5076 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5079 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5080 (w << 16) | (beta[w] << 13) | inc);
5085 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5086 * clocks. The formula is
5088 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5090 * which is equivalent to
5092 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5094 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5096 u64 v = bytes256 * adap->params.vpd.cclk;
5098 return v * 62 + v / 2;
5102 * t4_get_chan_txrate - get the current per channel Tx rates
5103 * @adap: the adapter
5104 * @nic_rate: rates for NIC traffic
5105 * @ofld_rate: rates for offloaded traffic
5107 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5110 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5114 v = t4_read_reg(adap, TP_TX_TRATE_A);
5115 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5116 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5117 if (adap->params.arch.nchan == NCHAN) {
5118 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5119 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5122 v = t4_read_reg(adap, TP_TX_ORATE_A);
5123 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5124 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5125 if (adap->params.arch.nchan == NCHAN) {
5126 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5127 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5132 * t4_set_trace_filter - configure one of the tracing filters
5133 * @adap: the adapter
5134 * @tp: the desired trace filter parameters
5135 * @idx: which filter to configure
5136 * @enable: whether to enable or disable the filter
5138 * Configures one of the tracing filters available in HW. If @enable is
5139 * %0 @tp is not examined and may be %NULL. The user is responsible to
5140 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5142 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5143 int idx, int enable)
5145 int i, ofst = idx * 4;
5146 u32 data_reg, mask_reg, cfg;
5147 u32 multitrc = TRCMULTIFILTER_F;
5150 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5154 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5155 if (cfg & TRCMULTIFILTER_F) {
5156 /* If multiple tracers are enabled, then maximum
5157 * capture size is 2.5KB (FIFO size of a single channel)
5158 * minus 2 flits for CPL_TRACE_PKT header.
5160 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5163 /* If multiple tracers are disabled, to avoid deadlocks
5164 * maximum packet capture size of 9600 bytes is recommended.
5165 * Also in this mode, only trace0 can be enabled and running.
5168 if (tp->snap_len > 9600 || idx)
5172 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5173 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5174 tp->min_len > TFMINPKTSIZE_M)
5177 /* stop the tracer we'll be changing */
5178 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5180 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5181 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5182 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5184 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5185 t4_write_reg(adap, data_reg, tp->data[i]);
5186 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5188 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5189 TFCAPTUREMAX_V(tp->snap_len) |
5190 TFMINPKTSIZE_V(tp->min_len));
5191 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5192 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5193 (is_t4(adap->params.chip) ?
5194 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5195 T5_TFPORT_V(tp->port) | T5_TFEN_F |
5196 T5_TFINVERTMATCH_V(tp->invert)));
5202 * t4_get_trace_filter - query one of the tracing filters
5203 * @adap: the adapter
5204 * @tp: the current trace filter parameters
5205 * @idx: which trace filter to query
5206 * @enabled: non-zero if the filter is enabled
5208 * Returns the current settings of one of the HW tracing filters.
5210 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5214 int i, ofst = idx * 4;
5215 u32 data_reg, mask_reg;
5217 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5218 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5220 if (is_t4(adap->params.chip)) {
5221 *enabled = !!(ctla & TFEN_F);
5222 tp->port = TFPORT_G(ctla);
5223 tp->invert = !!(ctla & TFINVERTMATCH_F);
5225 *enabled = !!(ctla & T5_TFEN_F);
5226 tp->port = T5_TFPORT_G(ctla);
5227 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5229 tp->snap_len = TFCAPTUREMAX_G(ctlb);
5230 tp->min_len = TFMINPKTSIZE_G(ctlb);
5231 tp->skip_ofst = TFOFFSET_G(ctla);
5232 tp->skip_len = TFLENGTH_G(ctla);
5234 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5235 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5236 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5238 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5239 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5240 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5245 * t4_pmtx_get_stats - returns the HW stats from PMTX
5246 * @adap: the adapter
5247 * @cnt: where to store the count statistics
5248 * @cycles: where to store the cycle statistics
5250 * Returns performance statistics from PMTX.
5252 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5257 for (i = 0; i < PM_NSTATS; i++) {
5258 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5259 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5260 if (is_t4(adap->params.chip)) {
5261 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5263 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5264 PM_TX_DBG_DATA_A, data, 2,
5265 PM_TX_DBG_STAT_MSB_A);
5266 cycles[i] = (((u64)data[0] << 32) | data[1]);
5272 * t4_pmrx_get_stats - returns the HW stats from PMRX
5273 * @adap: the adapter
5274 * @cnt: where to store the count statistics
5275 * @cycles: where to store the cycle statistics
5277 * Returns performance statistics from PMRX.
5279 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5284 for (i = 0; i < PM_NSTATS; i++) {
5285 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5286 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5287 if (is_t4(adap->params.chip)) {
5288 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5290 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5291 PM_RX_DBG_DATA_A, data, 2,
5292 PM_RX_DBG_STAT_MSB_A);
5293 cycles[i] = (((u64)data[0] << 32) | data[1]);
5299 * t4_get_mps_bg_map - return the buffer groups associated with a port
5300 * @adap: the adapter
5301 * @idx: the port index
5303 * Returns a bitmap indicating which MPS buffer groups are associated
5304 * with the given port. Bit i is set if buffer group i is used by the
5307 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5309 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5312 return idx == 0 ? 0xf : 0;
5314 return idx < 2 ? (3 << (2 * idx)) : 0;
5319 * t4_get_port_type_description - return Port Type string description
5320 * @port_type: firmware Port Type enumeration
5322 const char *t4_get_port_type_description(enum fw_port_type port_type)
5324 static const char *const port_type_description[] = {
5343 if (port_type < ARRAY_SIZE(port_type_description))
5344 return port_type_description[port_type];
5349 * t4_get_port_stats_offset - collect port stats relative to a previous
5351 * @adap: The adapter
5353 * @stats: Current stats to fill
5354 * @offset: Previous stats snapshot
5356 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5357 struct port_stats *stats,
5358 struct port_stats *offset)
5363 t4_get_port_stats(adap, idx, stats);
5364 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5365 i < (sizeof(struct port_stats) / sizeof(u64));
5371 * t4_get_port_stats - collect port statistics
5372 * @adap: the adapter
5373 * @idx: the port index
5374 * @p: the stats structure to fill
5376 * Collect statistics related to the given port from HW.
5378 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5380 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5382 #define GET_STAT(name) \
5383 t4_read_reg64(adap, \
5384 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5385 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5386 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5388 p->tx_octets = GET_STAT(TX_PORT_BYTES);
5389 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
5390 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
5391 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
5392 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
5393 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
5394 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
5395 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
5396 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
5397 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
5398 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
5399 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5400 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
5401 p->tx_drop = GET_STAT(TX_PORT_DROP);
5402 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
5403 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
5404 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
5405 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
5406 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
5407 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
5408 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
5409 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
5410 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
5412 p->rx_octets = GET_STAT(RX_PORT_BYTES);
5413 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
5414 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
5415 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
5416 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
5417 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
5418 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5419 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
5420 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
5421 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
5422 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
5423 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
5424 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
5425 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
5426 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
5427 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
5428 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
5429 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
5430 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
5431 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
5432 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
5433 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
5434 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
5435 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
5436 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
5437 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
5438 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
5440 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5441 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5442 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5443 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5444 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5445 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5446 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5447 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5454 * t4_get_lb_stats - collect loopback port statistics
5455 * @adap: the adapter
5456 * @idx: the loopback port index
5457 * @p: the stats structure to fill
5459 * Return HW statistics for the given loopback port.
5461 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5463 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5465 #define GET_STAT(name) \
5466 t4_read_reg64(adap, \
5467 (is_t4(adap->params.chip) ? \
5468 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
5469 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
5470 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5472 p->octets = GET_STAT(BYTES);
5473 p->frames = GET_STAT(FRAMES);
5474 p->bcast_frames = GET_STAT(BCAST);
5475 p->mcast_frames = GET_STAT(MCAST);
5476 p->ucast_frames = GET_STAT(UCAST);
5477 p->error_frames = GET_STAT(ERROR);
5479 p->frames_64 = GET_STAT(64B);
5480 p->frames_65_127 = GET_STAT(65B_127B);
5481 p->frames_128_255 = GET_STAT(128B_255B);
5482 p->frames_256_511 = GET_STAT(256B_511B);
5483 p->frames_512_1023 = GET_STAT(512B_1023B);
5484 p->frames_1024_1518 = GET_STAT(1024B_1518B);
5485 p->frames_1519_max = GET_STAT(1519B_MAX);
5486 p->drop = GET_STAT(DROP_FRAMES);
5488 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5489 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5490 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5491 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5492 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5493 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5494 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5495 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5501 /* t4_mk_filtdelwr - create a delete filter WR
5502 * @ftid: the filter ID
5503 * @wr: the filter work request to populate
5504 * @qid: ingress queue to receive the delete notification
5506 * Creates a filter work request to delete the supplied filter. If @qid is
5507 * negative the delete notification is suppressed.
5509 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5511 memset(wr, 0, sizeof(*wr));
5512 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
5513 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
5514 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
5515 FW_FILTER_WR_NOREPLY_V(qid < 0));
5516 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
5518 wr->rx_chan_rx_rpl_iq =
5519 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
5522 #define INIT_CMD(var, cmd, rd_wr) do { \
5523 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
5524 FW_CMD_REQUEST_F | \
5525 FW_CMD_##rd_wr##_F); \
5526 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5529 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5533 struct fw_ldst_cmd c;
5535 memset(&c, 0, sizeof(c));
5536 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
5537 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5541 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5542 c.u.addrval.addr = cpu_to_be32(addr);
5543 c.u.addrval.val = cpu_to_be32(val);
5545 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5549 * t4_mdio_rd - read a PHY register through MDIO
5550 * @adap: the adapter
5551 * @mbox: mailbox to use for the FW command
5552 * @phy_addr: the PHY address
5553 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5554 * @reg: the register to read
5555 * @valp: where to store the value
5557 * Issues a FW command through the given mailbox to read a PHY register.
5559 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5560 unsigned int mmd, unsigned int reg, u16 *valp)
5564 struct fw_ldst_cmd c;
5566 memset(&c, 0, sizeof(c));
5567 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5568 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5569 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5571 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5572 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5573 FW_LDST_CMD_MMD_V(mmd));
5574 c.u.mdio.raddr = cpu_to_be16(reg);
5576 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5578 *valp = be16_to_cpu(c.u.mdio.rval);
5583 * t4_mdio_wr - write a PHY register through MDIO
5584 * @adap: the adapter
5585 * @mbox: mailbox to use for the FW command
5586 * @phy_addr: the PHY address
5587 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5588 * @reg: the register to write
5589 * @valp: value to write
5591 * Issues a FW command through the given mailbox to write a PHY register.
5593 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5594 unsigned int mmd, unsigned int reg, u16 val)
5597 struct fw_ldst_cmd c;
5599 memset(&c, 0, sizeof(c));
5600 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5601 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5602 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5604 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5605 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5606 FW_LDST_CMD_MMD_V(mmd));
5607 c.u.mdio.raddr = cpu_to_be16(reg);
5608 c.u.mdio.rval = cpu_to_be16(val);
5610 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5614 * t4_sge_decode_idma_state - decode the idma state
5615 * @adap: the adapter
5616 * @state: the state idma is stuck in
5618 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
5620 static const char * const t4_decode[] = {
5622 "IDMA_PUSH_MORE_CPL_FIFO",
5623 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5625 "IDMA_PHYSADDR_SEND_PCIEHDR",
5626 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5627 "IDMA_PHYSADDR_SEND_PAYLOAD",
5628 "IDMA_SEND_FIFO_TO_IMSG",
5629 "IDMA_FL_REQ_DATA_FL_PREP",
5630 "IDMA_FL_REQ_DATA_FL",
5632 "IDMA_FL_H_REQ_HEADER_FL",
5633 "IDMA_FL_H_SEND_PCIEHDR",
5634 "IDMA_FL_H_PUSH_CPL_FIFO",
5635 "IDMA_FL_H_SEND_CPL",
5636 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5637 "IDMA_FL_H_SEND_IP_HDR",
5638 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5639 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5640 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5641 "IDMA_FL_D_SEND_PCIEHDR",
5642 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5643 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5644 "IDMA_FL_SEND_PCIEHDR",
5645 "IDMA_FL_PUSH_CPL_FIFO",
5647 "IDMA_FL_SEND_PAYLOAD_FIRST",
5648 "IDMA_FL_SEND_PAYLOAD",
5649 "IDMA_FL_REQ_NEXT_DATA_FL",
5650 "IDMA_FL_SEND_NEXT_PCIEHDR",
5651 "IDMA_FL_SEND_PADDING",
5652 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5653 "IDMA_FL_SEND_FIFO_TO_IMSG",
5654 "IDMA_FL_REQ_DATAFL_DONE",
5655 "IDMA_FL_REQ_HEADERFL_DONE",
5657 static const char * const t5_decode[] = {
5660 "IDMA_PUSH_MORE_CPL_FIFO",
5661 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5662 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5663 "IDMA_PHYSADDR_SEND_PCIEHDR",
5664 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5665 "IDMA_PHYSADDR_SEND_PAYLOAD",
5666 "IDMA_SEND_FIFO_TO_IMSG",
5667 "IDMA_FL_REQ_DATA_FL",
5669 "IDMA_FL_DROP_SEND_INC",
5670 "IDMA_FL_H_REQ_HEADER_FL",
5671 "IDMA_FL_H_SEND_PCIEHDR",
5672 "IDMA_FL_H_PUSH_CPL_FIFO",
5673 "IDMA_FL_H_SEND_CPL",
5674 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5675 "IDMA_FL_H_SEND_IP_HDR",
5676 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5677 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5678 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5679 "IDMA_FL_D_SEND_PCIEHDR",
5680 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5681 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5682 "IDMA_FL_SEND_PCIEHDR",
5683 "IDMA_FL_PUSH_CPL_FIFO",
5685 "IDMA_FL_SEND_PAYLOAD_FIRST",
5686 "IDMA_FL_SEND_PAYLOAD",
5687 "IDMA_FL_REQ_NEXT_DATA_FL",
5688 "IDMA_FL_SEND_NEXT_PCIEHDR",
5689 "IDMA_FL_SEND_PADDING",
5690 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5692 static const u32 sge_regs[] = {
5693 SGE_DEBUG_DATA_LOW_INDEX_2_A,
5694 SGE_DEBUG_DATA_LOW_INDEX_3_A,
5695 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
5697 const char **sge_idma_decode;
5698 int sge_idma_decode_nstates;
5701 if (is_t4(adapter->params.chip)) {
5702 sge_idma_decode = (const char **)t4_decode;
5703 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5705 sge_idma_decode = (const char **)t5_decode;
5706 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5709 if (state < sge_idma_decode_nstates)
5710 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
5712 CH_WARN(adapter, "idma state %d unknown\n", state);
5714 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
5715 CH_WARN(adapter, "SGE register %#x value %#x\n",
5716 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
5720 * t4_sge_ctxt_flush - flush the SGE context cache
5721 * @adap: the adapter
5722 * @mbox: mailbox to use for the FW command
5724 * Issues a FW command through the given mailbox to flush the
5725 * SGE context cache.
5727 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
5731 struct fw_ldst_cmd c;
5733 memset(&c, 0, sizeof(c));
5734 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
5735 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5736 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5738 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5739 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
5741 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5746 * t4_fw_hello - establish communication with FW
5747 * @adap: the adapter
5748 * @mbox: mailbox to use for the FW command
5749 * @evt_mbox: mailbox to receive async FW events
5750 * @master: specifies the caller's willingness to be the device master
5751 * @state: returns the current device state (if non-NULL)
5753 * Issues a command to establish communication with FW. Returns either
5754 * an error (negative integer) or the mailbox of the Master PF.
5756 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
5757 enum dev_master master, enum dev_state *state)
5760 struct fw_hello_cmd c;
5762 unsigned int master_mbox;
5763 int retries = FW_CMD_HELLO_RETRIES;
5766 memset(&c, 0, sizeof(c));
5767 INIT_CMD(c, HELLO, WRITE);
5768 c.err_to_clearinit = cpu_to_be32(
5769 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
5770 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
5771 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
5772 mbox : FW_HELLO_CMD_MBMASTER_M) |
5773 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
5774 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
5775 FW_HELLO_CMD_CLEARINIT_F);
5778 * Issue the HELLO command to the firmware. If it's not successful
5779 * but indicates that we got a "busy" or "timeout" condition, retry
5780 * the HELLO until we exhaust our retry limit. If we do exceed our
5781 * retry limit, check to see if the firmware left us any error
5782 * information and report that if so.
5784 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5786 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
5788 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
5789 t4_report_fw_error(adap);
5793 v = be32_to_cpu(c.err_to_clearinit);
5794 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
5796 if (v & FW_HELLO_CMD_ERR_F)
5797 *state = DEV_STATE_ERR;
5798 else if (v & FW_HELLO_CMD_INIT_F)
5799 *state = DEV_STATE_INIT;
5801 *state = DEV_STATE_UNINIT;
5805 * If we're not the Master PF then we need to wait around for the
5806 * Master PF Driver to finish setting up the adapter.
5808 * Note that we also do this wait if we're a non-Master-capable PF and
5809 * there is no current Master PF; a Master PF may show up momentarily
5810 * and we wouldn't want to fail pointlessly. (This can happen when an
5811 * OS loads lots of different drivers rapidly at the same time). In
5812 * this case, the Master PF returned by the firmware will be
5813 * PCIE_FW_MASTER_M so the test below will work ...
5815 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
5816 master_mbox != mbox) {
5817 int waiting = FW_CMD_HELLO_TIMEOUT;
5820 * Wait for the firmware to either indicate an error or
5821 * initialized state. If we see either of these we bail out
5822 * and report the issue to the caller. If we exhaust the
5823 * "hello timeout" and we haven't exhausted our retries, try
5824 * again. Otherwise bail with a timeout error.
5833 * If neither Error nor Initialialized are indicated
5834 * by the firmware keep waiting till we exaust our
5835 * timeout ... and then retry if we haven't exhausted
5838 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
5839 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
5850 * We either have an Error or Initialized condition
5851 * report errors preferentially.
5854 if (pcie_fw & PCIE_FW_ERR_F)
5855 *state = DEV_STATE_ERR;
5856 else if (pcie_fw & PCIE_FW_INIT_F)
5857 *state = DEV_STATE_INIT;
5861 * If we arrived before a Master PF was selected and
5862 * there's not a valid Master PF, grab its identity
5865 if (master_mbox == PCIE_FW_MASTER_M &&
5866 (pcie_fw & PCIE_FW_MASTER_VLD_F))
5867 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
5876 * t4_fw_bye - end communication with FW
5877 * @adap: the adapter
5878 * @mbox: mailbox to use for the FW command
5880 * Issues a command to terminate communication with FW.
5882 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
5884 struct fw_bye_cmd c;
5886 memset(&c, 0, sizeof(c));
5887 INIT_CMD(c, BYE, WRITE);
5888 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5892 * t4_init_cmd - ask FW to initialize the device
5893 * @adap: the adapter
5894 * @mbox: mailbox to use for the FW command
5896 * Issues a command to FW to partially initialize the device. This
5897 * performs initialization that generally doesn't depend on user input.
5899 int t4_early_init(struct adapter *adap, unsigned int mbox)
5901 struct fw_initialize_cmd c;
5903 memset(&c, 0, sizeof(c));
5904 INIT_CMD(c, INITIALIZE, WRITE);
5905 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5909 * t4_fw_reset - issue a reset to FW
5910 * @adap: the adapter
5911 * @mbox: mailbox to use for the FW command
5912 * @reset: specifies the type of reset to perform
5914 * Issues a reset command of the specified type to FW.
5916 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
5918 struct fw_reset_cmd c;
5920 memset(&c, 0, sizeof(c));
5921 INIT_CMD(c, RESET, WRITE);
5922 c.val = cpu_to_be32(reset);
5923 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5927 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
5928 * @adap: the adapter
5929 * @mbox: mailbox to use for the FW RESET command (if desired)
5930 * @force: force uP into RESET even if FW RESET command fails
5932 * Issues a RESET command to firmware (if desired) with a HALT indication
5933 * and then puts the microprocessor into RESET state. The RESET command
5934 * will only be issued if a legitimate mailbox is provided (mbox <=
5935 * PCIE_FW_MASTER_M).
5937 * This is generally used in order for the host to safely manipulate the
5938 * adapter without fear of conflicting with whatever the firmware might
5939 * be doing. The only way out of this state is to RESTART the firmware
5942 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
5947 * If a legitimate mailbox is provided, issue a RESET command
5948 * with a HALT indication.
5950 if (mbox <= PCIE_FW_MASTER_M) {
5951 struct fw_reset_cmd c;
5953 memset(&c, 0, sizeof(c));
5954 INIT_CMD(c, RESET, WRITE);
5955 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
5956 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
5957 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5961 * Normally we won't complete the operation if the firmware RESET
5962 * command fails but if our caller insists we'll go ahead and put the
5963 * uP into RESET. This can be useful if the firmware is hung or even
5964 * missing ... We'll have to take the risk of putting the uP into
5965 * RESET without the cooperation of firmware in that case.
5967 * We also force the firmware's HALT flag to be on in case we bypassed
5968 * the firmware RESET command above or we're dealing with old firmware
5969 * which doesn't have the HALT capability. This will serve as a flag
5970 * for the incoming firmware to know that it's coming out of a HALT
5971 * rather than a RESET ... if it's new enough to understand that ...
5973 if (ret == 0 || force) {
5974 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
5975 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
5980 * And we always return the result of the firmware RESET command
5981 * even when we force the uP into RESET ...
5987 * t4_fw_restart - restart the firmware by taking the uP out of RESET
5988 * @adap: the adapter
5989 * @reset: if we want to do a RESET to restart things
5991 * Restart firmware previously halted by t4_fw_halt(). On successful
5992 * return the previous PF Master remains as the new PF Master and there
5993 * is no need to issue a new HELLO command, etc.
5995 * We do this in two ways:
5997 * 1. If we're dealing with newer firmware we'll simply want to take
5998 * the chip's microprocessor out of RESET. This will cause the
5999 * firmware to start up from its start vector. And then we'll loop
6000 * until the firmware indicates it's started again (PCIE_FW.HALT
6001 * reset to 0) or we timeout.
6003 * 2. If we're dealing with older firmware then we'll need to RESET
6004 * the chip since older firmware won't recognize the PCIE_FW.HALT
6005 * flag and automatically RESET itself on startup.
6007 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6011 * Since we're directing the RESET instead of the firmware
6012 * doing it automatically, we need to clear the PCIE_FW.HALT
6015 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6018 * If we've been given a valid mailbox, first try to get the
6019 * firmware to do the RESET. If that works, great and we can
6020 * return success. Otherwise, if we haven't been given a
6021 * valid mailbox or the RESET command failed, fall back to
6022 * hitting the chip with a hammer.
6024 if (mbox <= PCIE_FW_MASTER_M) {
6025 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6027 if (t4_fw_reset(adap, mbox,
6028 PIORST_F | PIORSTMODE_F) == 0)
6032 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6037 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6038 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6039 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6050 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6051 * @adap: the adapter
6052 * @mbox: mailbox to use for the FW RESET command (if desired)
6053 * @fw_data: the firmware image to write
6055 * @force: force upgrade even if firmware doesn't cooperate
6057 * Perform all of the steps necessary for upgrading an adapter's
6058 * firmware image. Normally this requires the cooperation of the
6059 * existing firmware in order to halt all existing activities
6060 * but if an invalid mailbox token is passed in we skip that step
6061 * (though we'll still put the adapter microprocessor into RESET in
6064 * On successful return the new firmware will have been loaded and
6065 * the adapter will have been fully RESET losing all previous setup
6066 * state. On unsuccessful return the adapter may be completely hosed ...
6067 * positive errno indicates that the adapter is ~probably~ intact, a
6068 * negative errno indicates that things are looking bad ...
6070 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6071 const u8 *fw_data, unsigned int size, int force)
6073 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6076 if (!t4_fw_matches_chip(adap, fw_hdr))
6079 ret = t4_fw_halt(adap, mbox, force);
6080 if (ret < 0 && !force)
6083 ret = t4_load_fw(adap, fw_data, size);
6088 * Older versions of the firmware don't understand the new
6089 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6090 * restart. So for newly loaded older firmware we'll have to do the
6091 * RESET for it so it starts up on a clean slate. We can tell if
6092 * the newly loaded firmware will handle this right by checking
6093 * its header flags to see if it advertises the capability.
6095 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6096 return t4_fw_restart(adap, mbox, reset);
6100 * t4_fixup_host_params - fix up host-dependent parameters
6101 * @adap: the adapter
6102 * @page_size: the host's Base Page Size
6103 * @cache_line_size: the host's Cache Line Size
6105 * Various registers in T4 contain values which are dependent on the
6106 * host's Base Page and Cache Line Sizes. This function will fix all of
6107 * those registers with the appropriate values as passed in ...
6109 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6110 unsigned int cache_line_size)
6112 unsigned int page_shift = fls(page_size) - 1;
6113 unsigned int sge_hps = page_shift - 10;
6114 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6115 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6116 unsigned int fl_align_log = fls(fl_align) - 1;
6118 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6119 HOSTPAGESIZEPF0_V(sge_hps) |
6120 HOSTPAGESIZEPF1_V(sge_hps) |
6121 HOSTPAGESIZEPF2_V(sge_hps) |
6122 HOSTPAGESIZEPF3_V(sge_hps) |
6123 HOSTPAGESIZEPF4_V(sge_hps) |
6124 HOSTPAGESIZEPF5_V(sge_hps) |
6125 HOSTPAGESIZEPF6_V(sge_hps) |
6126 HOSTPAGESIZEPF7_V(sge_hps));
6128 if (is_t4(adap->params.chip)) {
6129 t4_set_reg_field(adap, SGE_CONTROL_A,
6130 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6131 EGRSTATUSPAGESIZE_F,
6132 INGPADBOUNDARY_V(fl_align_log -
6133 INGPADBOUNDARY_SHIFT_X) |
6134 EGRSTATUSPAGESIZE_V(stat_len != 64));
6136 /* T5 introduced the separation of the Free List Padding and
6137 * Packing Boundaries. Thus, we can select a smaller Padding
6138 * Boundary to avoid uselessly chewing up PCIe Link and Memory
6139 * Bandwidth, and use a Packing Boundary which is large enough
6140 * to avoid false sharing between CPUs, etc.
6142 * For the PCI Link, the smaller the Padding Boundary the
6143 * better. For the Memory Controller, a smaller Padding
6144 * Boundary is better until we cross under the Memory Line
6145 * Size (the minimum unit of transfer to/from Memory). If we
6146 * have a Padding Boundary which is smaller than the Memory
6147 * Line Size, that'll involve a Read-Modify-Write cycle on the
6148 * Memory Controller which is never good. For T5 the smallest
6149 * Padding Boundary which we can select is 32 bytes which is
6150 * larger than any known Memory Controller Line Size so we'll
6153 * T5 has a different interpretation of the "0" value for the
6154 * Packing Boundary. This corresponds to 16 bytes instead of
6155 * the expected 32 bytes. We never have a Packing Boundary
6156 * less than 32 bytes so we can't use that special value but
6157 * on the other hand, if we wanted 32 bytes, the best we can
6158 * really do is 64 bytes.
6160 if (fl_align <= 32) {
6164 t4_set_reg_field(adap, SGE_CONTROL_A,
6165 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6166 EGRSTATUSPAGESIZE_F,
6167 INGPADBOUNDARY_V(INGPCIEBOUNDARY_32B_X) |
6168 EGRSTATUSPAGESIZE_V(stat_len != 64));
6169 t4_set_reg_field(adap, SGE_CONTROL2_A,
6170 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6171 INGPACKBOUNDARY_V(fl_align_log -
6172 INGPACKBOUNDARY_SHIFT_X));
6175 * Adjust various SGE Free List Host Buffer Sizes.
6177 * This is something of a crock since we're using fixed indices into
6178 * the array which are also known by the sge.c code and the T4
6179 * Firmware Configuration File. We need to come up with a much better
6180 * approach to managing this array. For now, the first four entries
6185 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6186 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6188 * For the single-MTU buffers in unpacked mode we need to include
6189 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6190 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6191 * Padding boundary. All of these are accommodated in the Factory
6192 * Default Firmware Configuration File but we need to adjust it for
6193 * this host's cache line size.
6195 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6196 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6197 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6199 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6200 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6203 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6209 * t4_fw_initialize - ask FW to initialize the device
6210 * @adap: the adapter
6211 * @mbox: mailbox to use for the FW command
6213 * Issues a command to FW to partially initialize the device. This
6214 * performs initialization that generally doesn't depend on user input.
6216 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6218 struct fw_initialize_cmd c;
6220 memset(&c, 0, sizeof(c));
6221 INIT_CMD(c, INITIALIZE, WRITE);
6222 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6226 * t4_query_params_rw - query FW or device parameters
6227 * @adap: the adapter
6228 * @mbox: mailbox to use for the FW command
6231 * @nparams: the number of parameters
6232 * @params: the parameter names
6233 * @val: the parameter values
6234 * @rw: Write and read flag
6236 * Reads the value of FW or device parameters. Up to 7 parameters can be
6239 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6240 unsigned int vf, unsigned int nparams, const u32 *params,
6244 struct fw_params_cmd c;
6245 __be32 *p = &c.param[0].mnem;
6250 memset(&c, 0, sizeof(c));
6251 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6252 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6253 FW_PARAMS_CMD_PFN_V(pf) |
6254 FW_PARAMS_CMD_VFN_V(vf));
6255 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6257 for (i = 0; i < nparams; i++) {
6258 *p++ = cpu_to_be32(*params++);
6260 *p = cpu_to_be32(*(val + i));
6264 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6266 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6267 *val++ = be32_to_cpu(*p);
6271 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6272 unsigned int vf, unsigned int nparams, const u32 *params,
6275 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6279 * t4_set_params_timeout - sets FW or device parameters
6280 * @adap: the adapter
6281 * @mbox: mailbox to use for the FW command
6284 * @nparams: the number of parameters
6285 * @params: the parameter names
6286 * @val: the parameter values
6287 * @timeout: the timeout time
6289 * Sets the value of FW or device parameters. Up to 7 parameters can be
6290 * specified at once.
6292 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6293 unsigned int pf, unsigned int vf,
6294 unsigned int nparams, const u32 *params,
6295 const u32 *val, int timeout)
6297 struct fw_params_cmd c;
6298 __be32 *p = &c.param[0].mnem;
6303 memset(&c, 0, sizeof(c));
6304 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6305 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6306 FW_PARAMS_CMD_PFN_V(pf) |
6307 FW_PARAMS_CMD_VFN_V(vf));
6308 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6311 *p++ = cpu_to_be32(*params++);
6312 *p++ = cpu_to_be32(*val++);
6315 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6319 * t4_set_params - sets FW or device parameters
6320 * @adap: the adapter
6321 * @mbox: mailbox to use for the FW command
6324 * @nparams: the number of parameters
6325 * @params: the parameter names
6326 * @val: the parameter values
6328 * Sets the value of FW or device parameters. Up to 7 parameters can be
6329 * specified at once.
6331 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6332 unsigned int vf, unsigned int nparams, const u32 *params,
6335 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6336 FW_CMD_MAX_TIMEOUT);
6340 * t4_cfg_pfvf - configure PF/VF resource limits
6341 * @adap: the adapter
6342 * @mbox: mailbox to use for the FW command
6343 * @pf: the PF being configured
6344 * @vf: the VF being configured
6345 * @txq: the max number of egress queues
6346 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
6347 * @rxqi: the max number of interrupt-capable ingress queues
6348 * @rxq: the max number of interruptless ingress queues
6349 * @tc: the PCI traffic class
6350 * @vi: the max number of virtual interfaces
6351 * @cmask: the channel access rights mask for the PF/VF
6352 * @pmask: the port access rights mask for the PF/VF
6353 * @nexact: the maximum number of exact MPS filters
6354 * @rcaps: read capabilities
6355 * @wxcaps: write/execute capabilities
6357 * Configures resource limits and capabilities for a physical or virtual
6360 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6361 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6362 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6363 unsigned int vi, unsigned int cmask, unsigned int pmask,
6364 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6366 struct fw_pfvf_cmd c;
6368 memset(&c, 0, sizeof(c));
6369 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
6370 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
6371 FW_PFVF_CMD_VFN_V(vf));
6372 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6373 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
6374 FW_PFVF_CMD_NIQ_V(rxq));
6375 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
6376 FW_PFVF_CMD_PMASK_V(pmask) |
6377 FW_PFVF_CMD_NEQ_V(txq));
6378 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
6379 FW_PFVF_CMD_NVI_V(vi) |
6380 FW_PFVF_CMD_NEXACTF_V(nexact));
6381 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
6382 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
6383 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
6384 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6388 * t4_alloc_vi - allocate a virtual interface
6389 * @adap: the adapter
6390 * @mbox: mailbox to use for the FW command
6391 * @port: physical port associated with the VI
6392 * @pf: the PF owning the VI
6393 * @vf: the VF owning the VI
6394 * @nmac: number of MAC addresses needed (1 to 5)
6395 * @mac: the MAC addresses of the VI
6396 * @rss_size: size of RSS table slice associated with this VI
6398 * Allocates a virtual interface for the given physical port. If @mac is
6399 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
6400 * @mac should be large enough to hold @nmac Ethernet addresses, they are
6401 * stored consecutively so the space needed is @nmac * 6 bytes.
6402 * Returns a negative error number or the non-negative VI id.
6404 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6405 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6406 unsigned int *rss_size)
6411 memset(&c, 0, sizeof(c));
6412 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
6413 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
6414 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
6415 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
6416 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
6419 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6424 memcpy(mac, c.mac, sizeof(c.mac));
6427 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6429 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6431 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6433 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
6437 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
6438 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
6442 * t4_free_vi - free a virtual interface
6443 * @adap: the adapter
6444 * @mbox: mailbox to use for the FW command
6445 * @pf: the PF owning the VI
6446 * @vf: the VF owning the VI
6447 * @viid: virtual interface identifiler
6449 * Free a previously allocated virtual interface.
6451 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6452 unsigned int vf, unsigned int viid)
6456 memset(&c, 0, sizeof(c));
6457 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
6460 FW_VI_CMD_PFN_V(pf) |
6461 FW_VI_CMD_VFN_V(vf));
6462 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
6463 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
6465 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6469 * t4_set_rxmode - set Rx properties of a virtual interface
6470 * @adap: the adapter
6471 * @mbox: mailbox to use for the FW command
6473 * @mtu: the new MTU or -1
6474 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6475 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6476 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6477 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6478 * @sleep_ok: if true we may sleep while awaiting command completion
6480 * Sets Rx properties of a virtual interface.
6482 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6483 int mtu, int promisc, int all_multi, int bcast, int vlanex,
6486 struct fw_vi_rxmode_cmd c;
6488 /* convert to FW values */
6490 mtu = FW_RXMODE_MTU_NO_CHG;
6492 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
6494 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
6496 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
6498 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
6500 memset(&c, 0, sizeof(c));
6501 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
6502 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6503 FW_VI_RXMODE_CMD_VIID_V(viid));
6504 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6506 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
6507 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
6508 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
6509 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
6510 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
6511 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6515 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6516 * @adap: the adapter
6517 * @mbox: mailbox to use for the FW command
6519 * @free: if true any existing filters for this VI id are first removed
6520 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6521 * @addr: the MAC address(es)
6522 * @idx: where to store the index of each allocated filter
6523 * @hash: pointer to hash address filter bitmap
6524 * @sleep_ok: call is allowed to sleep
6526 * Allocates an exact-match filter for each of the supplied addresses and
6527 * sets it to the corresponding address. If @idx is not %NULL it should
6528 * have at least @naddr entries, each of which will be set to the index of
6529 * the filter allocated for the corresponding MAC address. If a filter
6530 * could not be allocated for an address its index is set to 0xffff.
6531 * If @hash is not %NULL addresses that fail to allocate an exact filter
6532 * are hashed and update the hash filter bitmap pointed at by @hash.
6534 * Returns a negative error number or the number of filters allocated.
6536 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
6537 unsigned int viid, bool free, unsigned int naddr,
6538 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
6540 int offset, ret = 0;
6541 struct fw_vi_mac_cmd c;
6542 unsigned int nfilters = 0;
6543 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
6544 unsigned int rem = naddr;
6546 if (naddr > max_naddr)
6549 for (offset = 0; offset < naddr ; /**/) {
6550 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
6551 rem : ARRAY_SIZE(c.u.exact));
6552 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6553 u.exact[fw_naddr]), 16);
6554 struct fw_vi_mac_exact *p;
6557 memset(&c, 0, sizeof(c));
6558 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6561 FW_CMD_EXEC_V(free) |
6562 FW_VI_MAC_CMD_VIID_V(viid));
6563 c.freemacs_to_len16 =
6564 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
6565 FW_CMD_LEN16_V(len16));
6567 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6569 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6570 FW_VI_MAC_CMD_IDX_V(
6571 FW_VI_MAC_ADD_MAC));
6572 memcpy(p->macaddr, addr[offset + i],
6573 sizeof(p->macaddr));
6576 /* It's okay if we run out of space in our MAC address arena.
6577 * Some of the addresses we submit may get stored so we need
6578 * to run through the reply to see what the results were ...
6580 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6581 if (ret && ret != -FW_ENOMEM)
6584 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6585 u16 index = FW_VI_MAC_CMD_IDX_G(
6586 be16_to_cpu(p->valid_to_idx));
6589 idx[offset + i] = (index >= max_naddr ?
6591 if (index < max_naddr)
6595 hash_mac_addr(addr[offset + i]));
6603 if (ret == 0 || ret == -FW_ENOMEM)
6609 * t4_change_mac - modifies the exact-match filter for a MAC address
6610 * @adap: the adapter
6611 * @mbox: mailbox to use for the FW command
6613 * @idx: index of existing filter for old value of MAC address, or -1
6614 * @addr: the new MAC address value
6615 * @persist: whether a new MAC allocation should be persistent
6616 * @add_smt: if true also add the address to the HW SMT
6618 * Modifies an exact-match filter and sets it to the new MAC address.
6619 * Note that in general it is not possible to modify the value of a given
6620 * filter so the generic way to modify an address filter is to free the one
6621 * being used by the old address value and allocate a new filter for the
6622 * new address value. @idx can be -1 if the address is a new addition.
6624 * Returns a negative error number or the index of the filter with the new
6627 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
6628 int idx, const u8 *addr, bool persist, bool add_smt)
6631 struct fw_vi_mac_cmd c;
6632 struct fw_vi_mac_exact *p = c.u.exact;
6633 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
6635 if (idx < 0) /* new allocation */
6636 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
6637 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
6639 memset(&c, 0, sizeof(c));
6640 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6641 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6642 FW_VI_MAC_CMD_VIID_V(viid));
6643 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
6644 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6645 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
6646 FW_VI_MAC_CMD_IDX_V(idx));
6647 memcpy(p->macaddr, addr, sizeof(p->macaddr));
6649 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6651 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
6652 if (ret >= max_mac_addr)
6659 * t4_set_addr_hash - program the MAC inexact-match hash filter
6660 * @adap: the adapter
6661 * @mbox: mailbox to use for the FW command
6663 * @ucast: whether the hash filter should also match unicast addresses
6664 * @vec: the value to be written to the hash filter
6665 * @sleep_ok: call is allowed to sleep
6667 * Sets the 64-bit inexact-match hash filter for a virtual interface.
6669 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
6670 bool ucast, u64 vec, bool sleep_ok)
6672 struct fw_vi_mac_cmd c;
6674 memset(&c, 0, sizeof(c));
6675 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6676 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6677 FW_VI_ENABLE_CMD_VIID_V(viid));
6678 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
6679 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
6681 c.u.hash.hashvec = cpu_to_be64(vec);
6682 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6686 * t4_enable_vi_params - enable/disable a virtual interface
6687 * @adap: the adapter
6688 * @mbox: mailbox to use for the FW command
6690 * @rx_en: 1=enable Rx, 0=disable Rx
6691 * @tx_en: 1=enable Tx, 0=disable Tx
6692 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
6694 * Enables/disables a virtual interface. Note that setting DCB Enable
6695 * only makes sense when enabling a Virtual Interface ...
6697 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
6698 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
6700 struct fw_vi_enable_cmd c;
6702 memset(&c, 0, sizeof(c));
6703 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6704 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6705 FW_VI_ENABLE_CMD_VIID_V(viid));
6706 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
6707 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
6708 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
6710 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
6714 * t4_enable_vi - enable/disable a virtual interface
6715 * @adap: the adapter
6716 * @mbox: mailbox to use for the FW command
6718 * @rx_en: 1=enable Rx, 0=disable Rx
6719 * @tx_en: 1=enable Tx, 0=disable Tx
6721 * Enables/disables a virtual interface.
6723 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
6724 bool rx_en, bool tx_en)
6726 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
6730 * t4_identify_port - identify a VI's port by blinking its LED
6731 * @adap: the adapter
6732 * @mbox: mailbox to use for the FW command
6734 * @nblinks: how many times to blink LED at 2.5 Hz
6736 * Identifies a VI's port by blinking its LED.
6738 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
6739 unsigned int nblinks)
6741 struct fw_vi_enable_cmd c;
6743 memset(&c, 0, sizeof(c));
6744 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6745 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6746 FW_VI_ENABLE_CMD_VIID_V(viid));
6747 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
6748 c.blinkdur = cpu_to_be16(nblinks);
6749 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6753 * t4_iq_free - free an ingress queue and its FLs
6754 * @adap: the adapter
6755 * @mbox: mailbox to use for the FW command
6756 * @pf: the PF owning the queues
6757 * @vf: the VF owning the queues
6758 * @iqtype: the ingress queue type
6759 * @iqid: ingress queue id
6760 * @fl0id: FL0 queue id or 0xffff if no attached FL0
6761 * @fl1id: FL1 queue id or 0xffff if no attached FL1
6763 * Frees an ingress queue and its associated FLs, if any.
6765 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
6766 unsigned int vf, unsigned int iqtype, unsigned int iqid,
6767 unsigned int fl0id, unsigned int fl1id)
6771 memset(&c, 0, sizeof(c));
6772 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
6773 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
6774 FW_IQ_CMD_VFN_V(vf));
6775 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
6776 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
6777 c.iqid = cpu_to_be16(iqid);
6778 c.fl0id = cpu_to_be16(fl0id);
6779 c.fl1id = cpu_to_be16(fl1id);
6780 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6784 * t4_eth_eq_free - free an Ethernet egress queue
6785 * @adap: the adapter
6786 * @mbox: mailbox to use for the FW command
6787 * @pf: the PF owning the queue
6788 * @vf: the VF owning the queue
6789 * @eqid: egress queue id
6791 * Frees an Ethernet egress queue.
6793 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
6794 unsigned int vf, unsigned int eqid)
6796 struct fw_eq_eth_cmd c;
6798 memset(&c, 0, sizeof(c));
6799 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
6800 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6801 FW_EQ_ETH_CMD_PFN_V(pf) |
6802 FW_EQ_ETH_CMD_VFN_V(vf));
6803 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
6804 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
6805 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6809 * t4_ctrl_eq_free - free a control egress queue
6810 * @adap: the adapter
6811 * @mbox: mailbox to use for the FW command
6812 * @pf: the PF owning the queue
6813 * @vf: the VF owning the queue
6814 * @eqid: egress queue id
6816 * Frees a control egress queue.
6818 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
6819 unsigned int vf, unsigned int eqid)
6821 struct fw_eq_ctrl_cmd c;
6823 memset(&c, 0, sizeof(c));
6824 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
6825 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6826 FW_EQ_CTRL_CMD_PFN_V(pf) |
6827 FW_EQ_CTRL_CMD_VFN_V(vf));
6828 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
6829 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
6830 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6834 * t4_ofld_eq_free - free an offload egress queue
6835 * @adap: the adapter
6836 * @mbox: mailbox to use for the FW command
6837 * @pf: the PF owning the queue
6838 * @vf: the VF owning the queue
6839 * @eqid: egress queue id
6841 * Frees a control egress queue.
6843 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
6844 unsigned int vf, unsigned int eqid)
6846 struct fw_eq_ofld_cmd c;
6848 memset(&c, 0, sizeof(c));
6849 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
6850 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6851 FW_EQ_OFLD_CMD_PFN_V(pf) |
6852 FW_EQ_OFLD_CMD_VFN_V(vf));
6853 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
6854 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
6855 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6859 * t4_handle_fw_rpl - process a FW reply message
6860 * @adap: the adapter
6861 * @rpl: start of the FW message
6863 * Processes a FW message, such as link state change messages.
6865 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
6867 u8 opcode = *(const u8 *)rpl;
6869 if (opcode == FW_PORT_CMD) { /* link/module state change message */
6870 int speed = 0, fc = 0;
6871 const struct fw_port_cmd *p = (void *)rpl;
6872 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
6873 int port = adap->chan_map[chan];
6874 struct port_info *pi = adap2pinfo(adap, port);
6875 struct link_config *lc = &pi->link_cfg;
6876 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
6877 int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
6878 u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
6880 if (stat & FW_PORT_CMD_RXPAUSE_F)
6882 if (stat & FW_PORT_CMD_TXPAUSE_F)
6884 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
6886 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
6888 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
6890 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
6893 if (link_ok != lc->link_ok || speed != lc->speed ||
6894 fc != lc->fc) { /* something changed */
6895 lc->link_ok = link_ok;
6898 lc->supported = be16_to_cpu(p->u.info.pcap);
6899 t4_os_link_changed(adap, port, link_ok);
6901 if (mod != pi->mod_type) {
6903 t4_os_portmod_changed(adap, port);
6909 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
6913 if (pci_is_pcie(adapter->pdev)) {
6914 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
6915 p->speed = val & PCI_EXP_LNKSTA_CLS;
6916 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
6921 * init_link_config - initialize a link's SW state
6922 * @lc: structure holding the link state
6923 * @caps: link capabilities
6925 * Initializes the SW state maintained for each link, including the link's
6926 * capabilities and default speed/flow-control/autonegotiation settings.
6928 static void init_link_config(struct link_config *lc, unsigned int caps)
6930 lc->supported = caps;
6931 lc->requested_speed = 0;
6933 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
6934 if (lc->supported & FW_PORT_CAP_ANEG) {
6935 lc->advertising = lc->supported & ADVERT_MASK;
6936 lc->autoneg = AUTONEG_ENABLE;
6937 lc->requested_fc |= PAUSE_AUTONEG;
6939 lc->advertising = 0;
6940 lc->autoneg = AUTONEG_DISABLE;
6944 #define CIM_PF_NOACCESS 0xeeeeeeee
6946 int t4_wait_dev_ready(void __iomem *regs)
6950 whoami = readl(regs + PL_WHOAMI_A);
6951 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
6955 whoami = readl(regs + PL_WHOAMI_A);
6956 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
6960 u32 vendor_and_model_id;
6964 static int get_flash_params(struct adapter *adap)
6966 /* Table for non-Numonix supported flash parts. Numonix parts are left
6967 * to the preexisting code. All flash parts have 64KB sectors.
6969 static struct flash_desc supported_flash[] = {
6970 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
6976 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
6978 ret = sf1_read(adap, 3, 0, 1, &info);
6979 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
6983 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
6984 if (supported_flash[ret].vendor_and_model_id == info) {
6985 adap->params.sf_size = supported_flash[ret].size_mb;
6986 adap->params.sf_nsec =
6987 adap->params.sf_size / SF_SEC_SIZE;
6991 if ((info & 0xff) != 0x20) /* not a Numonix flash */
6993 info >>= 16; /* log2 of size */
6994 if (info >= 0x14 && info < 0x18)
6995 adap->params.sf_nsec = 1 << (info - 16);
6996 else if (info == 0x18)
6997 adap->params.sf_nsec = 64;
7000 adap->params.sf_size = 1 << info;
7001 adap->params.sf_fw_start =
7002 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
7004 if (adap->params.sf_size < FLASH_MIN_SIZE)
7005 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
7006 adap->params.sf_size, FLASH_MIN_SIZE);
7010 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
7015 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
7017 pci_read_config_word(adapter->pdev,
7018 pcie_cap + PCI_EXP_DEVCTL2, &val);
7019 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
7021 pci_write_config_word(adapter->pdev,
7022 pcie_cap + PCI_EXP_DEVCTL2, val);
7027 * t4_prep_adapter - prepare SW and HW for operation
7028 * @adapter: the adapter
7029 * @reset: if true perform a HW reset
7031 * Initialize adapter SW state for the various HW modules, set initial
7032 * values for some adapter tunables, take PHYs out of reset, and
7033 * initialize the MDIO interface.
7035 int t4_prep_adapter(struct adapter *adapter)
7041 get_pci_mode(adapter, &adapter->params.pci);
7042 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
7044 ret = get_flash_params(adapter);
7046 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
7050 /* Retrieve adapter's device ID
7052 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
7053 ver = device_id >> 12;
7054 adapter->params.chip = 0;
7057 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
7058 adapter->params.arch.sge_fl_db = DBPRIO_F;
7059 adapter->params.arch.mps_tcam_size =
7060 NUM_MPS_CLS_SRAM_L_INSTANCES;
7061 adapter->params.arch.mps_rplc_size = 128;
7062 adapter->params.arch.nchan = NCHAN;
7063 adapter->params.arch.vfcount = 128;
7066 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
7067 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
7068 adapter->params.arch.mps_tcam_size =
7069 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7070 adapter->params.arch.mps_rplc_size = 128;
7071 adapter->params.arch.nchan = NCHAN;
7072 adapter->params.arch.vfcount = 128;
7075 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
7076 adapter->params.arch.sge_fl_db = 0;
7077 adapter->params.arch.mps_tcam_size =
7078 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7079 adapter->params.arch.mps_rplc_size = 256;
7080 adapter->params.arch.nchan = 2;
7081 adapter->params.arch.vfcount = 256;
7084 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
7089 adapter->params.cim_la_size = CIMLA_SIZE;
7090 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7093 * Default port for debugging in case we can't reach FW.
7095 adapter->params.nports = 1;
7096 adapter->params.portvec = 1;
7097 adapter->params.vpd.cclk = 50000;
7099 /* Set pci completion timeout value to 4 seconds. */
7100 set_pcie_completion_timeout(adapter, 0xd);
7105 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
7106 * @adapter: the adapter
7107 * @qid: the Queue ID
7108 * @qtype: the Ingress or Egress type for @qid
7109 * @user: true if this request is for a user mode queue
7110 * @pbar2_qoffset: BAR2 Queue Offset
7111 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
7113 * Returns the BAR2 SGE Queue Registers information associated with the
7114 * indicated Absolute Queue ID. These are passed back in return value
7115 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
7116 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
7118 * This may return an error which indicates that BAR2 SGE Queue
7119 * registers aren't available. If an error is not returned, then the
7120 * following values are returned:
7122 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
7123 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
7125 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
7126 * require the "Inferred Queue ID" ability may be used. E.g. the
7127 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
7128 * then these "Inferred Queue ID" register may not be used.
7130 int t4_bar2_sge_qregs(struct adapter *adapter,
7132 enum t4_bar2_qtype qtype,
7135 unsigned int *pbar2_qid)
7137 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
7138 u64 bar2_page_offset, bar2_qoffset;
7139 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
7141 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
7142 if (!user && is_t4(adapter->params.chip))
7145 /* Get our SGE Page Size parameters.
7147 page_shift = adapter->params.sge.hps + 10;
7148 page_size = 1 << page_shift;
7150 /* Get the right Queues per Page parameters for our Queue.
7152 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
7153 ? adapter->params.sge.eq_qpp
7154 : adapter->params.sge.iq_qpp);
7155 qpp_mask = (1 << qpp_shift) - 1;
7157 /* Calculate the basics of the BAR2 SGE Queue register area:
7158 * o The BAR2 page the Queue registers will be in.
7159 * o The BAR2 Queue ID.
7160 * o The BAR2 Queue ID Offset into the BAR2 page.
7162 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
7163 bar2_qid = qid & qpp_mask;
7164 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
7166 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
7167 * hardware will infer the Absolute Queue ID simply from the writes to
7168 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
7169 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
7170 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
7171 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
7172 * from the BAR2 Page and BAR2 Queue ID.
7174 * One important censequence of this is that some BAR2 SGE registers
7175 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
7176 * there. But other registers synthesize the SGE Queue ID purely
7177 * from the writes to the registers -- the Write Combined Doorbell
7178 * Buffer is a good example. These BAR2 SGE Registers are only
7179 * available for those BAR2 SGE Register areas where the SGE Absolute
7180 * Queue ID can be inferred from simple writes.
7182 bar2_qoffset = bar2_page_offset;
7183 bar2_qinferred = (bar2_qid_offset < page_size);
7184 if (bar2_qinferred) {
7185 bar2_qoffset += bar2_qid_offset;
7189 *pbar2_qoffset = bar2_qoffset;
7190 *pbar2_qid = bar2_qid;
7195 * t4_init_devlog_params - initialize adapter->params.devlog
7196 * @adap: the adapter
7198 * Initialize various fields of the adapter's Firmware Device Log
7199 * Parameters structure.
7201 int t4_init_devlog_params(struct adapter *adap)
7203 struct devlog_params *dparams = &adap->params.devlog;
7205 unsigned int devlog_meminfo;
7206 struct fw_devlog_cmd devlog_cmd;
7209 /* If we're dealing with newer firmware, the Device Log Paramerters
7210 * are stored in a designated register which allows us to access the
7211 * Device Log even if we can't talk to the firmware.
7214 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
7216 unsigned int nentries, nentries128;
7218 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
7219 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
7221 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
7222 nentries = (nentries128 + 1) * 128;
7223 dparams->size = nentries * sizeof(struct fw_devlog_e);
7228 /* Otherwise, ask the firmware for it's Device Log Parameters.
7230 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
7231 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
7232 FW_CMD_REQUEST_F | FW_CMD_READ_F);
7233 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7234 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7240 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7241 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
7242 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
7243 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7249 * t4_init_sge_params - initialize adap->params.sge
7250 * @adapter: the adapter
7252 * Initialize various fields of the adapter's SGE Parameters structure.
7254 int t4_init_sge_params(struct adapter *adapter)
7256 struct sge_params *sge_params = &adapter->params.sge;
7258 unsigned int s_hps, s_qpp;
7260 /* Extract the SGE Page Size for our PF.
7262 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
7263 s_hps = (HOSTPAGESIZEPF0_S +
7264 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
7265 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
7267 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
7269 s_qpp = (QUEUESPERPAGEPF0_S +
7270 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
7271 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
7272 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7273 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
7274 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7280 * t4_init_tp_params - initialize adap->params.tp
7281 * @adap: the adapter
7283 * Initialize various fields of the adapter's TP Parameters structure.
7285 int t4_init_tp_params(struct adapter *adap)
7290 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
7291 adap->params.tp.tre = TIMERRESOLUTION_G(v);
7292 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
7294 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7295 for (chan = 0; chan < NCHAN; chan++)
7296 adap->params.tp.tx_modq[chan] = chan;
7298 /* Cache the adapter's Compressed Filter Mode and global Incress
7301 if (t4_use_ldst(adap)) {
7302 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
7303 TP_VLAN_PRI_MAP_A, 1);
7304 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
7305 TP_INGRESS_CONFIG_A, 1);
7307 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7308 &adap->params.tp.vlan_pri_map, 1,
7310 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7311 &adap->params.tp.ingress_config, 1,
7312 TP_INGRESS_CONFIG_A);
7315 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7316 * shift positions of several elements of the Compressed Filter Tuple
7317 * for this adapter which we need frequently ...
7319 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
7320 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
7321 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
7322 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
7325 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7326 * represents the presence of an Outer VLAN instead of a VNIC ID.
7328 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
7329 adap->params.tp.vnic_shift = -1;
7335 * t4_filter_field_shift - calculate filter field shift
7336 * @adap: the adapter
7337 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
7339 * Return the shift position of a filter field within the Compressed
7340 * Filter Tuple. The filter field is specified via its selection bit
7341 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
7343 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
7345 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
7349 if ((filter_mode & filter_sel) == 0)
7352 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
7353 switch (filter_mode & sel) {
7355 field_shift += FT_FCOE_W;
7358 field_shift += FT_PORT_W;
7361 field_shift += FT_VNIC_ID_W;
7364 field_shift += FT_VLAN_W;
7367 field_shift += FT_TOS_W;
7370 field_shift += FT_PROTOCOL_W;
7373 field_shift += FT_ETHERTYPE_W;
7376 field_shift += FT_MACMATCH_W;
7379 field_shift += FT_MPSHITTYPE_W;
7381 case FRAGMENTATION_F:
7382 field_shift += FT_FRAGMENTATION_W;
7389 int t4_init_rss_mode(struct adapter *adap, int mbox)
7392 struct fw_rss_vi_config_cmd rvc;
7394 memset(&rvc, 0, sizeof(rvc));
7396 for_each_port(adap, i) {
7397 struct port_info *p = adap2pinfo(adap, i);
7400 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7401 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7402 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
7403 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7404 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7407 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7412 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
7416 struct fw_port_cmd c;
7417 struct fw_rss_vi_config_cmd rvc;
7419 memset(&c, 0, sizeof(c));
7420 memset(&rvc, 0, sizeof(rvc));
7422 for_each_port(adap, i) {
7423 unsigned int rss_size;
7424 struct port_info *p = adap2pinfo(adap, i);
7426 while ((adap->params.portvec & (1 << j)) == 0)
7429 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
7430 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7431 FW_PORT_CMD_PORTID_V(j));
7432 c.action_to_len16 = cpu_to_be32(
7433 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
7435 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7439 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
7446 p->rss_size = rss_size;
7447 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
7448 adap->port[i]->dev_port = j;
7450 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
7451 p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
7452 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
7453 p->port_type = FW_PORT_CMD_PTYPE_G(ret);
7454 p->mod_type = FW_PORT_MOD_TYPE_NA;
7457 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7458 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7459 FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
7460 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7461 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7464 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7466 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap));
7473 * t4_read_cimq_cfg - read CIM queue configuration
7474 * @adap: the adapter
7475 * @base: holds the queue base addresses in bytes
7476 * @size: holds the queue sizes in bytes
7477 * @thres: holds the queue full thresholds in bytes
7479 * Returns the current configuration of the CIM queues, starting with
7480 * the IBQs, then the OBQs.
7482 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
7485 int cim_num_obq = is_t4(adap->params.chip) ?
7486 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7488 for (i = 0; i < CIM_NUM_IBQ; i++) {
7489 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
7491 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7492 /* value is in 256-byte units */
7493 *base++ = CIMQBASE_G(v) * 256;
7494 *size++ = CIMQSIZE_G(v) * 256;
7495 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
7497 for (i = 0; i < cim_num_obq; i++) {
7498 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7500 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7501 /* value is in 256-byte units */
7502 *base++ = CIMQBASE_G(v) * 256;
7503 *size++ = CIMQSIZE_G(v) * 256;
7508 * t4_read_cim_ibq - read the contents of a CIM inbound queue
7509 * @adap: the adapter
7510 * @qid: the queue index
7511 * @data: where to store the queue contents
7512 * @n: capacity of @data in 32-bit words
7514 * Reads the contents of the selected CIM queue starting at address 0 up
7515 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7516 * error and the number of 32-bit words actually read on success.
7518 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7520 int i, err, attempts;
7522 const unsigned int nwords = CIM_IBQ_SIZE * 4;
7524 if (qid > 5 || (n & 3))
7527 addr = qid * nwords;
7531 /* It might take 3-10ms before the IBQ debug read access is allowed.
7532 * Wait for 1 Sec with a delay of 1 usec.
7536 for (i = 0; i < n; i++, addr++) {
7537 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
7539 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
7543 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
7545 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
7550 * t4_read_cim_obq - read the contents of a CIM outbound queue
7551 * @adap: the adapter
7552 * @qid: the queue index
7553 * @data: where to store the queue contents
7554 * @n: capacity of @data in 32-bit words
7556 * Reads the contents of the selected CIM queue starting at address 0 up
7557 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7558 * error and the number of 32-bit words actually read on success.
7560 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7563 unsigned int addr, v, nwords;
7564 int cim_num_obq = is_t4(adap->params.chip) ?
7565 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7567 if ((qid > (cim_num_obq - 1)) || (n & 3))
7570 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7571 QUENUMSELECT_V(qid));
7572 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7574 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
7575 nwords = CIMQSIZE_G(v) * 64; /* same */
7579 for (i = 0; i < n; i++, addr++) {
7580 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
7582 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
7586 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
7588 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
7593 * t4_cim_read - read a block from CIM internal address space
7594 * @adap: the adapter
7595 * @addr: the start address within the CIM address space
7596 * @n: number of words to read
7597 * @valp: where to store the result
7599 * Reads a block of 4-byte words from the CIM intenal address space.
7601 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
7606 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
7609 for ( ; !ret && n--; addr += 4) {
7610 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
7611 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
7614 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
7620 * t4_cim_write - write a block into CIM internal address space
7621 * @adap: the adapter
7622 * @addr: the start address within the CIM address space
7623 * @n: number of words to write
7624 * @valp: set of values to write
7626 * Writes a block of 4-byte words into the CIM intenal address space.
7628 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
7629 const unsigned int *valp)
7633 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
7636 for ( ; !ret && n--; addr += 4) {
7637 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
7638 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
7639 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
7645 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
7648 return t4_cim_write(adap, addr, 1, &val);
7652 * t4_cim_read_la - read CIM LA capture buffer
7653 * @adap: the adapter
7654 * @la_buf: where to store the LA data
7655 * @wrptr: the HW write pointer within the capture buffer
7657 * Reads the contents of the CIM LA buffer with the most recent entry at
7658 * the end of the returned data and with the entry at @wrptr first.
7659 * We try to leave the LA in the running state we find it in.
7661 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
7664 unsigned int cfg, val, idx;
7666 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
7670 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
7671 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
7676 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
7680 idx = UPDBGLAWRPTR_G(val);
7684 for (i = 0; i < adap->params.cim_la_size; i++) {
7685 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
7686 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
7689 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
7692 if (val & UPDBGLARDEN_F) {
7696 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
7699 idx = (idx + 1) & UPDBGLARDPTR_M;
7702 if (cfg & UPDBGLAEN_F) {
7703 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
7704 cfg & ~UPDBGLARDEN_F);
7712 * t4_tp_read_la - read TP LA capture buffer
7713 * @adap: the adapter
7714 * @la_buf: where to store the LA data
7715 * @wrptr: the HW write pointer within the capture buffer
7717 * Reads the contents of the TP LA buffer with the most recent entry at
7718 * the end of the returned data and with the entry at @wrptr first.
7719 * We leave the LA in the running state we find it in.
7721 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
7723 bool last_incomplete;
7724 unsigned int i, cfg, val, idx;
7726 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
7727 if (cfg & DBGLAENABLE_F) /* freeze LA */
7728 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
7729 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
7731 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
7732 idx = DBGLAWPTR_G(val);
7733 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
7734 if (last_incomplete)
7735 idx = (idx + 1) & DBGLARPTR_M;
7740 val &= ~DBGLARPTR_V(DBGLARPTR_M);
7741 val |= adap->params.tp.la_mask;
7743 for (i = 0; i < TPLA_SIZE; i++) {
7744 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
7745 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
7746 idx = (idx + 1) & DBGLARPTR_M;
7749 /* Wipe out last entry if it isn't valid */
7750 if (last_incomplete)
7751 la_buf[TPLA_SIZE - 1] = ~0ULL;
7753 if (cfg & DBGLAENABLE_F) /* restore running state */
7754 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
7755 cfg | adap->params.tp.la_mask);
7758 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
7759 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
7760 * state for more than the Warning Threshold then we'll issue a warning about
7761 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
7762 * appears to be hung every Warning Repeat second till the situation clears.
7763 * If the situation clears, we'll note that as well.
7765 #define SGE_IDMA_WARN_THRESH 1
7766 #define SGE_IDMA_WARN_REPEAT 300
7769 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
7770 * @adapter: the adapter
7771 * @idma: the adapter IDMA Monitor state
7773 * Initialize the state of an SGE Ingress DMA Monitor.
7775 void t4_idma_monitor_init(struct adapter *adapter,
7776 struct sge_idma_monitor_state *idma)
7778 /* Initialize the state variables for detecting an SGE Ingress DMA
7779 * hang. The SGE has internal counters which count up on each clock
7780 * tick whenever the SGE finds its Ingress DMA State Engines in the
7781 * same state they were on the previous clock tick. The clock used is
7782 * the Core Clock so we have a limit on the maximum "time" they can
7783 * record; typically a very small number of seconds. For instance,
7784 * with a 600MHz Core Clock, we can only count up to a bit more than
7785 * 7s. So we'll synthesize a larger counter in order to not run the
7786 * risk of having the "timers" overflow and give us the flexibility to
7787 * maintain a Hung SGE State Machine of our own which operates across
7788 * a longer time frame.
7790 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
7791 idma->idma_stalled[0] = 0;
7792 idma->idma_stalled[1] = 0;
7796 * t4_idma_monitor - monitor SGE Ingress DMA state
7797 * @adapter: the adapter
7798 * @idma: the adapter IDMA Monitor state
7799 * @hz: number of ticks/second
7800 * @ticks: number of ticks since the last IDMA Monitor call
7802 void t4_idma_monitor(struct adapter *adapter,
7803 struct sge_idma_monitor_state *idma,
7806 int i, idma_same_state_cnt[2];
7808 /* Read the SGE Debug Ingress DMA Same State Count registers. These
7809 * are counters inside the SGE which count up on each clock when the
7810 * SGE finds its Ingress DMA State Engines in the same states they
7811 * were in the previous clock. The counters will peg out at
7812 * 0xffffffff without wrapping around so once they pass the 1s
7813 * threshold they'll stay above that till the IDMA state changes.
7815 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
7816 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
7817 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
7819 for (i = 0; i < 2; i++) {
7820 u32 debug0, debug11;
7822 /* If the Ingress DMA Same State Counter ("timer") is less
7823 * than 1s, then we can reset our synthesized Stall Timer and
7824 * continue. If we have previously emitted warnings about a
7825 * potential stalled Ingress Queue, issue a note indicating
7826 * that the Ingress Queue has resumed forward progress.
7828 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
7829 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
7830 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
7831 "resumed after %d seconds\n",
7832 i, idma->idma_qid[i],
7833 idma->idma_stalled[i] / hz);
7834 idma->idma_stalled[i] = 0;
7838 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
7839 * domain. The first time we get here it'll be because we
7840 * passed the 1s Threshold; each additional time it'll be
7841 * because the RX Timer Callback is being fired on its regular
7844 * If the stall is below our Potential Hung Ingress Queue
7845 * Warning Threshold, continue.
7847 if (idma->idma_stalled[i] == 0) {
7848 idma->idma_stalled[i] = hz;
7849 idma->idma_warn[i] = 0;
7851 idma->idma_stalled[i] += ticks;
7852 idma->idma_warn[i] -= ticks;
7855 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
7858 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
7860 if (idma->idma_warn[i] > 0)
7862 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
7864 /* Read and save the SGE IDMA State and Queue ID information.
7865 * We do this every time in case it changes across time ...
7866 * can't be too careful ...
7868 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
7869 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
7870 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
7872 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
7873 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
7874 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
7876 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
7877 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
7878 i, idma->idma_qid[i], idma->idma_state[i],
7879 idma->idma_stalled[i] / hz,
7881 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);