1 Hisilicon Platforms Device Tree Bindings
2 ----------------------------------------------------
4 Required root node properties:
5 - compatible = "hisilicon,hi6220";
8 Required root node properties:
9 - compatible = "hisilicon,hi3620-hi4511";
12 Required root node properties:
13 - compatible = "hisilicon,hip04-d01";
16 Required root node properties:
17 - compatible = "hisilicon,hip01-ca9x2";
20 Required root node properties:
21 - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
23 Hisilicon system controller
26 - compatible : "hisilicon,sysctrl"
27 - reg : Register address and size
30 - smp-offset : offset in sysctrl for notifying slave cpu booting
34 If reg value is not zero, cpun exit wfi and go
35 - resume-offset : offset in sysctrl for notifying cpu0 when resume
36 - reboot-offset : offset in sysctrl for system reboot
41 sysctrl: system-controller@fc802000 {
42 compatible = "hisilicon,sysctrl";
43 reg = <0xfc802000 0x1000>;
45 resume-offset = <0x308>;
46 reboot-offset = <0x4>;
49 -----------------------------------------------------------------------
50 Hisilicon Hi6220 system controller
53 - compatible : "hisilicon,hi6220-sysctrl"
54 - reg : Register address and size
55 - #clock-cells: should be set to 1, many clock registers are defined
56 under this controller and this property must be present.
58 Hisilicon designs this controller as one of the system controllers,
59 its main functions are the same as Hisilicon system controller, but
60 the register offset of some core modules are different.
64 sys_ctrl: sys_ctrl@f7030000 {
65 compatible = "hisilicon,hi6220-sysctrl", "syscon";
66 reg = <0x0 0xf7030000 0x0 0x2000>;
71 Hisilicon Hi6220 Power Always ON domain controller
74 - compatible : "hisilicon,hi6220-aoctrl"
75 - reg : Register address and size
76 - #clock-cells: should be set to 1, many clock registers are defined
77 under this controller and this property must be present.
79 Hisilicon designs this system controller to control the power always
80 on domain for mobile platform.
84 ao_ctrl: ao_ctrl@f7800000 {
85 compatible = "hisilicon,hi6220-aoctrl", "syscon";
86 reg = <0x0 0xf7800000 0x0 0x2000>;
91 Hisilicon Hi6220 Media domain controller
94 - compatible : "hisilicon,hi6220-mediactrl"
95 - reg : Register address and size
96 - #clock-cells: should be set to 1, many clock registers are defined
97 under this controller and this property must be present.
99 Hisilicon designs this system controller to control the multimedia
100 domain(e.g. codec, G3D ...) for mobile platform.
104 media_ctrl: media_ctrl@f4410000 {
105 compatible = "hisilicon,hi6220-mediactrl", "syscon";
106 reg = <0x0 0xf4410000 0x0 0x1000>;
111 Hisilicon Hi6220 Power Management domain controller
114 - compatible : "hisilicon,hi6220-pmctrl"
115 - reg : Register address and size
116 - #clock-cells: should be set to 1, some clock registers are define
117 under this controller and this property must be present.
119 Hisilicon designs this system controller to control the power management
120 domain for mobile platform.
124 pm_ctrl: pm_ctrl@f7032000 {
125 compatible = "hisilicon,hi6220-pmctrl", "syscon";
126 reg = <0x0 0xf7032000 0x0 0x1000>;
131 Hisilicon Hi6220 SRAM controller
134 - compatible : "hisilicon,hi6220-sramctrl", "syscon"
135 - reg : Register address and size
137 Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
138 SRAM banks for power management, modem, security, etc. Further, use "syscon"
139 managing the common sram which can be shared by multiple modules.
143 sram: sram@fff80000 {
144 compatible = "hisilicon,hi6220-sramctrl", "syscon";
145 reg = <0x0 0xfff80000 0x0 0x12000>;
148 -----------------------------------------------------------------------
149 Hisilicon HiP01 system controller
152 - compatible : "hisilicon,hip01-sysctrl"
153 - reg : Register address and size
155 The HiP01 system controller is mostly compatible with hisilicon
156 system controller,but it has some specific control registers for
157 HIP01 SoC family, such as slave core boot, and also some same
158 registers located at different offset.
162 /* for hip01-ca9x2 */
163 sysctrl: system-controller@10000000 {
164 compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
165 reg = <0x10000000 0x1000>;
166 reboot-offset = <0x4>;
169 -----------------------------------------------------------------------
170 Hisilicon CPU controller
173 - compatible : "hisilicon,cpuctrl"
174 - reg : Register address and size
176 The clock registers and power registers of secondary cores are defined
177 in CPU controller, especially in HIX5HD2 SoC.
179 -----------------------------------------------------------------------
180 PCTRL: Peripheral misc control register
183 - compatible: "hisilicon,pctrl"
184 - reg: Address and size of pctrl.
189 pctrl: pctrl@fca09000 {
190 compatible = "hisilicon,pctrl";
191 reg = <0xfca09000 0x1000>;
194 -----------------------------------------------------------------------
198 - compatible: "hisilicon,hip04-fabric";
199 - reg: Address and size of Fabric
201 -----------------------------------------------------------------------
202 Bootwrapper boot method (software protocol on SMP):
205 - compatible: "hisilicon,hip04-bootwrapper";
206 - boot-method: Address and size of boot method.
207 [0]: bootwrapper physical address
208 [1]: bootwrapper size
209 [2]: relocation physical address