2 * TLB Management (flush/create/diagnostics) for ARC700
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
14 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
15 * some of the LMBench tests improved amazingly
16 * = page-fault thrice as fast (75 usec to 28 usec)
17 * = mmap twice as fast (9.6 msec to 4.6 msec),
18 * = fork (5.3 msec to 3.7 msec)
20 * vineetg: April 2011 :
21 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
22 * helps avoid a shift when preparing PD0 from PTE
24 * vineetg: April 2011 : Preparing for MMU V3
25 * -MMU v2/v3 BCRs decoded differently
26 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
27 * -tlb_entry_erase( ) can be void
28 * -local_flush_tlb_range( ):
29 * = need not "ceil" @end
30 * = walks MMU only if range spans < 32 entries, as opposed to 256
32 * Vineetg: Sept 10th 2008
33 * -Changes related to MMU v2 (Rel 4.8)
35 * Vineetg: Aug 29th 2008
36 * -In TLB Flush operations (Metal Fix MMU) there is a explict command to
37 * flush Micro-TLBS. If TLB Index Reg is invalid prior to TLBIVUTLB cmd,
38 * it fails. Thus need to load it with ANY valid value before invoking
41 * Vineetg: Aug 21th 2008:
42 * -Reduced the duration of IRQ lockouts in TLB Flush routines
43 * -Multiple copies of TLB erase code seperated into a "single" function
44 * -In TLB Flush routines, interrupt disabling moved UP to retrieve ASID
45 * in interrupt-safe region.
47 * Vineetg: April 23rd Bug #93131
48 * Problem: tlb_flush_kernel_range() doesnt do anything if the range to
49 * flush is more than the size of TLB itself.
51 * Rahul Trivedi : Codito Technologies 2004
54 #include <linux/module.h>
55 #include <linux/bug.h>
56 #include <asm/arcregs.h>
57 #include <asm/setup.h>
58 #include <asm/mmu_context.h>
61 /* Need for ARC MMU v2
63 * ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc.
64 * For a memcpy operation with 3 players (src/dst/code) such that all 3 pages
65 * map into same set, there would be contention for the 2 ways causing severe
68 * Although J-TLB is 2 way set assoc, ARC700 caches J-TLB into uTLBS which has
69 * much higher associativity. u-D-TLB is 8 ways, u-I-TLB is 4 ways.
70 * Given this, the thrasing problem should never happen because once the 3
71 * J-TLB entries are created (even though 3rd will knock out one of the prev
72 * two), the u-D-TLB and u-I-TLB will have what is required to accomplish memcpy
74 * Yet we still see the Thrashing because a J-TLB Write cause flush of u-TLBs.
75 * This is a simple design for keeping them in sync. So what do we do?
76 * The solution which James came up was pretty neat. It utilised the assoc
77 * of uTLBs by not invalidating always but only when absolutely necessary.
79 * - Existing TLB commands work as before
80 * - New command (TLBWriteNI) for TLB write without clearing uTLBs
81 * - New command (TLBIVUTLB) to invalidate uTLBs.
83 * The uTLBs need only be invalidated when pages are being removed from the
84 * OS page table. If a 'victim' TLB entry is being overwritten in the main TLB
85 * as a result of a miss, the removed entry is still allowed to exist in the
86 * uTLBs as it is still valid and present in the OS page table. This allows the
87 * full associativity of the uTLBs to hide the limited associativity of the main
90 * During a miss handler, the new "TLBWriteNI" command is used to load
91 * entries without clearing the uTLBs.
93 * When the OS page table is updated, TLB entries that may be associated with a
94 * removed page are removed (flushed) from the TLB using TLBWrite. In this
95 * circumstance, the uTLBs must also be cleared. This is done by using the
96 * existing TLBWrite command. An explicit IVUTLB is also required for those
97 * corner cases when TLBWrite was not executed at all because the corresp
98 * J-TLB entry got evicted/replaced.
102 /* A copy of the ASID from the PID reg is kept in asid_cache */
103 DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;
106 * Utility Routine to erase a J-TLB entry
107 * Caller needs to setup Index Reg (manually or via getIndex)
109 static inline void __tlb_entry_erase(void)
111 write_aux_reg(ARC_REG_TLBPD1, 0);
112 write_aux_reg(ARC_REG_TLBPD0, 0);
113 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
116 #if (CONFIG_ARC_MMU_VER < 4)
118 static inline unsigned int tlb_entry_lkup(unsigned long vaddr_n_asid)
122 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid);
124 write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe);
125 idx = read_aux_reg(ARC_REG_TLBINDEX);
130 static void tlb_entry_erase(unsigned int vaddr_n_asid)
134 /* Locate the TLB entry for this vaddr + ASID */
135 idx = tlb_entry_lkup(vaddr_n_asid);
137 /* No error means entry found, zero it out */
138 if (likely(!(idx & TLB_LKUP_ERR))) {
141 /* Duplicate entry error */
142 WARN(idx == TLB_DUP_ERR, "Probe returned Dup PD for %x\n",
147 /****************************************************************************
148 * ARC700 MMU caches recently used J-TLB entries (RAM) as uTLBs (FLOPs)
150 * New IVUTLB cmd in MMU v2 explictly invalidates the uTLB
152 * utlb_invalidate ( )
153 * -For v2 MMU calls Flush uTLB Cmd
154 * -For v1 MMU does nothing (except for Metal Fix v1 MMU)
155 * This is because in v1 TLBWrite itself invalidate uTLBs
156 ***************************************************************************/
158 static void utlb_invalidate(void)
160 #if (CONFIG_ARC_MMU_VER >= 2)
162 #if (CONFIG_ARC_MMU_VER == 2)
163 /* MMU v2 introduced the uTLB Flush command.
164 * There was however an obscure hardware bug, where uTLB flush would
165 * fail when a prior probe for J-TLB (both totally unrelated) would
166 * return lkup err - because the entry didnt exist in MMU.
167 * The Workround was to set Index reg with some valid value, prior to
168 * flush. This was fixed in MMU v3 hence not needed any more
172 /* make sure INDEX Reg is valid */
173 idx = read_aux_reg(ARC_REG_TLBINDEX);
175 /* If not write some dummy val */
176 if (unlikely(idx & TLB_LKUP_ERR))
177 write_aux_reg(ARC_REG_TLBINDEX, 0xa);
180 write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB);
185 static void tlb_entry_insert(unsigned int pd0, unsigned int pd1)
190 * First verify if entry for this vaddr+ASID already exists
191 * This also sets up PD0 (vaddr, ASID..) for final commit
193 idx = tlb_entry_lkup(pd0);
196 * If Not already present get a free slot from MMU.
197 * Otherwise, Probe would have located the entry and set INDEX Reg
198 * with existing location. This will cause Write CMD to over-write
199 * existing entry with new PD0 and PD1
201 if (likely(idx & TLB_LKUP_ERR))
202 write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex);
204 /* setup the other half of TLB entry (pfn, rwx..) */
205 write_aux_reg(ARC_REG_TLBPD1, pd1);
208 * Commit the Entry to MMU
209 * It doesnt sound safe to use the TLBWriteNI cmd here
210 * which doesn't flush uTLBs. I'd rather be safe than sorry.
212 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
215 #else /* CONFIG_ARC_MMU_VER >= 4) */
217 static void utlb_invalidate(void)
219 /* No need since uTLB is always in sync with JTLB */
222 static void tlb_entry_erase(unsigned int vaddr_n_asid)
224 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid | _PAGE_PRESENT);
225 write_aux_reg(ARC_REG_TLBCOMMAND, TLBDeleteEntry);
228 static void tlb_entry_insert(unsigned int pd0, unsigned int pd1)
230 write_aux_reg(ARC_REG_TLBPD0, pd0);
231 write_aux_reg(ARC_REG_TLBPD1, pd1);
232 write_aux_reg(ARC_REG_TLBCOMMAND, TLBInsertEntry);
238 * Un-conditionally (without lookup) erase the entire MMU contents
241 noinline void local_flush_tlb_all(void)
243 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
246 int num_tlb = mmu->sets * mmu->ways;
248 local_irq_save(flags);
250 /* Load PD0 and PD1 with template for a Blank Entry */
251 write_aux_reg(ARC_REG_TLBPD1, 0);
252 write_aux_reg(ARC_REG_TLBPD0, 0);
254 for (entry = 0; entry < num_tlb; entry++) {
255 /* write this entry to the TLB */
256 write_aux_reg(ARC_REG_TLBINDEX, entry);
257 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
260 if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE)) {
261 const int stlb_idx = 0x800;
263 /* Blank sTLB entry */
264 write_aux_reg(ARC_REG_TLBPD0, _PAGE_HW_SZ);
266 for (entry = stlb_idx; entry < stlb_idx + 16; entry++) {
267 write_aux_reg(ARC_REG_TLBINDEX, entry);
268 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
274 local_irq_restore(flags);
278 * Flush the entrie MM for userland. The fastest way is to move to Next ASID
280 noinline void local_flush_tlb_mm(struct mm_struct *mm)
283 * Small optimisation courtesy IA64
284 * flush_mm called during fork,exit,munmap etc, multiple times as well.
285 * Only for fork( ) do we need to move parent to a new MMU ctxt,
286 * all other cases are NOPs, hence this check.
288 if (atomic_read(&mm->mm_users) == 0)
292 * - Move to a new ASID, but only if the mm is still wired in
293 * (Android Binder ended up calling this for vma->mm != tsk->mm,
294 * causing h/w - s/w ASID to get out of sync)
295 * - Also get_new_mmu_context() new implementation allocates a new
296 * ASID only if it is not allocated already - so unallocate first
299 if (current->mm == mm)
300 get_new_mmu_context(mm);
304 * Flush a Range of TLB entries for userland.
305 * @start is inclusive, while @end is exclusive
306 * Difference between this and Kernel Range Flush is
307 * -Here the fastest way (if range is too large) is to move to next ASID
308 * without doing any explicit Shootdown
309 * -In case of kernel Flush, entry has to be shot down explictly
311 void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
314 const unsigned int cpu = smp_processor_id();
317 /* If range @start to @end is more than 32 TLB entries deep,
318 * its better to move to a new ASID rather than searching for
319 * individual entries and then shooting them down
321 * The calc above is rough, doesn't account for unaligned parts,
322 * since this is heuristics based anyways
324 if (unlikely((end - start) >= PAGE_SIZE * 32)) {
325 local_flush_tlb_mm(vma->vm_mm);
330 * @start moved to page start: this alone suffices for checking
331 * loop end condition below, w/o need for aligning @end to end
332 * e.g. 2000 to 4001 will anyhow loop twice
336 local_irq_save(flags);
338 if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
339 while (start < end) {
340 tlb_entry_erase(start | hw_pid(vma->vm_mm, cpu));
347 local_irq_restore(flags);
350 /* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
351 * @start, @end interpreted as kvaddr
352 * Interestingly, shared TLB entries can also be flushed using just
353 * @start,@end alone (interpreted as user vaddr), although technically SASID
354 * is also needed. However our smart TLbProbe lookup takes care of that.
356 void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
360 /* exactly same as above, except for TLB entry not taking ASID */
362 if (unlikely((end - start) >= PAGE_SIZE * 32)) {
363 local_flush_tlb_all();
369 local_irq_save(flags);
370 while (start < end) {
371 tlb_entry_erase(start);
377 local_irq_restore(flags);
381 * Delete TLB entry in MMU for a given page (??? address)
382 * NOTE One TLB entry contains translation for single PAGE
385 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
387 const unsigned int cpu = smp_processor_id();
390 /* Note that it is critical that interrupts are DISABLED between
391 * checking the ASID and using it flush the TLB entry
393 local_irq_save(flags);
395 if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
396 tlb_entry_erase((page & PAGE_MASK) | hw_pid(vma->vm_mm, cpu));
400 local_irq_restore(flags);
406 struct vm_area_struct *ta_vma;
407 unsigned long ta_start;
408 unsigned long ta_end;
411 static inline void ipi_flush_tlb_page(void *arg)
413 struct tlb_args *ta = arg;
415 local_flush_tlb_page(ta->ta_vma, ta->ta_start);
418 static inline void ipi_flush_tlb_range(void *arg)
420 struct tlb_args *ta = arg;
422 local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
425 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
426 static inline void ipi_flush_pmd_tlb_range(void *arg)
428 struct tlb_args *ta = arg;
430 local_flush_pmd_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
434 static inline void ipi_flush_tlb_kernel_range(void *arg)
436 struct tlb_args *ta = (struct tlb_args *)arg;
438 local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end);
441 void flush_tlb_all(void)
443 on_each_cpu((smp_call_func_t)local_flush_tlb_all, NULL, 1);
446 void flush_tlb_mm(struct mm_struct *mm)
448 on_each_cpu_mask(mm_cpumask(mm), (smp_call_func_t)local_flush_tlb_mm,
452 void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
454 struct tlb_args ta = {
459 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_page, &ta, 1);
462 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
465 struct tlb_args ta = {
471 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_range, &ta, 1);
474 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
475 void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
478 struct tlb_args ta = {
484 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_pmd_tlb_range, &ta, 1);
488 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
490 struct tlb_args ta = {
495 on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
500 * Routine to create a TLB entry
502 void create_tlb(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
505 unsigned int asid_or_sasid, rwx;
506 unsigned long pd0, pd1;
509 * create_tlb() assumes that current->mm == vma->mm, since
510 * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr)
511 * -completes the lazy write to SASID reg (again valid for curr tsk)
513 * Removing the assumption involves
514 * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.
515 * -Fix the TLB paranoid debug code to not trigger false negatives.
516 * -More importantly it makes this handler inconsistent with fast-path
517 * TLB Refill handler which always deals with "current"
519 * Lets see the use cases when current->mm != vma->mm and we land here
520 * 1. execve->copy_strings()->__get_user_pages->handle_mm_fault
521 * Here VM wants to pre-install a TLB entry for user stack while
522 * current->mm still points to pre-execve mm (hence the condition).
523 * However the stack vaddr is soon relocated (randomization) and
524 * move_page_tables() tries to undo that TLB entry.
525 * Thus not creating TLB entry is not any worse.
527 * 2. ptrace(POKETEXT) causes a CoW - debugger(current) inserting a
528 * breakpoint in debugged task. Not creating a TLB now is not
529 * performance critical.
531 * Both the cases above are not good enough for code churn.
533 if (current->active_mm != vma->vm_mm)
536 local_irq_save(flags);
538 tlb_paranoid_check(asid_mm(vma->vm_mm, smp_processor_id()), address);
540 address &= PAGE_MASK;
542 /* update this PTE credentials */
543 pte_val(*ptep) |= (_PAGE_PRESENT | _PAGE_ACCESSED);
545 /* Create HW TLB(PD0,PD1) from PTE */
547 /* ASID for this task */
548 asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff;
550 pd0 = address | asid_or_sasid | (pte_val(*ptep) & PTE_BITS_IN_PD0);
553 * ARC MMU provides fully orthogonal access bits for K/U mode,
554 * however Linux only saves 1 set to save PTE real-estate
555 * Here we convert 3 PTE bits into 6 MMU bits:
556 * -Kernel only entries have Kr Kw Kx 0 0 0
557 * -User entries have mirrored K and U bits
559 rwx = pte_val(*ptep) & PTE_BITS_RWX;
561 if (pte_val(*ptep) & _PAGE_GLOBAL)
562 rwx <<= 3; /* r w x => Kr Kw Kx 0 0 0 */
564 rwx |= (rwx << 3); /* r w x => Kr Kw Kx Ur Uw Ux */
566 pd1 = rwx | (pte_val(*ptep) & PTE_BITS_NON_RWX_IN_PD1);
568 tlb_entry_insert(pd0, pd1);
570 local_irq_restore(flags);
574 * Called at the end of pagefault, for a userspace mapped page
575 * -pre-install the corresponding TLB entry into MMU
576 * -Finalize the delayed D-cache flush of kernel mapping of page due to
577 * flush_dcache_page(), copy_user_page()
579 * Note that flush (when done) involves both WBACK - so physical page is
580 * in sync as well as INV - so any non-congruent aliases don't remain
582 void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
585 unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
586 unsigned long paddr = pte_val(*ptep) & PAGE_MASK;
587 struct page *page = pfn_to_page(pte_pfn(*ptep));
589 create_tlb(vma, vaddr, ptep);
591 if (page == ZERO_PAGE(0)) {
596 * Exec page : Independent of aliasing/page-color considerations,
597 * since icache doesn't snoop dcache on ARC, any dirty
598 * K-mapping of a code page needs to be wback+inv so that
599 * icache fetch by userspace sees code correctly.
600 * !EXEC page: If K-mapping is NOT congruent to U-mapping, flush it
601 * so userspace sees the right data.
602 * (Avoids the flush for Non-exec + congruent mapping case)
604 if ((vma->vm_flags & VM_EXEC) ||
605 addr_not_cache_congruent(paddr, vaddr)) {
607 int dirty = !test_and_set_bit(PG_dc_clean, &page->flags);
609 /* wback + inv dcache lines */
610 __flush_dcache_page(paddr, paddr);
612 /* invalidate any existing icache lines */
613 if (vma->vm_flags & VM_EXEC)
614 __inv_icache_page(paddr, vaddr);
619 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
622 * MMUv4 in HS38x cores supports Super Pages which are basis for Linux THP
625 * Normal and Super pages can co-exist (ofcourse not overlap) in TLB with a
626 * new bit "SZ" in TLB page desciptor to distinguish between them.
627 * Super Page size is configurable in hardware (4K to 16M), but fixed once
630 * The exact THP size a Linx configuration will support is a function of:
631 * - MMU page size (typical 8K, RTL fixed)
632 * - software page walker address split between PGD:PTE:PFN (typical
633 * 11:8:13, but can be changed with 1 line)
634 * So for above default, THP size supported is 8K * (2^8) = 2M
636 * Default Page Walker is 2 levels, PGD:PTE:PFN, which in THP regime
637 * reduces to 1 level (as PTE is folded into PGD and canonically referred
639 * Thus THP PMD accessors are implemented in terms of PTE (just like sparc)
642 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
645 pte_t pte = __pte(pmd_val(*pmd));
646 update_mmu_cache(vma, addr, &pte);
649 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
652 struct list_head *lh = (struct list_head *) pgtable;
654 assert_spin_locked(&mm->page_table_lock);
657 if (!pmd_huge_pte(mm, pmdp))
660 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
661 pmd_huge_pte(mm, pmdp) = pgtable;
664 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
666 struct list_head *lh;
669 assert_spin_locked(&mm->page_table_lock);
671 pgtable = pmd_huge_pte(mm, pmdp);
672 lh = (struct list_head *) pgtable;
674 pmd_huge_pte(mm, pmdp) = NULL;
676 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
680 pte_val(pgtable[0]) = 0;
681 pte_val(pgtable[1]) = 0;
686 void local_flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
692 local_irq_save(flags);
694 cpu = smp_processor_id();
696 if (likely(asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID)) {
697 unsigned int asid = hw_pid(vma->vm_mm, cpu);
699 /* No need to loop here: this will always be for 1 Huge Page */
700 tlb_entry_erase(start | _PAGE_HW_SZ | asid);
703 local_irq_restore(flags);
708 /* Read the Cache Build Confuration Registers, Decode them and save into
709 * the cpuinfo structure for later use.
710 * No Validation is done here, simply read/convert the BCRs
712 void read_decode_mmu_bcr(void)
714 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
717 #ifdef CONFIG_CPU_BIG_ENDIAN
718 unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
720 unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
725 #ifdef CONFIG_CPU_BIG_ENDIAN
726 unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,
729 unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,
735 #ifdef CONFIG_CPU_BIG_ENDIAN
736 unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
737 n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
739 /* DTLB ITLB JES JE JA */
740 unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
741 pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
745 tmp = read_aux_reg(ARC_REG_MMU_BCR);
746 mmu->ver = (tmp >> 24);
749 mmu2 = (struct bcr_mmu_1_2 *)&tmp;
750 mmu->pg_sz_k = TO_KB(PAGE_SIZE);
751 mmu->sets = 1 << mmu2->sets;
752 mmu->ways = 1 << mmu2->ways;
753 mmu->u_dtlb = mmu2->u_dtlb;
754 mmu->u_itlb = mmu2->u_itlb;
755 } else if (mmu->ver == 3) {
756 mmu3 = (struct bcr_mmu_3 *)&tmp;
757 mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1);
758 mmu->sets = 1 << mmu3->sets;
759 mmu->ways = 1 << mmu3->ways;
760 mmu->u_dtlb = mmu3->u_dtlb;
761 mmu->u_itlb = mmu3->u_itlb;
763 mmu4 = (struct bcr_mmu_4 *)&tmp;
764 mmu->pg_sz_k = 1 << (mmu4->sz0 - 1);
765 mmu->s_pg_sz_m = 1 << (mmu4->sz1 - 11);
766 mmu->sets = 64 << mmu4->n_entry;
767 mmu->ways = mmu4->n_ways * 2;
768 mmu->u_dtlb = mmu4->u_dtlb * 4;
769 mmu->u_itlb = mmu4->u_itlb * 4;
773 char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
776 struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu;
777 char super_pg[64] = "";
779 if (p_mmu->s_pg_sz_m)
780 scnprintf(super_pg, 64, "%dM Super Page%s, ",
782 IS_USED_CFG(CONFIG_TRANSPARENT_HUGEPAGE));
784 n += scnprintf(buf + n, len - n,
785 "MMU [v%x]\t: %dk PAGE, %sJTLB %d (%dx%d), uDTLB %d, uITLB %d %s\n",
786 p_mmu->ver, p_mmu->pg_sz_k, super_pg,
787 p_mmu->sets * p_mmu->ways, p_mmu->sets, p_mmu->ways,
788 p_mmu->u_dtlb, p_mmu->u_itlb,
789 IS_ENABLED(CONFIG_ARC_MMU_SASID) ? ",SASID" : "");
794 void arc_mmu_init(void)
797 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
799 printk(arc_mmu_mumbojumbo(0, str, sizeof(str)));
801 /* For efficiency sake, kernel is compile time built for a MMU ver
802 * This must match the hardware it is running on.
803 * Linux built for MMU V2, if run on MMU V1 will break down because V1
804 * hardware doesn't understand cmds such as WriteNI, or IVUTLB
805 * On the other hand, Linux built for V1 if run on MMU V2 will do
806 * un-needed workarounds to prevent memcpy thrashing.
807 * Similarly MMU V3 has new features which won't work on older MMU
809 if (mmu->ver != CONFIG_ARC_MMU_VER) {
810 panic("MMU ver %d doesn't match kernel built for %d...\n",
811 mmu->ver, CONFIG_ARC_MMU_VER);
814 if (mmu->pg_sz_k != TO_KB(PAGE_SIZE))
815 panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));
817 if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) &&
818 mmu->s_pg_sz_m != TO_MB(HPAGE_PMD_SIZE))
819 panic("MMU Super pg size != Linux HPAGE_PMD_SIZE (%luM)\n",
820 (unsigned long)TO_MB(HPAGE_PMD_SIZE));
823 write_aux_reg(ARC_REG_PID, MMU_ENABLE);
825 /* In smp we use this reg for interrupt 1 scratch */
827 /* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
828 write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
833 * TLB Programmer's Model uses Linear Indexes: 0 to {255, 511} for 128 x {2,4}
834 * The mapping is Column-first.
835 * --------------------- -----------
836 * |way0|way1|way2|way3| |way0|way1|
837 * --------------------- -----------
838 * [set0] | 0 | 1 | 2 | 3 | | 0 | 1 |
839 * [set1] | 4 | 5 | 6 | 7 | | 2 | 3 |
841 * [set127] | 508| 509| 510| 511| | 254| 255|
842 * --------------------- -----------
843 * For normal operations we don't(must not) care how above works since
844 * MMU cmd getIndex(vaddr) abstracts that out.
845 * However for walking WAYS of a SET, we need to know this
847 #define SET_WAY_TO_IDX(mmu, set, way) ((set) * mmu->ways + (way))
849 /* Handling of Duplicate PD (TLB entry) in MMU.
850 * -Could be due to buggy customer tapeouts or obscure kernel bugs
851 * -MMU complaints not at the time of duplicate PD installation, but at the
852 * time of lookup matching multiple ways.
853 * -Ideally these should never happen - but if they do - workaround by deleting
855 * -Knob to be verbose abt it.(TODO: hook them up to debugfs)
857 volatile int dup_pd_verbose = 1;/* Be slient abt it or complain (default) */
859 void do_tlb_overlap_fault(unsigned long cause, unsigned long address,
860 struct pt_regs *regs)
863 unsigned long flags, is_valid;
864 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
865 unsigned int pd0[mmu->ways], pd1[mmu->ways];
867 local_irq_save(flags);
869 /* re-enable the MMU */
870 write_aux_reg(ARC_REG_PID, MMU_ENABLE | read_aux_reg(ARC_REG_PID));
872 /* loop thru all sets of TLB */
873 for (set = 0; set < mmu->sets; set++) {
875 /* read out all the ways of current set */
876 for (way = 0, is_valid = 0; way < mmu->ways; way++) {
877 write_aux_reg(ARC_REG_TLBINDEX,
878 SET_WAY_TO_IDX(mmu, set, way));
879 write_aux_reg(ARC_REG_TLBCOMMAND, TLBRead);
880 pd0[way] = read_aux_reg(ARC_REG_TLBPD0);
881 pd1[way] = read_aux_reg(ARC_REG_TLBPD1);
882 is_valid |= pd0[way] & _PAGE_PRESENT;
885 /* If all the WAYS in SET are empty, skip to next SET */
889 /* Scan the set for duplicate ways: needs a nested loop */
890 for (way = 0; way < mmu->ways - 1; way++) {
894 for (n = way + 1; n < mmu->ways; n++) {
895 if ((pd0[way] & PAGE_MASK) ==
896 (pd0[n] & PAGE_MASK)) {
898 if (dup_pd_verbose) {
899 pr_info("Duplicate PD's @"
902 pr_info("TLBPD0[%u]: %08x\n",
907 * clear entry @way and not @n. This is
908 * critical to our optimised loop
910 pd0[way] = pd1[way] = 0;
911 write_aux_reg(ARC_REG_TLBINDEX,
912 SET_WAY_TO_IDX(mmu, set, way));
919 local_irq_restore(flags);
922 /***********************************************************************
923 * Diagnostic Routines
924 * -Called from Low Level TLB Hanlders if things don;t look good
925 **********************************************************************/
927 #ifdef CONFIG_ARC_DBG_TLB_PARANOIA
930 * Low Level ASM TLB handler calls this if it finds that HW and SW ASIDS
933 void print_asid_mismatch(int mm_asid, int mmu_asid, int is_fast_path)
935 pr_emerg("ASID Mismatch in %s Path Handler: sw-pid=0x%x hw-pid=0x%x\n",
936 is_fast_path ? "Fast" : "Slow", mm_asid, mmu_asid);
938 __asm__ __volatile__("flag 1");
941 void tlb_paranoid_check(unsigned int mm_asid, unsigned long addr)
943 unsigned int mmu_asid;
945 mmu_asid = read_aux_reg(ARC_REG_PID) & 0xff;
948 * At the time of a TLB miss/installation
949 * - HW version needs to match SW version
950 * - SW needs to have a valid ASID
952 if (addr < 0x70000000 &&
953 ((mm_asid == MM_CTXT_NO_ASID) ||
954 (mmu_asid != (mm_asid & MM_CTXT_ASID_MASK))))
955 print_asid_mismatch(mm_asid, mmu_asid, 0);