2 * TLB Management (flush/create/diagnostics) for ARC700
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
14 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
15 * some of the LMBench tests improved amazingly
16 * = page-fault thrice as fast (75 usec to 28 usec)
17 * = mmap twice as fast (9.6 msec to 4.6 msec),
18 * = fork (5.3 msec to 3.7 msec)
20 * vineetg: April 2011 :
21 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
22 * helps avoid a shift when preparing PD0 from PTE
24 * vineetg: April 2011 : Preparing for MMU V3
25 * -MMU v2/v3 BCRs decoded differently
26 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
27 * -tlb_entry_erase( ) can be void
28 * -local_flush_tlb_range( ):
29 * = need not "ceil" @end
30 * = walks MMU only if range spans < 32 entries, as opposed to 256
32 * Vineetg: Sept 10th 2008
33 * -Changes related to MMU v2 (Rel 4.8)
35 * Vineetg: Aug 29th 2008
36 * -In TLB Flush operations (Metal Fix MMU) there is a explict command to
37 * flush Micro-TLBS. If TLB Index Reg is invalid prior to TLBIVUTLB cmd,
38 * it fails. Thus need to load it with ANY valid value before invoking
41 * Vineetg: Aug 21th 2008:
42 * -Reduced the duration of IRQ lockouts in TLB Flush routines
43 * -Multiple copies of TLB erase code seperated into a "single" function
44 * -In TLB Flush routines, interrupt disabling moved UP to retrieve ASID
45 * in interrupt-safe region.
47 * Vineetg: April 23rd Bug #93131
48 * Problem: tlb_flush_kernel_range() doesnt do anything if the range to
49 * flush is more than the size of TLB itself.
51 * Rahul Trivedi : Codito Technologies 2004
54 #include <linux/module.h>
55 #include <linux/bug.h>
56 #include <asm/arcregs.h>
57 #include <asm/setup.h>
58 #include <asm/mmu_context.h>
61 /* Need for ARC MMU v2
63 * ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc.
64 * For a memcpy operation with 3 players (src/dst/code) such that all 3 pages
65 * map into same set, there would be contention for the 2 ways causing severe
68 * Although J-TLB is 2 way set assoc, ARC700 caches J-TLB into uTLBS which has
69 * much higher associativity. u-D-TLB is 8 ways, u-I-TLB is 4 ways.
70 * Given this, the thrasing problem should never happen because once the 3
71 * J-TLB entries are created (even though 3rd will knock out one of the prev
72 * two), the u-D-TLB and u-I-TLB will have what is required to accomplish memcpy
74 * Yet we still see the Thrashing because a J-TLB Write cause flush of u-TLBs.
75 * This is a simple design for keeping them in sync. So what do we do?
76 * The solution which James came up was pretty neat. It utilised the assoc
77 * of uTLBs by not invalidating always but only when absolutely necessary.
79 * - Existing TLB commands work as before
80 * - New command (TLBWriteNI) for TLB write without clearing uTLBs
81 * - New command (TLBIVUTLB) to invalidate uTLBs.
83 * The uTLBs need only be invalidated when pages are being removed from the
84 * OS page table. If a 'victim' TLB entry is being overwritten in the main TLB
85 * as a result of a miss, the removed entry is still allowed to exist in the
86 * uTLBs as it is still valid and present in the OS page table. This allows the
87 * full associativity of the uTLBs to hide the limited associativity of the main
90 * During a miss handler, the new "TLBWriteNI" command is used to load
91 * entries without clearing the uTLBs.
93 * When the OS page table is updated, TLB entries that may be associated with a
94 * removed page are removed (flushed) from the TLB using TLBWrite. In this
95 * circumstance, the uTLBs must also be cleared. This is done by using the
96 * existing TLBWrite command. An explicit IVUTLB is also required for those
97 * corner cases when TLBWrite was not executed at all because the corresp
98 * J-TLB entry got evicted/replaced.
102 /* A copy of the ASID from the PID reg is kept in asid_cache */
103 DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;
106 * Utility Routine to erase a J-TLB entry
107 * Caller needs to setup Index Reg (manually or via getIndex)
109 static inline void __tlb_entry_erase(void)
111 write_aux_reg(ARC_REG_TLBPD1, 0);
112 write_aux_reg(ARC_REG_TLBPD0, 0);
113 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
116 #if (CONFIG_ARC_MMU_VER < 4)
118 static inline unsigned int tlb_entry_lkup(unsigned long vaddr_n_asid)
122 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid);
124 write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe);
125 idx = read_aux_reg(ARC_REG_TLBINDEX);
130 static void tlb_entry_erase(unsigned int vaddr_n_asid)
134 /* Locate the TLB entry for this vaddr + ASID */
135 idx = tlb_entry_lkup(vaddr_n_asid);
137 /* No error means entry found, zero it out */
138 if (likely(!(idx & TLB_LKUP_ERR))) {
141 /* Duplicate entry error */
142 WARN(idx == TLB_DUP_ERR, "Probe returned Dup PD for %x\n",
147 /****************************************************************************
148 * ARC700 MMU caches recently used J-TLB entries (RAM) as uTLBs (FLOPs)
150 * New IVUTLB cmd in MMU v2 explictly invalidates the uTLB
152 * utlb_invalidate ( )
153 * -For v2 MMU calls Flush uTLB Cmd
154 * -For v1 MMU does nothing (except for Metal Fix v1 MMU)
155 * This is because in v1 TLBWrite itself invalidate uTLBs
156 ***************************************************************************/
158 static void utlb_invalidate(void)
160 #if (CONFIG_ARC_MMU_VER >= 2)
162 #if (CONFIG_ARC_MMU_VER == 2)
163 /* MMU v2 introduced the uTLB Flush command.
164 * There was however an obscure hardware bug, where uTLB flush would
165 * fail when a prior probe for J-TLB (both totally unrelated) would
166 * return lkup err - because the entry didnt exist in MMU.
167 * The Workround was to set Index reg with some valid value, prior to
168 * flush. This was fixed in MMU v3 hence not needed any more
172 /* make sure INDEX Reg is valid */
173 idx = read_aux_reg(ARC_REG_TLBINDEX);
175 /* If not write some dummy val */
176 if (unlikely(idx & TLB_LKUP_ERR))
177 write_aux_reg(ARC_REG_TLBINDEX, 0xa);
180 write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB);
185 static void tlb_entry_insert(unsigned int pd0, unsigned int pd1)
190 * First verify if entry for this vaddr+ASID already exists
191 * This also sets up PD0 (vaddr, ASID..) for final commit
193 idx = tlb_entry_lkup(pd0);
196 * If Not already present get a free slot from MMU.
197 * Otherwise, Probe would have located the entry and set INDEX Reg
198 * with existing location. This will cause Write CMD to over-write
199 * existing entry with new PD0 and PD1
201 if (likely(idx & TLB_LKUP_ERR))
202 write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex);
204 /* setup the other half of TLB entry (pfn, rwx..) */
205 write_aux_reg(ARC_REG_TLBPD1, pd1);
208 * Commit the Entry to MMU
209 * It doesnt sound safe to use the TLBWriteNI cmd here
210 * which doesn't flush uTLBs. I'd rather be safe than sorry.
212 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
215 #else /* CONFIG_ARC_MMU_VER >= 4) */
217 static void utlb_invalidate(void)
219 /* No need since uTLB is always in sync with JTLB */
222 static void tlb_entry_erase(unsigned int vaddr_n_asid)
224 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid | _PAGE_PRESENT);
225 write_aux_reg(ARC_REG_TLBCOMMAND, TLBDeleteEntry);
228 static void tlb_entry_insert(unsigned int pd0, unsigned int pd1)
230 write_aux_reg(ARC_REG_TLBPD0, pd0);
231 write_aux_reg(ARC_REG_TLBPD1, pd1);
232 write_aux_reg(ARC_REG_TLBCOMMAND, TLBInsertEntry);
238 * Un-conditionally (without lookup) erase the entire MMU contents
241 noinline void local_flush_tlb_all(void)
245 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
247 local_irq_save(flags);
249 /* Load PD0 and PD1 with template for a Blank Entry */
250 write_aux_reg(ARC_REG_TLBPD1, 0);
251 write_aux_reg(ARC_REG_TLBPD0, 0);
253 for (entry = 0; entry < mmu->num_tlb; entry++) {
254 /* write this entry to the TLB */
255 write_aux_reg(ARC_REG_TLBINDEX, entry);
256 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
259 if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE)) {
260 const int stlb_idx = 0x800;
262 /* Blank sTLB entry */
263 write_aux_reg(ARC_REG_TLBPD0, _PAGE_HW_SZ);
265 for (entry = stlb_idx; entry < stlb_idx + 16; entry++) {
266 write_aux_reg(ARC_REG_TLBINDEX, entry);
267 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
273 local_irq_restore(flags);
277 * Flush the entrie MM for userland. The fastest way is to move to Next ASID
279 noinline void local_flush_tlb_mm(struct mm_struct *mm)
282 * Small optimisation courtesy IA64
283 * flush_mm called during fork,exit,munmap etc, multiple times as well.
284 * Only for fork( ) do we need to move parent to a new MMU ctxt,
285 * all other cases are NOPs, hence this check.
287 if (atomic_read(&mm->mm_users) == 0)
291 * - Move to a new ASID, but only if the mm is still wired in
292 * (Android Binder ended up calling this for vma->mm != tsk->mm,
293 * causing h/w - s/w ASID to get out of sync)
294 * - Also get_new_mmu_context() new implementation allocates a new
295 * ASID only if it is not allocated already - so unallocate first
298 if (current->mm == mm)
299 get_new_mmu_context(mm);
303 * Flush a Range of TLB entries for userland.
304 * @start is inclusive, while @end is exclusive
305 * Difference between this and Kernel Range Flush is
306 * -Here the fastest way (if range is too large) is to move to next ASID
307 * without doing any explicit Shootdown
308 * -In case of kernel Flush, entry has to be shot down explictly
310 void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
313 const unsigned int cpu = smp_processor_id();
316 /* If range @start to @end is more than 32 TLB entries deep,
317 * its better to move to a new ASID rather than searching for
318 * individual entries and then shooting them down
320 * The calc above is rough, doesn't account for unaligned parts,
321 * since this is heuristics based anyways
323 if (unlikely((end - start) >= PAGE_SIZE * 32)) {
324 local_flush_tlb_mm(vma->vm_mm);
329 * @start moved to page start: this alone suffices for checking
330 * loop end condition below, w/o need for aligning @end to end
331 * e.g. 2000 to 4001 will anyhow loop twice
335 local_irq_save(flags);
337 if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
338 while (start < end) {
339 tlb_entry_erase(start | hw_pid(vma->vm_mm, cpu));
346 local_irq_restore(flags);
349 /* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
350 * @start, @end interpreted as kvaddr
351 * Interestingly, shared TLB entries can also be flushed using just
352 * @start,@end alone (interpreted as user vaddr), although technically SASID
353 * is also needed. However our smart TLbProbe lookup takes care of that.
355 void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
359 /* exactly same as above, except for TLB entry not taking ASID */
361 if (unlikely((end - start) >= PAGE_SIZE * 32)) {
362 local_flush_tlb_all();
368 local_irq_save(flags);
369 while (start < end) {
370 tlb_entry_erase(start);
376 local_irq_restore(flags);
380 * Delete TLB entry in MMU for a given page (??? address)
381 * NOTE One TLB entry contains translation for single PAGE
384 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
386 const unsigned int cpu = smp_processor_id();
389 /* Note that it is critical that interrupts are DISABLED between
390 * checking the ASID and using it flush the TLB entry
392 local_irq_save(flags);
394 if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
395 tlb_entry_erase((page & PAGE_MASK) | hw_pid(vma->vm_mm, cpu));
399 local_irq_restore(flags);
405 struct vm_area_struct *ta_vma;
406 unsigned long ta_start;
407 unsigned long ta_end;
410 static inline void ipi_flush_tlb_page(void *arg)
412 struct tlb_args *ta = arg;
414 local_flush_tlb_page(ta->ta_vma, ta->ta_start);
417 static inline void ipi_flush_tlb_range(void *arg)
419 struct tlb_args *ta = arg;
421 local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
424 static inline void ipi_flush_tlb_kernel_range(void *arg)
426 struct tlb_args *ta = (struct tlb_args *)arg;
428 local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end);
431 void flush_tlb_all(void)
433 on_each_cpu((smp_call_func_t)local_flush_tlb_all, NULL, 1);
436 void flush_tlb_mm(struct mm_struct *mm)
438 on_each_cpu_mask(mm_cpumask(mm), (smp_call_func_t)local_flush_tlb_mm,
442 void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
444 struct tlb_args ta = {
449 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_page, &ta, 1);
452 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
455 struct tlb_args ta = {
461 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_range, &ta, 1);
464 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
466 struct tlb_args ta = {
471 on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
476 * Routine to create a TLB entry
478 void create_tlb(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
481 unsigned int asid_or_sasid, rwx;
482 unsigned long pd0, pd1;
485 * create_tlb() assumes that current->mm == vma->mm, since
486 * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr)
487 * -completes the lazy write to SASID reg (again valid for curr tsk)
489 * Removing the assumption involves
490 * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.
491 * -Fix the TLB paranoid debug code to not trigger false negatives.
492 * -More importantly it makes this handler inconsistent with fast-path
493 * TLB Refill handler which always deals with "current"
495 * Lets see the use cases when current->mm != vma->mm and we land here
496 * 1. execve->copy_strings()->__get_user_pages->handle_mm_fault
497 * Here VM wants to pre-install a TLB entry for user stack while
498 * current->mm still points to pre-execve mm (hence the condition).
499 * However the stack vaddr is soon relocated (randomization) and
500 * move_page_tables() tries to undo that TLB entry.
501 * Thus not creating TLB entry is not any worse.
503 * 2. ptrace(POKETEXT) causes a CoW - debugger(current) inserting a
504 * breakpoint in debugged task. Not creating a TLB now is not
505 * performance critical.
507 * Both the cases above are not good enough for code churn.
509 if (current->active_mm != vma->vm_mm)
512 local_irq_save(flags);
514 tlb_paranoid_check(asid_mm(vma->vm_mm, smp_processor_id()), address);
516 address &= PAGE_MASK;
518 /* update this PTE credentials */
519 pte_val(*ptep) |= (_PAGE_PRESENT | _PAGE_ACCESSED);
521 /* Create HW TLB(PD0,PD1) from PTE */
523 /* ASID for this task */
524 asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff;
526 pd0 = address | asid_or_sasid | (pte_val(*ptep) & PTE_BITS_IN_PD0);
529 * ARC MMU provides fully orthogonal access bits for K/U mode,
530 * however Linux only saves 1 set to save PTE real-estate
531 * Here we convert 3 PTE bits into 6 MMU bits:
532 * -Kernel only entries have Kr Kw Kx 0 0 0
533 * -User entries have mirrored K and U bits
535 rwx = pte_val(*ptep) & PTE_BITS_RWX;
537 if (pte_val(*ptep) & _PAGE_GLOBAL)
538 rwx <<= 3; /* r w x => Kr Kw Kx 0 0 0 */
540 rwx |= (rwx << 3); /* r w x => Kr Kw Kx Ur Uw Ux */
542 pd1 = rwx | (pte_val(*ptep) & PTE_BITS_NON_RWX_IN_PD1);
544 tlb_entry_insert(pd0, pd1);
546 local_irq_restore(flags);
550 * Called at the end of pagefault, for a userspace mapped page
551 * -pre-install the corresponding TLB entry into MMU
552 * -Finalize the delayed D-cache flush of kernel mapping of page due to
553 * flush_dcache_page(), copy_user_page()
555 * Note that flush (when done) involves both WBACK - so physical page is
556 * in sync as well as INV - so any non-congruent aliases don't remain
558 void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
561 unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
562 unsigned long paddr = pte_val(*ptep) & PAGE_MASK;
563 struct page *page = pfn_to_page(pte_pfn(*ptep));
565 create_tlb(vma, vaddr, ptep);
567 if (page == ZERO_PAGE(0)) {
572 * Exec page : Independent of aliasing/page-color considerations,
573 * since icache doesn't snoop dcache on ARC, any dirty
574 * K-mapping of a code page needs to be wback+inv so that
575 * icache fetch by userspace sees code correctly.
576 * !EXEC page: If K-mapping is NOT congruent to U-mapping, flush it
577 * so userspace sees the right data.
578 * (Avoids the flush for Non-exec + congruent mapping case)
580 if ((vma->vm_flags & VM_EXEC) ||
581 addr_not_cache_congruent(paddr, vaddr)) {
583 int dirty = !test_and_set_bit(PG_dc_clean, &page->flags);
585 /* wback + inv dcache lines */
586 __flush_dcache_page(paddr, paddr);
588 /* invalidate any existing icache lines */
589 if (vma->vm_flags & VM_EXEC)
590 __inv_icache_page(paddr, vaddr);
595 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
598 * MMUv4 in HS38x cores supports Super Pages which are basis for Linux THP
601 * Normal and Super pages can co-exist (ofcourse not overlap) in TLB with a
602 * new bit "SZ" in TLB page desciptor to distinguish between them.
603 * Super Page size is configurable in hardware (4K to 16M), but fixed once
606 * The exact THP size a Linx configuration will support is a function of:
607 * - MMU page size (typical 8K, RTL fixed)
608 * - software page walker address split between PGD:PTE:PFN (typical
609 * 11:8:13, but can be changed with 1 line)
610 * So for above default, THP size supported is 8K * (2^8) = 2M
612 * Default Page Walker is 2 levels, PGD:PTE:PFN, which in THP regime
613 * reduces to 1 level (as PTE is folded into PGD and canonically referred
615 * Thus THP PMD accessors are implemented in terms of PTE (just like sparc)
618 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
621 pte_t pte = __pte(pmd_val(*pmd));
622 update_mmu_cache(vma, addr, &pte);
625 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
628 struct list_head *lh = (struct list_head *) pgtable;
630 assert_spin_locked(&mm->page_table_lock);
633 if (!pmd_huge_pte(mm, pmdp))
636 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
637 pmd_huge_pte(mm, pmdp) = pgtable;
640 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
642 struct list_head *lh;
645 assert_spin_locked(&mm->page_table_lock);
647 pgtable = pmd_huge_pte(mm, pmdp);
648 lh = (struct list_head *) pgtable;
650 pmd_huge_pte(mm, pmdp) = NULL;
652 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
656 pte_val(pgtable[0]) = 0;
657 pte_val(pgtable[1]) = 0;
664 /* Read the Cache Build Confuration Registers, Decode them and save into
665 * the cpuinfo structure for later use.
666 * No Validation is done here, simply read/convert the BCRs
668 void read_decode_mmu_bcr(void)
670 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
673 #ifdef CONFIG_CPU_BIG_ENDIAN
674 unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
676 unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
681 #ifdef CONFIG_CPU_BIG_ENDIAN
682 unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,
685 unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,
691 #ifdef CONFIG_CPU_BIG_ENDIAN
692 unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
693 n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
695 /* DTLB ITLB JES JE JA */
696 unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
697 pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
701 tmp = read_aux_reg(ARC_REG_MMU_BCR);
702 mmu->ver = (tmp >> 24);
705 mmu2 = (struct bcr_mmu_1_2 *)&tmp;
706 mmu->pg_sz_k = TO_KB(PAGE_SIZE);
707 mmu->sets = 1 << mmu2->sets;
708 mmu->ways = 1 << mmu2->ways;
709 mmu->u_dtlb = mmu2->u_dtlb;
710 mmu->u_itlb = mmu2->u_itlb;
711 } else if (mmu->ver == 3) {
712 mmu3 = (struct bcr_mmu_3 *)&tmp;
713 mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1);
714 mmu->sets = 1 << mmu3->sets;
715 mmu->ways = 1 << mmu3->ways;
716 mmu->u_dtlb = mmu3->u_dtlb;
717 mmu->u_itlb = mmu3->u_itlb;
719 mmu4 = (struct bcr_mmu_4 *)&tmp;
720 mmu->pg_sz_k = 1 << (mmu4->sz0 - 1);
721 mmu->s_pg_sz_m = 1 << (mmu4->sz1 - 11);
722 mmu->sets = 64 << mmu4->n_entry;
723 mmu->ways = mmu4->n_ways * 2;
724 mmu->u_dtlb = mmu4->u_dtlb * 4;
725 mmu->u_itlb = mmu4->u_itlb * 4;
728 mmu->num_tlb = mmu->sets * mmu->ways;
731 char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
734 struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu;
735 char super_pg[64] = "";
737 if (p_mmu->s_pg_sz_m)
738 scnprintf(super_pg, 64, "%dM Super Page%s, ",
739 p_mmu->s_pg_sz_m, " (not used)");
741 n += scnprintf(buf + n, len - n,
742 "MMU [v%x]\t: %dk PAGE, %sJTLB %d (%dx%d), uDTLB %d, uITLB %d %s\n",
743 p_mmu->ver, p_mmu->pg_sz_k, super_pg,
744 p_mmu->num_tlb, p_mmu->sets, p_mmu->ways,
745 p_mmu->u_dtlb, p_mmu->u_itlb,
746 IS_ENABLED(CONFIG_ARC_MMU_SASID) ? ",SASID" : "");
751 void arc_mmu_init(void)
754 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
756 printk(arc_mmu_mumbojumbo(0, str, sizeof(str)));
758 /* For efficiency sake, kernel is compile time built for a MMU ver
759 * This must match the hardware it is running on.
760 * Linux built for MMU V2, if run on MMU V1 will break down because V1
761 * hardware doesn't understand cmds such as WriteNI, or IVUTLB
762 * On the other hand, Linux built for V1 if run on MMU V2 will do
763 * un-needed workarounds to prevent memcpy thrashing.
764 * Similarly MMU V3 has new features which won't work on older MMU
766 if (mmu->ver != CONFIG_ARC_MMU_VER) {
767 panic("MMU ver %d doesn't match kernel built for %d...\n",
768 mmu->ver, CONFIG_ARC_MMU_VER);
771 if (mmu->pg_sz_k != TO_KB(PAGE_SIZE))
772 panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));
775 write_aux_reg(ARC_REG_PID, MMU_ENABLE);
777 /* In smp we use this reg for interrupt 1 scratch */
779 /* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
780 write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
785 * TLB Programmer's Model uses Linear Indexes: 0 to {255, 511} for 128 x {2,4}
786 * The mapping is Column-first.
787 * --------------------- -----------
788 * |way0|way1|way2|way3| |way0|way1|
789 * --------------------- -----------
790 * [set0] | 0 | 1 | 2 | 3 | | 0 | 1 |
791 * [set1] | 4 | 5 | 6 | 7 | | 2 | 3 |
793 * [set127] | 508| 509| 510| 511| | 254| 255|
794 * --------------------- -----------
795 * For normal operations we don't(must not) care how above works since
796 * MMU cmd getIndex(vaddr) abstracts that out.
797 * However for walking WAYS of a SET, we need to know this
799 #define SET_WAY_TO_IDX(mmu, set, way) ((set) * mmu->ways + (way))
801 /* Handling of Duplicate PD (TLB entry) in MMU.
802 * -Could be due to buggy customer tapeouts or obscure kernel bugs
803 * -MMU complaints not at the time of duplicate PD installation, but at the
804 * time of lookup matching multiple ways.
805 * -Ideally these should never happen - but if they do - workaround by deleting
807 * -Knob to be verbose abt it.(TODO: hook them up to debugfs)
809 volatile int dup_pd_verbose = 1;/* Be slient abt it or complain (default) */
811 void do_tlb_overlap_fault(unsigned long cause, unsigned long address,
812 struct pt_regs *regs)
815 unsigned long flags, is_valid;
816 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
817 unsigned int pd0[mmu->ways], pd1[mmu->ways];
819 local_irq_save(flags);
821 /* re-enable the MMU */
822 write_aux_reg(ARC_REG_PID, MMU_ENABLE | read_aux_reg(ARC_REG_PID));
824 /* loop thru all sets of TLB */
825 for (set = 0; set < mmu->sets; set++) {
827 /* read out all the ways of current set */
828 for (way = 0, is_valid = 0; way < mmu->ways; way++) {
829 write_aux_reg(ARC_REG_TLBINDEX,
830 SET_WAY_TO_IDX(mmu, set, way));
831 write_aux_reg(ARC_REG_TLBCOMMAND, TLBRead);
832 pd0[way] = read_aux_reg(ARC_REG_TLBPD0);
833 pd1[way] = read_aux_reg(ARC_REG_TLBPD1);
834 is_valid |= pd0[way] & _PAGE_PRESENT;
837 /* If all the WAYS in SET are empty, skip to next SET */
841 /* Scan the set for duplicate ways: needs a nested loop */
842 for (way = 0; way < mmu->ways - 1; way++) {
846 for (n = way + 1; n < mmu->ways; n++) {
847 if ((pd0[way] & PAGE_MASK) ==
848 (pd0[n] & PAGE_MASK)) {
850 if (dup_pd_verbose) {
851 pr_info("Duplicate PD's @"
854 pr_info("TLBPD0[%u]: %08x\n",
859 * clear entry @way and not @n. This is
860 * critical to our optimised loop
862 pd0[way] = pd1[way] = 0;
863 write_aux_reg(ARC_REG_TLBINDEX,
864 SET_WAY_TO_IDX(mmu, set, way));
871 local_irq_restore(flags);
874 /***********************************************************************
875 * Diagnostic Routines
876 * -Called from Low Level TLB Hanlders if things don;t look good
877 **********************************************************************/
879 #ifdef CONFIG_ARC_DBG_TLB_PARANOIA
882 * Low Level ASM TLB handler calls this if it finds that HW and SW ASIDS
885 void print_asid_mismatch(int mm_asid, int mmu_asid, int is_fast_path)
887 pr_emerg("ASID Mismatch in %s Path Handler: sw-pid=0x%x hw-pid=0x%x\n",
888 is_fast_path ? "Fast" : "Slow", mm_asid, mmu_asid);
890 __asm__ __volatile__("flag 1");
893 void tlb_paranoid_check(unsigned int mm_asid, unsigned long addr)
895 unsigned int mmu_asid;
897 mmu_asid = read_aux_reg(ARC_REG_PID) & 0xff;
900 * At the time of a TLB miss/installation
901 * - HW version needs to match SW version
902 * - SW needs to have a valid ASID
904 if (addr < 0x70000000 &&
905 ((mm_asid == MM_CTXT_NO_ASID) ||
906 (mmu_asid != (mm_asid & MM_CTXT_ASID_MASK))))
907 print_asid_mismatch(mm_asid, mmu_asid, 0);