4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_WANT_IPC_PARSE_VERSION
8 select BUILDTIME_EXTABLE_SORT if MMU
9 select CPU_PM if (SUSPEND || CPU_IDLE)
10 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
13 select GENERIC_IRQ_PROBE
14 select GENERIC_IRQ_SHOW
15 select GENERIC_KERNEL_THREAD
16 select GENERIC_KERNEL_EXECVE
17 select GENERIC_PCI_IOMAP
18 select GENERIC_SMP_IDLE_THREAD
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_SECCOMP_FILTER
26 select HAVE_ARCH_TRACEHOOK
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_API_DEBUG
32 select HAVE_DMA_CONTIGUOUS if MMU
33 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
34 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
35 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
36 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
37 select HAVE_GENERIC_DMA_COHERENT
38 select HAVE_GENERIC_HARDIRQS
39 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
40 select HAVE_IDE if PCI || ISA || PCMCIA
42 select HAVE_KERNEL_GZIP
43 select HAVE_KERNEL_LZMA
44 select HAVE_KERNEL_LZO
46 select HAVE_KPROBES if !XIP_KERNEL
47 select HAVE_KRETPROBES if (HAVE_KPROBES)
49 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
50 select HAVE_PERF_EVENTS
51 select HAVE_REGS_AND_STACK_ACCESS_API
52 select HAVE_SYSCALL_TRACEPOINTS
55 select PERF_USE_VMALLOC
57 select SYS_SUPPORTS_APM_EMULATION
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select MODULES_USE_ELF_REL
60 select CLONE_BACKWARDS
62 The ARM series is a line of low-power-consumption RISC chip designs
63 licensed by ARM Ltd and targeted at embedded applications and
64 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
65 manufactured, but legacy ARM-based PC hardware remains popular in
66 Europe. There is an ARM Linux project with a web page at
67 <http://www.arm.linux.org.uk/>.
69 config ARM_HAS_SG_CHAIN
72 config NEED_SG_DMA_LENGTH
75 config ARM_DMA_USE_IOMMU
77 select ARM_HAS_SG_CHAIN
78 select NEED_SG_DMA_LENGTH
86 config SYS_SUPPORTS_APM_EMULATION
94 select GENERIC_ALLOCATOR
105 The Extended Industry Standard Architecture (EISA) bus was
106 developed as an open alternative to the IBM MicroChannel bus.
108 The EISA bus provided some of the features of the IBM MicroChannel
109 bus while maintaining backward compatibility with cards made for
110 the older ISA bus. The EISA bus saw limited use between 1988 and
111 1995 when it was made obsolete by the PCI bus.
113 Say Y here if you are building a kernel for an EISA-based machine.
120 config STACKTRACE_SUPPORT
124 config HAVE_LATENCYTOP_SUPPORT
129 config LOCKDEP_SUPPORT
133 config TRACE_IRQFLAGS_SUPPORT
137 config RWSEM_GENERIC_SPINLOCK
141 config RWSEM_XCHGADD_ALGORITHM
144 config ARCH_HAS_ILOG2_U32
147 config ARCH_HAS_ILOG2_U64
150 config ARCH_HAS_CPUFREQ
153 Internal node to signify that the ARCH has CPUFREQ support
154 and that the relevant menu configurations are displayed for
157 config GENERIC_HWEIGHT
161 config GENERIC_CALIBRATE_DELAY
165 config ARCH_MAY_HAVE_PC_FDC
171 config NEED_DMA_MAP_STATE
174 config ARCH_HAS_DMA_SET_COHERENT_MASK
177 config GENERIC_ISA_DMA
183 config NEED_RET_TO_USER
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
214 config NEED_MACH_GPIO_H
217 Select this when mach/gpio.h is required to provide special
218 definitions for this platform. The need for mach/gpio.h should
219 be avoided when possible.
221 config NEED_MACH_IO_H
224 Select this when mach/io.h is required to provide special
225 definitions for this platform. The need for mach/io.h should
226 be avoided when possible.
228 config NEED_MACH_MEMORY_H
231 Select this when mach/memory.h is required to provide special
232 definitions for this platform. The need for mach/memory.h should
233 be avoided when possible.
236 hex "Physical address of main memory" if MMU
237 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
238 default DRAM_BASE if !MMU
240 Please provide the physical address corresponding to the
241 location of main memory in your system.
247 source "init/Kconfig"
249 source "kernel/Kconfig.freezer"
254 bool "MMU-based Paged Memory Management Support"
257 Select if you want MMU-based virtualised addressing space
258 support by paged memory management. If unsure, say 'Y'.
261 # The "ARM system type" choice list is ordered alphabetically by option
262 # text. Please add new entries in the option alphabetic order.
265 prompt "ARM system type"
266 default ARCH_MULTIPLATFORM
268 config ARCH_MULTIPLATFORM
269 bool "Allow multiple platforms to be selected"
271 select ARM_PATCH_PHYS_VIRT
274 select MULTI_IRQ_HANDLER
278 config ARCH_INTEGRATOR
279 bool "ARM Ltd. Integrator family"
280 select ARCH_HAS_CPUFREQ
283 select COMMON_CLK_VERSATILE
284 select GENERIC_CLOCKEVENTS
287 select MULTI_IRQ_HANDLER
288 select NEED_MACH_MEMORY_H
289 select PLAT_VERSATILE
291 select VERSATILE_FPGA_IRQ
293 Support for ARM's Integrator platform.
296 bool "ARM Ltd. RealView family"
297 select ARCH_WANT_OPTIONAL_GPIOLIB
299 select ARM_TIMER_SP804
301 select COMMON_CLK_VERSATILE
302 select GENERIC_CLOCKEVENTS
303 select GPIO_PL061 if GPIOLIB
305 select NEED_MACH_MEMORY_H
306 select PLAT_VERSATILE
307 select PLAT_VERSATILE_CLCD
309 This enables support for ARM Ltd RealView boards.
311 config ARCH_VERSATILE
312 bool "ARM Ltd. Versatile family"
313 select ARCH_WANT_OPTIONAL_GPIOLIB
315 select ARM_TIMER_SP804
318 select GENERIC_CLOCKEVENTS
319 select HAVE_MACH_CLKDEV
321 select PLAT_VERSATILE
322 select PLAT_VERSATILE_CLCD
323 select PLAT_VERSATILE_CLOCK
324 select VERSATILE_FPGA_IRQ
326 This enables support for ARM Ltd Versatile board.
330 select ARCH_REQUIRE_GPIOLIB
334 select NEED_MACH_GPIO_H
335 select NEED_MACH_IO_H if PCCARD
337 select PINCTRL_AT91 if USE_OF
339 This enables support for systems based on Atmel
340 AT91RM9200 and AT91SAM9* processors.
343 bool "Broadcom BCM2835 family"
344 select ARCH_REQUIRE_GPIOLIB
346 select ARM_ERRATA_411920
347 select ARM_TIMER_SP804
351 select GENERIC_CLOCKEVENTS
353 select MULTI_IRQ_HANDLER
355 select PINCTRL_BCM2835
359 This enables support for the Broadcom BCM2835 SoC. This SoC is
360 use in the Raspberry Pi, and Roku 2 devices.
363 bool "Cavium Networks CNS3XXX family"
366 select GENERIC_CLOCKEVENTS
367 select MIGHT_HAVE_CACHE_L2X0
368 select MIGHT_HAVE_PCI
369 select PCI_DOMAINS if PCI
371 Support for Cavium Networks CNS3XXX platform.
374 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
375 select ARCH_REQUIRE_GPIOLIB
376 select ARCH_USES_GETTIMEOFFSET
381 select GENERIC_CLOCKEVENTS
382 select MULTI_IRQ_HANDLER
383 select NEED_MACH_MEMORY_H
386 Support for Cirrus Logic 711x/721x/731x based boards.
389 bool "Cortina Systems Gemini"
390 select ARCH_REQUIRE_GPIOLIB
391 select ARCH_USES_GETTIMEOFFSET
394 Support for the Cortina Systems Gemini family SoCs
398 select ARCH_REQUIRE_GPIOLIB
400 select GENERIC_CLOCKEVENTS
401 select GENERIC_IRQ_CHIP
402 select MIGHT_HAVE_CACHE_L2X0
408 Support for CSR SiRFprimaII/Marco/Polo platforms
412 select ARCH_USES_GETTIMEOFFSET
415 select NEED_MACH_IO_H
416 select NEED_MACH_MEMORY_H
419 This is an evaluation board for the StrongARM processor available
420 from Digital. It has limited hardware on-board, including an
421 Ethernet interface, two PCMCIA sockets, two serial ports and a
426 select ARCH_HAS_HOLES_MEMORYMODEL
427 select ARCH_REQUIRE_GPIOLIB
428 select ARCH_USES_GETTIMEOFFSET
433 select NEED_MACH_MEMORY_H
435 This enables support for the Cirrus EP93xx series of CPUs.
437 config ARCH_FOOTBRIDGE
441 select GENERIC_CLOCKEVENTS
443 select NEED_MACH_IO_H if !MMU
444 select NEED_MACH_MEMORY_H
446 Support for systems based on the DC21285 companion chip
447 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
450 bool "Freescale MXS-based"
451 select ARCH_REQUIRE_GPIOLIB
455 select GENERIC_CLOCKEVENTS
456 select HAVE_CLK_PREPARE
457 select MULTI_IRQ_HANDLER
462 Support for Freescale MXS-based family of processors
465 bool "Hilscher NetX based"
469 select GENERIC_CLOCKEVENTS
471 This enables support for systems based on the Hilscher NetX Soc
474 bool "Hynix HMS720x-based"
475 select ARCH_USES_GETTIMEOFFSET
479 This enables support for systems based on the Hynix HMS720x
484 select ARCH_SUPPORTS_MSI
486 select NEED_MACH_MEMORY_H
487 select NEED_RET_TO_USER
492 Support for Intel's IOP13XX (XScale) family of processors.
497 select ARCH_REQUIRE_GPIOLIB
499 select NEED_MACH_GPIO_H
500 select NEED_RET_TO_USER
504 Support for Intel's 80219 and IOP32X (XScale) family of
510 select ARCH_REQUIRE_GPIOLIB
512 select NEED_MACH_GPIO_H
513 select NEED_RET_TO_USER
517 Support for Intel's IOP33X (XScale) family of processors.
522 select ARCH_HAS_DMA_SET_COHERENT_MASK
523 select ARCH_REQUIRE_GPIOLIB
526 select DMABOUNCE if PCI
527 select GENERIC_CLOCKEVENTS
528 select MIGHT_HAVE_PCI
529 select NEED_MACH_IO_H
531 Support for Intel's IXP4XX (XScale) family of processors.
535 select ARCH_REQUIRE_GPIOLIB
537 select GENERIC_CLOCKEVENTS
538 select MIGHT_HAVE_PCI
541 select PLAT_ORION_LEGACY
542 select USB_ARCH_HAS_EHCI
544 Support for the Marvell Dove SoC 88AP510
547 bool "Marvell Kirkwood"
548 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_CLOCKEVENTS
554 select PINCTRL_KIRKWOOD
555 select PLAT_ORION_LEGACY
557 Support for the following Marvell Kirkwood series SoCs:
558 88F6180, 88F6192 and 88F6281.
561 bool "Marvell MV78xx0"
562 select ARCH_REQUIRE_GPIOLIB
564 select GENERIC_CLOCKEVENTS
566 select PLAT_ORION_LEGACY
568 Support for the following Marvell MV78xx0 series SoCs:
574 select ARCH_REQUIRE_GPIOLIB
576 select GENERIC_CLOCKEVENTS
578 select PLAT_ORION_LEGACY
580 Support for the following Marvell Orion 5x series SoCs:
581 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
582 Orion-2 (5281), Orion-1-90 (6183).
585 bool "Marvell PXA168/910/MMP2"
587 select ARCH_REQUIRE_GPIOLIB
589 select GENERIC_ALLOCATOR
590 select GENERIC_CLOCKEVENTS
593 select NEED_MACH_GPIO_H
598 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
601 bool "Micrel/Kendin KS8695"
602 select ARCH_REQUIRE_GPIOLIB
605 select GENERIC_CLOCKEVENTS
606 select NEED_MACH_MEMORY_H
608 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
609 System-on-Chip devices.
612 bool "Nuvoton W90X900 CPU"
613 select ARCH_REQUIRE_GPIOLIB
617 select GENERIC_CLOCKEVENTS
619 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
620 At present, the w90x900 has been renamed nuc900, regarding
621 the ARM series product line, you can login the following
622 link address to know more.
624 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
625 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
629 select ARCH_REQUIRE_GPIOLIB
634 select GENERIC_CLOCKEVENTS
637 select USB_ARCH_HAS_OHCI
640 Support for the NXP LPC32XX family of processors
644 select ARCH_HAS_CPUFREQ
648 select GENERIC_CLOCKEVENTS
652 select MIGHT_HAVE_CACHE_L2X0
655 This enables support for NVIDIA Tegra based systems (Tegra APX,
656 Tegra 6xx and Tegra 2 series).
659 bool "PXA2xx/PXA3xx-based"
661 select ARCH_HAS_CPUFREQ
663 select ARCH_REQUIRE_GPIOLIB
664 select ARM_CPU_SUSPEND if PM
668 select GENERIC_CLOCKEVENTS
671 select MULTI_IRQ_HANDLER
672 select NEED_MACH_GPIO_H
676 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
680 select ARCH_REQUIRE_GPIOLIB
682 select GENERIC_CLOCKEVENTS
685 Support for Qualcomm MSM/QSD based systems. This runs on the
686 apps processor of the MSM/QSD and depends on a shared memory
687 interface to the modem processor which runs the baseband
688 stack and controls some vital subsystems
689 (clock and power control, etc).
692 bool "Renesas SH-Mobile / R-Mobile"
694 select GENERIC_CLOCKEVENTS
696 select HAVE_MACH_CLKDEV
698 select MIGHT_HAVE_CACHE_L2X0
699 select MULTI_IRQ_HANDLER
700 select NEED_MACH_MEMORY_H
702 select PM_GENERIC_DOMAINS if PM
705 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
710 select ARCH_MAY_HAVE_PC_FDC
711 select ARCH_SPARSEMEM_ENABLE
712 select ARCH_USES_GETTIMEOFFSET
715 select HAVE_PATA_PLATFORM
717 select NEED_MACH_IO_H
718 select NEED_MACH_MEMORY_H
721 On the Acorn Risc-PC, Linux can support the internal IDE disk and
722 CD-ROM interface, serial and parallel port, and the floppy drive.
726 select ARCH_HAS_CPUFREQ
728 select ARCH_REQUIRE_GPIOLIB
729 select ARCH_SPARSEMEM_ENABLE
734 select GENERIC_CLOCKEVENTS
737 select NEED_MACH_GPIO_H
738 select NEED_MACH_MEMORY_H
741 Support for StrongARM 11x0 based boards.
744 bool "Samsung S3C24XX SoCs"
745 select ARCH_HAS_CPUFREQ
746 select ARCH_USES_GETTIMEOFFSET
750 select HAVE_S3C2410_I2C if I2C
751 select HAVE_S3C2410_WATCHDOG if WATCHDOG
752 select HAVE_S3C_RTC if RTC_CLASS
753 select NEED_MACH_GPIO_H
754 select NEED_MACH_IO_H
756 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
757 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
758 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
759 Samsung SMDK2410 development board (and derivatives).
762 bool "Samsung S3C64XX"
763 select ARCH_HAS_CPUFREQ
764 select ARCH_REQUIRE_GPIOLIB
765 select ARCH_USES_GETTIMEOFFSET
770 select HAVE_S3C2410_I2C if I2C
771 select HAVE_S3C2410_WATCHDOG if WATCHDOG
773 select NEED_MACH_GPIO_H
777 select S3C_GPIO_TRACK
778 select SAMSUNG_CLKSRC
779 select SAMSUNG_GPIOLIB_4BIT
780 select SAMSUNG_IRQ_VIC_TIMER
781 select USB_ARCH_HAS_OHCI
783 Samsung S3C64XX series based systems
786 bool "Samsung S5P6440 S5P6450"
790 select GENERIC_CLOCKEVENTS
793 select HAVE_S3C2410_I2C if I2C
794 select HAVE_S3C2410_WATCHDOG if WATCHDOG
795 select HAVE_S3C_RTC if RTC_CLASS
796 select NEED_MACH_GPIO_H
798 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
802 bool "Samsung S5PC100"
803 select ARCH_USES_GETTIMEOFFSET
808 select HAVE_S3C2410_I2C if I2C
809 select HAVE_S3C2410_WATCHDOG if WATCHDOG
810 select HAVE_S3C_RTC if RTC_CLASS
811 select NEED_MACH_GPIO_H
813 Samsung S5PC100 series based systems
816 bool "Samsung S5PV210/S5PC110"
817 select ARCH_HAS_CPUFREQ
818 select ARCH_HAS_HOLES_MEMORYMODEL
819 select ARCH_SPARSEMEM_ENABLE
823 select GENERIC_CLOCKEVENTS
826 select HAVE_S3C2410_I2C if I2C
827 select HAVE_S3C2410_WATCHDOG if WATCHDOG
828 select HAVE_S3C_RTC if RTC_CLASS
829 select NEED_MACH_GPIO_H
830 select NEED_MACH_MEMORY_H
832 Samsung S5PV210/S5PC110 series based systems
835 bool "Samsung EXYNOS"
836 select ARCH_HAS_CPUFREQ
837 select ARCH_HAS_HOLES_MEMORYMODEL
838 select ARCH_SPARSEMEM_ENABLE
841 select GENERIC_CLOCKEVENTS
844 select HAVE_S3C2410_I2C if I2C
845 select HAVE_S3C2410_WATCHDOG if WATCHDOG
846 select HAVE_S3C_RTC if RTC_CLASS
847 select NEED_MACH_GPIO_H
848 select NEED_MACH_MEMORY_H
850 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
854 select ARCH_USES_GETTIMEOFFSET
858 select NEED_MACH_MEMORY_H
862 Support for the StrongARM based Digital DNARD machine, also known
863 as "Shark" (<http://www.shark-linux.de/shark.html>).
866 bool "ST-Ericsson U300 Series"
868 select ARCH_REQUIRE_GPIOLIB
870 select ARM_PATCH_PHYS_VIRT
876 select GENERIC_CLOCKEVENTS
881 Support for ST-Ericsson U300 series mobile platforms.
884 bool "ST-Ericsson U8500 Series"
886 select ARCH_HAS_CPUFREQ
887 select ARCH_REQUIRE_GPIOLIB
891 select GENERIC_CLOCKEVENTS
893 select MIGHT_HAVE_CACHE_L2X0
895 Support for ST-Ericsson's Ux500 architecture
898 bool "STMicroelectronics Nomadik"
899 select ARCH_REQUIRE_GPIOLIB
904 select GENERIC_CLOCKEVENTS
905 select MIGHT_HAVE_CACHE_L2X0
907 select PINCTRL_STN8815
909 Support for the Nomadik platform by ST-Ericsson
913 select ARCH_HAS_CPUFREQ
914 select ARCH_REQUIRE_GPIOLIB
919 select GENERIC_CLOCKEVENTS
922 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
926 select ARCH_HAS_HOLES_MEMORYMODEL
927 select ARCH_REQUIRE_GPIOLIB
929 select GENERIC_ALLOCATOR
930 select GENERIC_CLOCKEVENTS
931 select GENERIC_IRQ_CHIP
933 select NEED_MACH_GPIO_H
937 Support for TI's DaVinci platform.
942 select ARCH_HAS_CPUFREQ
943 select ARCH_HAS_HOLES_MEMORYMODEL
944 select ARCH_REQUIRE_GPIOLIB
946 select GENERIC_CLOCKEVENTS
949 Support for TI's OMAP platform (OMAP1/2/3/4).
952 bool "VIA/WonderMedia 85xx"
953 select ARCH_HAS_CPUFREQ
954 select ARCH_REQUIRE_GPIOLIB
958 select GENERIC_CLOCKEVENTS
963 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
966 bool "Xilinx Zynq ARM Cortex A9 Platform"
971 select GENERIC_CLOCKEVENTS
973 select MIGHT_HAVE_CACHE_L2X0
976 Support for Xilinx Zynq ARM Cortex A9 Platform
979 menu "Multiple platform selection"
980 depends on ARCH_MULTIPLATFORM
982 comment "CPU Core family selection"
985 bool "ARMv4 based platforms (FA526, StrongARM)"
986 depends on !ARCH_MULTI_V6_V7
987 select ARCH_MULTI_V4_V5
989 config ARCH_MULTI_V4T
990 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
991 depends on !ARCH_MULTI_V6_V7
992 select ARCH_MULTI_V4_V5
995 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
996 depends on !ARCH_MULTI_V6_V7
997 select ARCH_MULTI_V4_V5
999 config ARCH_MULTI_V4_V5
1002 config ARCH_MULTI_V6
1003 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
1004 select ARCH_MULTI_V6_V7
1007 config ARCH_MULTI_V7
1008 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1010 select ARCH_MULTI_V6_V7
1011 select ARCH_VEXPRESS
1014 config ARCH_MULTI_V6_V7
1017 config ARCH_MULTI_CPU_AUTO
1018 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1019 select ARCH_MULTI_V5
1024 # This is sorted alphabetically by mach-* pathname. However, plat-*
1025 # Kconfigs may be included either alphabetically (according to the
1026 # plat- suffix) or along side the corresponding mach-* source.
1028 source "arch/arm/mach-mvebu/Kconfig"
1030 source "arch/arm/mach-at91/Kconfig"
1032 source "arch/arm/mach-bcm/Kconfig"
1034 source "arch/arm/mach-clps711x/Kconfig"
1036 source "arch/arm/mach-cns3xxx/Kconfig"
1038 source "arch/arm/mach-davinci/Kconfig"
1040 source "arch/arm/mach-dove/Kconfig"
1042 source "arch/arm/mach-ep93xx/Kconfig"
1044 source "arch/arm/mach-footbridge/Kconfig"
1046 source "arch/arm/mach-gemini/Kconfig"
1048 source "arch/arm/mach-h720x/Kconfig"
1050 source "arch/arm/mach-highbank/Kconfig"
1052 source "arch/arm/mach-integrator/Kconfig"
1054 source "arch/arm/mach-iop32x/Kconfig"
1056 source "arch/arm/mach-iop33x/Kconfig"
1058 source "arch/arm/mach-iop13xx/Kconfig"
1060 source "arch/arm/mach-ixp4xx/Kconfig"
1062 source "arch/arm/mach-kirkwood/Kconfig"
1064 source "arch/arm/mach-ks8695/Kconfig"
1066 source "arch/arm/mach-msm/Kconfig"
1068 source "arch/arm/mach-mv78xx0/Kconfig"
1070 source "arch/arm/mach-imx/Kconfig"
1072 source "arch/arm/mach-mxs/Kconfig"
1074 source "arch/arm/mach-netx/Kconfig"
1076 source "arch/arm/mach-nomadik/Kconfig"
1077 source "arch/arm/plat-nomadik/Kconfig"
1079 source "arch/arm/plat-omap/Kconfig"
1081 source "arch/arm/mach-omap1/Kconfig"
1083 source "arch/arm/mach-omap2/Kconfig"
1085 source "arch/arm/mach-orion5x/Kconfig"
1087 source "arch/arm/mach-picoxcell/Kconfig"
1089 source "arch/arm/mach-pxa/Kconfig"
1090 source "arch/arm/plat-pxa/Kconfig"
1092 source "arch/arm/mach-mmp/Kconfig"
1094 source "arch/arm/mach-realview/Kconfig"
1096 source "arch/arm/mach-sa1100/Kconfig"
1098 source "arch/arm/plat-samsung/Kconfig"
1099 source "arch/arm/plat-s3c24xx/Kconfig"
1101 source "arch/arm/mach-socfpga/Kconfig"
1103 source "arch/arm/plat-spear/Kconfig"
1105 source "arch/arm/mach-s3c24xx/Kconfig"
1107 source "arch/arm/mach-s3c2412/Kconfig"
1108 source "arch/arm/mach-s3c2440/Kconfig"
1112 source "arch/arm/mach-s3c64xx/Kconfig"
1115 source "arch/arm/mach-s5p64x0/Kconfig"
1117 source "arch/arm/mach-s5pc100/Kconfig"
1119 source "arch/arm/mach-s5pv210/Kconfig"
1121 source "arch/arm/mach-exynos/Kconfig"
1123 source "arch/arm/mach-shmobile/Kconfig"
1125 source "arch/arm/mach-sunxi/Kconfig"
1127 source "arch/arm/mach-prima2/Kconfig"
1129 source "arch/arm/mach-tegra/Kconfig"
1131 source "arch/arm/mach-u300/Kconfig"
1133 source "arch/arm/mach-ux500/Kconfig"
1135 source "arch/arm/mach-versatile/Kconfig"
1137 source "arch/arm/mach-vexpress/Kconfig"
1138 source "arch/arm/plat-versatile/Kconfig"
1140 source "arch/arm/mach-w90x900/Kconfig"
1142 # Definitions to make life easier
1148 select GENERIC_CLOCKEVENTS
1154 select GENERIC_IRQ_CHIP
1157 config PLAT_ORION_LEGACY
1164 config PLAT_VERSATILE
1167 config ARM_TIMER_SP804
1170 select HAVE_SCHED_CLOCK
1172 source arch/arm/mm/Kconfig
1176 default 16 if ARCH_EP93XX
1180 bool "Enable iWMMXt support"
1181 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1182 default y if PXA27x || PXA3xx || ARCH_MMP
1184 Enable support for iWMMXt context switching at run time if
1185 running on a CPU that supports it.
1189 depends on CPU_XSCALE
1192 config MULTI_IRQ_HANDLER
1195 Allow each machine to specify it's own IRQ handler at run time.
1198 source "arch/arm/Kconfig-nommu"
1201 config ARM_ERRATA_326103
1202 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1205 Executing a SWP instruction to read-only memory does not set bit 11
1206 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1207 treat the access as a read, preventing a COW from occurring and
1208 causing the faulting task to livelock.
1210 config ARM_ERRATA_411920
1211 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1212 depends on CPU_V6 || CPU_V6K
1214 Invalidation of the Instruction Cache operation can
1215 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1216 It does not affect the MPCore. This option enables the ARM Ltd.
1217 recommended workaround.
1219 config ARM_ERRATA_430973
1220 bool "ARM errata: Stale prediction on replaced interworking branch"
1223 This option enables the workaround for the 430973 Cortex-A8
1224 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1225 interworking branch is replaced with another code sequence at the
1226 same virtual address, whether due to self-modifying code or virtual
1227 to physical address re-mapping, Cortex-A8 does not recover from the
1228 stale interworking branch prediction. This results in Cortex-A8
1229 executing the new code sequence in the incorrect ARM or Thumb state.
1230 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1231 and also flushes the branch target cache at every context switch.
1232 Note that setting specific bits in the ACTLR register may not be
1233 available in non-secure mode.
1235 config ARM_ERRATA_458693
1236 bool "ARM errata: Processor deadlock when a false hazard is created"
1239 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1240 erratum. For very specific sequences of memory operations, it is
1241 possible for a hazard condition intended for a cache line to instead
1242 be incorrectly associated with a different cache line. This false
1243 hazard might then cause a processor deadlock. The workaround enables
1244 the L1 caching of the NEON accesses and disables the PLD instruction
1245 in the ACTLR register. Note that setting specific bits in the ACTLR
1246 register may not be available in non-secure mode.
1248 config ARM_ERRATA_460075
1249 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1252 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1253 erratum. Any asynchronous access to the L2 cache may encounter a
1254 situation in which recent store transactions to the L2 cache are lost
1255 and overwritten with stale memory contents from external memory. The
1256 workaround disables the write-allocate mode for the L2 cache via the
1257 ACTLR register. Note that setting specific bits in the ACTLR register
1258 may not be available in non-secure mode.
1260 config ARM_ERRATA_742230
1261 bool "ARM errata: DMB operation may be faulty"
1262 depends on CPU_V7 && SMP
1264 This option enables the workaround for the 742230 Cortex-A9
1265 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1266 between two write operations may not ensure the correct visibility
1267 ordering of the two writes. This workaround sets a specific bit in
1268 the diagnostic register of the Cortex-A9 which causes the DMB
1269 instruction to behave as a DSB, ensuring the correct behaviour of
1272 config ARM_ERRATA_742231
1273 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1274 depends on CPU_V7 && SMP
1276 This option enables the workaround for the 742231 Cortex-A9
1277 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1278 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1279 accessing some data located in the same cache line, may get corrupted
1280 data due to bad handling of the address hazard when the line gets
1281 replaced from one of the CPUs at the same time as another CPU is
1282 accessing it. This workaround sets specific bits in the diagnostic
1283 register of the Cortex-A9 which reduces the linefill issuing
1284 capabilities of the processor.
1286 config PL310_ERRATA_588369
1287 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1288 depends on CACHE_L2X0
1290 The PL310 L2 cache controller implements three types of Clean &
1291 Invalidate maintenance operations: by Physical Address
1292 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1293 They are architecturally defined to behave as the execution of a
1294 clean operation followed immediately by an invalidate operation,
1295 both performing to the same memory location. This functionality
1296 is not correctly implemented in PL310 as clean lines are not
1297 invalidated as a result of these operations.
1299 config ARM_ERRATA_720789
1300 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1303 This option enables the workaround for the 720789 Cortex-A9 (prior to
1304 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1305 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1306 As a consequence of this erratum, some TLB entries which should be
1307 invalidated are not, resulting in an incoherency in the system page
1308 tables. The workaround changes the TLB flushing routines to invalidate
1309 entries regardless of the ASID.
1311 config PL310_ERRATA_727915
1312 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1313 depends on CACHE_L2X0
1315 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1316 operation (offset 0x7FC). This operation runs in background so that
1317 PL310 can handle normal accesses while it is in progress. Under very
1318 rare circumstances, due to this erratum, write data can be lost when
1319 PL310 treats a cacheable write transaction during a Clean &
1320 Invalidate by Way operation.
1322 config ARM_ERRATA_743622
1323 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1326 This option enables the workaround for the 743622 Cortex-A9
1327 (r2p*) erratum. Under very rare conditions, a faulty
1328 optimisation in the Cortex-A9 Store Buffer may lead to data
1329 corruption. This workaround sets a specific bit in the diagnostic
1330 register of the Cortex-A9 which disables the Store Buffer
1331 optimisation, preventing the defect from occurring. This has no
1332 visible impact on the overall performance or power consumption of the
1335 config ARM_ERRATA_751472
1336 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1339 This option enables the workaround for the 751472 Cortex-A9 (prior
1340 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1341 completion of a following broadcasted operation if the second
1342 operation is received by a CPU before the ICIALLUIS has completed,
1343 potentially leading to corrupted entries in the cache or TLB.
1345 config PL310_ERRATA_753970
1346 bool "PL310 errata: cache sync operation may be faulty"
1347 depends on CACHE_PL310
1349 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1351 Under some condition the effect of cache sync operation on
1352 the store buffer still remains when the operation completes.
1353 This means that the store buffer is always asked to drain and
1354 this prevents it from merging any further writes. The workaround
1355 is to replace the normal offset of cache sync operation (0x730)
1356 by another offset targeting an unmapped PL310 register 0x740.
1357 This has the same effect as the cache sync operation: store buffer
1358 drain and waiting for all buffers empty.
1360 config ARM_ERRATA_754322
1361 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1364 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1365 r3p*) erratum. A speculative memory access may cause a page table walk
1366 which starts prior to an ASID switch but completes afterwards. This
1367 can populate the micro-TLB with a stale entry which may be hit with
1368 the new ASID. This workaround places two dsb instructions in the mm
1369 switching code so that no page table walks can cross the ASID switch.
1371 config ARM_ERRATA_754327
1372 bool "ARM errata: no automatic Store Buffer drain"
1373 depends on CPU_V7 && SMP
1375 This option enables the workaround for the 754327 Cortex-A9 (prior to
1376 r2p0) erratum. The Store Buffer does not have any automatic draining
1377 mechanism and therefore a livelock may occur if an external agent
1378 continuously polls a memory location waiting to observe an update.
1379 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1380 written polling loops from denying visibility of updates to memory.
1382 config ARM_ERRATA_364296
1383 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1384 depends on CPU_V6 && !SMP
1386 This options enables the workaround for the 364296 ARM1136
1387 r0p2 erratum (possible cache data corruption with
1388 hit-under-miss enabled). It sets the undocumented bit 31 in
1389 the auxiliary control register and the FI bit in the control
1390 register, thus disabling hit-under-miss without putting the
1391 processor into full low interrupt latency mode. ARM11MPCore
1394 config ARM_ERRATA_764369
1395 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1396 depends on CPU_V7 && SMP
1398 This option enables the workaround for erratum 764369
1399 affecting Cortex-A9 MPCore with two or more processors (all
1400 current revisions). Under certain timing circumstances, a data
1401 cache line maintenance operation by MVA targeting an Inner
1402 Shareable memory region may fail to proceed up to either the
1403 Point of Coherency or to the Point of Unification of the
1404 system. This workaround adds a DSB instruction before the
1405 relevant cache maintenance functions and sets a specific bit
1406 in the diagnostic control register of the SCU.
1408 config PL310_ERRATA_769419
1409 bool "PL310 errata: no automatic Store Buffer drain"
1410 depends on CACHE_L2X0
1412 On revisions of the PL310 prior to r3p2, the Store Buffer does
1413 not automatically drain. This can cause normal, non-cacheable
1414 writes to be retained when the memory system is idle, leading
1415 to suboptimal I/O performance for drivers using coherent DMA.
1416 This option adds a write barrier to the cpu_idle loop so that,
1417 on systems with an outer cache, the store buffer is drained
1420 config ARM_ERRATA_775420
1421 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1424 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1425 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1426 operation aborts with MMU exception, it might cause the processor
1427 to deadlock. This workaround puts DSB before executing ISB if
1428 an abort may occur on cache maintenance.
1432 source "arch/arm/common/Kconfig"
1442 Find out whether you have ISA slots on your motherboard. ISA is the
1443 name of a bus system, i.e. the way the CPU talks to the other stuff
1444 inside your box. Other bus systems are PCI, EISA, MicroChannel
1445 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1446 newer boards don't support it. If you have ISA, say Y, otherwise N.
1448 # Select ISA DMA controller support
1453 # Select ISA DMA interface
1458 bool "PCI support" if MIGHT_HAVE_PCI
1460 Find out whether you have a PCI motherboard. PCI is the name of a
1461 bus system, i.e. the way the CPU talks to the other stuff inside
1462 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1463 VESA. If you have PCI, say Y, otherwise N.
1469 config PCI_NANOENGINE
1470 bool "BSE nanoEngine PCI support"
1471 depends on SA1100_NANOENGINE
1473 Enable PCI on the BSE nanoEngine board.
1478 # Select the host bridge type
1479 config PCI_HOST_VIA82C505
1481 depends on PCI && ARCH_SHARK
1484 config PCI_HOST_ITE8152
1486 depends on PCI && MACH_ARMCORE
1490 source "drivers/pci/Kconfig"
1492 source "drivers/pcmcia/Kconfig"
1496 menu "Kernel Features"
1501 This option should be selected by machines which have an SMP-
1504 The only effect of this option is to make the SMP-related
1505 options available to the user for configuration.
1508 bool "Symmetric Multi-Processing"
1509 depends on CPU_V6K || CPU_V7
1510 depends on GENERIC_CLOCKEVENTS
1513 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1514 select USE_GENERIC_SMP_HELPERS
1516 This enables support for systems with more than one CPU. If you have
1517 a system with only one CPU, like most personal computers, say N. If
1518 you have a system with more than one CPU, say Y.
1520 If you say N here, the kernel will run on single and multiprocessor
1521 machines, but will use only one CPU of a multiprocessor machine. If
1522 you say Y here, the kernel will run on many, but not all, single
1523 processor machines. On a single processor machine, the kernel will
1524 run faster if you say N here.
1526 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1527 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1528 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1530 If you don't know what to do here, say N.
1533 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1534 depends on EXPERIMENTAL
1535 depends on SMP && !XIP_KERNEL
1538 SMP kernels contain instructions which fail on non-SMP processors.
1539 Enabling this option allows the kernel to modify itself to make
1540 these instructions safe. Disabling it allows about 1K of space
1543 If you don't know what to do here, say Y.
1545 config ARM_CPU_TOPOLOGY
1546 bool "Support cpu topology definition"
1547 depends on SMP && CPU_V7
1550 Support ARM cpu topology definition. The MPIDR register defines
1551 affinity between processors which is then used to describe the cpu
1552 topology of an ARM System.
1555 bool "Multi-core scheduler support"
1556 depends on ARM_CPU_TOPOLOGY
1558 Multi-core scheduler support improves the CPU scheduler's decision
1559 making when dealing with multi-core CPU chips at a cost of slightly
1560 increased overhead in some places. If unsure say N here.
1563 bool "SMT scheduler support"
1564 depends on ARM_CPU_TOPOLOGY
1566 Improves the CPU scheduler's decision making when dealing with
1567 MultiThreading at a cost of slightly increased overhead in some
1568 places. If unsure say N here.
1573 This option enables support for the ARM system coherency unit
1575 config ARM_ARCH_TIMER
1576 bool "Architected timer support"
1579 This option enables support for the ARM architected timer
1585 This options enables support for the ARM timer and watchdog unit
1588 prompt "Memory split"
1591 Select the desired split between kernel and user memory.
1593 If you are not absolutely sure what you are doing, leave this
1597 bool "3G/1G user/kernel split"
1599 bool "2G/2G user/kernel split"
1601 bool "1G/3G user/kernel split"
1606 default 0x40000000 if VMSPLIT_1G
1607 default 0x80000000 if VMSPLIT_2G
1611 int "Maximum number of CPUs (2-32)"
1617 bool "Support for hot-pluggable CPUs"
1618 depends on SMP && HOTPLUG
1620 Say Y here to experiment with turning CPUs off and on. CPUs
1621 can be controlled through /sys/devices/system/cpu.
1624 bool "Use local timer interrupts"
1627 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1629 Enable support for local timers on SMP platforms, rather then the
1630 legacy IPI broadcast method. Local timers allows the system
1631 accounting to be spread across the timer interval, preventing a
1632 "thundering herd" at every timer tick.
1636 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1637 default 355 if ARCH_U8500
1638 default 264 if MACH_H4700
1639 default 512 if SOC_OMAP5
1640 default 288 if ARCH_VT8500
1643 Maximum number of GPIOs in the system.
1645 If unsure, leave the default value.
1647 source kernel/Kconfig.preempt
1651 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1652 ARCH_S5PV210 || ARCH_EXYNOS4
1653 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1654 default AT91_TIMER_HZ if ARCH_AT91
1655 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1658 config THUMB2_KERNEL
1659 bool "Compile the kernel in Thumb-2 mode"
1660 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1662 select ARM_ASM_UNIFIED
1665 By enabling this option, the kernel will be compiled in
1666 Thumb-2 mode. A compiler/assembler that understand the unified
1667 ARM-Thumb syntax is needed.
1671 config THUMB2_AVOID_R_ARM_THM_JUMP11
1672 bool "Work around buggy Thumb-2 short branch relocations in gas"
1673 depends on THUMB2_KERNEL && MODULES
1676 Various binutils versions can resolve Thumb-2 branches to
1677 locally-defined, preemptible global symbols as short-range "b.n"
1678 branch instructions.
1680 This is a problem, because there's no guarantee the final
1681 destination of the symbol, or any candidate locations for a
1682 trampoline, are within range of the branch. For this reason, the
1683 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1684 relocation in modules at all, and it makes little sense to add
1687 The symptom is that the kernel fails with an "unsupported
1688 relocation" error when loading some modules.
1690 Until fixed tools are available, passing
1691 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1692 code which hits this problem, at the cost of a bit of extra runtime
1693 stack usage in some cases.
1695 The problem is described in more detail at:
1696 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1698 Only Thumb-2 kernels are affected.
1700 Unless you are sure your tools don't have this problem, say Y.
1702 config ARM_ASM_UNIFIED
1706 bool "Use the ARM EABI to compile the kernel"
1708 This option allows for the kernel to be compiled using the latest
1709 ARM ABI (aka EABI). This is only useful if you are using a user
1710 space environment that is also compiled with EABI.
1712 Since there are major incompatibilities between the legacy ABI and
1713 EABI, especially with regard to structure member alignment, this
1714 option also changes the kernel syscall calling convention to
1715 disambiguate both ABIs and allow for backward compatibility support
1716 (selected with CONFIG_OABI_COMPAT).
1718 To use this you need GCC version 4.0.0 or later.
1721 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1722 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1725 This option preserves the old syscall interface along with the
1726 new (ARM EABI) one. It also provides a compatibility layer to
1727 intercept syscalls that have structure arguments which layout
1728 in memory differs between the legacy ABI and the new ARM EABI
1729 (only for non "thumb" binaries). This option adds a tiny
1730 overhead to all syscalls and produces a slightly larger kernel.
1731 If you know you'll be using only pure EABI user space then you
1732 can say N here. If this option is not selected and you attempt
1733 to execute a legacy ABI binary then the result will be
1734 UNPREDICTABLE (in fact it can be predicted that it won't work
1735 at all). If in doubt say Y.
1737 config ARCH_HAS_HOLES_MEMORYMODEL
1740 config ARCH_SPARSEMEM_ENABLE
1743 config ARCH_SPARSEMEM_DEFAULT
1744 def_bool ARCH_SPARSEMEM_ENABLE
1746 config ARCH_SELECT_MEMORY_MODEL
1747 def_bool ARCH_SPARSEMEM_ENABLE
1749 config HAVE_ARCH_PFN_VALID
1750 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1753 bool "High Memory Support"
1756 The address space of ARM processors is only 4 Gigabytes large
1757 and it has to accommodate user address space, kernel address
1758 space as well as some memory mapped IO. That means that, if you
1759 have a large amount of physical memory and/or IO, not all of the
1760 memory can be "permanently mapped" by the kernel. The physical
1761 memory that is not permanently mapped is called "high memory".
1763 Depending on the selected kernel/user memory split, minimum
1764 vmalloc space and actual amount of RAM, you may not need this
1765 option which should result in a slightly faster kernel.
1770 bool "Allocate 2nd-level pagetables from highmem"
1773 config HW_PERF_EVENTS
1774 bool "Enable hardware performance counter support for perf events"
1775 depends on PERF_EVENTS
1778 Enable hardware performance counter support for perf events. If
1779 disabled, perf events will use software events only.
1783 config FORCE_MAX_ZONEORDER
1784 int "Maximum zone order" if ARCH_SHMOBILE
1785 range 11 64 if ARCH_SHMOBILE
1786 default "12" if SOC_AM33XX
1787 default "9" if SA1111
1790 The kernel memory allocator divides physically contiguous memory
1791 blocks into "zones", where each zone is a power of two number of
1792 pages. This option selects the largest power of two that the kernel
1793 keeps in the memory allocator. If you need to allocate very large
1794 blocks of physically contiguous memory, then you may need to
1795 increase this value.
1797 This config option is actually maximum order plus one. For example,
1798 a value of 11 means that the largest free memory block is 2^10 pages.
1800 config ALIGNMENT_TRAP
1802 depends on CPU_CP15_MMU
1803 default y if !ARCH_EBSA110
1804 select HAVE_PROC_CPU if PROC_FS
1806 ARM processors cannot fetch/store information which is not
1807 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1808 address divisible by 4. On 32-bit ARM processors, these non-aligned
1809 fetch/store instructions will be emulated in software if you say
1810 here, which has a severe performance impact. This is necessary for
1811 correct operation of some network protocols. With an IP-only
1812 configuration it is safe to say N, otherwise say Y.
1814 config UACCESS_WITH_MEMCPY
1815 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1817 default y if CPU_FEROCEON
1819 Implement faster copy_to_user and clear_user methods for CPU
1820 cores where a 8-word STM instruction give significantly higher
1821 memory write throughput than a sequence of individual 32bit stores.
1823 A possible side effect is a slight increase in scheduling latency
1824 between threads sharing the same address space if they invoke
1825 such copy operations with large buffers.
1827 However, if the CPU data cache is using a write-allocate mode,
1828 this option is unlikely to provide any performance gain.
1832 prompt "Enable seccomp to safely compute untrusted bytecode"
1834 This kernel feature is useful for number crunching applications
1835 that may need to compute untrusted bytecode during their
1836 execution. By using pipes or other transports made available to
1837 the process as file descriptors supporting the read/write
1838 syscalls, it's possible to isolate those applications in
1839 their own address space using seccomp. Once seccomp is
1840 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1841 and the task is only allowed to execute a few safe syscalls
1842 defined by each seccomp mode.
1844 config CC_STACKPROTECTOR
1845 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1846 depends on EXPERIMENTAL
1848 This option turns on the -fstack-protector GCC feature. This
1849 feature puts, at the beginning of functions, a canary value on
1850 the stack just before the return address, and validates
1851 the value just before actually returning. Stack based buffer
1852 overflows (that need to overwrite this return address) now also
1853 overwrite the canary, which gets detected and the attack is then
1854 neutralized via a kernel panic.
1855 This feature requires gcc version 4.2 or above.
1862 bool "Xen guest support on ARM (EXPERIMENTAL)"
1863 depends on EXPERIMENTAL && ARM && OF
1864 depends on CPU_V7 && !CPU_V6
1866 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1873 bool "Flattened Device Tree support"
1876 select OF_EARLY_FLATTREE
1878 Include support for flattened device tree machine descriptions.
1881 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1884 This is the traditional way of passing data to the kernel at boot
1885 time. If you are solely relying on the flattened device tree (or
1886 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1887 to remove ATAGS support from your kernel binary. If unsure,
1890 config DEPRECATED_PARAM_STRUCT
1891 bool "Provide old way to pass kernel parameters"
1894 This was deprecated in 2001 and announced to live on for 5 years.
1895 Some old boot loaders still use this way.
1897 # Compressed boot loader in ROM. Yes, we really want to ask about
1898 # TEXT and BSS so we preserve their values in the config files.
1899 config ZBOOT_ROM_TEXT
1900 hex "Compressed ROM boot loader base address"
1903 The physical address at which the ROM-able zImage is to be
1904 placed in the target. Platforms which normally make use of
1905 ROM-able zImage formats normally set this to a suitable
1906 value in their defconfig file.
1908 If ZBOOT_ROM is not enabled, this has no effect.
1910 config ZBOOT_ROM_BSS
1911 hex "Compressed ROM boot loader BSS address"
1914 The base address of an area of read/write memory in the target
1915 for the ROM-able zImage which must be available while the
1916 decompressor is running. It must be large enough to hold the
1917 entire decompressed kernel plus an additional 128 KiB.
1918 Platforms which normally make use of ROM-able zImage formats
1919 normally set this to a suitable value in their defconfig file.
1921 If ZBOOT_ROM is not enabled, this has no effect.
1924 bool "Compressed boot loader in ROM/flash"
1925 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1927 Say Y here if you intend to execute your compressed kernel image
1928 (zImage) directly from ROM or flash. If unsure, say N.
1931 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1932 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1933 default ZBOOT_ROM_NONE
1935 Include experimental SD/MMC loading code in the ROM-able zImage.
1936 With this enabled it is possible to write the ROM-able zImage
1937 kernel image to an MMC or SD card and boot the kernel straight
1938 from the reset vector. At reset the processor Mask ROM will load
1939 the first part of the ROM-able zImage which in turn loads the
1940 rest the kernel image to RAM.
1942 config ZBOOT_ROM_NONE
1943 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1945 Do not load image from SD or MMC
1947 config ZBOOT_ROM_MMCIF
1948 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1950 Load image from MMCIF hardware block.
1952 config ZBOOT_ROM_SH_MOBILE_SDHI
1953 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1955 Load image from SDHI hardware block
1959 config ARM_APPENDED_DTB
1960 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1961 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1963 With this option, the boot code will look for a device tree binary
1964 (DTB) appended to zImage
1965 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1967 This is meant as a backward compatibility convenience for those
1968 systems with a bootloader that can't be upgraded to accommodate
1969 the documented boot protocol using a device tree.
1971 Beware that there is very little in terms of protection against
1972 this option being confused by leftover garbage in memory that might
1973 look like a DTB header after a reboot if no actual DTB is appended
1974 to zImage. Do not leave this option active in a production kernel
1975 if you don't intend to always append a DTB. Proper passing of the
1976 location into r2 of a bootloader provided DTB is always preferable
1979 config ARM_ATAG_DTB_COMPAT
1980 bool "Supplement the appended DTB with traditional ATAG information"
1981 depends on ARM_APPENDED_DTB
1983 Some old bootloaders can't be updated to a DTB capable one, yet
1984 they provide ATAGs with memory configuration, the ramdisk address,
1985 the kernel cmdline string, etc. Such information is dynamically
1986 provided by the bootloader and can't always be stored in a static
1987 DTB. To allow a device tree enabled kernel to be used with such
1988 bootloaders, this option allows zImage to extract the information
1989 from the ATAG list and store it at run time into the appended DTB.
1992 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1993 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1995 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1996 bool "Use bootloader kernel arguments if available"
1998 Uses the command-line options passed by the boot loader instead of
1999 the device tree bootargs property. If the boot loader doesn't provide
2000 any, the device tree bootargs property will be used.
2002 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2003 bool "Extend with bootloader kernel arguments"
2005 The command-line arguments provided by the boot loader will be
2006 appended to the the device tree bootargs property.
2011 string "Default kernel command string"
2014 On some architectures (EBSA110 and CATS), there is currently no way
2015 for the boot loader to pass arguments to the kernel. For these
2016 architectures, you should supply some command-line options at build
2017 time by entering them here. As a minimum, you should specify the
2018 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2021 prompt "Kernel command line type" if CMDLINE != ""
2022 default CMDLINE_FROM_BOOTLOADER
2025 config CMDLINE_FROM_BOOTLOADER
2026 bool "Use bootloader kernel arguments if available"
2028 Uses the command-line options passed by the boot loader. If
2029 the boot loader doesn't provide any, the default kernel command
2030 string provided in CMDLINE will be used.
2032 config CMDLINE_EXTEND
2033 bool "Extend bootloader kernel arguments"
2035 The command-line arguments provided by the boot loader will be
2036 appended to the default kernel command string.
2038 config CMDLINE_FORCE
2039 bool "Always use the default kernel command string"
2041 Always use the default kernel command string, even if the boot
2042 loader passes other arguments to the kernel.
2043 This is useful if you cannot or don't want to change the
2044 command-line options your boot loader passes to the kernel.
2048 bool "Kernel Execute-In-Place from ROM"
2049 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2051 Execute-In-Place allows the kernel to run from non-volatile storage
2052 directly addressable by the CPU, such as NOR flash. This saves RAM
2053 space since the text section of the kernel is not loaded from flash
2054 to RAM. Read-write sections, such as the data section and stack,
2055 are still copied to RAM. The XIP kernel is not compressed since
2056 it has to run directly from flash, so it will take more space to
2057 store it. The flash address used to link the kernel object files,
2058 and for storing it, is configuration dependent. Therefore, if you
2059 say Y here, you must know the proper physical address where to
2060 store the kernel image depending on your own flash memory usage.
2062 Also note that the make target becomes "make xipImage" rather than
2063 "make zImage" or "make Image". The final kernel binary to put in
2064 ROM memory will be arch/arm/boot/xipImage.
2068 config XIP_PHYS_ADDR
2069 hex "XIP Kernel Physical Location"
2070 depends on XIP_KERNEL
2071 default "0x00080000"
2073 This is the physical address in your flash memory the kernel will
2074 be linked for and stored to. This address is dependent on your
2078 bool "Kexec system call (EXPERIMENTAL)"
2079 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2081 kexec is a system call that implements the ability to shutdown your
2082 current kernel, and to start another kernel. It is like a reboot
2083 but it is independent of the system firmware. And like a reboot
2084 you can start any kernel with it, not just Linux.
2086 It is an ongoing process to be certain the hardware in a machine
2087 is properly shutdown, so do not be surprised if this code does not
2088 initially work for you. It may help to enable device hotplugging
2092 bool "Export atags in procfs"
2093 depends on ATAGS && KEXEC
2096 Should the atags used to boot the kernel be exported in an "atags"
2097 file in procfs. Useful with kexec.
2100 bool "Build kdump crash kernel (EXPERIMENTAL)"
2101 depends on EXPERIMENTAL
2103 Generate crash dump after being started by kexec. This should
2104 be normally only set in special crash dump kernels which are
2105 loaded in the main kernel with kexec-tools into a specially
2106 reserved region and then later executed after a crash by
2107 kdump/kexec. The crash dump kernel must be compiled to a
2108 memory address not used by the main kernel
2110 For more details see Documentation/kdump/kdump.txt
2112 config AUTO_ZRELADDR
2113 bool "Auto calculation of the decompressed kernel image address"
2114 depends on !ZBOOT_ROM && !ARCH_U300
2116 ZRELADDR is the physical address where the decompressed kernel
2117 image will be placed. If AUTO_ZRELADDR is selected, the address
2118 will be determined at run-time by masking the current IP with
2119 0xf8000000. This assumes the zImage being placed in the first 128MB
2120 from start of memory.
2124 menu "CPU Power Management"
2128 source "drivers/cpufreq/Kconfig"
2131 tristate "CPUfreq driver for i.MX CPUs"
2132 depends on ARCH_MXC && CPU_FREQ
2133 select CPU_FREQ_TABLE
2135 This enables the CPUfreq driver for i.MX CPUs.
2137 config CPU_FREQ_SA1100
2140 config CPU_FREQ_SA1110
2143 config CPU_FREQ_INTEGRATOR
2144 tristate "CPUfreq driver for ARM Integrator CPUs"
2145 depends on ARCH_INTEGRATOR && CPU_FREQ
2148 This enables the CPUfreq driver for ARM Integrator CPUs.
2150 For details, take a look at <file:Documentation/cpu-freq>.
2156 depends on CPU_FREQ && ARCH_PXA && PXA25x
2158 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2159 select CPU_FREQ_TABLE
2164 Internal configuration node for common cpufreq on Samsung SoC
2166 config CPU_FREQ_S3C24XX
2167 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2168 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2171 This enables the CPUfreq driver for the Samsung S3C24XX family
2174 For details, take a look at <file:Documentation/cpu-freq>.
2178 config CPU_FREQ_S3C24XX_PLL
2179 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2180 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2182 Compile in support for changing the PLL frequency from the
2183 S3C24XX series CPUfreq driver. The PLL takes time to settle
2184 after a frequency change, so by default it is not enabled.
2186 This also means that the PLL tables for the selected CPU(s) will
2187 be built which may increase the size of the kernel image.
2189 config CPU_FREQ_S3C24XX_DEBUG
2190 bool "Debug CPUfreq Samsung driver core"
2191 depends on CPU_FREQ_S3C24XX
2193 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2195 config CPU_FREQ_S3C24XX_IODEBUG
2196 bool "Debug CPUfreq Samsung driver IO timing"
2197 depends on CPU_FREQ_S3C24XX
2199 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2201 config CPU_FREQ_S3C24XX_DEBUGFS
2202 bool "Export debugfs for CPUFreq"
2203 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2205 Export status information via debugfs.
2209 source "drivers/cpuidle/Kconfig"
2213 menu "Floating point emulation"
2215 comment "At least one emulation must be selected"
2218 bool "NWFPE math emulation"
2219 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2221 Say Y to include the NWFPE floating point emulator in the kernel.
2222 This is necessary to run most binaries. Linux does not currently
2223 support floating point hardware so you need to say Y here even if
2224 your machine has an FPA or floating point co-processor podule.
2226 You may say N here if you are going to load the Acorn FPEmulator
2227 early in the bootup.
2230 bool "Support extended precision"
2231 depends on FPE_NWFPE
2233 Say Y to include 80-bit support in the kernel floating-point
2234 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2235 Note that gcc does not generate 80-bit operations by default,
2236 so in most cases this option only enlarges the size of the
2237 floating point emulator without any good reason.
2239 You almost surely want to say N here.
2242 bool "FastFPE math emulation (EXPERIMENTAL)"
2243 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2245 Say Y here to include the FAST floating point emulator in the kernel.
2246 This is an experimental much faster emulator which now also has full
2247 precision for the mantissa. It does not support any exceptions.
2248 It is very simple, and approximately 3-6 times faster than NWFPE.
2250 It should be sufficient for most programs. It may be not suitable
2251 for scientific calculations, but you have to check this for yourself.
2252 If you do not feel you need a faster FP emulation you should better
2256 bool "VFP-format floating point maths"
2257 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2259 Say Y to include VFP support code in the kernel. This is needed
2260 if your hardware includes a VFP unit.
2262 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2263 release notes and additional status information.
2265 Say N if your target does not have VFP hardware.
2273 bool "Advanced SIMD (NEON) Extension support"
2274 depends on VFPv3 && CPU_V7
2276 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2281 menu "Userspace binary formats"
2283 source "fs/Kconfig.binfmt"
2286 tristate "RISC OS personality"
2289 Say Y here to include the kernel code necessary if you want to run
2290 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2291 experimental; if this sounds frightening, say N and sleep in peace.
2292 You can also say M here to compile this support as a module (which
2293 will be called arthur).
2297 menu "Power management options"
2299 source "kernel/power/Kconfig"
2301 config ARCH_SUSPEND_POSSIBLE
2302 depends on !ARCH_S5PC100
2303 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2304 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2307 config ARM_CPU_SUSPEND
2312 source "net/Kconfig"
2314 source "drivers/Kconfig"
2318 source "arch/arm/Kconfig.debug"
2320 source "security/Kconfig"
2322 source "crypto/Kconfig"
2324 source "lib/Kconfig"