arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 #define MAX_SOURCES 400
  16
  17 / {
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         compatible = "ti,dra7xx";
  22         interrupt-parent = <&crossbar_mpu>;
  23
  24         aliases {
  25                 i2c0 = &i2c1;
  26                 i2c1 = &i2c2;
  27                 i2c2 = &i2c3;
  28                 i2c3 = &i2c4;
  29                 i2c4 = &i2c5;
  30                 serial0 = &uart1;
  31                 serial1 = &uart2;
  32                 serial2 = &uart3;
  33                 serial3 = &uart4;
  34                 serial4 = &uart5;
  35                 serial5 = &uart6;
  36                 serial6 = &uart7;
  37                 serial7 = &uart8;
  38                 serial8 = &uart9;
  39                 serial9 = &uart10;
  40                 ethernet0 = &cpsw_emac0;
  41                 ethernet1 = &cpsw_emac1;
  42                 d_can0 = &dcan1;
  43                 d_can1 = &dcan2;
  44         };
  45
  46         timer {
  47                 compatible = "arm,armv7-timer";
  48                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  49                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  52                 interrupt-parent = <&gic>;
  53         };
  54
  55         gic: interrupt-controller@48211000 {
  56                 compatible = "arm,cortex-a15-gic";
  57                 interrupt-controller;
  58                 #interrupt-cells = <3>;
  59                 reg = <0x48211000 0x1000>,
  60                       <0x48212000 0x1000>,
  61                       <0x48214000 0x2000>,
  62                       <0x48216000 0x2000>;
  63                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  64                 interrupt-parent = <&gic>;
  65         };
  66
  67         wakeupgen: interrupt-controller@48281000 {
  68                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  69                 interrupt-controller;
  70                 #interrupt-cells = <3>;
  71                 reg = <0x48281000 0x1000>;
  72                 interrupt-parent = <&gic>;
  73         };
  74
  75         /*
  76          * The soc node represents the soc top level view. It is used for IPs
  77          * that are not memory mapped in the MPU view or for the MPU itself.
  78          */
  79         soc {
  80                 compatible = "ti,omap-infra";
  81                 mpu {
  82                         compatible = "ti,omap5-mpu";
  83                         ti,hwmods = "mpu";
  84                 };
  85         };
  86
  87         /*
  88          * XXX: Use a flat representation of the SOC interconnect.
  89          * The real OMAP interconnect network is quite complex.
  90          * Since it will not bring real advantage to represent that in DT for
  91          * the moment, just use a fake OCP bus entry to represent the whole bus
  92          * hierarchy.
  93          */
  94         ocp {
  95                 compatible = "ti,dra7-l3-noc", "simple-bus";
  96                 #address-cells = <1>;
  97                 #size-cells = <1>;
  98                 ranges;
  99                 ti,hwmods = "l3_main_1", "l3_main_2";
 100                 reg = <0x44000000 0x1000000>,
 101                       <0x45000000 0x1000>;
 102                 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 103                                       <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 104
 105                 l4_cfg: l4@4a000000 {
 106                         compatible = "ti,dra7-l4-cfg", "simple-bus";
 107                         #address-cells = <1>;
 108                         #size-cells = <1>;
 109                         ranges = <0 0x4a000000 0x22c000>;
 110
 111                         scm: scm@2000 {
 112                                 compatible = "ti,dra7-scm-core", "simple-bus";
 113                                 reg = <0x2000 0x2000>;
 114                                 #address-cells = <1>;
 115                                 #size-cells = <1>;
 116                                 ranges = <0 0x2000 0x2000>;
 117
 118                                 scm_conf: scm_conf@0 {
 119                                         compatible = "syscon", "simple-bus";
 120                                         reg = <0x0 0x1400>;
 121                                         #address-cells = <1>;
 122                                         #size-cells = <1>;
 123
 124                                         pbias_regulator: pbias_regulator {
 125                                                 compatible = "ti,pbias-omap";
 126                                                 reg = <0xe00 0x4>;
 127                                                 syscon = <&scm_conf>;
 128                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 129                                                         regulator-name = "pbias_mmc_omap5";
 130                                                         regulator-min-microvolt = <1800000>;
 131                                                         regulator-max-microvolt = <3000000>;
 132                                                 };
 133                                         };
 134
 135                                         scm_conf_clocks: clocks {
 136                                                 #address-cells = <1>;
 137                                                 #size-cells = <0>;
 138                                         };
 139                                 };
 140
 141                                 dra7_pmx_core: pinmux@1400 {
 142                                         compatible = "ti,dra7-padconf",
 143                                                      "pinctrl-single";
 144                                         reg = <0x1400 0x0468>;
 145                                         #address-cells = <1>;
 146                                         #size-cells = <0>;
 147                                         #interrupt-cells = <1>;
 148                                         interrupt-controller;
 149                                         pinctrl-single,register-width = <32>;
 150                                         pinctrl-single,function-mask = <0x3fffffff>;
 151                                 };
 152
 153                                 scm_conf1: scm_conf@1c04 {
 154                                         compatible = "syscon";
 155                                         reg = <0x1c04 0x0020>;
 156                                 };
 157                         };
 158
 159                         cm_core_aon: cm_core_aon@5000 {
 160                                 compatible = "ti,dra7-cm-core-aon";
 161                                 reg = <0x5000 0x2000>;
 162
 163                                 cm_core_aon_clocks: clocks {
 164                                         #address-cells = <1>;
 165                                         #size-cells = <0>;
 166                                 };
 167
 168                                 cm_core_aon_clockdomains: clockdomains {
 169                                 };
 170                         };
 171
 172                         cm_core: cm_core@8000 {
 173                                 compatible = "ti,dra7-cm-core";
 174                                 reg = <0x8000 0x3000>;
 175
 176                                 cm_core_clocks: clocks {
 177                                         #address-cells = <1>;
 178                                         #size-cells = <0>;
 179                                 };
 180
 181                                 cm_core_clockdomains: clockdomains {
 182                                 };
 183                         };
 184                 };
 185
 186                 l4_wkup: l4@4ae00000 {
 187                         compatible = "ti,dra7-l4-wkup", "simple-bus";
 188                         #address-cells = <1>;
 189                         #size-cells = <1>;
 190                         ranges = <0 0x4ae00000 0x3f000>;
 191
 192                         counter32k: counter@4000 {
 193                                 compatible = "ti,omap-counter32k";
 194                                 reg = <0x4000 0x40>;
 195                                 ti,hwmods = "counter_32k";
 196                         };
 197
 198                         prm: prm@6000 {
 199                                 compatible = "ti,dra7-prm";
 200                                 reg = <0x6000 0x3000>;
 201                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 202
 203                                 prm_clocks: clocks {
 204                                         #address-cells = <1>;
 205                                         #size-cells = <0>;
 206                                 };
 207
 208                                 prm_clockdomains: clockdomains {
 209                                 };
 210                         };
 211                 };
 212
 213                 axi@0 {
 214                         compatible = "simple-bus";
 215                         #size-cells = <1>;
 216                         #address-cells = <1>;
 217                         ranges = <0x51000000 0x51000000 0x3000
 218                                   0x0        0x20000000 0x10000000>;
 219                         pcie1: pcie@51000000 {
 220                                 compatible = "ti,dra7-pcie";
 221                                 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
 222                                 reg-names = "rc_dbics", "ti_conf", "config";
 223                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 224                                 #address-cells = <3>;
 225                                 #size-cells = <2>;
 226                                 device_type = "pci";
 227                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 228                                           0x82000000 0 0x20013000 0x13000 0 0xffed000>;
 229                                 #interrupt-cells = <1>;
 230                                 num-lanes = <1>;
 231                                 ti,hwmods = "pcie1";
 232                                 phys = <&pcie1_phy>;
 233                                 phy-names = "pcie-phy0";
 234                                 interrupt-map-mask = <0 0 0 7>;
 235                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 236                                                 <0 0 0 2 &pcie1_intc 2>,
 237                                                 <0 0 0 3 &pcie1_intc 3>,
 238                                                 <0 0 0 4 &pcie1_intc 4>;
 239                                 pcie1_intc: interrupt-controller {
 240                                         interrupt-controller;
 241                                         #address-cells = <0>;
 242                                         #interrupt-cells = <1>;
 243                                 };
 244                         };
 245                 };
 246
 247                 axi@1 {
 248                         compatible = "simple-bus";
 249                         #size-cells = <1>;
 250                         #address-cells = <1>;
 251                         ranges = <0x51800000 0x51800000 0x3000
 252                                   0x0        0x30000000 0x10000000>;
 253                         status = "disabled";
 254                         pcie@51000000 {
 255                                 compatible = "ti,dra7-pcie";
 256                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 257                                 reg-names = "rc_dbics", "ti_conf", "config";
 258                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 259                                 #address-cells = <3>;
 260                                 #size-cells = <2>;
 261                                 device_type = "pci";
 262                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 263                                           0x82000000 0 0x30013000 0x13000 0 0xffed000>;
 264                                 #interrupt-cells = <1>;
 265                                 num-lanes = <1>;
 266                                 ti,hwmods = "pcie2";
 267                                 phys = <&pcie2_phy>;
 268                                 phy-names = "pcie-phy0";
 269                                 interrupt-map-mask = <0 0 0 7>;
 270                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 271                                                 <0 0 0 2 &pcie2_intc 2>,
 272                                                 <0 0 0 3 &pcie2_intc 3>,
 273                                                 <0 0 0 4 &pcie2_intc 4>;
 274                                 pcie2_intc: interrupt-controller {
 275                                         interrupt-controller;
 276                                         #address-cells = <0>;
 277                                         #interrupt-cells = <1>;
 278                                 };
 279                         };
 280                 };
 281
 282                 bandgap: bandgap@4a0021e0 {
 283                         reg = <0x4a0021e0 0xc
 284                                 0x4a00232c 0xc
 285                                 0x4a002380 0x2c
 286                                 0x4a0023C0 0x3c
 287                                 0x4a002564 0x8
 288                                 0x4a002574 0x50>;
 289                                 compatible = "ti,dra752-bandgap";
 290                                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 291                                 #thermal-sensor-cells = <1>;
 292                 };
 293
 294                 sdma: dma-controller@4a056000 {
 295                         compatible = "ti,omap4430-sdma";
 296                         reg = <0x4a056000 0x1000>;
 297                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 298                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 299                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 300                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 301                         #dma-cells = <1>;
 302                         dma-channels = <32>;
 303                         dma-requests = <127>;
 304                 };
 305
 306                 sdma_xbar: dma-router@4a002b78 {
 307                         compatible = "ti,dra7-dma-crossbar";
 308                         reg = <0x4a002b78 0xfc>;
 309                         #dma-cells = <1>;
 310                         dma-requests = <205>;
 311                         ti,dma-safe-map = <0>;
 312                         dma-masters = <&sdma>;
 313                 };
 314
 315                 gpio1: gpio@4ae10000 {
 316                         compatible = "ti,omap4-gpio";
 317                         reg = <0x4ae10000 0x200>;
 318                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 319                         ti,hwmods = "gpio1";
 320                         gpio-controller;
 321                         #gpio-cells = <2>;
 322                         interrupt-controller;
 323                         #interrupt-cells = <2>;
 324                 };
 325
 326                 gpio2: gpio@48055000 {
 327                         compatible = "ti,omap4-gpio";
 328                         reg = <0x48055000 0x200>;
 329                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 330                         ti,hwmods = "gpio2";
 331                         gpio-controller;
 332                         #gpio-cells = <2>;
 333                         interrupt-controller;
 334                         #interrupt-cells = <2>;
 335                 };
 336
 337                 gpio3: gpio@48057000 {
 338                         compatible = "ti,omap4-gpio";
 339                         reg = <0x48057000 0x200>;
 340                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 341                         ti,hwmods = "gpio3";
 342                         gpio-controller;
 343                         #gpio-cells = <2>;
 344                         interrupt-controller;
 345                         #interrupt-cells = <2>;
 346                 };
 347
 348                 gpio4: gpio@48059000 {
 349                         compatible = "ti,omap4-gpio";
 350                         reg = <0x48059000 0x200>;
 351                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 352                         ti,hwmods = "gpio4";
 353                         gpio-controller;
 354                         #gpio-cells = <2>;
 355                         interrupt-controller;
 356                         #interrupt-cells = <2>;
 357                 };
 358
 359                 gpio5: gpio@4805b000 {
 360                         compatible = "ti,omap4-gpio";
 361                         reg = <0x4805b000 0x200>;
 362                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 363                         ti,hwmods = "gpio5";
 364                         gpio-controller;
 365                         #gpio-cells = <2>;
 366                         interrupt-controller;
 367                         #interrupt-cells = <2>;
 368                 };
 369
 370                 gpio6: gpio@4805d000 {
 371                         compatible = "ti,omap4-gpio";
 372                         reg = <0x4805d000 0x200>;
 373                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 374                         ti,hwmods = "gpio6";
 375                         gpio-controller;
 376                         #gpio-cells = <2>;
 377                         interrupt-controller;
 378                         #interrupt-cells = <2>;
 379                 };
 380
 381                 gpio7: gpio@48051000 {
 382                         compatible = "ti,omap4-gpio";
 383                         reg = <0x48051000 0x200>;
 384                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 385                         ti,hwmods = "gpio7";
 386                         gpio-controller;
 387                         #gpio-cells = <2>;
 388                         interrupt-controller;
 389                         #interrupt-cells = <2>;
 390                 };
 391
 392                 gpio8: gpio@48053000 {
 393                         compatible = "ti,omap4-gpio";
 394                         reg = <0x48053000 0x200>;
 395                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 396                         ti,hwmods = "gpio8";
 397                         gpio-controller;
 398                         #gpio-cells = <2>;
 399                         interrupt-controller;
 400                         #interrupt-cells = <2>;
 401                 };
 402
 403                 uart1: serial@4806a000 {
 404                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 405                         reg = <0x4806a000 0x100>;
 406                         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 407                         ti,hwmods = "uart1";
 408                         clock-frequency = <48000000>;
 409                         status = "disabled";
 410                         dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
 411                         dma-names = "tx", "rx";
 412                 };
 413
 414                 uart2: serial@4806c000 {
 415                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 416                         reg = <0x4806c000 0x100>;
 417                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 418                         ti,hwmods = "uart2";
 419                         clock-frequency = <48000000>;
 420                         status = "disabled";
 421                         dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
 422                         dma-names = "tx", "rx";
 423                 };
 424
 425                 uart3: serial@48020000 {
 426                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 427                         reg = <0x48020000 0x100>;
 428                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 429                         ti,hwmods = "uart3";
 430                         clock-frequency = <48000000>;
 431                         status = "disabled";
 432                         dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
 433                         dma-names = "tx", "rx";
 434                 };
 435
 436                 uart4: serial@4806e000 {
 437                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 438                         reg = <0x4806e000 0x100>;
 439                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 440                         ti,hwmods = "uart4";
 441                         clock-frequency = <48000000>;
 442                         status = "disabled";
 443                         dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
 444                         dma-names = "tx", "rx";
 445                 };
 446
 447                 uart5: serial@48066000 {
 448                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 449                         reg = <0x48066000 0x100>;
 450                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 451                         ti,hwmods = "uart5";
 452                         clock-frequency = <48000000>;
 453                         status = "disabled";
 454                         dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
 455                         dma-names = "tx", "rx";
 456                 };
 457
 458                 uart6: serial@48068000 {
 459                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 460                         reg = <0x48068000 0x100>;
 461                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 462                         ti,hwmods = "uart6";
 463                         clock-frequency = <48000000>;
 464                         status = "disabled";
 465                         dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
 466                         dma-names = "tx", "rx";
 467                 };
 468
 469                 uart7: serial@48420000 {
 470                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 471                         reg = <0x48420000 0x100>;
 472                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 473                         ti,hwmods = "uart7";
 474                         clock-frequency = <48000000>;
 475                         status = "disabled";
 476                 };
 477
 478                 uart8: serial@48422000 {
 479                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 480                         reg = <0x48422000 0x100>;
 481                         interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 482                         ti,hwmods = "uart8";
 483                         clock-frequency = <48000000>;
 484                         status = "disabled";
 485                 };
 486
 487                 uart9: serial@48424000 {
 488                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 489                         reg = <0x48424000 0x100>;
 490                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 491                         ti,hwmods = "uart9";
 492                         clock-frequency = <48000000>;
 493                         status = "disabled";
 494                 };
 495
 496                 uart10: serial@4ae2b000 {
 497                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 498                         reg = <0x4ae2b000 0x100>;
 499                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 500                         ti,hwmods = "uart10";
 501                         clock-frequency = <48000000>;
 502                         status = "disabled";
 503                 };
 504
 505                 mailbox1: mailbox@4a0f4000 {
 506                         compatible = "ti,omap4-mailbox";
 507                         reg = <0x4a0f4000 0x200>;
 508                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 509                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 510                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 511                         ti,hwmods = "mailbox1";
 512                         #mbox-cells = <1>;
 513                         ti,mbox-num-users = <3>;
 514                         ti,mbox-num-fifos = <8>;
 515                         status = "disabled";
 516                 };
 517
 518                 mailbox2: mailbox@4883a000 {
 519                         compatible = "ti,omap4-mailbox";
 520                         reg = <0x4883a000 0x200>;
 521                         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 522                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 523                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 524                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 525                         ti,hwmods = "mailbox2";
 526                         #mbox-cells = <1>;
 527                         ti,mbox-num-users = <4>;
 528                         ti,mbox-num-fifos = <12>;
 529                         status = "disabled";
 530                 };
 531
 532                 mailbox3: mailbox@4883c000 {
 533                         compatible = "ti,omap4-mailbox";
 534                         reg = <0x4883c000 0x200>;
 535                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 536                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 537                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 538                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 539                         ti,hwmods = "mailbox3";
 540                         #mbox-cells = <1>;
 541                         ti,mbox-num-users = <4>;
 542                         ti,mbox-num-fifos = <12>;
 543                         status = "disabled";
 544                 };
 545
 546                 mailbox4: mailbox@4883e000 {
 547                         compatible = "ti,omap4-mailbox";
 548                         reg = <0x4883e000 0x200>;
 549                         interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 550                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 551                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 552                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 553                         ti,hwmods = "mailbox4";
 554                         #mbox-cells = <1>;
 555                         ti,mbox-num-users = <4>;
 556                         ti,mbox-num-fifos = <12>;
 557                         status = "disabled";
 558                 };
 559
 560                 mailbox5: mailbox@48840000 {
 561                         compatible = "ti,omap4-mailbox";
 562                         reg = <0x48840000 0x200>;
 563                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 564                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 565                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 566                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 567                         ti,hwmods = "mailbox5";
 568                         #mbox-cells = <1>;
 569                         ti,mbox-num-users = <4>;
 570                         ti,mbox-num-fifos = <12>;
 571                         status = "disabled";
 572                 };
 573
 574                 mailbox6: mailbox@48842000 {
 575                         compatible = "ti,omap4-mailbox";
 576                         reg = <0x48842000 0x200>;
 577                         interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 578                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 579                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 580                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 581                         ti,hwmods = "mailbox6";
 582                         #mbox-cells = <1>;
 583                         ti,mbox-num-users = <4>;
 584                         ti,mbox-num-fifos = <12>;
 585                         status = "disabled";
 586                 };
 587
 588                 mailbox7: mailbox@48844000 {
 589                         compatible = "ti,omap4-mailbox";
 590                         reg = <0x48844000 0x200>;
 591                         interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 592                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 593                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 594                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
 595                         ti,hwmods = "mailbox7";
 596                         #mbox-cells = <1>;
 597                         ti,mbox-num-users = <4>;
 598                         ti,mbox-num-fifos = <12>;
 599                         status = "disabled";
 600                 };
 601
 602                 mailbox8: mailbox@48846000 {
 603                         compatible = "ti,omap4-mailbox";
 604                         reg = <0x48846000 0x200>;
 605                         interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 606                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 607                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 608                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
 609                         ti,hwmods = "mailbox8";
 610                         #mbox-cells = <1>;
 611                         ti,mbox-num-users = <4>;
 612                         ti,mbox-num-fifos = <12>;
 613                         status = "disabled";
 614                 };
 615
 616                 mailbox9: mailbox@4885e000 {
 617                         compatible = "ti,omap4-mailbox";
 618                         reg = <0x4885e000 0x200>;
 619                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 620                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
 621                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
 622                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 623                         ti,hwmods = "mailbox9";
 624                         #mbox-cells = <1>;
 625                         ti,mbox-num-users = <4>;
 626                         ti,mbox-num-fifos = <12>;
 627                         status = "disabled";
 628                 };
 629
 630                 mailbox10: mailbox@48860000 {
 631                         compatible = "ti,omap4-mailbox";
 632                         reg = <0x48860000 0x200>;
 633                         interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
 634                                      <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
 635                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
 636                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 637                         ti,hwmods = "mailbox10";
 638                         #mbox-cells = <1>;
 639                         ti,mbox-num-users = <4>;
 640                         ti,mbox-num-fifos = <12>;
 641                         status = "disabled";
 642                 };
 643
 644                 mailbox11: mailbox@48862000 {
 645                         compatible = "ti,omap4-mailbox";
 646                         reg = <0x48862000 0x200>;
 647                         interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
 648                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
 649                                      <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
 650                                      <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
 651                         ti,hwmods = "mailbox11";
 652                         #mbox-cells = <1>;
 653                         ti,mbox-num-users = <4>;
 654                         ti,mbox-num-fifos = <12>;
 655                         status = "disabled";
 656                 };
 657
 658                 mailbox12: mailbox@48864000 {
 659                         compatible = "ti,omap4-mailbox";
 660                         reg = <0x48864000 0x200>;
 661                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 662                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 663                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 664                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
 665                         ti,hwmods = "mailbox12";
 666                         #mbox-cells = <1>;
 667                         ti,mbox-num-users = <4>;
 668                         ti,mbox-num-fifos = <12>;
 669                         status = "disabled";
 670                 };
 671
 672                 mailbox13: mailbox@48802000 {
 673                         compatible = "ti,omap4-mailbox";
 674                         reg = <0x48802000 0x200>;
 675                         interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
 676                                      <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 677                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 678                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
 679                         ti,hwmods = "mailbox13";
 680                         #mbox-cells = <1>;
 681                         ti,mbox-num-users = <4>;
 682                         ti,mbox-num-fifos = <12>;
 683                         status = "disabled";
 684                 };
 685
 686                 timer1: timer@4ae18000 {
 687                         compatible = "ti,omap5430-timer";
 688                         reg = <0x4ae18000 0x80>;
 689                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 690                         ti,hwmods = "timer1";
 691                         ti,timer-alwon;
 692                 };
 693
 694                 timer2: timer@48032000 {
 695                         compatible = "ti,omap5430-timer";
 696                         reg = <0x48032000 0x80>;
 697                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 698                         ti,hwmods = "timer2";
 699                 };
 700
 701                 timer3: timer@48034000 {
 702                         compatible = "ti,omap5430-timer";
 703                         reg = <0x48034000 0x80>;
 704                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 705                         ti,hwmods = "timer3";
 706                 };
 707
 708                 timer4: timer@48036000 {
 709                         compatible = "ti,omap5430-timer";
 710                         reg = <0x48036000 0x80>;
 711                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 712                         ti,hwmods = "timer4";
 713                 };
 714
 715                 timer5: timer@48820000 {
 716                         compatible = "ti,omap5430-timer";
 717                         reg = <0x48820000 0x80>;
 718                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 719                         ti,hwmods = "timer5";
 720                 };
 721
 722                 timer6: timer@48822000 {
 723                         compatible = "ti,omap5430-timer";
 724                         reg = <0x48822000 0x80>;
 725                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 726                         ti,hwmods = "timer6";
 727                 };
 728
 729                 timer7: timer@48824000 {
 730                         compatible = "ti,omap5430-timer";
 731                         reg = <0x48824000 0x80>;
 732                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 733                         ti,hwmods = "timer7";
 734                 };
 735
 736                 timer8: timer@48826000 {
 737                         compatible = "ti,omap5430-timer";
 738                         reg = <0x48826000 0x80>;
 739                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 740                         ti,hwmods = "timer8";
 741                 };
 742
 743                 timer9: timer@4803e000 {
 744                         compatible = "ti,omap5430-timer";
 745                         reg = <0x4803e000 0x80>;
 746                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 747                         ti,hwmods = "timer9";
 748                 };
 749
 750                 timer10: timer@48086000 {
 751                         compatible = "ti,omap5430-timer";
 752                         reg = <0x48086000 0x80>;
 753                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 754                         ti,hwmods = "timer10";
 755                 };
 756
 757                 timer11: timer@48088000 {
 758                         compatible = "ti,omap5430-timer";
 759                         reg = <0x48088000 0x80>;
 760                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 761                         ti,hwmods = "timer11";
 762                 };
 763
 764                 timer13: timer@48828000 {
 765                         compatible = "ti,omap5430-timer";
 766                         reg = <0x48828000 0x80>;
 767                         interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 768                         ti,hwmods = "timer13";
 769                         status = "disabled";
 770                 };
 771
 772                 timer14: timer@4882a000 {
 773                         compatible = "ti,omap5430-timer";
 774                         reg = <0x4882a000 0x80>;
 775                         interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 776                         ti,hwmods = "timer14";
 777                         status = "disabled";
 778                 };
 779
 780                 timer15: timer@4882c000 {
 781                         compatible = "ti,omap5430-timer";
 782                         reg = <0x4882c000 0x80>;
 783                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 784                         ti,hwmods = "timer15";
 785                         status = "disabled";
 786                 };
 787
 788                 timer16: timer@4882e000 {
 789                         compatible = "ti,omap5430-timer";
 790                         reg = <0x4882e000 0x80>;
 791                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 792                         ti,hwmods = "timer16";
 793                         status = "disabled";
 794                 };
 795
 796                 wdt2: wdt@4ae14000 {
 797                         compatible = "ti,omap3-wdt";
 798                         reg = <0x4ae14000 0x80>;
 799                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 800                         ti,hwmods = "wd_timer2";
 801                 };
 802
 803                 hwspinlock: spinlock@4a0f6000 {
 804                         compatible = "ti,omap4-hwspinlock";
 805                         reg = <0x4a0f6000 0x1000>;
 806                         ti,hwmods = "spinlock";
 807                         #hwlock-cells = <1>;
 808                 };
 809
 810                 dmm@4e000000 {
 811                         compatible = "ti,omap5-dmm";
 812                         reg = <0x4e000000 0x800>;
 813                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 814                         ti,hwmods = "dmm";
 815                 };
 816
 817                 i2c1: i2c@48070000 {
 818                         compatible = "ti,omap4-i2c";
 819                         reg = <0x48070000 0x100>;
 820                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 821                         #address-cells = <1>;
 822                         #size-cells = <0>;
 823                         ti,hwmods = "i2c1";
 824                         status = "disabled";
 825                 };
 826
 827                 i2c2: i2c@48072000 {
 828                         compatible = "ti,omap4-i2c";
 829                         reg = <0x48072000 0x100>;
 830                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 831                         #address-cells = <1>;
 832                         #size-cells = <0>;
 833                         ti,hwmods = "i2c2";
 834                         status = "disabled";
 835                 };
 836
 837                 i2c3: i2c@48060000 {
 838                         compatible = "ti,omap4-i2c";
 839                         reg = <0x48060000 0x100>;
 840                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 841                         #address-cells = <1>;
 842                         #size-cells = <0>;
 843                         ti,hwmods = "i2c3";
 844                         status = "disabled";
 845                 };
 846
 847                 i2c4: i2c@4807a000 {
 848                         compatible = "ti,omap4-i2c";
 849                         reg = <0x4807a000 0x100>;
 850                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 851                         #address-cells = <1>;
 852                         #size-cells = <0>;
 853                         ti,hwmods = "i2c4";
 854                         status = "disabled";
 855                 };
 856
 857                 i2c5: i2c@4807c000 {
 858                         compatible = "ti,omap4-i2c";
 859                         reg = <0x4807c000 0x100>;
 860                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 861                         #address-cells = <1>;
 862                         #size-cells = <0>;
 863                         ti,hwmods = "i2c5";
 864                         status = "disabled";
 865                 };
 866
 867                 mmc1: mmc@4809c000 {
 868                         compatible = "ti,omap4-hsmmc";
 869                         reg = <0x4809c000 0x400>;
 870                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 871                         ti,hwmods = "mmc1";
 872                         ti,dual-volt;
 873                         ti,needs-special-reset;
 874                         dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
 875                         dma-names = "tx", "rx";
 876                         status = "disabled";
 877                         pbias-supply = <&pbias_mmc_reg>;
 878                 };
 879
 880                 mmc2: mmc@480b4000 {
 881                         compatible = "ti,omap4-hsmmc";
 882                         reg = <0x480b4000 0x400>;
 883                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 884                         ti,hwmods = "mmc2";
 885                         ti,needs-special-reset;
 886                         dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
 887                         dma-names = "tx", "rx";
 888                         status = "disabled";
 889                 };
 890
 891                 mmc3: mmc@480ad000 {
 892                         compatible = "ti,omap4-hsmmc";
 893                         reg = <0x480ad000 0x400>;
 894                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 895                         ti,hwmods = "mmc3";
 896                         ti,needs-special-reset;
 897                         dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
 898                         dma-names = "tx", "rx";
 899                         status = "disabled";
 900                 };
 901
 902                 mmc4: mmc@480d1000 {
 903                         compatible = "ti,omap4-hsmmc";
 904                         reg = <0x480d1000 0x400>;
 905                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 906                         ti,hwmods = "mmc4";
 907                         ti,needs-special-reset;
 908                         dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
 909                         dma-names = "tx", "rx";
 910                         status = "disabled";
 911                 };
 912
 913                 abb_mpu: regulator-abb-mpu {
 914                         compatible = "ti,abb-v3";
 915                         regulator-name = "abb_mpu";
 916                         #address-cells = <0>;
 917                         #size-cells = <0>;
 918                         clocks = <&sys_clkin1>;
 919                         ti,settling-time = <50>;
 920                         ti,clock-cycles = <16>;
 921
 922                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
 923                               <0x4ae06014 0x4>, <0x4a003b20 0xc>,
 924                               <0x4ae0c158 0x4>;
 925                         reg-names = "setup-address", "control-address",
 926                                     "int-address", "efuse-address",
 927                                     "ldo-address";
 928                         ti,tranxdone-status-mask = <0x80>;
 929                         /* LDOVBBMPU_FBB_MUX_CTRL */
 930                         ti,ldovbb-override-mask = <0x400>;
 931                         /* LDOVBBMPU_FBB_VSET_OUT */
 932                         ti,ldovbb-vset-mask = <0x1F>;
 933
 934                         /*
 935                          * NOTE: only FBB mode used but actual vset will
 936                          * determine final biasing
 937                          */
 938                         ti,abb_info = <
 939                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 940                         1060000         0       0x0     0 0x02000000 0x01F00000
 941                         1160000         0       0x4     0 0x02000000 0x01F00000
 942                         1210000         0       0x8     0 0x02000000 0x01F00000
 943                         >;
 944                 };
 945
 946                 abb_ivahd: regulator-abb-ivahd {
 947                         compatible = "ti,abb-v3";
 948                         regulator-name = "abb_ivahd";
 949                         #address-cells = <0>;
 950                         #size-cells = <0>;
 951                         clocks = <&sys_clkin1>;
 952                         ti,settling-time = <50>;
 953                         ti,clock-cycles = <16>;
 954
 955                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
 956                               <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
 957                               <0x4a002470 0x4>;
 958                         reg-names = "setup-address", "control-address",
 959                                     "int-address", "efuse-address",
 960                                     "ldo-address";
 961                         ti,tranxdone-status-mask = <0x40000000>;
 962                         /* LDOVBBIVA_FBB_MUX_CTRL */
 963                         ti,ldovbb-override-mask = <0x400>;
 964                         /* LDOVBBIVA_FBB_VSET_OUT */
 965                         ti,ldovbb-vset-mask = <0x1F>;
 966
 967                         /*
 968                          * NOTE: only FBB mode used but actual vset will
 969                          * determine final biasing
 970                          */
 971                         ti,abb_info = <
 972                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 973                         1055000         0       0x0     0 0x02000000 0x01F00000
 974                         1150000         0       0x4     0 0x02000000 0x01F00000
 975                         1250000         0       0x8     0 0x02000000 0x01F00000
 976                         >;
 977                 };
 978
 979                 abb_dspeve: regulator-abb-dspeve {
 980                         compatible = "ti,abb-v3";
 981                         regulator-name = "abb_dspeve";
 982                         #address-cells = <0>;
 983                         #size-cells = <0>;
 984                         clocks = <&sys_clkin1>;
 985                         ti,settling-time = <50>;
 986                         ti,clock-cycles = <16>;
 987
 988                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
 989                               <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
 990                               <0x4a00246c 0x4>;
 991                         reg-names = "setup-address", "control-address",
 992                                     "int-address", "efuse-address",
 993                                     "ldo-address";
 994                         ti,tranxdone-status-mask = <0x20000000>;
 995                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
 996                         ti,ldovbb-override-mask = <0x400>;
 997                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
 998                         ti,ldovbb-vset-mask = <0x1F>;
 999
1000                         /*
1001                          * NOTE: only FBB mode used but actual vset will
1002                          * determine final biasing
1003                          */
1004                         ti,abb_info = <
1005                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1006                         1055000         0       0x0     0 0x02000000 0x01F00000
1007                         1150000         0       0x4     0 0x02000000 0x01F00000
1008                         1250000         0       0x8     0 0x02000000 0x01F00000
1009                         >;
1010                 };
1011
1012                 abb_gpu: regulator-abb-gpu {
1013                         compatible = "ti,abb-v3";
1014                         regulator-name = "abb_gpu";
1015                         #address-cells = <0>;
1016                         #size-cells = <0>;
1017                         clocks = <&sys_clkin1>;
1018                         ti,settling-time = <50>;
1019                         ti,clock-cycles = <16>;
1020
1021                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1022                               <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1023                               <0x4ae0c154 0x4>;
1024                         reg-names = "setup-address", "control-address",
1025                                     "int-address", "efuse-address",
1026                                     "ldo-address";
1027                         ti,tranxdone-status-mask = <0x10000000>;
1028                         /* LDOVBBGPU_FBB_MUX_CTRL */
1029                         ti,ldovbb-override-mask = <0x400>;
1030                         /* LDOVBBGPU_FBB_VSET_OUT */
1031                         ti,ldovbb-vset-mask = <0x1F>;
1032
1033                         /*
1034                          * NOTE: only FBB mode used but actual vset will
1035                          * determine final biasing
1036                          */
1037                         ti,abb_info = <
1038                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1039                         1090000         0       0x0     0 0x02000000 0x01F00000
1040                         1210000         0       0x4     0 0x02000000 0x01F00000
1041                         1280000         0       0x8     0 0x02000000 0x01F00000
1042                         >;
1043                 };
1044
1045                 mcspi1: spi@48098000 {
1046                         compatible = "ti,omap4-mcspi";
1047                         reg = <0x48098000 0x200>;
1048                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1049                         #address-cells = <1>;
1050                         #size-cells = <0>;
1051                         ti,hwmods = "mcspi1";
1052                         ti,spi-num-cs = <4>;
1053                         dmas = <&sdma_xbar 35>,
1054                                <&sdma_xbar 36>,
1055                                <&sdma_xbar 37>,
1056                                <&sdma_xbar 38>,
1057                                <&sdma_xbar 39>,
1058                                <&sdma_xbar 40>,
1059                                <&sdma_xbar 41>,
1060                                <&sdma_xbar 42>;
1061                         dma-names = "tx0", "rx0", "tx1", "rx1",
1062                                     "tx2", "rx2", "tx3", "rx3";
1063                         status = "disabled";
1064                 };
1065
1066                 mcspi2: spi@4809a000 {
1067                         compatible = "ti,omap4-mcspi";
1068                         reg = <0x4809a000 0x200>;
1069                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1070                         #address-cells = <1>;
1071                         #size-cells = <0>;
1072                         ti,hwmods = "mcspi2";
1073                         ti,spi-num-cs = <2>;
1074                         dmas = <&sdma_xbar 43>,
1075                                <&sdma_xbar 44>,
1076                                <&sdma_xbar 45>,
1077                                <&sdma_xbar 46>;
1078                         dma-names = "tx0", "rx0", "tx1", "rx1";
1079                         status = "disabled";
1080                 };
1081
1082                 mcspi3: spi@480b8000 {
1083                         compatible = "ti,omap4-mcspi";
1084                         reg = <0x480b8000 0x200>;
1085                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1086                         #address-cells = <1>;
1087                         #size-cells = <0>;
1088                         ti,hwmods = "mcspi3";
1089                         ti,spi-num-cs = <2>;
1090                         dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1091                         dma-names = "tx0", "rx0";
1092                         status = "disabled";
1093                 };
1094
1095                 mcspi4: spi@480ba000 {
1096                         compatible = "ti,omap4-mcspi";
1097                         reg = <0x480ba000 0x200>;
1098                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1099                         #address-cells = <1>;
1100                         #size-cells = <0>;
1101                         ti,hwmods = "mcspi4";
1102                         ti,spi-num-cs = <1>;
1103                         dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1104                         dma-names = "tx0", "rx0";
1105                         status = "disabled";
1106                 };
1107
1108                 qspi: qspi@4b300000 {
1109                         compatible = "ti,dra7xxx-qspi";
1110                         reg = <0x4b300000 0x100>;
1111                         reg-names = "qspi_base";
1112                         #address-cells = <1>;
1113                         #size-cells = <0>;
1114                         ti,hwmods = "qspi";
1115                         clocks = <&qspi_gfclk_div>;
1116                         clock-names = "fck";
1117                         num-cs = <4>;
1118                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1119                         status = "disabled";
1120                 };
1121
1122                 omap_control_sata: control-phy@4a002374 {
1123                         compatible = "ti,control-phy-pipe3";
1124                         reg = <0x4a002374 0x4>;
1125                         reg-names = "power";
1126                         clocks = <&sys_clkin1>;
1127                         clock-names = "sysclk";
1128                 };
1129
1130                 /* OCP2SCP3 */
1131                 ocp2scp@4a090000 {
1132                         compatible = "ti,omap-ocp2scp";
1133                         #address-cells = <1>;
1134                         #size-cells = <1>;
1135                         ranges;
1136                         reg = <0x4a090000 0x20>;
1137                         ti,hwmods = "ocp2scp3";
1138                         sata_phy: phy@4A096000 {
1139                                 compatible = "ti,phy-pipe3-sata";
1140                                 reg = <0x4A096000 0x80>, /* phy_rx */
1141                                       <0x4A096400 0x64>, /* phy_tx */
1142                                       <0x4A096800 0x40>; /* pll_ctrl */
1143                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1144                                 ctrl-module = <&omap_control_sata>;
1145                                 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1146                                 clock-names = "sysclk", "refclk";
1147                                 syscon-pllreset = <&scm_conf 0x3fc>;
1148                                 #phy-cells = <0>;
1149                         };
1150
1151                         pcie1_phy: pciephy@4a094000 {
1152                                 compatible = "ti,phy-pipe3-pcie";
1153                                 reg = <0x4a094000 0x80>, /* phy_rx */
1154                                       <0x4a094400 0x64>; /* phy_tx */
1155                                 reg-names = "phy_rx", "phy_tx";
1156                                 ctrl-module = <&omap_control_pcie1phy>;
1157                                 clocks = <&dpll_pcie_ref_ck>,
1158                                          <&dpll_pcie_ref_m2ldo_ck>,
1159                                          <&optfclk_pciephy1_32khz>,
1160                                          <&optfclk_pciephy1_clk>,
1161                                          <&optfclk_pciephy1_div_clk>,
1162                                          <&optfclk_pciephy_div>;
1163                                 clock-names = "dpll_ref", "dpll_ref_m2",
1164                                               "wkupclk", "refclk",
1165                                               "div-clk", "phy-div";
1166                                 #phy-cells = <0>;
1167                         };
1168
1169                         pcie2_phy: pciephy@4a095000 {
1170                                 compatible = "ti,phy-pipe3-pcie";
1171                                 reg = <0x4a095000 0x80>, /* phy_rx */
1172                                       <0x4a095400 0x64>; /* phy_tx */
1173                                 reg-names = "phy_rx", "phy_tx";
1174                                 ctrl-module = <&omap_control_pcie2phy>;
1175                                 clocks = <&dpll_pcie_ref_ck>,
1176                                          <&dpll_pcie_ref_m2ldo_ck>,
1177                                          <&optfclk_pciephy2_32khz>,
1178                                          <&optfclk_pciephy2_clk>,
1179                                          <&optfclk_pciephy2_div_clk>,
1180                                          <&optfclk_pciephy_div>;
1181                                 clock-names = "dpll_ref", "dpll_ref_m2",
1182                                               "wkupclk", "refclk",
1183                                               "div-clk", "phy-div";
1184                                 #phy-cells = <0>;
1185                                 status = "disabled";
1186                         };
1187                 };
1188
1189                 sata: sata@4a141100 {
1190                         compatible = "snps,dwc-ahci";
1191                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1192                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1193                         phys = <&sata_phy>;
1194                         phy-names = "sata-phy";
1195                         clocks = <&sata_ref_clk>;
1196                         ti,hwmods = "sata";
1197                 };
1198
1199                 omap_control_pcie1phy: control-phy@0x4a003c40 {
1200                         compatible = "ti,control-phy-pcie";
1201                         reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1202                         reg-names = "power", "control_sma", "pcie_pcs";
1203                         clocks = <&sys_clkin1>;
1204                         clock-names = "sysclk";
1205                 };
1206
1207                 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1208                         compatible = "ti,control-phy-pcie";
1209                         reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1210                         reg-names = "power", "control_sma", "pcie_pcs";
1211                         clocks = <&sys_clkin1>;
1212                         clock-names = "sysclk";
1213                         status = "disabled";
1214                 };
1215
1216                 rtc: rtc@48838000 {
1217                         compatible = "ti,am3352-rtc";
1218                         reg = <0x48838000 0x100>;
1219                         interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1220                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1221                         ti,hwmods = "rtcss";
1222                         clocks = <&sys_32k_ck>;
1223                 };
1224
1225                 omap_control_usb2phy1: control-phy@4a002300 {
1226                         compatible = "ti,control-phy-usb2";
1227                         reg = <0x4a002300 0x4>;
1228                         reg-names = "power";
1229                 };
1230
1231                 omap_control_usb3phy1: control-phy@4a002370 {
1232                         compatible = "ti,control-phy-pipe3";
1233                         reg = <0x4a002370 0x4>;
1234                         reg-names = "power";
1235                 };
1236
1237                 omap_control_usb2phy2: control-phy@0x4a002e74 {
1238                         compatible = "ti,control-phy-usb2-dra7";
1239                         reg = <0x4a002e74 0x4>;
1240                         reg-names = "power";
1241                 };
1242
1243                 /* OCP2SCP1 */
1244                 ocp2scp@4a080000 {
1245                         compatible = "ti,omap-ocp2scp";
1246                         #address-cells = <1>;
1247                         #size-cells = <1>;
1248                         ranges;
1249                         reg = <0x4a080000 0x20>;
1250                         ti,hwmods = "ocp2scp1";
1251
1252                         usb2_phy1: phy@4a084000 {
1253                                 compatible = "ti,omap-usb2";
1254                                 reg = <0x4a084000 0x400>;
1255                                 ctrl-module = <&omap_control_usb2phy1>;
1256                                 clocks = <&usb_phy1_always_on_clk32k>,
1257                                          <&usb_otg_ss1_refclk960m>;
1258                                 clock-names =   "wkupclk",
1259                                                 "refclk";
1260                                 #phy-cells = <0>;
1261                         };
1262
1263                         usb2_phy2: phy@4a085000 {
1264                                 compatible = "ti,omap-usb2";
1265                                 reg = <0x4a085000 0x400>;
1266                                 ctrl-module = <&omap_control_usb2phy2>;
1267                                 clocks = <&usb_phy2_always_on_clk32k>,
1268                                          <&usb_otg_ss2_refclk960m>;
1269                                 clock-names =   "wkupclk",
1270                                                 "refclk";
1271                                 #phy-cells = <0>;
1272                         };
1273
1274                         usb3_phy1: phy@4a084400 {
1275                                 compatible = "ti,omap-usb3";
1276                                 reg = <0x4a084400 0x80>,
1277                                       <0x4a084800 0x64>,
1278                                       <0x4a084c00 0x40>;
1279                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1280                                 ctrl-module = <&omap_control_usb3phy1>;
1281                                 clocks = <&usb_phy3_always_on_clk32k>,
1282                                          <&sys_clkin1>,
1283                                          <&usb_otg_ss1_refclk960m>;
1284                                 clock-names =   "wkupclk",
1285                                                 "sysclk",
1286                                                 "refclk";
1287                                 #phy-cells = <0>;
1288                         };
1289                 };
1290
1291                 omap_dwc3_1: omap_dwc3_1@48880000 {
1292                         compatible = "ti,dwc3";
1293                         ti,hwmods = "usb_otg_ss1";
1294                         reg = <0x48880000 0x10000>;
1295                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1296                         #address-cells = <1>;
1297                         #size-cells = <1>;
1298                         utmi-mode = <2>;
1299                         ranges;
1300                         usb1: usb@48890000 {
1301                                 compatible = "snps,dwc3";
1302                                 reg = <0x48890000 0x17000>;
1303                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1304                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1305                                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1306                                 interrupt-names = "peripheral",
1307                                                   "host",
1308                                                   "otg";
1309                                 phys = <&usb2_phy1>, <&usb3_phy1>;
1310                                 phy-names = "usb2-phy", "usb3-phy";
1311                                 tx-fifo-resize;
1312                                 maximum-speed = "super-speed";
1313                                 dr_mode = "otg";
1314                                 snps,dis_u3_susphy_quirk;
1315                                 snps,dis_u2_susphy_quirk;
1316                         };
1317                 };
1318
1319                 omap_dwc3_2: omap_dwc3_2@488c0000 {
1320                         compatible = "ti,dwc3";
1321                         ti,hwmods = "usb_otg_ss2";
1322                         reg = <0x488c0000 0x10000>;
1323                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1324                         #address-cells = <1>;
1325                         #size-cells = <1>;
1326                         utmi-mode = <2>;
1327                         ranges;
1328                         usb2: usb@488d0000 {
1329                                 compatible = "snps,dwc3";
1330                                 reg = <0x488d0000 0x17000>;
1331                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1332                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1333                                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1334                                 interrupt-names = "peripheral",
1335                                                   "host",
1336                                                   "otg";
1337                                 phys = <&usb2_phy2>;
1338                                 phy-names = "usb2-phy";
1339                                 tx-fifo-resize;
1340                                 maximum-speed = "high-speed";
1341                                 dr_mode = "otg";
1342                                 snps,dis_u3_susphy_quirk;
1343                                 snps,dis_u2_susphy_quirk;
1344                         };
1345                 };
1346
1347                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1348                 omap_dwc3_3: omap_dwc3_3@48900000 {
1349                         compatible = "ti,dwc3";
1350                         ti,hwmods = "usb_otg_ss3";
1351                         reg = <0x48900000 0x10000>;
1352                         interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1353                         #address-cells = <1>;
1354                         #size-cells = <1>;
1355                         utmi-mode = <2>;
1356                         ranges;
1357                         status = "disabled";
1358                         usb3: usb@48910000 {
1359                                 compatible = "snps,dwc3";
1360                                 reg = <0x48910000 0x17000>;
1361                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1362                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1363                                              <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1364                                 interrupt-names = "peripheral",
1365                                                   "host",
1366                                                   "otg";
1367                                 tx-fifo-resize;
1368                                 maximum-speed = "high-speed";
1369                                 dr_mode = "otg";
1370                                 snps,dis_u3_susphy_quirk;
1371                                 snps,dis_u2_susphy_quirk;
1372                         };
1373                 };
1374
1375                 elm: elm@48078000 {
1376                         compatible = "ti,am3352-elm";
1377                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1378                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1379                         ti,hwmods = "elm";
1380                         status = "disabled";
1381                 };
1382
1383                 gpmc: gpmc@50000000 {
1384                         compatible = "ti,am3352-gpmc";
1385                         ti,hwmods = "gpmc";
1386                         reg = <0x50000000 0x37c>;      /* device IO registers */
1387                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1388                         gpmc,num-cs = <8>;
1389                         gpmc,num-waitpins = <2>;
1390                         #address-cells = <2>;
1391                         #size-cells = <1>;
1392                         status = "disabled";
1393                 };
1394
1395                 atl: atl@4843c000 {
1396                         compatible = "ti,dra7-atl";
1397                         reg = <0x4843c000 0x3ff>;
1398                         ti,hwmods = "atl";
1399                         ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1400                                              <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1401                         clocks = <&atl_gfclk_mux>;
1402                         clock-names = "fck";
1403                         status = "disabled";
1404                 };
1405
1406                 crossbar_mpu: crossbar@4a002a48 {
1407                         compatible = "ti,irq-crossbar";
1408                         reg = <0x4a002a48 0x130>;
1409                         interrupt-controller;
1410                         interrupt-parent = <&wakeupgen>;
1411                         #interrupt-cells = <3>;
1412                         ti,max-irqs = <160>;
1413                         ti,max-crossbar-sources = <MAX_SOURCES>;
1414                         ti,reg-size = <2>;
1415                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1416                         ti,irqs-skip = <10 133 139 140>;
1417                         ti,irqs-safe-map = <0>;
1418                 };
1419
1420                 mac: ethernet@4a100000 {
1421                         compatible = "ti,dra7-cpsw","ti,cpsw";
1422                         ti,hwmods = "gmac";
1423                         clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1424                         clock-names = "fck", "cpts";
1425                         cpdma_channels = <8>;
1426                         ale_entries = <1024>;
1427                         bd_ram_size = <0x2000>;
1428                         no_bd_ram = <0>;
1429                         rx_descs = <64>;
1430                         mac_control = <0x20>;
1431                         slaves = <2>;
1432                         active_slave = <0>;
1433                         cpts_clock_mult = <0x80000000>;
1434                         cpts_clock_shift = <29>;
1435                         reg = <0x48484000 0x1000
1436                                0x48485200 0x2E00>;
1437                         #address-cells = <1>;
1438                         #size-cells = <1>;
1439                         /*
1440                          * rx_thresh_pend
1441                          * rx_pend
1442                          * tx_pend
1443                          * misc_pend
1444                          */
1445                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1446                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1447                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1448                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1449                         ranges;
1450                         status = "disabled";
1451
1452                         davinci_mdio: mdio@48485000 {
1453                                 compatible = "ti,davinci_mdio";
1454                                 #address-cells = <1>;
1455                                 #size-cells = <0>;
1456                                 ti,hwmods = "davinci_mdio";
1457                                 bus_freq = <1000000>;
1458                                 reg = <0x48485000 0x100>;
1459                         };
1460
1461                         cpsw_emac0: slave@48480200 {
1462                                 /* Filled in by U-Boot */
1463                                 mac-address = [ 00 00 00 00 00 00 ];
1464                         };
1465
1466                         cpsw_emac1: slave@48480300 {
1467                                 /* Filled in by U-Boot */
1468                                 mac-address = [ 00 00 00 00 00 00 ];
1469                         };
1470
1471                         phy_sel: cpsw-phy-sel@4a002554 {
1472                                 compatible = "ti,dra7xx-cpsw-phy-sel";
1473                                 reg= <0x4a002554 0x4>;
1474                                 reg-names = "gmii-sel";
1475                         };
1476                 };
1477
1478                 dcan1: can@481cc000 {
1479                         compatible = "ti,dra7-d_can";
1480                         ti,hwmods = "dcan1";
1481                         reg = <0x4ae3c000 0x2000>;
1482                         syscon-raminit = <&scm_conf 0x558 0>;
1483                         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1484                         clocks = <&dcan1_sys_clk_mux>;
1485                         status = "disabled";
1486                 };
1487
1488                 dcan2: can@481d0000 {
1489                         compatible = "ti,dra7-d_can";
1490                         ti,hwmods = "dcan2";
1491                         reg = <0x48480000 0x2000>;
1492                         syscon-raminit = <&scm_conf 0x558 1>;
1493                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1494                         clocks = <&sys_clkin1>;
1495                         status = "disabled";
1496                 };
1497
1498                 dss: dss@58000000 {
1499                         compatible = "ti,dra7-dss";
1500                         /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1501                         /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1502                         status = "disabled";
1503                         ti,hwmods = "dss_core";
1504                         /* CTRL_CORE_DSS_PLL_CONTROL */
1505                         syscon-pll-ctrl = <&scm_conf 0x538>;
1506                         #address-cells = <1>;
1507                         #size-cells = <1>;
1508                         ranges;
1509
1510                         dispc@58001000 {
1511                                 compatible = "ti,dra7-dispc";
1512                                 reg = <0x58001000 0x1000>;
1513                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1514                                 ti,hwmods = "dss_dispc";
1515                                 clocks = <&dss_dss_clk>;
1516                                 clock-names = "fck";
1517                                 /* CTRL_CORE_SMA_SW_1 */
1518                                 syscon-pol = <&scm_conf 0x534>;
1519                         };
1520
1521                         hdmi: encoder@58060000 {
1522                                 compatible = "ti,dra7-hdmi";
1523                                 reg = <0x58040000 0x200>,
1524                                       <0x58040200 0x80>,
1525                                       <0x58040300 0x80>,
1526                                       <0x58060000 0x19000>;
1527                                 reg-names = "wp", "pll", "phy", "core";
1528                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1529                                 status = "disabled";
1530                                 ti,hwmods = "dss_hdmi";
1531                                 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1532                                 clock-names = "fck", "sys_clk";
1533                         };
1534                 };
1535         };
1536
1537         thermal_zones: thermal-zones {
1538                 #include "omap4-cpu-thermal.dtsi"
1539                 #include "omap5-gpu-thermal.dtsi"
1540                 #include "omap5-core-thermal.dtsi"
1541         };
1542
1543 };
1544
1545 &cpu_thermal {
1546         polling-delay = <500>; /* milliseconds */
1547 };
1548
1549 /include/ "dra7xx-clocks.dtsi"