2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
26 tzic: tz-interrupt-controller@e0000000 {
27 compatible = "fsl,imx51-tzic", "fsl,tzic";
29 #interrupt-cells = <1>;
30 reg = <0xe0000000 0x4000>;
38 compatible = "fsl,imx-ckil", "fixed-clock";
39 clock-frequency = <32768>;
43 compatible = "fsl,imx-ckih1", "fixed-clock";
44 clock-frequency = <22579200>;
48 compatible = "fsl,imx-ckih2", "fixed-clock";
49 clock-frequency = <0>;
53 compatible = "fsl,imx-osc", "fixed-clock";
54 clock-frequency = <24000000>;
61 compatible = "simple-bus";
62 interrupt-parent = <&tzic>;
67 compatible = "fsl,imx51-ipu";
68 reg = <0x40000000 0x20000000>;
72 aips@70000000 { /* AIPS1 */
73 compatible = "fsl,aips-bus", "simple-bus";
76 reg = <0x70000000 0x10000000>;
80 compatible = "fsl,spba-bus", "simple-bus";
83 reg = <0x70000000 0x40000>;
86 esdhc@70004000 { /* ESDHC1 */
87 compatible = "fsl,imx51-esdhc";
88 reg = <0x70004000 0x4000>;
90 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
91 clock-names = "ipg", "ahb", "per";
95 esdhc@70008000 { /* ESDHC2 */
96 compatible = "fsl,imx51-esdhc";
97 reg = <0x70008000 0x4000>;
99 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
100 clock-names = "ipg", "ahb", "per";
104 uart3: serial@7000c000 {
105 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
106 reg = <0x7000c000 0x4000>;
108 clocks = <&clks 32>, <&clks 33>;
109 clock-names = "ipg", "per";
113 ecspi@70010000 { /* ECSPI1 */
114 #address-cells = <1>;
116 compatible = "fsl,imx51-ecspi";
117 reg = <0x70010000 0x4000>;
119 clocks = <&clks 51>, <&clks 52>;
120 clock-names = "ipg", "per";
125 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
126 reg = <0x70014000 0x4000>;
129 fsl,fifo-depth = <15>;
130 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
134 esdhc@70020000 { /* ESDHC3 */
135 compatible = "fsl,imx51-esdhc";
136 reg = <0x70020000 0x4000>;
138 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
139 clock-names = "ipg", "ahb", "per";
143 esdhc@70024000 { /* ESDHC4 */
144 compatible = "fsl,imx51-esdhc";
145 reg = <0x70024000 0x4000>;
147 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
148 clock-names = "ipg", "ahb", "per";
154 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
155 reg = <0x73f80000 0x0200>;
161 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
162 reg = <0x73f80200 0x0200>;
168 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
169 reg = <0x73f80400 0x0200>;
175 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
176 reg = <0x73f80600 0x0200>;
181 gpio1: gpio@73f84000 {
182 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
183 reg = <0x73f84000 0x4000>;
184 interrupts = <50 51>;
187 interrupt-controller;
188 #interrupt-cells = <2>;
191 gpio2: gpio@73f88000 {
192 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
193 reg = <0x73f88000 0x4000>;
194 interrupts = <52 53>;
197 interrupt-controller;
198 #interrupt-cells = <2>;
201 gpio3: gpio@73f8c000 {
202 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
203 reg = <0x73f8c000 0x4000>;
204 interrupts = <54 55>;
207 interrupt-controller;
208 #interrupt-cells = <2>;
211 gpio4: gpio@73f90000 {
212 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
213 reg = <0x73f90000 0x4000>;
214 interrupts = <56 57>;
217 interrupt-controller;
218 #interrupt-cells = <2>;
221 wdog@73f98000 { /* WDOG1 */
222 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
223 reg = <0x73f98000 0x4000>;
228 wdog@73f9c000 { /* WDOG2 */
229 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
230 reg = <0x73f9c000 0x4000>;
237 compatible = "fsl,imx51-iomuxc";
238 reg = <0x73fa8000 0x4000>;
241 pinctrl_audmux_1: audmuxgrp-1 {
243 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
244 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
245 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
246 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
252 pinctrl_fec_1: fecgrp-1 {
254 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
255 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
256 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
257 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
258 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
259 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
260 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
261 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
262 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
263 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
264 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
265 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
266 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
267 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
268 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
269 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
270 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
276 pinctrl_ecspi1_1: ecspi1grp-1 {
278 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
279 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
280 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
286 pinctrl_esdhc1_1: esdhc1grp-1 {
288 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
289 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
290 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
291 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
292 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
293 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
299 pinctrl_esdhc2_1: esdhc2grp-1 {
301 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
302 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
303 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
304 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
305 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
306 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
312 pinctrl_i2c2_1: i2c2grp-1 {
314 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
315 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
321 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
323 528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
324 529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
325 530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
326 531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
327 532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
328 533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
329 535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
330 537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
331 539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
332 541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
333 543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
334 545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
335 547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
336 549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
337 551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
338 553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
339 555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
340 557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
341 559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
342 563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
343 567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
344 571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
345 575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
346 579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
347 584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */
348 583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */
354 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
356 603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
357 608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
358 613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
359 614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
360 615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
361 616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
362 617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
363 622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
364 627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
365 633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
366 637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
367 643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
368 648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
369 652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
370 656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
371 661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
372 593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */
373 595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */
374 597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
375 599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */
381 pinctrl_uart1_1: uart1grp-1 {
383 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
384 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
385 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
386 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
392 pinctrl_uart2_1: uart2grp-1 {
394 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
395 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
401 pinctrl_uart3_1: uart3grp-1 {
403 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
404 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
405 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
406 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
414 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
415 reg = <0x73fb4000 0x4000>;
416 clocks = <&clks 37>, <&clks 38>;
417 clock-names = "ipg", "per";
423 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
424 reg = <0x73fb8000 0x4000>;
425 clocks = <&clks 39>, <&clks 40>;
426 clock-names = "ipg", "per";
430 uart1: serial@73fbc000 {
431 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
432 reg = <0x73fbc000 0x4000>;
434 clocks = <&clks 28>, <&clks 29>;
435 clock-names = "ipg", "per";
439 uart2: serial@73fc0000 {
440 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
441 reg = <0x73fc0000 0x4000>;
443 clocks = <&clks 30>, <&clks 31>;
444 clock-names = "ipg", "per";
449 compatible = "fsl,imx51-ccm";
450 reg = <0x73fd4000 0x4000>;
451 interrupts = <0 71 0x04 0 72 0x04>;
456 aips@80000000 { /* AIPS2 */
457 compatible = "fsl,aips-bus", "simple-bus";
458 #address-cells = <1>;
460 reg = <0x80000000 0x10000000>;
463 ecspi@83fac000 { /* ECSPI2 */
464 #address-cells = <1>;
466 compatible = "fsl,imx51-ecspi";
467 reg = <0x83fac000 0x4000>;
469 clocks = <&clks 53>, <&clks 54>;
470 clock-names = "ipg", "per";
475 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
476 reg = <0x83fb0000 0x4000>;
478 clocks = <&clks 56>, <&clks 56>;
479 clock-names = "ipg", "ahb";
480 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
484 #address-cells = <1>;
486 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
487 reg = <0x83fc0000 0x4000>;
489 clocks = <&clks 55>, <&clks 0>;
490 clock-names = "ipg", "per";
494 i2c@83fc4000 { /* I2C2 */
495 #address-cells = <1>;
497 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
498 reg = <0x83fc4000 0x4000>;
504 i2c@83fc8000 { /* I2C1 */
505 #address-cells = <1>;
507 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
508 reg = <0x83fc8000 0x4000>;
515 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
516 reg = <0x83fcc000 0x4000>;
519 fsl,fifo-depth = <15>;
520 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
525 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
526 reg = <0x83fd0000 0x4000>;
531 compatible = "fsl,imx51-nand";
532 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
539 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
540 reg = <0x83fe8000 0x4000>;
543 fsl,fifo-depth = <15>;
544 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
549 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
550 reg = <0x83fec000 0x4000>;
552 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
553 clock-names = "ipg", "ahb", "ptp";