arch/arm/boot/dts/imx6ul.dtsi

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6ul-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include "imx6ul-pinfunc.h"
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 ethernet0 = &fec1;
  18                 ethernet1 = &fec2;
  19                 gpio0 = &gpio1;
  20                 gpio1 = &gpio2;
  21                 gpio2 = &gpio3;
  22                 gpio3 = &gpio4;
  23                 gpio4 = &gpio5;
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 mmc0 = &usdhc1;
  29                 mmc1 = &usdhc2;
  30                 serial0 = &uart1;
  31                 serial1 = &uart2;
  32                 serial2 = &uart3;
  33                 serial3 = &uart4;
  34                 serial4 = &uart5;
  35                 serial5 = &uart6;
  36                 serial6 = &uart7;
  37                 serial7 = &uart8;
  38                 spi0 = &ecspi1;
  39                 spi1 = &ecspi2;
  40                 spi2 = &ecspi3;
  41                 spi3 = &ecspi4;
  42                 usbphy0 = &usbphy1;
  43                 usbphy1 = &usbphy2;
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 cpu0: cpu@0 {
  51                         compatible = "arm,cortex-a7";
  52                         device_type = "cpu";
  53                         reg = <0>;
  54                         clock-latency = <61036>; /* two CLK32 periods */
  55                         operating-points = <
  56                                 /* kHz  uV */
  57                                 528000  1250000
  58                                 396000  1150000
  59                                 198000  1150000
  60                         >;
  61                         fsl,soc-operating-points = <
  62                                 /* KHz  uV */
  63                                 528000  1250000
  64                                 396000  1150000
  65                                 198000  1150000
  66                         >;
  67                         clocks = <&clks IMX6UL_CLK_ARM>,
  68                                  <&clks IMX6UL_CLK_PLL2_BUS>,
  69                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
  70                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
  71                                  <&clks IMX6UL_CLK_STEP>,
  72                                  <&clks IMX6UL_CLK_PLL1_SW>,
  73                                  <&clks IMX6UL_CLK_PLL1_SYS>,
  74                                  <&clks IMX6UL_PLL1_BYPASS>,
  75                                  <&clks IMX6UL_CLK_PLL1>,
  76                                  <&clks IMX6UL_PLL1_BYPASS_SRC>,
  77                                  <&clks IMX6UL_CLK_OSC>;
  78                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
  79                                       "secondary_sel", "step", "pll1_sw",
  80                                       "pll1_sys", "pll1_bypass", "pll1",
  81                                       "pll1_bypass_src", "osc";
  82                         arm-supply = <&reg_arm>;
  83                         soc-supply = <&reg_soc>;
  84                 };
  85         };
  86
  87         intc: interrupt-controller@00a01000 {
  88                 compatible = "arm,cortex-a7-gic";
  89                 #interrupt-cells = <3>;
  90                 interrupt-controller;
  91                 reg = <0x00a01000 0x1000>,
  92                       <0x00a02000 0x1000>,
  93                       <0x00a04000 0x2000>,
  94                       <0x00a06000 0x2000>;
  95         };
  96
  97         ckil: clock-cli {
  98                 compatible = "fixed-clock";
  99                 #clock-cells = <0>;
 100                 clock-frequency = <32768>;
 101                 clock-output-names = "ckil";
 102         };
 103
 104         osc: clock-osc {
 105                 compatible = "fixed-clock";
 106                 #clock-cells = <0>;
 107                 clock-frequency = <24000000>;
 108                 clock-output-names = "osc";
 109         };
 110
 111         ipp_di0: clock-di0 {
 112                 compatible = "fixed-clock";
 113                 #clock-cells = <0>;
 114                 clock-frequency = <0>;
 115                 clock-output-names = "ipp_di0";
 116         };
 117
 118         ipp_di1: clock-di1 {
 119                 compatible = "fixed-clock";
 120                 #clock-cells = <0>;
 121                 clock-frequency = <0>;
 122                 clock-output-names = "ipp_di1";
 123         };
 124
 125         soc {
 126                 #address-cells = <1>;
 127                 #size-cells = <1>;
 128                 compatible = "simple-bus";
 129                 interrupt-parent = <&gpc>;
 130                 ranges;
 131
 132                 pmu {
 133                         compatible = "arm,cortex-a7-pmu";
 134                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 135                         status = "disabled";
 136                 };
 137
 138                 ocram: sram@00900000 {
 139                         compatible = "mmio-sram";
 140                         reg = <0x00900000 0x20000>;
 141                 };
 142
 143                 aips1: aips-bus@02000000 {
 144                         compatible = "fsl,aips-bus", "simple-bus";
 145                         #address-cells = <1>;
 146                         #size-cells = <1>;
 147                         reg = <0x02000000 0x100000>;
 148                         ranges;
 149
 150                         spba-bus@02000000 {
 151                                 compatible = "fsl,spba-bus", "simple-bus";
 152                                 #address-cells = <1>;
 153                                 #size-cells = <1>;
 154                                 reg = <0x02000000 0x40000>;
 155                                 ranges;
 156
 157                                 ecspi1: ecspi@02008000 {
 158                                         #address-cells = <1>;
 159                                         #size-cells = <0>;
 160                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 161                                         reg = <0x02008000 0x4000>;
 162                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 163                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
 164                                                  <&clks IMX6UL_CLK_ECSPI1>;
 165                                         clock-names = "ipg", "per";
 166                                         status = "disabled";
 167                                 };
 168
 169                                 ecspi2: ecspi@0200c000 {
 170                                         #address-cells = <1>;
 171                                         #size-cells = <0>;
 172                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 173                                         reg = <0x0200c000 0x4000>;
 174                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 175                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
 176                                                  <&clks IMX6UL_CLK_ECSPI2>;
 177                                         clock-names = "ipg", "per";
 178                                         status = "disabled";
 179                                 };
 180
 181                                 ecspi3: ecspi@02010000 {
 182                                         #address-cells = <1>;
 183                                         #size-cells = <0>;
 184                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 185                                         reg = <0x02010000 0x4000>;
 186                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 187                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
 188                                                  <&clks IMX6UL_CLK_ECSPI3>;
 189                                         clock-names = "ipg", "per";
 190                                         status = "disabled";
 191                                 };
 192
 193                                 ecspi4: ecspi@02014000 {
 194                                         #address-cells = <1>;
 195                                         #size-cells = <0>;
 196                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 197                                         reg = <0x02014000 0x4000>;
 198                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 199                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
 200                                                  <&clks IMX6UL_CLK_ECSPI4>;
 201                                         clock-names = "ipg", "per";
 202                                         status = "disabled";
 203                                 };
 204
 205                                 uart7: serial@02018000 {
 206                                         compatible = "fsl,imx6ul-uart",
 207                                                      "fsl,imx6q-uart";
 208                                         reg = <0x02018000 0x4000>;
 209                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 210                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
 211                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
 212                                         clock-names = "ipg", "per";
 213                                         status = "disabled";
 214                                 };
 215
 216                                 uart1: serial@02020000 {
 217                                         compatible = "fsl,imx6ul-uart",
 218                                                      "fsl,imx6q-uart";
 219                                         reg = <0x02020000 0x4000>;
 220                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 221                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
 222                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
 223                                         clock-names = "ipg", "per";
 224                                         status = "disabled";
 225                                 };
 226
 227                                 uart8: serial@02024000 {
 228                                         compatible = "fsl,imx6ul-uart",
 229                                                      "fsl,imx6q-uart";
 230                                         reg = <0x02024000 0x4000>;
 231                                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 232                                         clocks = <&clks IMX6UL_CLK_UART8_IPG>,
 233                                                  <&clks IMX6UL_CLK_UART8_SERIAL>;
 234                                         clock-names = "ipg", "per";
 235                                         status = "disabled";
 236                                 };
 237                         };
 238
 239                         gpt1: gpt@02098000 {
 240                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 241                                 reg = <0x02098000 0x4000>;
 242                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 243                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
 244                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
 245                                 clock-names = "ipg", "per";
 246                         };
 247
 248                         gpio1: gpio@0209c000 {
 249                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 250                                 reg = <0x0209c000 0x4000>;
 251                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 252                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 253                                 gpio-controller;
 254                                 #gpio-cells = <2>;
 255                                 interrupt-controller;
 256                                 #interrupt-cells = <2>;
 257                         };
 258
 259                         gpio2: gpio@020a0000 {
 260                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 261                                 reg = <0x020a0000 0x4000>;
 262                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 263                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 264                                 gpio-controller;
 265                                 #gpio-cells = <2>;
 266                                 interrupt-controller;
 267                                 #interrupt-cells = <2>;
 268                         };
 269
 270                         gpio3: gpio@020a4000 {
 271                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 272                                 reg = <0x020a4000 0x4000>;
 273                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 274                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 275                                 gpio-controller;
 276                                 #gpio-cells = <2>;
 277                                 interrupt-controller;
 278                                 #interrupt-cells = <2>;
 279                         };
 280
 281                         gpio4: gpio@020a8000 {
 282                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 283                                 reg = <0x020a8000 0x4000>;
 284                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 285                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 286                                 gpio-controller;
 287                                 #gpio-cells = <2>;
 288                                 interrupt-controller;
 289                                 #interrupt-cells = <2>;
 290                         };
 291
 292                         gpio5: gpio@020ac000 {
 293                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 294                                 reg = <0x020ac000 0x4000>;
 295                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 296                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 297                                 gpio-controller;
 298                                 #gpio-cells = <2>;
 299                                 interrupt-controller;
 300                                 #interrupt-cells = <2>;
 301                         };
 302
 303                         fec2: ethernet@020b4000 {
 304                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 305                                 reg = <0x020b4000 0x4000>;
 306                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 307                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 308                                 clocks = <&clks IMX6UL_CLK_ENET>,
 309                                          <&clks IMX6UL_CLK_ENET_AHB>,
 310                                          <&clks IMX6UL_CLK_ENET_PTP>,
 311                                          <&clks IMX6UL_CLK_ENET2_REF_125M>,
 312                                          <&clks IMX6UL_CLK_ENET2_REF_125M>;
 313                                 clock-names = "ipg", "ahb", "ptp",
 314                                               "enet_clk_ref", "enet_out";
 315                                 fsl,num-tx-queues=<1>;
 316                                 fsl,num-rx-queues=<1>;
 317                                 status = "disabled";
 318                         };
 319
 320                         wdog1: wdog@020bc000 {
 321                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 322                                 reg = <0x020bc000 0x4000>;
 323                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 324                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
 325                         };
 326
 327                         wdog2: wdog@020c0000 {
 328                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 329                                 reg = <0x020c0000 0x4000>;
 330                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 331                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
 332                                 status = "disabled";
 333                         };
 334
 335                         clks: ccm@020c4000 {
 336                                 compatible = "fsl,imx6ul-ccm";
 337                                 reg = <0x020c4000 0x4000>;
 338                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 339                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 340                                 #clock-cells = <1>;
 341                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 342                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 343                         };
 344
 345                         anatop: anatop@020c8000 {
 346                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
 347                                              "syscon", "simple-bus";
 348                                 reg = <0x020c8000 0x1000>;
 349                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 350                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 351                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 352
 353                                 reg_3p0: regulator-3p0@120 {
 354                                         compatible = "fsl,anatop-regulator";
 355                                         regulator-name = "vdd3p0";
 356                                         regulator-min-microvolt = <2625000>;
 357                                         regulator-max-microvolt = <3400000>;
 358                                         anatop-reg-offset = <0x120>;
 359                                         anatop-vol-bit-shift = <8>;
 360                                         anatop-vol-bit-width = <5>;
 361                                         anatop-min-bit-val = <0>;
 362                                         anatop-min-voltage = <2625000>;
 363                                         anatop-max-voltage = <3400000>;
 364                                         anatop-enable-bit = <0>;
 365                                 };
 366
 367                                 reg_arm: regulator-vddcore@140 {
 368                                         compatible = "fsl,anatop-regulator";
 369                                         regulator-name = "cpu";
 370                                         regulator-min-microvolt = <725000>;
 371                                         regulator-max-microvolt = <1450000>;
 372                                         regulator-always-on;
 373                                         anatop-reg-offset = <0x140>;
 374                                         anatop-vol-bit-shift = <0>;
 375                                         anatop-vol-bit-width = <5>;
 376                                         anatop-delay-reg-offset = <0x170>;
 377                                         anatop-delay-bit-shift = <24>;
 378                                         anatop-delay-bit-width = <2>;
 379                                         anatop-min-bit-val = <1>;
 380                                         anatop-min-voltage = <725000>;
 381                                         anatop-max-voltage = <1450000>;
 382                                 };
 383
 384                                 reg_soc: regulator-vddsoc@140 {
 385                                         compatible = "fsl,anatop-regulator";
 386                                         regulator-name = "vddsoc";
 387                                         regulator-min-microvolt = <725000>;
 388                                         regulator-max-microvolt = <1450000>;
 389                                         regulator-always-on;
 390                                         anatop-reg-offset = <0x140>;
 391                                         anatop-vol-bit-shift = <18>;
 392                                         anatop-vol-bit-width = <5>;
 393                                         anatop-delay-reg-offset = <0x170>;
 394                                         anatop-delay-bit-shift = <28>;
 395                                         anatop-delay-bit-width = <2>;
 396                                         anatop-min-bit-val = <1>;
 397                                         anatop-min-voltage = <725000>;
 398                                         anatop-max-voltage = <1450000>;
 399                                 };
 400                         };
 401
 402                         usbphy1: usbphy@020c9000 {
 403                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 404                                 reg = <0x020c9000 0x1000>;
 405                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 406                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
 407                                 phy-3p0-supply = <&reg_3p0>;
 408                                 fsl,anatop = <&anatop>;
 409                         };
 410
 411                         usbphy2: usbphy@020ca000 {
 412                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 413                                 reg = <0x020ca000 0x1000>;
 414                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 415                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
 416                                 phy-3p0-supply = <&reg_3p0>;
 417                                 fsl,anatop = <&anatop>;
 418                         };
 419
 420                         snvs: snvs@020cc000 {
 421                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 422                                 reg = <0x020cc000 0x4000>;
 423
 424                                 snvs_rtc: snvs-rtc-lp {
 425                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 426                                         regmap = <&snvs>;
 427                                         offset = <0x34>;
 428                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 429                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 430                                 };
 431
 432                                 snvs_pwrkey: snvs-powerkey {
 433                                         compatible = "fsl,sec-v4.0-pwrkey";
 434                                         regmap = <&snvs>;
 435                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 436                                         linux,keycode = <KEY_POWER>;
 437                                         wakeup-source;
 438                                 };
 439                         };
 440
 441                         epit1: epit@020d0000 {
 442                                 reg = <0x020d0000 0x4000>;
 443                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 444                         };
 445
 446                         epit2: epit@020d4000 {
 447                                 reg = <0x020d4000 0x4000>;
 448                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 449                         };
 450
 451                         src: src@020d8000 {
 452                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
 453                                 reg = <0x020d8000 0x4000>;
 454                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 455                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 456                                 #reset-cells = <1>;
 457                         };
 458
 459                         gpc: gpc@020dc000 {
 460                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
 461                                 reg = <0x020dc000 0x4000>;
 462                                 interrupt-controller;
 463                                 #interrupt-cells = <3>;
 464                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 465                                 interrupt-parent = <&intc>;
 466                         };
 467
 468                         iomuxc: iomuxc@020e0000 {
 469                                 compatible = "fsl,imx6ul-iomuxc";
 470                                 reg = <0x020e0000 0x4000>;
 471                         };
 472
 473                         gpr: iomuxc-gpr@020e4000 {
 474                                 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
 475                                 reg = <0x020e4000 0x4000>;
 476                         };
 477
 478                         gpt2: gpt@020e8000 {
 479                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 480                                 reg = <0x020e8000 0x4000>;
 481                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 482                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 483                                          <&clks IMX6UL_CLK_DUMMY>;
 484                                 clock-names = "ipg", "per";
 485                         };
 486
 487                         pwm5: pwm@020f0000 {
 488                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 489                                 reg = <0x020f0000 0x4000>;
 490                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 491                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 492                                          <&clks IMX6UL_CLK_DUMMY>;
 493                                 clock-names = "ipg", "per";
 494                                 #pwm-cells = <2>;
 495                         };
 496
 497                         pwm6: pwm@020f4000 {
 498                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 499                                 reg = <0x020f4000 0x4000>;
 500                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 501                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 502                                          <&clks IMX6UL_CLK_DUMMY>;
 503                                 clock-names = "ipg", "per";
 504                                 #pwm-cells = <2>;
 505                         };
 506
 507                         pwm7: pwm@020f8000 {
 508                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 509                                 reg = <0x020f8000 0x4000>;
 510                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 511                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 512                                          <&clks IMX6UL_CLK_DUMMY>;
 513                                 clock-names = "ipg", "per";
 514                                 #pwm-cells = <2>;
 515                         };
 516
 517                         pwm8: pwm@020fc000 {
 518                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 519                                 reg = <0x020fc000 0x4000>;
 520                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 521                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 522                                          <&clks IMX6UL_CLK_DUMMY>;
 523                                 clock-names = "ipg", "per";
 524                                 #pwm-cells = <2>;
 525                         };
 526                 };
 527
 528                 aips2: aips-bus@02100000 {
 529                         compatible = "fsl,aips-bus", "simple-bus";
 530                         #address-cells = <1>;
 531                         #size-cells = <1>;
 532                         reg = <0x02100000 0x100000>;
 533                         ranges;
 534
 535                         usbotg1: usb@02184000 {
 536                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 537                                 reg = <0x02184000 0x200>;
 538                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 539                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 540                                 fsl,usbphy = <&usbphy1>;
 541                                 fsl,usbmisc = <&usbmisc 0>;
 542                                 fsl,anatop = <&anatop>;
 543                                 status = "disabled";
 544                         };
 545
 546                         usbotg2: usb@02184200 {
 547                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 548                                 reg = <0x02184200 0x200>;
 549                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 550                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 551                                 fsl,usbphy = <&usbphy2>;
 552                                 fsl,usbmisc = <&usbmisc 1>;
 553                                 status = "disabled";
 554                         };
 555
 556                         usbmisc: usbmisc@02184800 {
 557                                 #index-cells = <1>;
 558                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
 559                                 reg = <0x02184800 0x200>;
 560                         };
 561
 562                         fec1: ethernet@02188000 {
 563                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 564                                 reg = <0x02188000 0x4000>;
 565                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 566                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 567                                 clocks = <&clks IMX6UL_CLK_ENET>,
 568                                          <&clks IMX6UL_CLK_ENET_AHB>,
 569                                          <&clks IMX6UL_CLK_ENET_PTP>,
 570                                          <&clks IMX6UL_CLK_ENET_REF>,
 571                                          <&clks IMX6UL_CLK_ENET_REF>;
 572                                 clock-names = "ipg", "ahb", "ptp",
 573                                               "enet_clk_ref", "enet_out";
 574                                 fsl,num-tx-queues=<1>;
 575                                 fsl,num-rx-queues=<1>;
 576                                 status = "disabled";
 577                         };
 578
 579                         usdhc1: usdhc@02190000 {
 580                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 581                                 reg = <0x02190000 0x4000>;
 582                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 583                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
 584                                          <&clks IMX6UL_CLK_USDHC1>,
 585                                          <&clks IMX6UL_CLK_USDHC1>;
 586                                 clock-names = "ipg", "ahb", "per";
 587                                 bus-width = <4>;
 588                                 status = "disabled";
 589                         };
 590
 591                         usdhc2: usdhc@02194000 {
 592                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 593                                 reg = <0x02194000 0x4000>;
 594                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 595                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
 596                                          <&clks IMX6UL_CLK_USDHC2>,
 597                                          <&clks IMX6UL_CLK_USDHC2>;
 598                                 clock-names = "ipg", "ahb", "per";
 599                                 bus-width = <4>;
 600                                 status = "disabled";
 601                         };
 602
 603                         i2c1: i2c@021a0000 {
 604                                 #address-cells = <1>;
 605                                 #size-cells = <0>;
 606                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 607                                 reg = <0x021a0000 0x4000>;
 608                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 609                                 clocks = <&clks IMX6UL_CLK_I2C1>;
 610                                 status = "disabled";
 611                         };
 612
 613                         i2c2: i2c@021a4000 {
 614                                 #address-cells = <1>;
 615                                 #size-cells = <0>;
 616                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 617                                 reg = <0x021a4000 0x4000>;
 618                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 619                                 clocks = <&clks IMX6UL_CLK_I2C2>;
 620                                 status = "disabled";
 621                         };
 622
 623                         i2c3: i2c@021a8000 {
 624                                 #address-cells = <1>;
 625                                 #size-cells = <0>;
 626                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 627                                 reg = <0x021a8000 0x4000>;
 628                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 629                                 clocks = <&clks IMX6UL_CLK_I2C3>;
 630                                 status = "disabled";
 631                         };
 632
 633                         qspi: qspi@021e0000 {
 634                                 #address-cells = <1>;
 635                                 #size-cells = <0>;
 636                                 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
 637                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
 638                                 reg-names = "QuadSPI", "QuadSPI-memory";
 639                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 640                                 clocks = <&clks IMX6UL_CLK_QSPI>,
 641                                          <&clks IMX6UL_CLK_QSPI>;
 642                                 clock-names = "qspi_en", "qspi";
 643                                 status = "disabled";
 644                         };
 645
 646                         uart2: serial@021e8000 {
 647                                 compatible = "fsl,imx6ul-uart",
 648                                              "fsl,imx6q-uart";
 649                                 reg = <0x021e8000 0x4000>;
 650                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 651                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
 652                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
 653                                 clock-names = "ipg", "per";
 654                                 status = "disabled";
 655                         };
 656
 657                         uart3: serial@021ec000 {
 658                                 compatible = "fsl,imx6ul-uart",
 659                                              "fsl,imx6q-uart";
 660                                 reg = <0x021ec000 0x4000>;
 661                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 662                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
 663                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
 664                                 clock-names = "ipg", "per";
 665                                 status = "disabled";
 666                         };
 667
 668                         uart4: serial@021f0000 {
 669                                 compatible = "fsl,imx6ul-uart",
 670                                              "fsl,imx6q-uart";
 671                                 reg = <0x021f0000 0x4000>;
 672                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 673                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
 674                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
 675                                 clock-names = "ipg", "per";
 676                                 status = "disabled";
 677                         };
 678
 679                         uart5: serial@021f4000 {
 680                                 compatible = "fsl,imx6ul-uart",
 681                                              "fsl,imx6q-uart";
 682                                 reg = <0x021f4000 0x4000>;
 683                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 684                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
 685                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
 686                                 clock-names = "ipg", "per";
 687                                 status = "disabled";
 688                         };
 689
 690                         i2c4: i2c@021f8000 {
 691                                 #address-cells = <1>;
 692                                 #size-cells = <0>;
 693                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 694                                 reg = <0x021f8000 0x4000>;
 695                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 696                                 clocks = <&clks IMX6UL_CLK_I2C4>;
 697                                 status = "disabled";
 698                         };
 699
 700                         uart6: serial@021fc000 {
 701                                 compatible = "fsl,imx6ul-uart",
 702                                              "fsl,imx6q-uart";
 703                                 reg = <0x021fc000 0x4000>;
 704                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 705                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
 706                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
 707                                 clock-names = "ipg", "per";
 708                                 status = "disabled";
 709                         };
 710                 };
 711         };
 712 };