2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
11 * Carveout for multimedia usecases
12 * It should be the last 48MB of the first 512MB memory part
13 * In theory, it should not even exist. That zone should be reserved
14 * dynamically during the .reserve callback.
16 /memreserve/ 0x9d000000 0x03000000;
18 /include/ "skeleton.dtsi"
24 compatible = "ti,omap5";
25 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a15";
47 compatible = "arm,cortex-a15";
53 compatible = "arm,armv7-timer";
54 /* PPI secure/nonsecure IRQ, active low level-sensitive */
55 interrupts = <1 13 0x308>,
59 clock-frequency = <6144000>;
62 gic: interrupt-controller@48211000 {
63 compatible = "arm,cortex-a15-gic";
65 #interrupt-cells = <3>;
66 reg = <0x48211000 0x1000>,
73 * The soc node represents the soc top level view. It is uses for IPs
74 * that are not memory mapped in the MPU view or for the MPU itself.
77 compatible = "ti,omap-infra";
79 compatible = "ti,omap5-mpu";
85 * XXX: Use a flat representation of the OMAP3 interconnect.
86 * The real OMAP interconnect network is quite complex.
87 * Since that will not bring real advantage to represent that in DT for
88 * the moment, just use a fake OCP bus entry to represent the whole bus
92 compatible = "ti,omap4-l3-noc", "simple-bus";
96 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
97 reg = <0x44000000 0x2000>,
100 interrupts = <0 9 0x4>,
103 counter32k: counter@4ae04000 {
104 compatible = "ti,omap-counter32k";
105 reg = <0x4ae04000 0x40>;
106 ti,hwmods = "counter_32k";
109 omap5_pmx_core: pinmux@4a002840 {
110 compatible = "ti,omap4-padconf", "pinctrl-single";
111 reg = <0x4a002840 0x01b6>;
112 #address-cells = <1>;
114 pinctrl-single,register-width = <16>;
115 pinctrl-single,function-mask = <0x7fff>;
117 omap5_pmx_wkup: pinmux@4ae0c840 {
118 compatible = "ti,omap4-padconf", "pinctrl-single";
119 reg = <0x4ae0c840 0x0038>;
120 #address-cells = <1>;
122 pinctrl-single,register-width = <16>;
123 pinctrl-single,function-mask = <0x7fff>;
126 sdma: dma-controller@4a056000 {
127 compatible = "ti,omap4430-sdma";
128 reg = <0x4a056000 0x1000>;
129 interrupts = <0 12 0x4>,
134 #dma-channels = <32>;
135 #dma-requests = <127>;
138 gpio1: gpio@4ae10000 {
139 compatible = "ti,omap4-gpio";
140 reg = <0x4ae10000 0x200>;
141 interrupts = <0 29 0x4>;
146 interrupt-controller;
147 #interrupt-cells = <2>;
150 gpio2: gpio@48055000 {
151 compatible = "ti,omap4-gpio";
152 reg = <0x48055000 0x200>;
153 interrupts = <0 30 0x4>;
157 interrupt-controller;
158 #interrupt-cells = <2>;
161 gpio3: gpio@48057000 {
162 compatible = "ti,omap4-gpio";
163 reg = <0x48057000 0x200>;
164 interrupts = <0 31 0x4>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
172 gpio4: gpio@48059000 {
173 compatible = "ti,omap4-gpio";
174 reg = <0x48059000 0x200>;
175 interrupts = <0 32 0x4>;
179 interrupt-controller;
180 #interrupt-cells = <2>;
183 gpio5: gpio@4805b000 {
184 compatible = "ti,omap4-gpio";
185 reg = <0x4805b000 0x200>;
186 interrupts = <0 33 0x4>;
190 interrupt-controller;
191 #interrupt-cells = <2>;
194 gpio6: gpio@4805d000 {
195 compatible = "ti,omap4-gpio";
196 reg = <0x4805d000 0x200>;
197 interrupts = <0 34 0x4>;
201 interrupt-controller;
202 #interrupt-cells = <2>;
205 gpio7: gpio@48051000 {
206 compatible = "ti,omap4-gpio";
207 reg = <0x48051000 0x200>;
208 interrupts = <0 35 0x4>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
216 gpio8: gpio@48053000 {
217 compatible = "ti,omap4-gpio";
218 reg = <0x48053000 0x200>;
219 interrupts = <0 121 0x4>;
223 interrupt-controller;
224 #interrupt-cells = <2>;
227 gpmc: gpmc@50000000 {
228 compatible = "ti,omap4430-gpmc";
229 reg = <0x50000000 0x1000>;
230 #address-cells = <2>;
232 interrupts = <0 20 0x4>;
234 gpmc,num-waitpins = <4>;
239 compatible = "ti,omap4-i2c";
240 reg = <0x48070000 0x100>;
241 interrupts = <0 56 0x4>;
242 #address-cells = <1>;
248 compatible = "ti,omap4-i2c";
249 reg = <0x48072000 0x100>;
250 interrupts = <0 57 0x4>;
251 #address-cells = <1>;
257 compatible = "ti,omap4-i2c";
258 reg = <0x48060000 0x100>;
259 interrupts = <0 61 0x4>;
260 #address-cells = <1>;
266 compatible = "ti,omap4-i2c";
267 reg = <0x4807a000 0x100>;
268 interrupts = <0 62 0x4>;
269 #address-cells = <1>;
275 compatible = "ti,omap4-i2c";
276 reg = <0x4807c000 0x100>;
277 interrupts = <0 60 0x4>;
278 #address-cells = <1>;
283 mcspi1: spi@48098000 {
284 compatible = "ti,omap4-mcspi";
285 reg = <0x48098000 0x200>;
286 interrupts = <0 65 0x4>;
287 #address-cells = <1>;
289 ti,hwmods = "mcspi1";
299 dma-names = "tx0", "rx0", "tx1", "rx1",
300 "tx2", "rx2", "tx3", "rx3";
303 mcspi2: spi@4809a000 {
304 compatible = "ti,omap4-mcspi";
305 reg = <0x4809a000 0x200>;
306 interrupts = <0 66 0x4>;
307 #address-cells = <1>;
309 ti,hwmods = "mcspi2";
315 dma-names = "tx0", "rx0", "tx1", "rx1";
318 mcspi3: spi@480b8000 {
319 compatible = "ti,omap4-mcspi";
320 reg = <0x480b8000 0x200>;
321 interrupts = <0 91 0x4>;
322 #address-cells = <1>;
324 ti,hwmods = "mcspi3";
326 dmas = <&sdma 15>, <&sdma 16>;
327 dma-names = "tx0", "rx0";
330 mcspi4: spi@480ba000 {
331 compatible = "ti,omap4-mcspi";
332 reg = <0x480ba000 0x200>;
333 interrupts = <0 48 0x4>;
334 #address-cells = <1>;
336 ti,hwmods = "mcspi4";
338 dmas = <&sdma 70>, <&sdma 71>;
339 dma-names = "tx0", "rx0";
342 uart1: serial@4806a000 {
343 compatible = "ti,omap4-uart";
344 reg = <0x4806a000 0x100>;
345 interrupts = <0 72 0x4>;
347 clock-frequency = <48000000>;
350 uart2: serial@4806c000 {
351 compatible = "ti,omap4-uart";
352 reg = <0x4806c000 0x100>;
353 interrupts = <0 73 0x4>;
355 clock-frequency = <48000000>;
358 uart3: serial@48020000 {
359 compatible = "ti,omap4-uart";
360 reg = <0x48020000 0x100>;
361 interrupts = <0 74 0x4>;
363 clock-frequency = <48000000>;
366 uart4: serial@4806e000 {
367 compatible = "ti,omap4-uart";
368 reg = <0x4806e000 0x100>;
369 interrupts = <0 70 0x4>;
371 clock-frequency = <48000000>;
374 uart5: serial@48066000 {
375 compatible = "ti,omap4-uart";
376 reg = <0x48066000 0x100>;
377 interrupts = <0 105 0x4>;
379 clock-frequency = <48000000>;
382 uart6: serial@48068000 {
383 compatible = "ti,omap4-uart";
384 reg = <0x48068000 0x100>;
385 interrupts = <0 106 0x4>;
387 clock-frequency = <48000000>;
391 compatible = "ti,omap4-hsmmc";
392 reg = <0x4809c000 0x400>;
393 interrupts = <0 83 0x4>;
396 ti,needs-special-reset;
397 dmas = <&sdma 61>, <&sdma 62>;
398 dma-names = "tx", "rx";
402 compatible = "ti,omap4-hsmmc";
403 reg = <0x480b4000 0x400>;
404 interrupts = <0 86 0x4>;
406 ti,needs-special-reset;
407 dmas = <&sdma 47>, <&sdma 48>;
408 dma-names = "tx", "rx";
412 compatible = "ti,omap4-hsmmc";
413 reg = <0x480ad000 0x400>;
414 interrupts = <0 94 0x4>;
416 ti,needs-special-reset;
417 dmas = <&sdma 77>, <&sdma 78>;
418 dma-names = "tx", "rx";
422 compatible = "ti,omap4-hsmmc";
423 reg = <0x480d1000 0x400>;
424 interrupts = <0 96 0x4>;
426 ti,needs-special-reset;
427 dmas = <&sdma 57>, <&sdma 58>;
428 dma-names = "tx", "rx";
432 compatible = "ti,omap4-hsmmc";
433 reg = <0x480d5000 0x400>;
434 interrupts = <0 59 0x4>;
436 ti,needs-special-reset;
437 dmas = <&sdma 59>, <&sdma 60>;
438 dma-names = "tx", "rx";
441 keypad: keypad@4ae1c000 {
442 compatible = "ti,omap4-keypad";
443 reg = <0x4ae1c000 0x400>;
447 mcpdm: mcpdm@40132000 {
448 compatible = "ti,omap4-mcpdm";
449 reg = <0x40132000 0x7f>, /* MPU private access */
450 <0x49032000 0x7f>; /* L3 Interconnect */
451 reg-names = "mpu", "dma";
452 interrupts = <0 112 0x4>;
456 dma-names = "up_link", "dn_link";
459 dmic: dmic@4012e000 {
460 compatible = "ti,omap4-dmic";
461 reg = <0x4012e000 0x7f>, /* MPU private access */
462 <0x4902e000 0x7f>; /* L3 Interconnect */
463 reg-names = "mpu", "dma";
464 interrupts = <0 114 0x4>;
467 dma-names = "up_link";
470 mcbsp1: mcbsp@40122000 {
471 compatible = "ti,omap4-mcbsp";
472 reg = <0x40122000 0xff>, /* MPU private access */
473 <0x49022000 0xff>; /* L3 Interconnect */
474 reg-names = "mpu", "dma";
475 interrupts = <0 17 0x4>;
476 interrupt-names = "common";
477 ti,buffer-size = <128>;
478 ti,hwmods = "mcbsp1";
481 dma-names = "tx", "rx";
484 mcbsp2: mcbsp@40124000 {
485 compatible = "ti,omap4-mcbsp";
486 reg = <0x40124000 0xff>, /* MPU private access */
487 <0x49024000 0xff>; /* L3 Interconnect */
488 reg-names = "mpu", "dma";
489 interrupts = <0 22 0x4>;
490 interrupt-names = "common";
491 ti,buffer-size = <128>;
492 ti,hwmods = "mcbsp2";
495 dma-names = "tx", "rx";
498 mcbsp3: mcbsp@40126000 {
499 compatible = "ti,omap4-mcbsp";
500 reg = <0x40126000 0xff>, /* MPU private access */
501 <0x49026000 0xff>; /* L3 Interconnect */
502 reg-names = "mpu", "dma";
503 interrupts = <0 23 0x4>;
504 interrupt-names = "common";
505 ti,buffer-size = <128>;
506 ti,hwmods = "mcbsp3";
509 dma-names = "tx", "rx";
512 timer1: timer@4ae18000 {
513 compatible = "ti,omap5430-timer";
514 reg = <0x4ae18000 0x80>;
515 interrupts = <0 37 0x4>;
516 ti,hwmods = "timer1";
520 timer2: timer@48032000 {
521 compatible = "ti,omap5430-timer";
522 reg = <0x48032000 0x80>;
523 interrupts = <0 38 0x4>;
524 ti,hwmods = "timer2";
527 timer3: timer@48034000 {
528 compatible = "ti,omap5430-timer";
529 reg = <0x48034000 0x80>;
530 interrupts = <0 39 0x4>;
531 ti,hwmods = "timer3";
534 timer4: timer@48036000 {
535 compatible = "ti,omap5430-timer";
536 reg = <0x48036000 0x80>;
537 interrupts = <0 40 0x4>;
538 ti,hwmods = "timer4";
541 timer5: timer@40138000 {
542 compatible = "ti,omap5430-timer";
543 reg = <0x40138000 0x80>,
545 interrupts = <0 41 0x4>;
546 ti,hwmods = "timer5";
550 timer6: timer@4013a000 {
551 compatible = "ti,omap5430-timer";
552 reg = <0x4013a000 0x80>,
554 interrupts = <0 42 0x4>;
555 ti,hwmods = "timer6";
560 timer7: timer@4013c000 {
561 compatible = "ti,omap5430-timer";
562 reg = <0x4013c000 0x80>,
564 interrupts = <0 43 0x4>;
565 ti,hwmods = "timer7";
569 timer8: timer@4013e000 {
570 compatible = "ti,omap5430-timer";
571 reg = <0x4013e000 0x80>,
573 interrupts = <0 44 0x4>;
574 ti,hwmods = "timer8";
579 timer9: timer@4803e000 {
580 compatible = "ti,omap5430-timer";
581 reg = <0x4803e000 0x80>;
582 interrupts = <0 45 0x4>;
583 ti,hwmods = "timer9";
586 timer10: timer@48086000 {
587 compatible = "ti,omap5430-timer";
588 reg = <0x48086000 0x80>;
589 interrupts = <0 46 0x4>;
590 ti,hwmods = "timer10";
593 timer11: timer@48088000 {
594 compatible = "ti,omap5430-timer";
595 reg = <0x48088000 0x80>;
596 interrupts = <0 47 0x4>;
597 ti,hwmods = "timer11";
602 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
603 reg = <0x4ae14000 0x80>;
604 interrupts = <0 80 0x4>;
605 ti,hwmods = "wd_timer2";
608 emif1: emif@0x4c000000 {
609 compatible = "ti,emif-4d5";
611 phy-type = <2>; /* DDR PHY type: Intelli PHY */
612 reg = <0x4c000000 0x400>;
613 interrupts = <0 110 0x4>;
614 hw-caps-read-idle-ctrl;
615 hw-caps-ll-interface;
619 emif2: emif@0x4d000000 {
620 compatible = "ti,emif-4d5";
622 phy-type = <2>; /* DDR PHY type: Intelli PHY */
623 reg = <0x4d000000 0x400>;
624 interrupts = <0 111 0x4>;
625 hw-caps-read-idle-ctrl;
626 hw-caps-ll-interface;
630 omap_control_usb: omap-control-usb@4a002300 {
631 compatible = "ti,omap-control-usb";
632 reg = <0x4a002300 0x4>,
634 reg-names = "control_dev_conf", "phy_power_usb";
639 compatible = "ti,dwc3";
640 ti,hwmods = "usb_otg_ss";
641 reg = <0x4a020000 0x1000>;
642 interrupts = <0 93 4>;
643 #address-cells = <1>;
648 compatible = "synopsys,dwc3";
649 reg = <0x4a030000 0x1000>;
650 interrupts = <0 92 4>;
651 usb-phy = <&usb2_phy>, <&usb3_phy>;
657 compatible = "ti,omap-ocp2scp";
658 #address-cells = <1>;
661 ti,hwmods = "ocp2scp1";
662 usb2_phy: usb2phy@4a084000 {
663 compatible = "ti,omap-usb2";
664 reg = <0x4a084000 0x7c>;
665 ctrl-module = <&omap_control_usb>;
668 usb3_phy: usb3phy@4a084400 {
669 compatible = "ti,omap-usb3";
670 reg = <0x4a084400 0x80>,
673 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
674 ctrl-module = <&omap_control_usb>;