arch/arm/boot/dts/qcom-msm8974.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/irq.h>
   4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
   5 #include "skeleton.dtsi"
   6
   7 / {
   8         model = "Qualcomm MSM8974";
   9         compatible = "qcom,msm8974";
  10         interrupt-parent = <&intc>;
  11
  12         reserved-memory {
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15                 ranges;
  16
  17                 smem_region: smem@fa00000 {
  18                         reg = <0xfa00000 0x200000>;
  19                         no-map;
  20                 };
  21         };
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26                 interrupts = <1 9 0xf04>;
  27
  28                 cpu@0 {
  29                         compatible = "qcom,krait";
  30                         enable-method = "qcom,kpss-acc-v2";
  31                         device_type = "cpu";
  32                         reg = <0>;
  33                         next-level-cache = <&L2>;
  34                         qcom,acc = <&acc0>;
  35                         qcom,saw = <&saw0>;
  36                         cpu-idle-states = <&CPU_SPC>;
  37                 };
  38
  39                 cpu@1 {
  40                         compatible = "qcom,krait";
  41                         enable-method = "qcom,kpss-acc-v2";
  42                         device_type = "cpu";
  43                         reg = <1>;
  44                         next-level-cache = <&L2>;
  45                         qcom,acc = <&acc1>;
  46                         qcom,saw = <&saw1>;
  47                         cpu-idle-states = <&CPU_SPC>;
  48                 };
  49
  50                 cpu@2 {
  51                         compatible = "qcom,krait";
  52                         enable-method = "qcom,kpss-acc-v2";
  53                         device_type = "cpu";
  54                         reg = <2>;
  55                         next-level-cache = <&L2>;
  56                         qcom,acc = <&acc2>;
  57                         qcom,saw = <&saw2>;
  58                         cpu-idle-states = <&CPU_SPC>;
  59                 };
  60
  61                 cpu@3 {
  62                         compatible = "qcom,krait";
  63                         enable-method = "qcom,kpss-acc-v2";
  64                         device_type = "cpu";
  65                         reg = <3>;
  66                         next-level-cache = <&L2>;
  67                         qcom,acc = <&acc3>;
  68                         qcom,saw = <&saw3>;
  69                         cpu-idle-states = <&CPU_SPC>;
  70                 };
  71
  72                 L2: l2-cache {
  73                         compatible = "cache";
  74                         cache-level = <2>;
  75                         qcom,saw = <&saw_l2>;
  76                 };
  77
  78                 idle-states {
  79                         CPU_SPC: spc {
  80                                 compatible = "qcom,idle-state-spc",
  81                                                 "arm,idle-state";
  82                                 entry-latency-us = <150>;
  83                                 exit-latency-us = <200>;
  84                                 min-residency-us = <2000>;
  85                         };
  86                 };
  87         };
  88
  89         cpu-pmu {
  90                 compatible = "qcom,krait-pmu";
  91                 interrupts = <1 7 0xf04>;
  92         };
  93
  94         timer {
  95                 compatible = "arm,armv7-timer";
  96                 interrupts = <1 2 0xf08>,
  97                              <1 3 0xf08>,
  98                              <1 4 0xf08>,
  99                              <1 1 0xf08>;
 100                 clock-frequency = <19200000>;
 101         };
 102
 103         soc: soc {
 104                 #address-cells = <1>;
 105                 #size-cells = <1>;
 106                 ranges;
 107                 compatible = "simple-bus";
 108
 109                 intc: interrupt-controller@f9000000 {
 110                         compatible = "qcom,msm-qgic2";
 111                         interrupt-controller;
 112                         #interrupt-cells = <3>;
 113                         reg = <0xf9000000 0x1000>,
 114                               <0xf9002000 0x1000>;
 115                 };
 116
 117                 apcs: syscon@f9011000 {
 118                         compatible = "syscon";
 119                         reg = <0xf9011000 0x1000>;
 120                 };
 121
 122                 timer@f9020000 {
 123                         #address-cells = <1>;
 124                         #size-cells = <1>;
 125                         ranges;
 126                         compatible = "arm,armv7-timer-mem";
 127                         reg = <0xf9020000 0x1000>;
 128                         clock-frequency = <19200000>;
 129
 130                         frame@f9021000 {
 131                                 frame-number = <0>;
 132                                 interrupts = <0 8 0x4>,
 133                                              <0 7 0x4>;
 134                                 reg = <0xf9021000 0x1000>,
 135                                       <0xf9022000 0x1000>;
 136                         };
 137
 138                         frame@f9023000 {
 139                                 frame-number = <1>;
 140                                 interrupts = <0 9 0x4>;
 141                                 reg = <0xf9023000 0x1000>;
 142                                 status = "disabled";
 143                         };
 144
 145                         frame@f9024000 {
 146                                 frame-number = <2>;
 147                                 interrupts = <0 10 0x4>;
 148                                 reg = <0xf9024000 0x1000>;
 149                                 status = "disabled";
 150                         };
 151
 152                         frame@f9025000 {
 153                                 frame-number = <3>;
 154                                 interrupts = <0 11 0x4>;
 155                                 reg = <0xf9025000 0x1000>;
 156                                 status = "disabled";
 157                         };
 158
 159                         frame@f9026000 {
 160                                 frame-number = <4>;
 161                                 interrupts = <0 12 0x4>;
 162                                 reg = <0xf9026000 0x1000>;
 163                                 status = "disabled";
 164                         };
 165
 166                         frame@f9027000 {
 167                                 frame-number = <5>;
 168                                 interrupts = <0 13 0x4>;
 169                                 reg = <0xf9027000 0x1000>;
 170                                 status = "disabled";
 171                         };
 172
 173                         frame@f9028000 {
 174                                 frame-number = <6>;
 175                                 interrupts = <0 14 0x4>;
 176                                 reg = <0xf9028000 0x1000>;
 177                                 status = "disabled";
 178                         };
 179                 };
 180
 181                 saw0: power-controller@f9089000 {
 182                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 183                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
 184                 };
 185
 186                 saw1: power-controller@f9099000 {
 187                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 188                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
 189                 };
 190
 191                 saw2: power-controller@f90a9000 {
 192                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 193                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
 194                 };
 195
 196                 saw3: power-controller@f90b9000 {
 197                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 198                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
 199                 };
 200
 201                 saw_l2: power-controller@f9012000 {
 202                         compatible = "qcom,saw2";
 203                         reg = <0xf9012000 0x1000>;
 204                         regulator;
 205                 };
 206
 207                 acc0: clock-controller@f9088000 {
 208                         compatible = "qcom,kpss-acc-v2";
 209                         reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 210                 };
 211
 212                 acc1: clock-controller@f9098000 {
 213                         compatible = "qcom,kpss-acc-v2";
 214                         reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 215                 };
 216
 217                 acc2: clock-controller@f90a8000 {
 218                         compatible = "qcom,kpss-acc-v2";
 219                         reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 220                 };
 221
 222                 acc3: clock-controller@f90b8000 {
 223                         compatible = "qcom,kpss-acc-v2";
 224                         reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 225                 };
 226
 227                 restart@fc4ab000 {
 228                         compatible = "qcom,pshold";
 229                         reg = <0xfc4ab000 0x4>;
 230                 };
 231
 232                 gcc: clock-controller@fc400000 {
 233                         compatible = "qcom,gcc-msm8974";
 234                         #clock-cells = <1>;
 235                         #reset-cells = <1>;
 236                         #power-domain-cells = <1>;
 237                         reg = <0xfc400000 0x4000>;
 238                 };
 239
 240                 tcsr_mutex_block: syscon@fd484000 {
 241                         compatible = "syscon";
 242                         reg = <0xfd484000 0x2000>;
 243                 };
 244
 245                 mmcc: clock-controller@fd8c0000 {
 246                         compatible = "qcom,mmcc-msm8974";
 247                         #clock-cells = <1>;
 248                         #reset-cells = <1>;
 249                         #power-domain-cells = <1>;
 250                         reg = <0xfd8c0000 0x6000>;
 251                 };
 252
 253                 tcsr_mutex: tcsr-mutex {
 254                         compatible = "qcom,tcsr-mutex";
 255                         syscon = <&tcsr_mutex_block 0 0x80>;
 256
 257                         #hwlock-cells = <1>;
 258                 };
 259
 260                 smem@fa00000 {
 261                         compatible = "qcom,smem";
 262
 263                         memory-region = <&smem_region>;
 264                         reg = <0xfc428000 0x4000>;
 265
 266                         hwlocks = <&tcsr_mutex 3>;
 267                 };
 268
 269                 blsp1_uart2: serial@f991e000 {
 270                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 271                         reg = <0xf991e000 0x1000>;
 272                         interrupts = <0 108 0x0>;
 273                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 274                         clock-names = "core", "iface";
 275                         status = "disabled";
 276                 };
 277
 278                 sdhci@f9824900 {
 279                         compatible = "qcom,sdhci-msm-v4";
 280                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 281                         reg-names = "hc_mem", "core_mem";
 282                         interrupts = <0 123 0>, <0 138 0>;
 283                         interrupt-names = "hc_irq", "pwr_irq";
 284                         clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
 285                         clock-names = "core", "iface";
 286                         status = "disabled";
 287                 };
 288
 289                 sdhci@f98a4900 {
 290                         compatible = "qcom,sdhci-msm-v4";
 291                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 292                         reg-names = "hc_mem", "core_mem";
 293                         interrupts = <0 125 0>, <0 221 0>;
 294                         interrupt-names = "hc_irq", "pwr_irq";
 295                         clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
 296                         clock-names = "core", "iface";
 297                         status = "disabled";
 298                 };
 299
 300                 rng@f9bff000 {
 301                         compatible = "qcom,prng";
 302                         reg = <0xf9bff000 0x200>;
 303                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 304                         clock-names = "core";
 305                 };
 306
 307                 msmgpio: pinctrl@fd510000 {
 308                         compatible = "qcom,msm8974-pinctrl";
 309                         reg = <0xfd510000 0x4000>;
 310                         gpio-controller;
 311                         #gpio-cells = <2>;
 312                         interrupt-controller;
 313                         #interrupt-cells = <2>;
 314                         interrupts = <0 208 0>;
 315                 };
 316
 317                 blsp_i2c11: i2c@f9967000 {
 318                         status = "disabled";
 319                         compatible = "qcom,i2c-qup-v2.1.1";
 320                         reg = <0xf9967000 0x1000>;
 321                         interrupts = <0 105 IRQ_TYPE_NONE>;
 322                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 323                         clock-names = "core", "iface";
 324                         #address-cells = <1>;
 325                         #size-cells = <0>;
 326                 };
 327
 328                 spmi_bus: spmi@fc4cf000 {
 329                         compatible = "qcom,spmi-pmic-arb";
 330                         reg-names = "core", "intr", "cnfg";
 331                         reg = <0xfc4cf000 0x1000>,
 332                               <0xfc4cb000 0x1000>,
 333                               <0xfc4ca000 0x1000>;
 334                         interrupt-names = "periph_irq";
 335                         interrupts = <0 190 0>;
 336                         qcom,ee = <0>;
 337                         qcom,channel = <0>;
 338                         #address-cells = <2>;
 339                         #size-cells = <0>;
 340                         interrupt-controller;
 341                         #interrupt-cells = <4>;
 342                 };
 343         };
 344
 345         smd {
 346                 compatible = "qcom,smd";
 347
 348                 rpm {
 349                         interrupts = <0 168 1>;
 350                         qcom,ipc = <&apcs 8 0>;
 351                         qcom,smd-edge = <15>;
 352
 353                         rpm_requests {
 354                                 compatible = "qcom,rpm-msm8974";
 355                                 qcom,smd-channels = "rpm_requests";
 356
 357                                 pm8841-regulators {
 358                                         compatible = "qcom,rpm-pm8841-regulators";
 359
 360                                         pm8841_s1: s1 {};
 361                                         pm8841_s2: s2 {};
 362                                         pm8841_s3: s3 {};
 363                                         pm8841_s4: s4 {};
 364                                         pm8841_s5: s5 {};
 365                                         pm8841_s6: s6 {};
 366                                         pm8841_s7: s7 {};
 367                                         pm8841_s8: s8 {};
 368                                 };
 369
 370                                 pm8941-regulators {
 371                                         compatible = "qcom,rpm-pm8941-regulators";
 372
 373                                         pm8941_s1: s1 {};
 374                                         pm8941_s2: s2 {};
 375                                         pm8941_s3: s3 {};
 376                                         pm8941_5v: s4 {};
 377
 378                                         pm8941_l1: l1 {};
 379                                         pm8941_l2: l2 {};
 380                                         pm8941_l3: l3 {};
 381                                         pm8941_l4: l4 {};
 382                                         pm8941_l5: l5 {};
 383                                         pm8941_l6: l6 {};
 384                                         pm8941_l7: l7 {};
 385                                         pm8941_l8: l8 {};
 386                                         pm8941_l9: l9 {};
 387                                         pm8941_l10: l10 {};
 388                                         pm8941_l11: l11 {};
 389                                         pm8941_l12: l12 {};
 390                                         pm8941_l13: l13 {};
 391                                         pm8941_l14: l14 {};
 392                                         pm8941_l15: l15 {};
 393                                         pm8941_l16: l16 {};
 394                                         pm8941_l17: l17 {};
 395                                         pm8941_l18: l18 {};
 396                                         pm8941_l19: l19 {};
 397                                         pm8941_l20: l20 {};
 398                                         pm8941_l21: l21 {};
 399                                         pm8941_l22: l22 {};
 400                                         pm8941_l23: l23 {};
 401                                         pm8941_l24: l24 {};
 402
 403                                         pm8941_lvs1: lvs1 {};
 404                                         pm8941_lvs2: lvs2 {};
 405                                         pm8941_lvs3: lvs3 {};
 406
 407                                         pm8941_5vs1: 5vs1 {};
 408                                         pm8941_5vs2: 5vs2 {};
 409                                 };
 410                         };
 411                 };
 412         };
 413 };