arch/arm/boot/dts/qcom-msm8974.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/irq.h>
   4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
   5 #include "skeleton.dtsi"
   6
   7 / {
   8         model = "Qualcomm MSM8974";
   9         compatible = "qcom,msm8974";
  10         interrupt-parent = <&intc>;
  11
  12         reserved-memory {
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15                 ranges;
  16
  17                 smem_region: smem@fa00000 {
  18                         reg = <0xfa00000 0x200000>;
  19                         no-map;
  20                 };
  21         };
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26                 interrupts = <1 9 0xf04>;
  27
  28                 cpu@0 {
  29                         compatible = "qcom,krait";
  30                         enable-method = "qcom,kpss-acc-v2";
  31                         device_type = "cpu";
  32                         reg = <0>;
  33                         next-level-cache = <&L2>;
  34                         qcom,acc = <&acc0>;
  35                         qcom,saw = <&saw0>;
  36                         cpu-idle-states = <&CPU_SPC>;
  37                 };
  38
  39                 cpu@1 {
  40                         compatible = "qcom,krait";
  41                         enable-method = "qcom,kpss-acc-v2";
  42                         device_type = "cpu";
  43                         reg = <1>;
  44                         next-level-cache = <&L2>;
  45                         qcom,acc = <&acc1>;
  46                         qcom,saw = <&saw1>;
  47                         cpu-idle-states = <&CPU_SPC>;
  48                 };
  49
  50                 cpu@2 {
  51                         compatible = "qcom,krait";
  52                         enable-method = "qcom,kpss-acc-v2";
  53                         device_type = "cpu";
  54                         reg = <2>;
  55                         next-level-cache = <&L2>;
  56                         qcom,acc = <&acc2>;
  57                         qcom,saw = <&saw2>;
  58                         cpu-idle-states = <&CPU_SPC>;
  59                 };
  60
  61                 cpu@3 {
  62                         compatible = "qcom,krait";
  63                         enable-method = "qcom,kpss-acc-v2";
  64                         device_type = "cpu";
  65                         reg = <3>;
  66                         next-level-cache = <&L2>;
  67                         qcom,acc = <&acc3>;
  68                         qcom,saw = <&saw3>;
  69                         cpu-idle-states = <&CPU_SPC>;
  70                 };
  71
  72                 L2: l2-cache {
  73                         compatible = "cache";
  74                         cache-level = <2>;
  75                         qcom,saw = <&saw_l2>;
  76                 };
  77
  78                 idle-states {
  79                         CPU_SPC: spc {
  80                                 compatible = "qcom,idle-state-spc",
  81                                                 "arm,idle-state";
  82                                 entry-latency-us = <150>;
  83                                 exit-latency-us = <200>;
  84                                 min-residency-us = <2000>;
  85                         };
  86                 };
  87         };
  88
  89         cpu-pmu {
  90                 compatible = "qcom,krait-pmu";
  91                 interrupts = <1 7 0xf04>;
  92         };
  93
  94         timer {
  95                 compatible = "arm,armv7-timer";
  96                 interrupts = <1 2 0xf08>,
  97                              <1 3 0xf08>,
  98                              <1 4 0xf08>,
  99                              <1 1 0xf08>;
 100                 clock-frequency = <19200000>;
 101         };
 102
 103         smem {
 104                 compatible = "qcom,smem";
 105
 106                 memory-region = <&smem_region>;
 107                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 108
 109                 hwlocks = <&tcsr_mutex 3>;
 110         };
 111
 112         soc: soc {
 113                 #address-cells = <1>;
 114                 #size-cells = <1>;
 115                 ranges;
 116                 compatible = "simple-bus";
 117
 118                 intc: interrupt-controller@f9000000 {
 119                         compatible = "qcom,msm-qgic2";
 120                         interrupt-controller;
 121                         #interrupt-cells = <3>;
 122                         reg = <0xf9000000 0x1000>,
 123                               <0xf9002000 0x1000>;
 124                 };
 125
 126                 timer@f9020000 {
 127                         #address-cells = <1>;
 128                         #size-cells = <1>;
 129                         ranges;
 130                         compatible = "arm,armv7-timer-mem";
 131                         reg = <0xf9020000 0x1000>;
 132                         clock-frequency = <19200000>;
 133
 134                         frame@f9021000 {
 135                                 frame-number = <0>;
 136                                 interrupts = <0 8 0x4>,
 137                                              <0 7 0x4>;
 138                                 reg = <0xf9021000 0x1000>,
 139                                       <0xf9022000 0x1000>;
 140                         };
 141
 142                         frame@f9023000 {
 143                                 frame-number = <1>;
 144                                 interrupts = <0 9 0x4>;
 145                                 reg = <0xf9023000 0x1000>;
 146                                 status = "disabled";
 147                         };
 148
 149                         frame@f9024000 {
 150                                 frame-number = <2>;
 151                                 interrupts = <0 10 0x4>;
 152                                 reg = <0xf9024000 0x1000>;
 153                                 status = "disabled";
 154                         };
 155
 156                         frame@f9025000 {
 157                                 frame-number = <3>;
 158                                 interrupts = <0 11 0x4>;
 159                                 reg = <0xf9025000 0x1000>;
 160                                 status = "disabled";
 161                         };
 162
 163                         frame@f9026000 {
 164                                 frame-number = <4>;
 165                                 interrupts = <0 12 0x4>;
 166                                 reg = <0xf9026000 0x1000>;
 167                                 status = "disabled";
 168                         };
 169
 170                         frame@f9027000 {
 171                                 frame-number = <5>;
 172                                 interrupts = <0 13 0x4>;
 173                                 reg = <0xf9027000 0x1000>;
 174                                 status = "disabled";
 175                         };
 176
 177                         frame@f9028000 {
 178                                 frame-number = <6>;
 179                                 interrupts = <0 14 0x4>;
 180                                 reg = <0xf9028000 0x1000>;
 181                                 status = "disabled";
 182                         };
 183                 };
 184
 185                 saw0: power-controller@f9089000 {
 186                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 187                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
 188                 };
 189
 190                 saw1: power-controller@f9099000 {
 191                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 192                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
 193                 };
 194
 195                 saw2: power-controller@f90a9000 {
 196                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 197                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
 198                 };
 199
 200                 saw3: power-controller@f90b9000 {
 201                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 202                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
 203                 };
 204
 205                 saw_l2: power-controller@f9012000 {
 206                         compatible = "qcom,saw2";
 207                         reg = <0xf9012000 0x1000>;
 208                         regulator;
 209                 };
 210
 211                 acc0: clock-controller@f9088000 {
 212                         compatible = "qcom,kpss-acc-v2";
 213                         reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 214                 };
 215
 216                 acc1: clock-controller@f9098000 {
 217                         compatible = "qcom,kpss-acc-v2";
 218                         reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 219                 };
 220
 221                 acc2: clock-controller@f90a8000 {
 222                         compatible = "qcom,kpss-acc-v2";
 223                         reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 224                 };
 225
 226                 acc3: clock-controller@f90b8000 {
 227                         compatible = "qcom,kpss-acc-v2";
 228                         reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 229                 };
 230
 231                 restart@fc4ab000 {
 232                         compatible = "qcom,pshold";
 233                         reg = <0xfc4ab000 0x4>;
 234                 };
 235
 236                 gcc: clock-controller@fc400000 {
 237                         compatible = "qcom,gcc-msm8974";
 238                         #clock-cells = <1>;
 239                         #reset-cells = <1>;
 240                         reg = <0xfc400000 0x4000>;
 241                 };
 242
 243                 tcsr_mutex_block: syscon@fd484000 {
 244                         compatible = "syscon";
 245                         reg = <0xfd484000 0x2000>;
 246                 };
 247
 248                 mmcc: clock-controller@fd8c0000 {
 249                         compatible = "qcom,mmcc-msm8974";
 250                         #clock-cells = <1>;
 251                         #reset-cells = <1>;
 252                         reg = <0xfd8c0000 0x6000>;
 253                 };
 254
 255                 tcsr_mutex: tcsr-mutex {
 256                         compatible = "qcom,tcsr-mutex";
 257                         syscon = <&tcsr_mutex_block 0 0x80>;
 258
 259                         #hwlock-cells = <1>;
 260                 };
 261
 262                 rpm_msg_ram: memory@fc428000 {
 263                         compatible = "qcom,rpm-msg-ram";
 264                         reg = <0xfc428000 0x4000>;
 265                 };
 266
 267                 blsp1_uart2: serial@f991e000 {
 268                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 269                         reg = <0xf991e000 0x1000>;
 270                         interrupts = <0 108 0x0>;
 271                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 272                         clock-names = "core", "iface";
 273                         status = "disabled";
 274                 };
 275
 276                 sdhci@f9824900 {
 277                         compatible = "qcom,sdhci-msm-v4";
 278                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 279                         reg-names = "hc_mem", "core_mem";
 280                         interrupts = <0 123 0>, <0 138 0>;
 281                         interrupt-names = "hc_irq", "pwr_irq";
 282                         clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
 283                         clock-names = "core", "iface";
 284                         status = "disabled";
 285                 };
 286
 287                 sdhci@f98a4900 {
 288                         compatible = "qcom,sdhci-msm-v4";
 289                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 290                         reg-names = "hc_mem", "core_mem";
 291                         interrupts = <0 125 0>, <0 221 0>;
 292                         interrupt-names = "hc_irq", "pwr_irq";
 293                         clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
 294                         clock-names = "core", "iface";
 295                         status = "disabled";
 296                 };
 297
 298                 rng@f9bff000 {
 299                         compatible = "qcom,prng";
 300                         reg = <0xf9bff000 0x200>;
 301                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 302                         clock-names = "core";
 303                 };
 304
 305                 msmgpio: pinctrl@fd510000 {
 306                         compatible = "qcom,msm8974-pinctrl";
 307                         reg = <0xfd510000 0x4000>;
 308                         gpio-controller;
 309                         #gpio-cells = <2>;
 310                         interrupt-controller;
 311                         #interrupt-cells = <2>;
 312                         interrupts = <0 208 0>;
 313                 };
 314
 315                 blsp_i2c11: i2c@f9967000 {
 316                         status = "disable";
 317                         compatible = "qcom,i2c-qup-v2.1.1";
 318                         reg = <0xf9967000 0x1000>;
 319                         interrupts = <0 105 IRQ_TYPE_NONE>;
 320                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 321                         clock-names = "core", "iface";
 322                         #address-cells = <1>;
 323                         #size-cells = <0>;
 324                 };
 325
 326                 spmi_bus: spmi@fc4cf000 {
 327                         compatible = "qcom,spmi-pmic-arb";
 328                         reg-names = "core", "intr", "cnfg";
 329                         reg = <0xfc4cf000 0x1000>,
 330                               <0xfc4cb000 0x1000>,
 331                               <0xfc4ca000 0x1000>;
 332                         interrupt-names = "periph_irq";
 333                         interrupts = <0 190 0>;
 334                         qcom,ee = <0>;
 335                         qcom,channel = <0>;
 336                         #address-cells = <2>;
 337                         #size-cells = <0>;
 338                         interrupt-controller;
 339                         #interrupt-cells = <4>;
 340                 };
 341         };
 342 };