arch/arm/boot/dts/sun5i-a13.dtsi

   1 /*
   2  * Copyright 2012 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         aliases {
  20                 serial0 = &uart1;
  21                 serial1 = &uart3;
  22         };
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27                 cpu@0 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a8";
  30                         reg = <0x0>;
  31                 };
  32         };
  33
  34         memory {
  35                 reg = <0x40000000 0x20000000>;
  36         };
  37
  38         clocks {
  39                 #address-cells = <1>;
  40                 #size-cells = <1>;
  41                 ranges;
  42
  43                 /*
  44                  * This is a dummy clock, to be used as placeholder on
  45                  * other mux clocks when a specific parent clock is not
  46                  * yet implemented. It should be dropped when the driver
  47                  * is complete.
  48                  */
  49                 dummy: dummy {
  50                         #clock-cells = <0>;
  51                         compatible = "fixed-clock";
  52                         clock-frequency = <0>;
  53                 };
  54
  55                 osc24M: clk@01c20050 {
  56                         #clock-cells = <0>;
  57                         compatible = "allwinner,sun4i-a10-osc-clk";
  58                         reg = <0x01c20050 0x4>;
  59                         clock-frequency = <24000000>;
  60                         clock-output-names = "osc24M";
  61                 };
  62
  63                 osc32k: clk@0 {
  64                         #clock-cells = <0>;
  65                         compatible = "fixed-clock";
  66                         clock-frequency = <32768>;
  67                         clock-output-names = "osc32k";
  68                 };
  69
  70                 pll1: clk@01c20000 {
  71                         #clock-cells = <0>;
  72                         compatible = "allwinner,sun4i-a10-pll1-clk";
  73                         reg = <0x01c20000 0x4>;
  74                         clocks = <&osc24M>;
  75                         clock-output-names = "pll1";
  76                 };
  77
  78                 pll4: clk@01c20018 {
  79                         #clock-cells = <0>;
  80                         compatible = "allwinner,sun4i-a10-pll1-clk";
  81                         reg = <0x01c20018 0x4>;
  82                         clocks = <&osc24M>;
  83                         clock-output-names = "pll4";
  84                 };
  85
  86                 pll5: clk@01c20020 {
  87                         #clock-cells = <1>;
  88                         compatible = "allwinner,sun4i-a10-pll5-clk";
  89                         reg = <0x01c20020 0x4>;
  90                         clocks = <&osc24M>;
  91                         clock-output-names = "pll5_ddr", "pll5_other";
  92                 };
  93
  94                 pll6: clk@01c20028 {
  95                         #clock-cells = <1>;
  96                         compatible = "allwinner,sun4i-a10-pll6-clk";
  97                         reg = <0x01c20028 0x4>;
  98                         clocks = <&osc24M>;
  99                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 100                 };
 101
 102                 /* dummy is 200M */
 103                 cpu: cpu@01c20054 {
 104                         #clock-cells = <0>;
 105                         compatible = "allwinner,sun4i-a10-cpu-clk";
 106                         reg = <0x01c20054 0x4>;
 107                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 108                         clock-output-names = "cpu";
 109                 };
 110
 111                 axi: axi@01c20054 {
 112                         #clock-cells = <0>;
 113                         compatible = "allwinner,sun4i-a10-axi-clk";
 114                         reg = <0x01c20054 0x4>;
 115                         clocks = <&cpu>;
 116                         clock-output-names = "axi";
 117                 };
 118
 119                 axi_gates: clk@01c2005c {
 120                         #clock-cells = <1>;
 121                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 122                         reg = <0x01c2005c 0x4>;
 123                         clocks = <&axi>;
 124                         clock-output-names = "axi_dram";
 125                 };
 126
 127                 ahb: ahb@01c20054 {
 128                         #clock-cells = <0>;
 129                         compatible = "allwinner,sun4i-a10-ahb-clk";
 130                         reg = <0x01c20054 0x4>;
 131                         clocks = <&axi>;
 132                         clock-output-names = "ahb";
 133                 };
 134
 135                 ahb_gates: clk@01c20060 {
 136                         #clock-cells = <1>;
 137                         compatible = "allwinner,sun5i-a13-ahb-gates-clk";
 138                         reg = <0x01c20060 0x8>;
 139                         clocks = <&ahb>;
 140                         clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
 141                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 142                                 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
 143                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
 144                                 "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
 145                                 "ahb_de_fe", "ahb_iep", "ahb_mali400";
 146                 };
 147
 148                 apb0: apb0@01c20054 {
 149                         #clock-cells = <0>;
 150                         compatible = "allwinner,sun4i-a10-apb0-clk";
 151                         reg = <0x01c20054 0x4>;
 152                         clocks = <&ahb>;
 153                         clock-output-names = "apb0";
 154                 };
 155
 156                 apb0_gates: clk@01c20068 {
 157                         #clock-cells = <1>;
 158                         compatible = "allwinner,sun5i-a13-apb0-gates-clk";
 159                         reg = <0x01c20068 0x4>;
 160                         clocks = <&apb0>;
 161                         clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
 162                 };
 163
 164                 apb1_mux: apb1_mux@01c20058 {
 165                         #clock-cells = <0>;
 166                         compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 167                         reg = <0x01c20058 0x4>;
 168                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 169                         clock-output-names = "apb1_mux";
 170                 };
 171
 172                 apb1: apb1@01c20058 {
 173                         #clock-cells = <0>;
 174                         compatible = "allwinner,sun4i-a10-apb1-clk";
 175                         reg = <0x01c20058 0x4>;
 176                         clocks = <&apb1_mux>;
 177                         clock-output-names = "apb1";
 178                 };
 179
 180                 apb1_gates: clk@01c2006c {
 181                         #clock-cells = <1>;
 182                         compatible = "allwinner,sun5i-a13-apb1-gates-clk";
 183                         reg = <0x01c2006c 0x4>;
 184                         clocks = <&apb1>;
 185                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 186                                 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
 187                 };
 188
 189                 nand_clk: clk@01c20080 {
 190                         #clock-cells = <0>;
 191                         compatible = "allwinner,sun4i-a10-mod0-clk";
 192                         reg = <0x01c20080 0x4>;
 193                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 194                         clock-output-names = "nand";
 195                 };
 196
 197                 ms_clk: clk@01c20084 {
 198                         #clock-cells = <0>;
 199                         compatible = "allwinner,sun4i-a10-mod0-clk";
 200                         reg = <0x01c20084 0x4>;
 201                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 202                         clock-output-names = "ms";
 203                 };
 204
 205                 mmc0_clk: clk@01c20088 {
 206                         #clock-cells = <0>;
 207                         compatible = "allwinner,sun4i-a10-mod0-clk";
 208                         reg = <0x01c20088 0x4>;
 209                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 210                         clock-output-names = "mmc0";
 211                 };
 212
 213                 mmc1_clk: clk@01c2008c {
 214                         #clock-cells = <0>;
 215                         compatible = "allwinner,sun4i-a10-mod0-clk";
 216                         reg = <0x01c2008c 0x4>;
 217                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 218                         clock-output-names = "mmc1";
 219                 };
 220
 221                 mmc2_clk: clk@01c20090 {
 222                         #clock-cells = <0>;
 223                         compatible = "allwinner,sun4i-a10-mod0-clk";
 224                         reg = <0x01c20090 0x4>;
 225                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 226                         clock-output-names = "mmc2";
 227                 };
 228
 229                 ts_clk: clk@01c20098 {
 230                         #clock-cells = <0>;
 231                         compatible = "allwinner,sun4i-a10-mod0-clk";
 232                         reg = <0x01c20098 0x4>;
 233                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 234                         clock-output-names = "ts";
 235                 };
 236
 237                 ss_clk: clk@01c2009c {
 238                         #clock-cells = <0>;
 239                         compatible = "allwinner,sun4i-a10-mod0-clk";
 240                         reg = <0x01c2009c 0x4>;
 241                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 242                         clock-output-names = "ss";
 243                 };
 244
 245                 spi0_clk: clk@01c200a0 {
 246                         #clock-cells = <0>;
 247                         compatible = "allwinner,sun4i-a10-mod0-clk";
 248                         reg = <0x01c200a0 0x4>;
 249                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 250                         clock-output-names = "spi0";
 251                 };
 252
 253                 spi1_clk: clk@01c200a4 {
 254                         #clock-cells = <0>;
 255                         compatible = "allwinner,sun4i-a10-mod0-clk";
 256                         reg = <0x01c200a4 0x4>;
 257                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 258                         clock-output-names = "spi1";
 259                 };
 260
 261                 spi2_clk: clk@01c200a8 {
 262                         #clock-cells = <0>;
 263                         compatible = "allwinner,sun4i-a10-mod0-clk";
 264                         reg = <0x01c200a8 0x4>;
 265                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 266                         clock-output-names = "spi2";
 267                 };
 268
 269                 ir0_clk: clk@01c200b0 {
 270                         #clock-cells = <0>;
 271                         compatible = "allwinner,sun4i-a10-mod0-clk";
 272                         reg = <0x01c200b0 0x4>;
 273                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 274                         clock-output-names = "ir0";
 275                 };
 276
 277                 usb_clk: clk@01c200cc {
 278                         #clock-cells = <1>;
 279                         #reset-cells = <1>;
 280                         compatible = "allwinner,sun5i-a13-usb-clk";
 281                         reg = <0x01c200cc 0x4>;
 282                         clocks = <&pll6 1>;
 283                         clock-output-names = "usb_ohci0", "usb_phy";
 284                 };
 285
 286                 mbus_clk: clk@01c2015c {
 287                         #clock-cells = <0>;
 288                         compatible = "allwinner,sun4i-a10-mod0-clk";
 289                         reg = <0x01c2015c 0x4>;
 290                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 291                         clock-output-names = "mbus";
 292                 };
 293         };
 294
 295         soc@01c00000 {
 296                 compatible = "simple-bus";
 297                 #address-cells = <1>;
 298                 #size-cells = <1>;
 299                 ranges;
 300
 301                 dma: dma-controller@01c02000 {
 302                         compatible = "allwinner,sun4i-a10-dma";
 303                         reg = <0x01c02000 0x1000>;
 304                         interrupts = <27>;
 305                         clocks = <&ahb_gates 6>;
 306                         #dma-cells = <2>;
 307                 };
 308
 309                 spi0: spi@01c05000 {
 310                         compatible = "allwinner,sun4i-a10-spi";
 311                         reg = <0x01c05000 0x1000>;
 312                         interrupts = <10>;
 313                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 314                         clock-names = "ahb", "mod";
 315                         status = "disabled";
 316                         #address-cells = <1>;
 317                         #size-cells = <0>;
 318                 };
 319
 320                 spi1: spi@01c06000 {
 321                         compatible = "allwinner,sun4i-a10-spi";
 322                         reg = <0x01c06000 0x1000>;
 323                         interrupts = <11>;
 324                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 325                         clock-names = "ahb", "mod";
 326                         status = "disabled";
 327                         #address-cells = <1>;
 328                         #size-cells = <0>;
 329                 };
 330
 331                 mmc0: mmc@01c0f000 {
 332                         compatible = "allwinner,sun5i-a13-mmc";
 333                         reg = <0x01c0f000 0x1000>;
 334                         clocks = <&ahb_gates 8>, <&mmc0_clk>;
 335                         clock-names = "ahb", "mmc";
 336                         interrupts = <32>;
 337                         status = "disabled";
 338                 };
 339
 340                 mmc2: mmc@01c11000 {
 341                         compatible = "allwinner,sun5i-a13-mmc";
 342                         reg = <0x01c11000 0x1000>;
 343                         clocks = <&ahb_gates 10>, <&mmc2_clk>;
 344                         clock-names = "ahb", "mmc";
 345                         interrupts = <34>;
 346                         status = "disabled";
 347                 };
 348
 349                 usbphy: phy@01c13400 {
 350                         #phy-cells = <1>;
 351                         compatible = "allwinner,sun5i-a13-usb-phy";
 352                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
 353                         reg-names = "phy_ctrl", "pmu1";
 354                         clocks = <&usb_clk 8>;
 355                         clock-names = "usb_phy";
 356                         resets = <&usb_clk 1>;
 357                         reset-names = "usb1_reset";
 358                         status = "disabled";
 359                 };
 360
 361                 ehci0: usb@01c14000 {
 362                         compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
 363                         reg = <0x01c14000 0x100>;
 364                         interrupts = <39>;
 365                         clocks = <&ahb_gates 1>;
 366                         phys = <&usbphy 1>;
 367                         phy-names = "usb";
 368                         status = "disabled";
 369                 };
 370
 371                 ohci0: usb@01c14400 {
 372                         compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
 373                         reg = <0x01c14400 0x100>;
 374                         interrupts = <40>;
 375                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 376                         phys = <&usbphy 1>;
 377                         phy-names = "usb";
 378                         status = "disabled";
 379                 };
 380
 381                 spi2: spi@01c17000 {
 382                         compatible = "allwinner,sun4i-a10-spi";
 383                         reg = <0x01c17000 0x1000>;
 384                         interrupts = <12>;
 385                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 386                         clock-names = "ahb", "mod";
 387                         status = "disabled";
 388                         #address-cells = <1>;
 389                         #size-cells = <0>;
 390                 };
 391
 392                 intc: interrupt-controller@01c20400 {
 393                         compatible = "allwinner,sun4i-a10-ic";
 394                         reg = <0x01c20400 0x400>;
 395                         interrupt-controller;
 396                         #interrupt-cells = <1>;
 397                 };
 398
 399                 pio: pinctrl@01c20800 {
 400                         compatible = "allwinner,sun5i-a13-pinctrl";
 401                         reg = <0x01c20800 0x400>;
 402                         interrupts = <28>;
 403                         clocks = <&apb0_gates 5>;
 404                         gpio-controller;
 405                         interrupt-controller;
 406                         #interrupt-cells = <2>;
 407                         #size-cells = <0>;
 408                         #gpio-cells = <3>;
 409
 410                         uart1_pins_a: uart1@0 {
 411                                 allwinner,pins = "PE10", "PE11";
 412                                 allwinner,function = "uart1";
 413                                 allwinner,drive = <0>;
 414                                 allwinner,pull = <0>;
 415                         };
 416
 417                         uart1_pins_b: uart1@1 {
 418                                 allwinner,pins = "PG3", "PG4";
 419                                 allwinner,function = "uart1";
 420                                 allwinner,drive = <0>;
 421                                 allwinner,pull = <0>;
 422                         };
 423
 424                         i2c0_pins_a: i2c0@0 {
 425                                 allwinner,pins = "PB0", "PB1";
 426                                 allwinner,function = "i2c0";
 427                                 allwinner,drive = <0>;
 428                                 allwinner,pull = <0>;
 429                         };
 430
 431                         i2c1_pins_a: i2c1@0 {
 432                                 allwinner,pins = "PB15", "PB16";
 433                                 allwinner,function = "i2c1";
 434                                 allwinner,drive = <0>;
 435                                 allwinner,pull = <0>;
 436                         };
 437
 438                         i2c2_pins_a: i2c2@0 {
 439                                 allwinner,pins = "PB17", "PB18";
 440                                 allwinner,function = "i2c2";
 441                                 allwinner,drive = <0>;
 442                                 allwinner,pull = <0>;
 443                         };
 444
 445                         mmc0_pins_a: mmc0@0 {
 446                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 447                                 allwinner,function = "mmc0";
 448                                 allwinner,drive = <2>;
 449                                 allwinner,pull = <0>;
 450                         };
 451                 };
 452
 453                 timer@01c20c00 {
 454                         compatible = "allwinner,sun4i-a10-timer";
 455                         reg = <0x01c20c00 0x90>;
 456                         interrupts = <22>;
 457                         clocks = <&osc24M>;
 458                 };
 459
 460                 wdt: watchdog@01c20c90 {
 461                         compatible = "allwinner,sun4i-a10-wdt";
 462                         reg = <0x01c20c90 0x10>;
 463                 };
 464
 465                 sid: eeprom@01c23800 {
 466                         compatible = "allwinner,sun4i-a10-sid";
 467                         reg = <0x01c23800 0x10>;
 468                 };
 469
 470                 rtp: rtp@01c25000 {
 471                         compatible = "allwinner,sun4i-a10-ts";
 472                         reg = <0x01c25000 0x100>;
 473                         interrupts = <29>;
 474                 };
 475
 476                 uart1: serial@01c28400 {
 477                         compatible = "snps,dw-apb-uart";
 478                         reg = <0x01c28400 0x400>;
 479                         interrupts = <2>;
 480                         reg-shift = <2>;
 481                         reg-io-width = <4>;
 482                         clocks = <&apb1_gates 17>;
 483                         status = "disabled";
 484                 };
 485
 486                 uart3: serial@01c28c00 {
 487                         compatible = "snps,dw-apb-uart";
 488                         reg = <0x01c28c00 0x400>;
 489                         interrupts = <4>;
 490                         reg-shift = <2>;
 491                         reg-io-width = <4>;
 492                         clocks = <&apb1_gates 19>;
 493                         status = "disabled";
 494                 };
 495
 496                 i2c0: i2c@01c2ac00 {
 497                         compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
 498                         reg = <0x01c2ac00 0x400>;
 499                         interrupts = <7>;
 500                         clocks = <&apb1_gates 0>;
 501                         clock-frequency = <100000>;
 502                         status = "disabled";
 503                         #address-cells = <1>;
 504                         #size-cells = <0>;
 505                 };
 506
 507                 i2c1: i2c@01c2b000 {
 508                         compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
 509                         reg = <0x01c2b000 0x400>;
 510                         interrupts = <8>;
 511                         clocks = <&apb1_gates 1>;
 512                         clock-frequency = <100000>;
 513                         status = "disabled";
 514                         #address-cells = <1>;
 515                         #size-cells = <0>;
 516                 };
 517
 518                 i2c2: i2c@01c2b400 {
 519                         compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
 520                         reg = <0x01c2b400 0x400>;
 521                         interrupts = <9>;
 522                         clocks = <&apb1_gates 2>;
 523                         clock-frequency = <100000>;
 524                         status = "disabled";
 525                         #address-cells = <1>;
 526                         #size-cells = <0>;
 527                 };
 528
 529                 timer@01c60000 {
 530                         compatible = "allwinner,sun5i-a13-hstimer";
 531                         reg = <0x01c60000 0x1000>;
 532                         interrupts = <82>, <83>;
 533                         clocks = <&ahb_gates 28>;
 534                 };
 535         };
 536 };