arch/arm/boot/dts/sunxi.dtsi

   1 /*
   2  * Copyright 2012 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         cpus {
  20                 cpu@0 {
  21                         compatible = "arm,cortex-a8";
  22                 };
  23         };
  24
  25         clocks {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 osc: oscillator {
  30                         #clock-cells = <0>;
  31                         compatible = "fixed-clock";
  32                         clock-frequency = <24000000>;
  33                 };
  34         };
  35
  36         soc {
  37                 compatible = "simple-bus";
  38                 #address-cells = <1>;
  39                 #size-cells = <1>;
  40                 reg = <0x01c20000 0x300000>;
  41                 ranges;
  42
  43                 timer@01c20c00 {
  44                         compatible = "allwinner,sunxi-timer";
  45                         reg = <0x01c20c00 0x90>;
  46                         interrupts = <22>;
  47                         clocks = <&osc>;
  48                 };
  49
  50                 wdt: watchdog@01c20c90 {
  51                         compatible = "allwinner,sunxi-wdt";
  52                         reg = <0x01c20c90 0x10>;
  53                 };
  54
  55                 intc: interrupt-controller@01c20400 {
  56                         compatible = "allwinner,sunxi-ic";
  57                         reg = <0x01c20400 0x400>;
  58                         interrupt-controller;
  59                         #interrupt-cells = <1>;
  60                 };
  61
  62                 uart0: uart@01c28000 {
  63                         compatible = "snps,dw-apb-uart";
  64                         reg = <0x01c28000 0x400>;
  65                         interrupts = <1>;
  66                         reg-shift = <2>;
  67                         reg-io-width = <4>;
  68                         clock-frequency = <24000000>;
  69                         status = "disabled";
  70                 };
  71
  72                 uart1: uart@01c28400 {
  73                         compatible = "snps,dw-apb-uart";
  74                         reg = <0x01c28400 0x400>;
  75                         interrupts = <2>;
  76                         reg-shift = <2>;
  77                         reg-io-width = <4>;
  78                         clock-frequency = <24000000>;
  79                         status = "disabled";
  80                 };
  81         };
  82 };