arch/arm/boot/dts/tegra124.dtsi

   1 #include <dt-bindings/clock/tegra124-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/memory/tegra124-mc.h>
   4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/thermal/tegra124-soctherm.h>
   8
   9 #include "skeleton.dtsi"
  10
  11 / {
  12         compatible = "nvidia,tegra124";
  13         interrupt-parent = <&lic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         pcie-controller@0,01003000 {
  18                 compatible = "nvidia,tegra124-pcie";
  19                 device_type = "pci";
  20                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
  21                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
  22                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
  23                 reg-names = "pads", "afi", "cs";
  24                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  25                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  26                 interrupt-names = "intr", "msi";
  27
  28                 #interrupt-cells = <1>;
  29                 interrupt-map-mask = <0 0 0 0>;
  30                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  31
  32                 bus-range = <0x00 0xff>;
  33                 #address-cells = <3>;
  34                 #size-cells = <2>;
  35
  36                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
  37                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
  38                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
  39                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
  40                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  41
  42                 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
  43                          <&tegra_car TEGRA124_CLK_AFI>,
  44                          <&tegra_car TEGRA124_CLK_PLL_E>,
  45                          <&tegra_car TEGRA124_CLK_CML0>;
  46                 clock-names = "pex", "afi", "pll_e", "cml";
  47                 resets = <&tegra_car 70>,
  48                          <&tegra_car 72>,
  49                          <&tegra_car 74>;
  50                 reset-names = "pex", "afi", "pcie_x";
  51                 status = "disabled";
  52
  53                 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
  54                 phy-names = "pcie";
  55
  56                 pci@1,0 {
  57                         device_type = "pci";
  58                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  59                         reg = <0x000800 0 0 0 0>;
  60                         status = "disabled";
  61
  62                         #address-cells = <3>;
  63                         #size-cells = <2>;
  64                         ranges;
  65
  66                         nvidia,num-lanes = <2>;
  67                 };
  68
  69                 pci@2,0 {
  70                         device_type = "pci";
  71                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  72                         reg = <0x001000 0 0 0 0>;
  73                         status = "disabled";
  74
  75                         #address-cells = <3>;
  76                         #size-cells = <2>;
  77                         ranges;
  78
  79                         nvidia,num-lanes = <1>;
  80                 };
  81         };
  82
  83         host1x@0,50000000 {
  84                 compatible = "nvidia,tegra124-host1x", "simple-bus";
  85                 reg = <0x0 0x50000000 0x0 0x00034000>;
  86                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  87                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  88                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  89                 resets = <&tegra_car 28>;
  90                 reset-names = "host1x";
  91
  92                 #address-cells = <2>;
  93                 #size-cells = <2>;
  94
  95                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
  96
  97                 dc@0,54200000 {
  98                         compatible = "nvidia,tegra124-dc";
  99                         reg = <0x0 0x54200000 0x0 0x00040000>;
 100                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 101                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
 102                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 103                         clock-names = "dc", "parent";
 104                         resets = <&tegra_car 27>;
 105                         reset-names = "dc";
 106
 107                         iommus = <&mc TEGRA_SWGROUP_DC>;
 108
 109                         nvidia,head = <0>;
 110                 };
 111
 112                 dc@0,54240000 {
 113                         compatible = "nvidia,tegra124-dc";
 114                         reg = <0x0 0x54240000 0x0 0x00040000>;
 115                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 116                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
 117                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 118                         clock-names = "dc", "parent";
 119                         resets = <&tegra_car 26>;
 120                         reset-names = "dc";
 121
 122                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 123
 124                         nvidia,head = <1>;
 125                 };
 126
 127                 hdmi@0,54280000 {
 128                         compatible = "nvidia,tegra124-hdmi";
 129                         reg = <0x0 0x54280000 0x0 0x00040000>;
 130                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 131                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
 132                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
 133                         clock-names = "hdmi", "parent";
 134                         resets = <&tegra_car 51>;
 135                         reset-names = "hdmi";
 136                         status = "disabled";
 137                 };
 138
 139                 sor@0,54540000 {
 140                         compatible = "nvidia,tegra124-sor";
 141                         reg = <0x0 0x54540000 0x0 0x00040000>;
 142                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 143                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
 144                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
 145                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
 146                                  <&tegra_car TEGRA124_CLK_CLK_M>;
 147                         clock-names = "sor", "parent", "dp", "safe";
 148                         resets = <&tegra_car 182>;
 149                         reset-names = "sor";
 150                         status = "disabled";
 151                 };
 152
 153                 dpaux: dpaux@0,545c0000 {
 154                         compatible = "nvidia,tegra124-dpaux";
 155                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 156                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 157                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
 158                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
 159                         clock-names = "dpaux", "parent";
 160                         resets = <&tegra_car 181>;
 161                         reset-names = "dpaux";
 162                         status = "disabled";
 163                 };
 164         };
 165
 166         gic: interrupt-controller@0,50041000 {
 167                 compatible = "arm,cortex-a15-gic";
 168                 #interrupt-cells = <3>;
 169                 interrupt-controller;
 170                 reg = <0x0 0x50041000 0x0 0x1000>,
 171                       <0x0 0x50042000 0x0 0x1000>,
 172                       <0x0 0x50044000 0x0 0x2000>,
 173                       <0x0 0x50046000 0x0 0x2000>;
 174                 interrupts = <GIC_PPI 9
 175                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 176                 interrupt-parent = <&gic>;
 177         };
 178
 179         gpu@0,57000000 {
 180                 compatible = "nvidia,gk20a";
 181                 reg = <0x0 0x57000000 0x0 0x01000000>,
 182                       <0x0 0x58000000 0x0 0x01000000>;
 183                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 184                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 185                 interrupt-names = "stall", "nonstall";
 186                 clocks = <&tegra_car TEGRA124_CLK_GPU>,
 187                          <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
 188                 clock-names = "gpu", "pwr";
 189                 resets = <&tegra_car 184>;
 190                 reset-names = "gpu";
 191                 status = "disabled";
 192         };
 193
 194         lic: interrupt-controller@60004000 {
 195                 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
 196                 reg = <0x0 0x60004000 0x0 0x100>,
 197                       <0x0 0x60004100 0x0 0x100>,
 198                       <0x0 0x60004200 0x0 0x100>,
 199                       <0x0 0x60004300 0x0 0x100>,
 200                       <0x0 0x60004400 0x0 0x100>;
 201                 interrupt-controller;
 202                 #interrupt-cells = <3>;
 203                 interrupt-parent = <&gic>;
 204         };
 205
 206         timer@0,60005000 {
 207                 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
 208                 reg = <0x0 0x60005000 0x0 0x400>;
 209                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 210                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 211                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 212                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 213                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 214                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 215                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
 216         };
 217
 218         tegra_car: clock@0,60006000 {
 219                 compatible = "nvidia,tegra124-car";
 220                 reg = <0x0 0x60006000 0x0 0x1000>;
 221                 #clock-cells = <1>;
 222                 #reset-cells = <1>;
 223         };
 224
 225         flow-controller@0,60007000 {
 226                 compatible = "nvidia,tegra124-flowctrl";
 227                 reg = <0x0 0x60007000 0x0 0x1000>;
 228         };
 229
 230         gpio: gpio@0,6000d000 {
 231                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 232                 reg = <0x0 0x6000d000 0x0 0x1000>;
 233                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 234                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 235                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 236                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 237                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 238                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 239                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 240                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 241                 #gpio-cells = <2>;
 242                 gpio-controller;
 243                 #interrupt-cells = <2>;
 244                 interrupt-controller;
 245         };
 246
 247         apbdma: dma@0,60020000 {
 248                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
 249                 reg = <0x0 0x60020000 0x0 0x1400>;
 250                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 251                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 252                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 253                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 254                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 255                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 256                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 257                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 258                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 259                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 260                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 265                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 266                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 268                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 269                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 270                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 271                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 272                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 273                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 274                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 275                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 276                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 277                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 278                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 279                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 280                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 281                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 282                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
 283                 resets = <&tegra_car 34>;
 284                 reset-names = "dma";
 285                 #dma-cells = <1>;
 286         };
 287
 288         apbmisc@0,70000800 {
 289                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
 290                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 291                       <0x0 0x7000E864 0x0 0x04>;   /* Strapping options */
 292         };
 293
 294         pinmux: pinmux@0,70000868 {
 295                 compatible = "nvidia,tegra124-pinmux";
 296                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
 297                       <0x0 0x70003000 0x0 0x434>, /* Mux registers */
 298                       <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
 299         };
 300
 301         /*
 302          * There are two serial driver i.e. 8250 based simple serial
 303          * driver and APB DMA based serial driver for higher baudrate
 304          * and performace. To enable the 8250 based driver, the compatible
 305          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 306          * the APB DMA based serial driver, the comptible is
 307          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 308          */
 309         uarta: serial@0,70006000 {
 310                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 311                 reg = <0x0 0x70006000 0x0 0x40>;
 312                 reg-shift = <2>;
 313                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 314                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 315                 resets = <&tegra_car 6>;
 316                 reset-names = "serial";
 317                 dmas = <&apbdma 8>, <&apbdma 8>;
 318                 dma-names = "rx", "tx";
 319                 status = "disabled";
 320         };
 321
 322         uartb: serial@0,70006040 {
 323                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 324                 reg = <0x0 0x70006040 0x0 0x40>;
 325                 reg-shift = <2>;
 326                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 327                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 328                 resets = <&tegra_car 7>;
 329                 reset-names = "serial";
 330                 dmas = <&apbdma 9>, <&apbdma 9>;
 331                 dma-names = "rx", "tx";
 332                 status = "disabled";
 333         };
 334
 335         uartc: serial@0,70006200 {
 336                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 337                 reg = <0x0 0x70006200 0x0 0x40>;
 338                 reg-shift = <2>;
 339                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 340                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 341                 resets = <&tegra_car 55>;
 342                 reset-names = "serial";
 343                 dmas = <&apbdma 10>, <&apbdma 10>;
 344                 dma-names = "rx", "tx";
 345                 status = "disabled";
 346         };
 347
 348         uartd: serial@0,70006300 {
 349                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 350                 reg = <0x0 0x70006300 0x0 0x40>;
 351                 reg-shift = <2>;
 352                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 353                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 354                 resets = <&tegra_car 65>;
 355                 reset-names = "serial";
 356                 dmas = <&apbdma 19>, <&apbdma 19>;
 357                 dma-names = "rx", "tx";
 358                 status = "disabled";
 359         };
 360
 361         pwm: pwm@0,7000a000 {
 362                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 363                 reg = <0x0 0x7000a000 0x0 0x100>;
 364                 #pwm-cells = <2>;
 365                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 366                 resets = <&tegra_car 17>;
 367                 reset-names = "pwm";
 368                 status = "disabled";
 369         };
 370
 371         i2c@0,7000c000 {
 372                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 373                 reg = <0x0 0x7000c000 0x0 0x100>;
 374                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 378                 clock-names = "div-clk";
 379                 resets = <&tegra_car 12>;
 380                 reset-names = "i2c";
 381                 dmas = <&apbdma 21>, <&apbdma 21>;
 382                 dma-names = "rx", "tx";
 383                 status = "disabled";
 384         };
 385
 386         i2c@0,7000c400 {
 387                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 388                 reg = <0x0 0x7000c400 0x0 0x100>;
 389                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 390                 #address-cells = <1>;
 391                 #size-cells = <0>;
 392                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 393                 clock-names = "div-clk";
 394                 resets = <&tegra_car 54>;
 395                 reset-names = "i2c";
 396                 dmas = <&apbdma 22>, <&apbdma 22>;
 397                 dma-names = "rx", "tx";
 398                 status = "disabled";
 399         };
 400
 401         i2c@0,7000c500 {
 402                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 403                 reg = <0x0 0x7000c500 0x0 0x100>;
 404                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 405                 #address-cells = <1>;
 406                 #size-cells = <0>;
 407                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 408                 clock-names = "div-clk";
 409                 resets = <&tegra_car 67>;
 410                 reset-names = "i2c";
 411                 dmas = <&apbdma 23>, <&apbdma 23>;
 412                 dma-names = "rx", "tx";
 413                 status = "disabled";
 414         };
 415
 416         i2c@0,7000c700 {
 417                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 418                 reg = <0x0 0x7000c700 0x0 0x100>;
 419                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 420                 #address-cells = <1>;
 421                 #size-cells = <0>;
 422                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 423                 clock-names = "div-clk";
 424                 resets = <&tegra_car 103>;
 425                 reset-names = "i2c";
 426                 dmas = <&apbdma 26>, <&apbdma 26>;
 427                 dma-names = "rx", "tx";
 428                 status = "disabled";
 429         };
 430
 431         i2c@0,7000d000 {
 432                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 433                 reg = <0x0 0x7000d000 0x0 0x100>;
 434                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 435                 #address-cells = <1>;
 436                 #size-cells = <0>;
 437                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 438                 clock-names = "div-clk";
 439                 resets = <&tegra_car 47>;
 440                 reset-names = "i2c";
 441                 dmas = <&apbdma 24>, <&apbdma 24>;
 442                 dma-names = "rx", "tx";
 443                 status = "disabled";
 444         };
 445
 446         i2c@0,7000d100 {
 447                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 448                 reg = <0x0 0x7000d100 0x0 0x100>;
 449                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 450                 #address-cells = <1>;
 451                 #size-cells = <0>;
 452                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 453                 clock-names = "div-clk";
 454                 resets = <&tegra_car 166>;
 455                 reset-names = "i2c";
 456                 dmas = <&apbdma 30>, <&apbdma 30>;
 457                 dma-names = "rx", "tx";
 458                 status = "disabled";
 459         };
 460
 461         spi@0,7000d400 {
 462                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 463                 reg = <0x0 0x7000d400 0x0 0x200>;
 464                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 465                 #address-cells = <1>;
 466                 #size-cells = <0>;
 467                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 468                 clock-names = "spi";
 469                 resets = <&tegra_car 41>;
 470                 reset-names = "spi";
 471                 dmas = <&apbdma 15>, <&apbdma 15>;
 472                 dma-names = "rx", "tx";
 473                 status = "disabled";
 474         };
 475
 476         spi@0,7000d600 {
 477                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 478                 reg = <0x0 0x7000d600 0x0 0x200>;
 479                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 480                 #address-cells = <1>;
 481                 #size-cells = <0>;
 482                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 483                 clock-names = "spi";
 484                 resets = <&tegra_car 44>;
 485                 reset-names = "spi";
 486                 dmas = <&apbdma 16>, <&apbdma 16>;
 487                 dma-names = "rx", "tx";
 488                 status = "disabled";
 489         };
 490
 491         spi@0,7000d800 {
 492                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 493                 reg = <0x0 0x7000d800 0x0 0x200>;
 494                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 495                 #address-cells = <1>;
 496                 #size-cells = <0>;
 497                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 498                 clock-names = "spi";
 499                 resets = <&tegra_car 46>;
 500                 reset-names = "spi";
 501                 dmas = <&apbdma 17>, <&apbdma 17>;
 502                 dma-names = "rx", "tx";
 503                 status = "disabled";
 504         };
 505
 506         spi@0,7000da00 {
 507                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 508                 reg = <0x0 0x7000da00 0x0 0x200>;
 509                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 510                 #address-cells = <1>;
 511                 #size-cells = <0>;
 512                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 513                 clock-names = "spi";
 514                 resets = <&tegra_car 68>;
 515                 reset-names = "spi";
 516                 dmas = <&apbdma 18>, <&apbdma 18>;
 517                 dma-names = "rx", "tx";
 518                 status = "disabled";
 519         };
 520
 521         spi@0,7000dc00 {
 522                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 523                 reg = <0x0 0x7000dc00 0x0 0x200>;
 524                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 525                 #address-cells = <1>;
 526                 #size-cells = <0>;
 527                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 528                 clock-names = "spi";
 529                 resets = <&tegra_car 104>;
 530                 reset-names = "spi";
 531                 dmas = <&apbdma 27>, <&apbdma 27>;
 532                 dma-names = "rx", "tx";
 533                 status = "disabled";
 534         };
 535
 536         spi@0,7000de00 {
 537                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 538                 reg = <0x0 0x7000de00 0x0 0x200>;
 539                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 540                 #address-cells = <1>;
 541                 #size-cells = <0>;
 542                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 543                 clock-names = "spi";
 544                 resets = <&tegra_car 105>;
 545                 reset-names = "spi";
 546                 dmas = <&apbdma 28>, <&apbdma 28>;
 547                 dma-names = "rx", "tx";
 548                 status = "disabled";
 549         };
 550
 551         rtc@0,7000e000 {
 552                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 553                 reg = <0x0 0x7000e000 0x0 0x100>;
 554                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 555                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 556         };
 557
 558         pmc@0,7000e400 {
 559                 compatible = "nvidia,tegra124-pmc";
 560                 reg = <0x0 0x7000e400 0x0 0x400>;
 561                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 562                 clock-names = "pclk", "clk32k_in";
 563         };
 564
 565         fuse@0,7000f800 {
 566                 compatible = "nvidia,tegra124-efuse";
 567                 reg = <0x0 0x7000f800 0x0 0x400>;
 568                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
 569                 clock-names = "fuse";
 570                 resets = <&tegra_car 39>;
 571                 reset-names = "fuse";
 572         };
 573
 574         mc: memory-controller@0,70019000 {
 575                 compatible = "nvidia,tegra124-mc";
 576                 reg = <0x0 0x70019000 0x0 0x1000>;
 577                 clocks = <&tegra_car TEGRA124_CLK_MC>;
 578                 clock-names = "mc";
 579
 580                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 581
 582                 #iommu-cells = <1>;
 583         };
 584
 585         sata@0,70020000 {
 586                 compatible = "nvidia,tegra124-ahci";
 587
 588                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
 589                         <0x0 0x70020000 0x0 0x7000>; /* SATA */
 590
 591                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 592
 593                 clocks = <&tegra_car TEGRA124_CLK_SATA>,
 594                         <&tegra_car TEGRA124_CLK_SATA_OOB>,
 595                         <&tegra_car TEGRA124_CLK_CML1>,
 596                         <&tegra_car TEGRA124_CLK_PLL_E>;
 597                 clock-names = "sata", "sata-oob", "cml1", "pll_e";
 598
 599                 resets = <&tegra_car 124>,
 600                         <&tegra_car 123>,
 601                         <&tegra_car 129>;
 602                 reset-names = "sata", "sata-oob", "sata-cold";
 603
 604                 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
 605                 phy-names = "sata-phy";
 606
 607                 status = "disabled";
 608         };
 609
 610         hda@0,70030000 {
 611                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
 612                 reg = <0x0 0x70030000 0x0 0x10000>;
 613                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 614                 clocks = <&tegra_car TEGRA124_CLK_HDA>,
 615                          <&tegra_car TEGRA124_CLK_HDA2HDMI>,
 616                          <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
 617                 clock-names = "hda", "hda2hdmi", "hdacodec_2x";
 618                 resets = <&tegra_car 125>, /* hda */
 619                          <&tegra_car 128>, /* hda2hdmi */
 620                          <&tegra_car 111>; /* hda2codec_2x */
 621                 reset-names = "hda", "hda2hdmi", "hdacodec_2x";
 622                 status = "disabled";
 623         };
 624
 625         padctl: padctl@0,7009f000 {
 626                 compatible = "nvidia,tegra124-xusb-padctl";
 627                 reg = <0x0 0x7009f000 0x0 0x1000>;
 628                 resets = <&tegra_car 142>;
 629                 reset-names = "padctl";
 630
 631                 #phy-cells = <1>;
 632         };
 633
 634         sdhci@0,700b0000 {
 635                 compatible = "nvidia,tegra124-sdhci";
 636                 reg = <0x0 0x700b0000 0x0 0x200>;
 637                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 638                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 639                 resets = <&tegra_car 14>;
 640                 reset-names = "sdhci";
 641                 status = "disabled";
 642         };
 643
 644         sdhci@0,700b0200 {
 645                 compatible = "nvidia,tegra124-sdhci";
 646                 reg = <0x0 0x700b0200 0x0 0x200>;
 647                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 648                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 649                 resets = <&tegra_car 9>;
 650                 reset-names = "sdhci";
 651                 status = "disabled";
 652         };
 653
 654         sdhci@0,700b0400 {
 655                 compatible = "nvidia,tegra124-sdhci";
 656                 reg = <0x0 0x700b0400 0x0 0x200>;
 657                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 658                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 659                 resets = <&tegra_car 69>;
 660                 reset-names = "sdhci";
 661                 status = "disabled";
 662         };
 663
 664         sdhci@0,700b0600 {
 665                 compatible = "nvidia,tegra124-sdhci";
 666                 reg = <0x0 0x700b0600 0x0 0x200>;
 667                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 668                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 669                 resets = <&tegra_car 15>;
 670                 reset-names = "sdhci";
 671                 status = "disabled";
 672         };
 673
 674         soctherm: thermal-sensor@0,700e2000 {
 675                 compatible = "nvidia,tegra124-soctherm";
 676                 reg = <0x0 0x700e2000 0x0 0x1000>;
 677                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 678                 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
 679                         <&tegra_car TEGRA124_CLK_SOC_THERM>;
 680                 clock-names = "tsensor", "soctherm";
 681                 resets = <&tegra_car 78>;
 682                 reset-names = "soctherm";
 683                 #thermal-sensor-cells = <1>;
 684         };
 685
 686         ahub@0,70300000 {
 687                 compatible = "nvidia,tegra124-ahub";
 688                 reg = <0x0 0x70300000 0x0 0x200>,
 689                       <0x0 0x70300800 0x0 0x800>,
 690                       <0x0 0x70300200 0x0 0x600>;
 691                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 692                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 693                          <&tegra_car TEGRA124_CLK_APBIF>;
 694                 clock-names = "d_audio", "apbif";
 695                 resets = <&tegra_car 106>, /* d_audio */
 696                          <&tegra_car 107>, /* apbif */
 697                          <&tegra_car 30>,  /* i2s0 */
 698                          <&tegra_car 11>,  /* i2s1 */
 699                          <&tegra_car 18>,  /* i2s2 */
 700                          <&tegra_car 101>, /* i2s3 */
 701                          <&tegra_car 102>, /* i2s4 */
 702                          <&tegra_car 108>, /* dam0 */
 703                          <&tegra_car 109>, /* dam1 */
 704                          <&tegra_car 110>, /* dam2 */
 705                          <&tegra_car 10>,  /* spdif */
 706                          <&tegra_car 153>, /* amx */
 707                          <&tegra_car 185>, /* amx1 */
 708                          <&tegra_car 154>, /* adx */
 709                          <&tegra_car 180>, /* adx1 */
 710                          <&tegra_car 186>, /* afc0 */
 711                          <&tegra_car 187>, /* afc1 */
 712                          <&tegra_car 188>, /* afc2 */
 713                          <&tegra_car 189>, /* afc3 */
 714                          <&tegra_car 190>, /* afc4 */
 715                          <&tegra_car 191>; /* afc5 */
 716                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 717                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 718                               "spdif", "amx", "amx1", "adx", "adx1",
 719                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 720                 dmas = <&apbdma 1>, <&apbdma 1>,
 721                        <&apbdma 2>, <&apbdma 2>,
 722                        <&apbdma 3>, <&apbdma 3>,
 723                        <&apbdma 4>, <&apbdma 4>,
 724                        <&apbdma 6>, <&apbdma 6>,
 725                        <&apbdma 7>, <&apbdma 7>,
 726                        <&apbdma 12>, <&apbdma 12>,
 727                        <&apbdma 13>, <&apbdma 13>,
 728                        <&apbdma 14>, <&apbdma 14>,
 729                        <&apbdma 29>, <&apbdma 29>;
 730                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 731                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 732                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 733                             "rx9", "tx9";
 734                 ranges;
 735                 #address-cells = <2>;
 736                 #size-cells = <2>;
 737
 738                 tegra_i2s0: i2s@0,70301000 {
 739                         compatible = "nvidia,tegra124-i2s";
 740                         reg = <0x0 0x70301000 0x0 0x100>;
 741                         nvidia,ahub-cif-ids = <4 4>;
 742                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 743                         resets = <&tegra_car 30>;
 744                         reset-names = "i2s";
 745                         status = "disabled";
 746                 };
 747
 748                 tegra_i2s1: i2s@0,70301100 {
 749                         compatible = "nvidia,tegra124-i2s";
 750                         reg = <0x0 0x70301100 0x0 0x100>;
 751                         nvidia,ahub-cif-ids = <5 5>;
 752                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 753                         resets = <&tegra_car 11>;
 754                         reset-names = "i2s";
 755                         status = "disabled";
 756                 };
 757
 758                 tegra_i2s2: i2s@0,70301200 {
 759                         compatible = "nvidia,tegra124-i2s";
 760                         reg = <0x0 0x70301200 0x0 0x100>;
 761                         nvidia,ahub-cif-ids = <6 6>;
 762                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
 763                         resets = <&tegra_car 18>;
 764                         reset-names = "i2s";
 765                         status = "disabled";
 766                 };
 767
 768                 tegra_i2s3: i2s@0,70301300 {
 769                         compatible = "nvidia,tegra124-i2s";
 770                         reg = <0x0 0x70301300 0x0 0x100>;
 771                         nvidia,ahub-cif-ids = <7 7>;
 772                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
 773                         resets = <&tegra_car 101>;
 774                         reset-names = "i2s";
 775                         status = "disabled";
 776                 };
 777
 778                 tegra_i2s4: i2s@0,70301400 {
 779                         compatible = "nvidia,tegra124-i2s";
 780                         reg = <0x0 0x70301400 0x0 0x100>;
 781                         nvidia,ahub-cif-ids = <8 8>;
 782                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
 783                         resets = <&tegra_car 102>;
 784                         reset-names = "i2s";
 785                         status = "disabled";
 786                 };
 787         };
 788
 789         usb@0,7d000000 {
 790                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 791                 reg = <0x0 0x7d000000 0x0 0x4000>;
 792                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 793                 phy_type = "utmi";
 794                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
 795                 resets = <&tegra_car 22>;
 796                 reset-names = "usb";
 797                 nvidia,phy = <&phy1>;
 798                 status = "disabled";
 799         };
 800
 801         phy1: usb-phy@0,7d000000 {
 802                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 803                 reg = <0x0 0x7d000000 0x0 0x4000>,
 804                       <0x0 0x7d000000 0x0 0x4000>;
 805                 phy_type = "utmi";
 806                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
 807                          <&tegra_car TEGRA124_CLK_PLL_U>,
 808                          <&tegra_car TEGRA124_CLK_USBD>;
 809                 clock-names = "reg", "pll_u", "utmi-pads";
 810                 resets = <&tegra_car 59>, <&tegra_car 22>;
 811                 reset-names = "usb", "utmi-pads";
 812                 nvidia,hssync-start-delay = <0>;
 813                 nvidia,idle-wait-delay = <17>;
 814                 nvidia,elastic-limit = <16>;
 815                 nvidia,term-range-adj = <6>;
 816                 nvidia,xcvr-setup = <9>;
 817                 nvidia,xcvr-lsfslew = <0>;
 818                 nvidia,xcvr-lsrslew = <3>;
 819                 nvidia,hssquelch-level = <2>;
 820                 nvidia,hsdiscon-level = <5>;
 821                 nvidia,xcvr-hsslew = <12>;
 822                 status = "disabled";
 823         };
 824
 825         usb@0,7d004000 {
 826                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 827                 reg = <0x0 0x7d004000 0x0 0x4000>;
 828                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 829                 phy_type = "utmi";
 830                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
 831                 resets = <&tegra_car 58>;
 832                 reset-names = "usb";
 833                 nvidia,phy = <&phy2>;
 834                 status = "disabled";
 835         };
 836
 837         phy2: usb-phy@0,7d004000 {
 838                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 839                 reg = <0x0 0x7d004000 0x0 0x4000>,
 840                       <0x0 0x7d000000 0x0 0x4000>;
 841                 phy_type = "utmi";
 842                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
 843                          <&tegra_car TEGRA124_CLK_PLL_U>,
 844                          <&tegra_car TEGRA124_CLK_USBD>;
 845                 clock-names = "reg", "pll_u", "utmi-pads";
 846                 resets = <&tegra_car 22>, <&tegra_car 22>;
 847                 reset-names = "usb", "utmi-pads";
 848                 nvidia,hssync-start-delay = <0>;
 849                 nvidia,idle-wait-delay = <17>;
 850                 nvidia,elastic-limit = <16>;
 851                 nvidia,term-range-adj = <6>;
 852                 nvidia,xcvr-setup = <9>;
 853                 nvidia,xcvr-lsfslew = <0>;
 854                 nvidia,xcvr-lsrslew = <3>;
 855                 nvidia,hssquelch-level = <2>;
 856                 nvidia,hsdiscon-level = <5>;
 857                 nvidia,xcvr-hsslew = <12>;
 858                 nvidia,has-utmi-pad-registers;
 859                 status = "disabled";
 860         };
 861
 862         usb@0,7d008000 {
 863                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 864                 reg = <0x0 0x7d008000 0x0 0x4000>;
 865                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 866                 phy_type = "utmi";
 867                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
 868                 resets = <&tegra_car 59>;
 869                 reset-names = "usb";
 870                 nvidia,phy = <&phy3>;
 871                 status = "disabled";
 872         };
 873
 874         phy3: usb-phy@0,7d008000 {
 875                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 876                 reg = <0x0 0x7d008000 0x0 0x4000>,
 877                       <0x0 0x7d000000 0x0 0x4000>;
 878                 phy_type = "utmi";
 879                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
 880                          <&tegra_car TEGRA124_CLK_PLL_U>,
 881                          <&tegra_car TEGRA124_CLK_USBD>;
 882                 clock-names = "reg", "pll_u", "utmi-pads";
 883                 resets = <&tegra_car 58>, <&tegra_car 22>;
 884                 reset-names = "usb", "utmi-pads";
 885                 nvidia,hssync-start-delay = <0>;
 886                 nvidia,idle-wait-delay = <17>;
 887                 nvidia,elastic-limit = <16>;
 888                 nvidia,term-range-adj = <6>;
 889                 nvidia,xcvr-setup = <9>;
 890                 nvidia,xcvr-lsfslew = <0>;
 891                 nvidia,xcvr-lsrslew = <3>;
 892                 nvidia,hssquelch-level = <2>;
 893                 nvidia,hsdiscon-level = <5>;
 894                 nvidia,xcvr-hsslew = <12>;
 895                 status = "disabled";
 896         };
 897
 898         cpus {
 899                 #address-cells = <1>;
 900                 #size-cells = <0>;
 901
 902                 cpu@0 {
 903                         device_type = "cpu";
 904                         compatible = "arm,cortex-a15";
 905                         reg = <0>;
 906                 };
 907
 908                 cpu@1 {
 909                         device_type = "cpu";
 910                         compatible = "arm,cortex-a15";
 911                         reg = <1>;
 912                 };
 913
 914                 cpu@2 {
 915                         device_type = "cpu";
 916                         compatible = "arm,cortex-a15";
 917                         reg = <2>;
 918                 };
 919
 920                 cpu@3 {
 921                         device_type = "cpu";
 922                         compatible = "arm,cortex-a15";
 923                         reg = <3>;
 924                 };
 925         };
 926
 927         thermal-zones {
 928                 cpu {
 929                         polling-delay-passive = <1000>;
 930                         polling-delay = <1000>;
 931
 932                         thermal-sensors =
 933                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
 934                 };
 935
 936                 mem {
 937                         polling-delay-passive = <1000>;
 938                         polling-delay = <1000>;
 939
 940                         thermal-sensors =
 941                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
 942                 };
 943
 944                 gpu {
 945                         polling-delay-passive = <1000>;
 946                         polling-delay = <1000>;
 947
 948                         thermal-sensors =
 949                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
 950                 };
 951
 952                 pllx {
 953                         polling-delay-passive = <1000>;
 954                         polling-delay = <1000>;
 955
 956                         thermal-sensors =
 957                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
 958                 };
 959         };
 960
 961         timer {
 962                 compatible = "arm,armv7-timer";
 963                 interrupts = <GIC_PPI 13
 964                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 965                              <GIC_PPI 14
 966                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 967                              <GIC_PPI 11
 968                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 969                              <GIC_PPI 10
 970                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 971                 interrupt-parent = <&gic>;
 972         };
 973 };