arch/arm/boot/dts/tegra30.dtsi

   1 #include <dt-bindings/clock/tegra30-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/memory/tegra30-mc.h>
   4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6
   7 #include "skeleton.dtsi"
   8
   9 / {
  10         compatible = "nvidia,tegra30";
  11         interrupt-parent = <&lic>;
  12
  13         pcie-controller@00003000 {
  14                 compatible = "nvidia,tegra30-pcie";
  15                 device_type = "pci";
  16                 reg = <0x00003000 0x00000800   /* PADS registers */
  17                        0x00003800 0x00000200   /* AFI registers */
  18                        0x10000000 0x10000000>; /* configuration space */
  19                 reg-names = "pads", "afi", "cs";
  20                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
  21                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  22                 interrupt-names = "intr", "msi";
  23
  24                 #interrupt-cells = <1>;
  25                 interrupt-map-mask = <0 0 0 0>;
  26                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  27
  28                 bus-range = <0x00 0xff>;
  29                 #address-cells = <3>;
  30                 #size-cells = <2>;
  31
  32                 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
  33                           0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
  34                           0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
  35                           0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
  36                           0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */
  37                           0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
  38
  39                 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
  40                          <&tegra_car TEGRA30_CLK_AFI>,
  41                          <&tegra_car TEGRA30_CLK_PLL_E>,
  42                          <&tegra_car TEGRA30_CLK_CML0>;
  43                 clock-names = "pex", "afi", "pll_e", "cml";
  44                 resets = <&tegra_car 70>,
  45                          <&tegra_car 72>,
  46                          <&tegra_car 74>;
  47                 reset-names = "pex", "afi", "pcie_x";
  48                 status = "disabled";
  49
  50                 pci@1,0 {
  51                         device_type = "pci";
  52                         assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
  53                         reg = <0x000800 0 0 0 0>;
  54                         status = "disabled";
  55
  56                         #address-cells = <3>;
  57                         #size-cells = <2>;
  58                         ranges;
  59
  60                         nvidia,num-lanes = <2>;
  61                 };
  62
  63                 pci@2,0 {
  64                         device_type = "pci";
  65                         assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
  66                         reg = <0x001000 0 0 0 0>;
  67                         status = "disabled";
  68
  69                         #address-cells = <3>;
  70                         #size-cells = <2>;
  71                         ranges;
  72
  73                         nvidia,num-lanes = <2>;
  74                 };
  75
  76                 pci@3,0 {
  77                         device_type = "pci";
  78                         assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
  79                         reg = <0x001800 0 0 0 0>;
  80                         status = "disabled";
  81
  82                         #address-cells = <3>;
  83                         #size-cells = <2>;
  84                         ranges;
  85
  86                         nvidia,num-lanes = <2>;
  87                 };
  88         };
  89
  90         host1x@50000000 {
  91                 compatible = "nvidia,tegra30-host1x", "simple-bus";
  92                 reg = <0x50000000 0x00024000>;
  93                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  94                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  95                 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
  96                 resets = <&tegra_car 28>;
  97                 reset-names = "host1x";
  98
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101
 102                 ranges = <0x54000000 0x54000000 0x04000000>;
 103
 104                 mpe@54040000 {
 105                         compatible = "nvidia,tegra30-mpe";
 106                         reg = <0x54040000 0x00040000>;
 107                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 108                         clocks = <&tegra_car TEGRA30_CLK_MPE>;
 109                         resets = <&tegra_car 60>;
 110                         reset-names = "mpe";
 111                 };
 112
 113                 vi@54080000 {
 114                         compatible = "nvidia,tegra30-vi";
 115                         reg = <0x54080000 0x00040000>;
 116                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 117                         clocks = <&tegra_car TEGRA30_CLK_VI>;
 118                         resets = <&tegra_car 20>;
 119                         reset-names = "vi";
 120                 };
 121
 122                 epp@540c0000 {
 123                         compatible = "nvidia,tegra30-epp";
 124                         reg = <0x540c0000 0x00040000>;
 125                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 126                         clocks = <&tegra_car TEGRA30_CLK_EPP>;
 127                         resets = <&tegra_car 19>;
 128                         reset-names = "epp";
 129                 };
 130
 131                 isp@54100000 {
 132                         compatible = "nvidia,tegra30-isp";
 133                         reg = <0x54100000 0x00040000>;
 134                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 135                         clocks = <&tegra_car TEGRA30_CLK_ISP>;
 136                         resets = <&tegra_car 23>;
 137                         reset-names = "isp";
 138                 };
 139
 140                 gr2d@54140000 {
 141                         compatible = "nvidia,tegra30-gr2d";
 142                         reg = <0x54140000 0x00040000>;
 143                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 144                         clocks = <&tegra_car TEGRA30_CLK_GR2D>;
 145                         resets = <&tegra_car 21>;
 146                         reset-names = "2d";
 147                 };
 148
 149                 gr3d@54180000 {
 150                         compatible = "nvidia,tegra30-gr3d";
 151                         reg = <0x54180000 0x00040000>;
 152                         clocks = <&tegra_car TEGRA30_CLK_GR3D
 153                                   &tegra_car TEGRA30_CLK_GR3D2>;
 154                         clock-names = "3d", "3d2";
 155                         resets = <&tegra_car 24>,
 156                                  <&tegra_car 98>;
 157                         reset-names = "3d", "3d2";
 158                 };
 159
 160                 dc@54200000 {
 161                         compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
 162                         reg = <0x54200000 0x00040000>;
 163                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 164                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
 165                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 166                         clock-names = "dc", "parent";
 167                         resets = <&tegra_car 27>;
 168                         reset-names = "dc";
 169
 170                         iommus = <&mc TEGRA_SWGROUP_DC>;
 171
 172                         nvidia,head = <0>;
 173
 174                         rgb {
 175                                 status = "disabled";
 176                         };
 177                 };
 178
 179                 dc@54240000 {
 180                         compatible = "nvidia,tegra30-dc";
 181                         reg = <0x54240000 0x00040000>;
 182                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 183                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
 184                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 185                         clock-names = "dc", "parent";
 186                         resets = <&tegra_car 26>;
 187                         reset-names = "dc";
 188
 189                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 190
 191                         nvidia,head = <1>;
 192
 193                         rgb {
 194                                 status = "disabled";
 195                         };
 196                 };
 197
 198                 hdmi@54280000 {
 199                         compatible = "nvidia,tegra30-hdmi";
 200                         reg = <0x54280000 0x00040000>;
 201                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 202                         clocks = <&tegra_car TEGRA30_CLK_HDMI>,
 203                                  <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
 204                         clock-names = "hdmi", "parent";
 205                         resets = <&tegra_car 51>;
 206                         reset-names = "hdmi";
 207                         status = "disabled";
 208                 };
 209
 210                 tvo@542c0000 {
 211                         compatible = "nvidia,tegra30-tvo";
 212                         reg = <0x542c0000 0x00040000>;
 213                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 214                         clocks = <&tegra_car TEGRA30_CLK_TVO>;
 215                         status = "disabled";
 216                 };
 217
 218                 dsi@54300000 {
 219                         compatible = "nvidia,tegra30-dsi";
 220                         reg = <0x54300000 0x00040000>;
 221                         clocks = <&tegra_car TEGRA30_CLK_DSIA>;
 222                         resets = <&tegra_car 48>;
 223                         reset-names = "dsi";
 224                         status = "disabled";
 225                 };
 226         };
 227
 228         timer@50040600 {
 229                 compatible = "arm,cortex-a9-twd-timer";
 230                 reg = <0x50040600 0x20>;
 231                 interrupt-parent = <&intc>;
 232                 interrupts = <GIC_PPI 13
 233                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 234                 clocks = <&tegra_car TEGRA30_CLK_TWD>;
 235         };
 236
 237         intc: interrupt-controller@50041000 {
 238                 compatible = "arm,cortex-a9-gic";
 239                 reg = <0x50041000 0x1000
 240                        0x50040100 0x0100>;
 241                 interrupt-controller;
 242                 #interrupt-cells = <3>;
 243                 interrupt-parent = <&intc>;
 244         };
 245
 246         cache-controller@50043000 {
 247                 compatible = "arm,pl310-cache";
 248                 reg = <0x50043000 0x1000>;
 249                 arm,data-latency = <6 6 2>;
 250                 arm,tag-latency = <5 5 2>;
 251                 cache-unified;
 252                 cache-level = <2>;
 253         };
 254
 255         lic: interrupt-controller@60004000 {
 256                 compatible = "nvidia,tegra30-ictlr";
 257                 reg = <0x60004000 0x100>,
 258                       <0x60004100 0x50>,
 259                       <0x60004200 0x50>,
 260                       <0x60004300 0x50>,
 261                       <0x60004400 0x50>;
 262                 interrupt-controller;
 263                 #interrupt-cells = <3>;
 264                 interrupt-parent = <&intc>;
 265         };
 266
 267         timer@60005000 {
 268                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 269                 reg = <0x60005000 0x400>;
 270                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 271                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 272                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 273                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 274                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 275                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 276                 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
 277         };
 278
 279         tegra_car: clock@60006000 {
 280                 compatible = "nvidia,tegra30-car";
 281                 reg = <0x60006000 0x1000>;
 282                 #clock-cells = <1>;
 283                 #reset-cells = <1>;
 284         };
 285
 286         flow-controller@60007000 {
 287                 compatible = "nvidia,tegra30-flowctrl";
 288                 reg = <0x60007000 0x1000>;
 289         };
 290
 291         apbdma: dma@6000a000 {
 292                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 293                 reg = <0x6000a000 0x1400>;
 294                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 295                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 296                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 297                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 298                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 299                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 300                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 301                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 302                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 303                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 305                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 306                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 307                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 308                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 309                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 310                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 311                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 312                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 313                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 314                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 315                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 316                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 317                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 318                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 319                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 320                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 321                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 322                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 323                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 324                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 325                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 326                 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 327                 resets = <&tegra_car 34>;
 328                 reset-names = "dma";
 329                 #dma-cells = <1>;
 330         };
 331
 332         ahb: ahb@6000c000 {
 333                 compatible = "nvidia,tegra30-ahb";
 334                 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
 335         };
 336
 337         gpio: gpio@6000d000 {
 338                 compatible = "nvidia,tegra30-gpio";
 339                 reg = <0x6000d000 0x1000>;
 340                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 341                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 342                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 343                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 344                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 345                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 346                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 347                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 348                 #gpio-cells = <2>;
 349                 gpio-controller;
 350                 #interrupt-cells = <2>;
 351                 interrupt-controller;
 352                 gpio-ranges = <&pinmux 0 0 248>;
 353         };
 354
 355         apbmisc@70000800 {
 356                 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
 357                 reg = <0x70000800 0x64   /* Chip revision */
 358                        0x70000008 0x04>; /* Strapping options */
 359         };
 360
 361         pinmux: pinmux@70000868 {
 362                 compatible = "nvidia,tegra30-pinmux";
 363                 reg = <0x70000868 0xd4    /* Pad control registers */
 364                        0x70003000 0x3e4>; /* Mux registers */
 365         };
 366
 367         /*
 368          * There are two serial driver i.e. 8250 based simple serial
 369          * driver and APB DMA based serial driver for higher baudrate
 370          * and performace. To enable the 8250 based driver, the compatible
 371          * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
 372          * the APB DMA based serial driver, the comptible is
 373          * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 374          */
 375         uarta: serial@70006000 {
 376                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 377                 reg = <0x70006000 0x40>;
 378                 reg-shift = <2>;
 379                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 380                 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 381                 resets = <&tegra_car 6>;
 382                 reset-names = "serial";
 383                 dmas = <&apbdma 8>, <&apbdma 8>;
 384                 dma-names = "rx", "tx";
 385                 status = "disabled";
 386         };
 387
 388         uartb: serial@70006040 {
 389                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 390                 reg = <0x70006040 0x40>;
 391                 reg-shift = <2>;
 392                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 393                 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 394                 resets = <&tegra_car 7>;
 395                 reset-names = "serial";
 396                 dmas = <&apbdma 9>, <&apbdma 9>;
 397                 dma-names = "rx", "tx";
 398                 status = "disabled";
 399         };
 400
 401         uartc: serial@70006200 {
 402                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 403                 reg = <0x70006200 0x100>;
 404                 reg-shift = <2>;
 405                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 406                 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 407                 resets = <&tegra_car 55>;
 408                 reset-names = "serial";
 409                 dmas = <&apbdma 10>, <&apbdma 10>;
 410                 dma-names = "rx", "tx";
 411                 status = "disabled";
 412         };
 413
 414         uartd: serial@70006300 {
 415                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 416                 reg = <0x70006300 0x100>;
 417                 reg-shift = <2>;
 418                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 419                 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 420                 resets = <&tegra_car 65>;
 421                 reset-names = "serial";
 422                 dmas = <&apbdma 19>, <&apbdma 19>;
 423                 dma-names = "rx", "tx";
 424                 status = "disabled";
 425         };
 426
 427         uarte: serial@70006400 {
 428                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 429                 reg = <0x70006400 0x100>;
 430                 reg-shift = <2>;
 431                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 432                 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 433                 resets = <&tegra_car 66>;
 434                 reset-names = "serial";
 435                 dmas = <&apbdma 20>, <&apbdma 20>;
 436                 dma-names = "rx", "tx";
 437                 status = "disabled";
 438         };
 439
 440         pwm: pwm@7000a000 {
 441                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 442                 reg = <0x7000a000 0x100>;
 443                 #pwm-cells = <2>;
 444                 clocks = <&tegra_car TEGRA30_CLK_PWM>;
 445                 resets = <&tegra_car 17>;
 446                 reset-names = "pwm";
 447                 status = "disabled";
 448         };
 449
 450         rtc@7000e000 {
 451                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 452                 reg = <0x7000e000 0x100>;
 453                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 454                 clocks = <&tegra_car TEGRA30_CLK_RTC>;
 455         };
 456
 457         i2c@7000c000 {
 458                 compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 459                 reg = <0x7000c000 0x100>;
 460                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 461                 #address-cells = <1>;
 462                 #size-cells = <0>;
 463                 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
 464                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 465                 clock-names = "div-clk", "fast-clk";
 466                 resets = <&tegra_car 12>;
 467                 reset-names = "i2c";
 468                 dmas = <&apbdma 21>, <&apbdma 21>;
 469                 dma-names = "rx", "tx";
 470                 status = "disabled";
 471         };
 472
 473         i2c@7000c400 {
 474                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 475                 reg = <0x7000c400 0x100>;
 476                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 477                 #address-cells = <1>;
 478                 #size-cells = <0>;
 479                 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
 480                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 481                 clock-names = "div-clk", "fast-clk";
 482                 resets = <&tegra_car 54>;
 483                 reset-names = "i2c";
 484                 dmas = <&apbdma 22>, <&apbdma 22>;
 485                 dma-names = "rx", "tx";
 486                 status = "disabled";
 487         };
 488
 489         i2c@7000c500 {
 490                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 491                 reg = <0x7000c500 0x100>;
 492                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 493                 #address-cells = <1>;
 494                 #size-cells = <0>;
 495                 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
 496                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 497                 clock-names = "div-clk", "fast-clk";
 498                 resets = <&tegra_car 67>;
 499                 reset-names = "i2c";
 500                 dmas = <&apbdma 23>, <&apbdma 23>;
 501                 dma-names = "rx", "tx";
 502                 status = "disabled";
 503         };
 504
 505         i2c@7000c700 {
 506                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 507                 reg = <0x7000c700 0x100>;
 508                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 509                 #address-cells = <1>;
 510                 #size-cells = <0>;
 511                 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
 512                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 513                 resets = <&tegra_car 103>;
 514                 reset-names = "i2c";
 515                 clock-names = "div-clk", "fast-clk";
 516                 dmas = <&apbdma 26>, <&apbdma 26>;
 517                 dma-names = "rx", "tx";
 518                 status = "disabled";
 519         };
 520
 521         i2c@7000d000 {
 522                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 523                 reg = <0x7000d000 0x100>;
 524                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 525                 #address-cells = <1>;
 526                 #size-cells = <0>;
 527                 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
 528                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 529                 clock-names = "div-clk", "fast-clk";
 530                 resets = <&tegra_car 47>;
 531                 reset-names = "i2c";
 532                 dmas = <&apbdma 24>, <&apbdma 24>;
 533                 dma-names = "rx", "tx";
 534                 status = "disabled";
 535         };
 536
 537         spi@7000d400 {
 538                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 539                 reg = <0x7000d400 0x200>;
 540                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 541                 #address-cells = <1>;
 542                 #size-cells = <0>;
 543                 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
 544                 resets = <&tegra_car 41>;
 545                 reset-names = "spi";
 546                 dmas = <&apbdma 15>, <&apbdma 15>;
 547                 dma-names = "rx", "tx";
 548                 status = "disabled";
 549         };
 550
 551         spi@7000d600 {
 552                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 553                 reg = <0x7000d600 0x200>;
 554                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 555                 #address-cells = <1>;
 556                 #size-cells = <0>;
 557                 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
 558                 resets = <&tegra_car 44>;
 559                 reset-names = "spi";
 560                 dmas = <&apbdma 16>, <&apbdma 16>;
 561                 dma-names = "rx", "tx";
 562                 status = "disabled";
 563         };
 564
 565         spi@7000d800 {
 566                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 567                 reg = <0x7000d800 0x200>;
 568                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 569                 #address-cells = <1>;
 570                 #size-cells = <0>;
 571                 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
 572                 resets = <&tegra_car 46>;
 573                 reset-names = "spi";
 574                 dmas = <&apbdma 17>, <&apbdma 17>;
 575                 dma-names = "rx", "tx";
 576                 status = "disabled";
 577         };
 578
 579         spi@7000da00 {
 580                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 581                 reg = <0x7000da00 0x200>;
 582                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 583                 #address-cells = <1>;
 584                 #size-cells = <0>;
 585                 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
 586                 resets = <&tegra_car 68>;
 587                 reset-names = "spi";
 588                 dmas = <&apbdma 18>, <&apbdma 18>;
 589                 dma-names = "rx", "tx";
 590                 status = "disabled";
 591         };
 592
 593         spi@7000dc00 {
 594                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 595                 reg = <0x7000dc00 0x200>;
 596                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 597                 #address-cells = <1>;
 598                 #size-cells = <0>;
 599                 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
 600                 resets = <&tegra_car 104>;
 601                 reset-names = "spi";
 602                 dmas = <&apbdma 27>, <&apbdma 27>;
 603                 dma-names = "rx", "tx";
 604                 status = "disabled";
 605         };
 606
 607         spi@7000de00 {
 608                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 609                 reg = <0x7000de00 0x200>;
 610                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 611                 #address-cells = <1>;
 612                 #size-cells = <0>;
 613                 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
 614                 resets = <&tegra_car 106>;
 615                 reset-names = "spi";
 616                 dmas = <&apbdma 28>, <&apbdma 28>;
 617                 dma-names = "rx", "tx";
 618                 status = "disabled";
 619         };
 620
 621         kbc@7000e200 {
 622                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 623                 reg = <0x7000e200 0x100>;
 624                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 625                 clocks = <&tegra_car TEGRA30_CLK_KBC>;
 626                 resets = <&tegra_car 36>;
 627                 reset-names = "kbc";
 628                 status = "disabled";
 629         };
 630
 631         pmc@7000e400 {
 632                 compatible = "nvidia,tegra30-pmc";
 633                 reg = <0x7000e400 0x400>;
 634                 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
 635                 clock-names = "pclk", "clk32k_in";
 636         };
 637
 638         mc: memory-controller@7000f000 {
 639                 compatible = "nvidia,tegra30-mc";
 640                 reg = <0x7000f000 0x400>;
 641                 clocks = <&tegra_car TEGRA30_CLK_MC>;
 642                 clock-names = "mc";
 643
 644                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 645
 646                 #iommu-cells = <1>;
 647         };
 648
 649         fuse@7000f800 {
 650                 compatible = "nvidia,tegra30-efuse";
 651                 reg = <0x7000f800 0x400>;
 652                 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
 653                 clock-names = "fuse";
 654                 resets = <&tegra_car 39>;
 655                 reset-names = "fuse";
 656         };
 657
 658         hda@70030000 {
 659                 compatible = "nvidia,tegra30-hda";
 660                 reg = <0x70030000 0x10000>;
 661                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 662                 clocks = <&tegra_car TEGRA30_CLK_HDA>,
 663                          <&tegra_car TEGRA30_CLK_HDA2HDMI>,
 664                          <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
 665                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 666                 resets = <&tegra_car 125>, /* hda */
 667                          <&tegra_car 128>, /* hda2hdmi */
 668                          <&tegra_car 111>; /* hda2codec_2x */
 669                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 670                 status = "disabled";
 671         };
 672
 673         ahub@70080000 {
 674                 compatible = "nvidia,tegra30-ahub";
 675                 reg = <0x70080000 0x200
 676                        0x70080200 0x100>;
 677                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 678                 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
 679                          <&tegra_car TEGRA30_CLK_APBIF>;
 680                 clock-names = "d_audio", "apbif";
 681                 resets = <&tegra_car 106>, /* d_audio */
 682                          <&tegra_car 107>, /* apbif */
 683                          <&tegra_car 30>,  /* i2s0 */
 684                          <&tegra_car 11>,  /* i2s1 */
 685                          <&tegra_car 18>,  /* i2s2 */
 686                          <&tegra_car 101>, /* i2s3 */
 687                          <&tegra_car 102>, /* i2s4 */
 688                          <&tegra_car 108>, /* dam0 */
 689                          <&tegra_car 109>, /* dam1 */
 690                          <&tegra_car 110>, /* dam2 */
 691                          <&tegra_car 10>;  /* spdif */
 692                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 693                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 694                               "spdif";
 695                 dmas = <&apbdma 1>, <&apbdma 1>,
 696                        <&apbdma 2>, <&apbdma 2>,
 697                        <&apbdma 3>, <&apbdma 3>,
 698                        <&apbdma 4>, <&apbdma 4>;
 699                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 700                             "rx3", "tx3";
 701                 ranges;
 702                 #address-cells = <1>;
 703                 #size-cells = <1>;
 704
 705                 tegra_i2s0: i2s@70080300 {
 706                         compatible = "nvidia,tegra30-i2s";
 707                         reg = <0x70080300 0x100>;
 708                         nvidia,ahub-cif-ids = <4 4>;
 709                         clocks = <&tegra_car TEGRA30_CLK_I2S0>;
 710                         resets = <&tegra_car 30>;
 711                         reset-names = "i2s";
 712                         status = "disabled";
 713                 };
 714
 715                 tegra_i2s1: i2s@70080400 {
 716                         compatible = "nvidia,tegra30-i2s";
 717                         reg = <0x70080400 0x100>;
 718                         nvidia,ahub-cif-ids = <5 5>;
 719                         clocks = <&tegra_car TEGRA30_CLK_I2S1>;
 720                         resets = <&tegra_car 11>;
 721                         reset-names = "i2s";
 722                         status = "disabled";
 723                 };
 724
 725                 tegra_i2s2: i2s@70080500 {
 726                         compatible = "nvidia,tegra30-i2s";
 727                         reg = <0x70080500 0x100>;
 728                         nvidia,ahub-cif-ids = <6 6>;
 729                         clocks = <&tegra_car TEGRA30_CLK_I2S2>;
 730                         resets = <&tegra_car 18>;
 731                         reset-names = "i2s";
 732                         status = "disabled";
 733                 };
 734
 735                 tegra_i2s3: i2s@70080600 {
 736                         compatible = "nvidia,tegra30-i2s";
 737                         reg = <0x70080600 0x100>;
 738                         nvidia,ahub-cif-ids = <7 7>;
 739                         clocks = <&tegra_car TEGRA30_CLK_I2S3>;
 740                         resets = <&tegra_car 101>;
 741                         reset-names = "i2s";
 742                         status = "disabled";
 743                 };
 744
 745                 tegra_i2s4: i2s@70080700 {
 746                         compatible = "nvidia,tegra30-i2s";
 747                         reg = <0x70080700 0x100>;
 748                         nvidia,ahub-cif-ids = <8 8>;
 749                         clocks = <&tegra_car TEGRA30_CLK_I2S4>;
 750                         resets = <&tegra_car 102>;
 751                         reset-names = "i2s";
 752                         status = "disabled";
 753                 };
 754         };
 755
 756         sdhci@78000000 {
 757                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 758                 reg = <0x78000000 0x200>;
 759                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 760                 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
 761                 resets = <&tegra_car 14>;
 762                 reset-names = "sdhci";
 763                 status = "disabled";
 764         };
 765
 766         sdhci@78000200 {
 767                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 768                 reg = <0x78000200 0x200>;
 769                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 770                 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
 771                 resets = <&tegra_car 9>;
 772                 reset-names = "sdhci";
 773                 status = "disabled";
 774         };
 775
 776         sdhci@78000400 {
 777                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 778                 reg = <0x78000400 0x200>;
 779                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 780                 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 781                 resets = <&tegra_car 69>;
 782                 reset-names = "sdhci";
 783                 status = "disabled";
 784         };
 785
 786         sdhci@78000600 {
 787                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 788                 reg = <0x78000600 0x200>;
 789                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 790                 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
 791                 resets = <&tegra_car 15>;
 792                 reset-names = "sdhci";
 793                 status = "disabled";
 794         };
 795
 796         usb@7d000000 {
 797                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 798                 reg = <0x7d000000 0x4000>;
 799                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 800                 phy_type = "utmi";
 801                 clocks = <&tegra_car TEGRA30_CLK_USBD>;
 802                 resets = <&tegra_car 22>;
 803                 reset-names = "usb";
 804                 nvidia,needs-double-reset;
 805                 nvidia,phy = <&phy1>;
 806                 status = "disabled";
 807         };
 808
 809         phy1: usb-phy@7d000000 {
 810                 compatible = "nvidia,tegra30-usb-phy";
 811                 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
 812                 phy_type = "utmi";
 813                 clocks = <&tegra_car TEGRA30_CLK_USBD>,
 814                          <&tegra_car TEGRA30_CLK_PLL_U>,
 815                          <&tegra_car TEGRA30_CLK_USBD>;
 816                 clock-names = "reg", "pll_u", "utmi-pads";
 817                 resets = <&tegra_car 22>, <&tegra_car 22>;
 818                 reset-names = "usb", "utmi-pads";
 819                 nvidia,hssync-start-delay = <9>;
 820                 nvidia,idle-wait-delay = <17>;
 821                 nvidia,elastic-limit = <16>;
 822                 nvidia,term-range-adj = <6>;
 823                 nvidia,xcvr-setup = <51>;
 824                 nvidia.xcvr-setup-use-fuses;
 825                 nvidia,xcvr-lsfslew = <1>;
 826                 nvidia,xcvr-lsrslew = <1>;
 827                 nvidia,xcvr-hsslew = <32>;
 828                 nvidia,hssquelch-level = <2>;
 829                 nvidia,hsdiscon-level = <5>;
 830                 nvidia,has-utmi-pad-registers;
 831                 status = "disabled";
 832         };
 833
 834         usb@7d004000 {
 835                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 836                 reg = <0x7d004000 0x4000>;
 837                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 838                 phy_type = "utmi";
 839                 clocks = <&tegra_car TEGRA30_CLK_USB2>;
 840                 resets = <&tegra_car 58>;
 841                 reset-names = "usb";
 842                 nvidia,phy = <&phy2>;
 843                 status = "disabled";
 844         };
 845
 846         phy2: usb-phy@7d004000 {
 847                 compatible = "nvidia,tegra30-usb-phy";
 848                 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
 849                 phy_type = "utmi";
 850                 clocks = <&tegra_car TEGRA30_CLK_USB2>,
 851                          <&tegra_car TEGRA30_CLK_PLL_U>,
 852                          <&tegra_car TEGRA30_CLK_USBD>;
 853                 clock-names = "reg", "pll_u", "utmi-pads";
 854                 resets = <&tegra_car 58>, <&tegra_car 22>;
 855                 reset-names = "usb", "utmi-pads";
 856                 nvidia,hssync-start-delay = <9>;
 857                 nvidia,idle-wait-delay = <17>;
 858                 nvidia,elastic-limit = <16>;
 859                 nvidia,term-range-adj = <6>;
 860                 nvidia,xcvr-setup = <51>;
 861                 nvidia.xcvr-setup-use-fuses;
 862                 nvidia,xcvr-lsfslew = <2>;
 863                 nvidia,xcvr-lsrslew = <2>;
 864                 nvidia,xcvr-hsslew = <32>;
 865                 nvidia,hssquelch-level = <2>;
 866                 nvidia,hsdiscon-level = <5>;
 867                 status = "disabled";
 868         };
 869
 870         usb@7d008000 {
 871                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 872                 reg = <0x7d008000 0x4000>;
 873                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 874                 phy_type = "utmi";
 875                 clocks = <&tegra_car TEGRA30_CLK_USB3>;
 876                 resets = <&tegra_car 59>;
 877                 reset-names = "usb";
 878                 nvidia,phy = <&phy3>;
 879                 status = "disabled";
 880         };
 881
 882         phy3: usb-phy@7d008000 {
 883                 compatible = "nvidia,tegra30-usb-phy";
 884                 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
 885                 phy_type = "utmi";
 886                 clocks = <&tegra_car TEGRA30_CLK_USB3>,
 887                          <&tegra_car TEGRA30_CLK_PLL_U>,
 888                          <&tegra_car TEGRA30_CLK_USBD>;
 889                 clock-names = "reg", "pll_u", "utmi-pads";
 890                 resets = <&tegra_car 59>, <&tegra_car 22>;
 891                 reset-names = "usb", "utmi-pads";
 892                 nvidia,hssync-start-delay = <0>;
 893                 nvidia,idle-wait-delay = <17>;
 894                 nvidia,elastic-limit = <16>;
 895                 nvidia,term-range-adj = <6>;
 896                 nvidia,xcvr-setup = <51>;
 897                 nvidia.xcvr-setup-use-fuses;
 898                 nvidia,xcvr-lsfslew = <2>;
 899                 nvidia,xcvr-lsrslew = <2>;
 900                 nvidia,xcvr-hsslew = <32>;
 901                 nvidia,hssquelch-level = <2>;
 902                 nvidia,hsdiscon-level = <5>;
 903                 status = "disabled";
 904         };
 905
 906         cpus {
 907                 #address-cells = <1>;
 908                 #size-cells = <0>;
 909
 910                 cpu@0 {
 911                         device_type = "cpu";
 912                         compatible = "arm,cortex-a9";
 913                         reg = <0>;
 914                 };
 915
 916                 cpu@1 {
 917                         device_type = "cpu";
 918                         compatible = "arm,cortex-a9";
 919                         reg = <1>;
 920                 };
 921
 922                 cpu@2 {
 923                         device_type = "cpu";
 924                         compatible = "arm,cortex-a9";
 925                         reg = <2>;
 926                 };
 927
 928                 cpu@3 {
 929                         device_type = "cpu";
 930                         compatible = "arm,cortex-a9";
 931                         reg = <3>;
 932                 };
 933         };
 934
 935         pmu {
 936                 compatible = "arm,cortex-a9-pmu";
 937                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 938                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 939                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 940                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 941         };
 942 };