2 * arch/arm/include/asm/atomic.h
4 * Copyright (C) 1996 Russell King.
5 * Copyright (C) 2002 Deep Blue Solutions Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef __ASM_ARM_ATOMIC_H
12 #define __ASM_ARM_ATOMIC_H
14 #include <linux/compiler.h>
15 #include <linux/prefetch.h>
16 #include <linux/types.h>
17 #include <linux/irqflags.h>
18 #include <asm/barrier.h>
19 #include <asm/cmpxchg.h>
21 #define ATOMIC_INIT(i) { (i) }
26 * On ARM, ordinary assignment (str instruction) doesn't clear the local
27 * strex/ldrex monitor on some implementations. The reason we can use it for
28 * atomic_set() is the clrex or dummy strex done on every exception return.
30 #define atomic_read(v) (*(volatile int *)&(v)->counter)
31 #define atomic_set(v,i) (((v)->counter) = (i))
33 #if __LINUX_ARM_ARCH__ >= 6
36 * ARMv6 UP and SMP safe atomic ops. We use load exclusive and
37 * store exclusive to ensure that these are atomic. We may loop
38 * to ensure that the update happens.
40 static inline void atomic_add(int i, atomic_t *v)
45 prefetchw(&v->counter);
46 __asm__ __volatile__("@ atomic_add\n"
49 " strex %1, %0, [%3]\n"
52 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
53 : "r" (&v->counter), "Ir" (i)
57 static inline int atomic_add_return(int i, atomic_t *v)
64 __asm__ __volatile__("@ atomic_add_return\n"
67 " strex %1, %0, [%3]\n"
70 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
71 : "r" (&v->counter), "Ir" (i)
79 static inline void atomic_sub(int i, atomic_t *v)
84 prefetchw(&v->counter);
85 __asm__ __volatile__("@ atomic_sub\n"
88 " strex %1, %0, [%3]\n"
91 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
92 : "r" (&v->counter), "Ir" (i)
96 static inline int atomic_sub_return(int i, atomic_t *v)
103 __asm__ __volatile__("@ atomic_sub_return\n"
104 "1: ldrex %0, [%3]\n"
106 " strex %1, %0, [%3]\n"
109 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
110 : "r" (&v->counter), "Ir" (i)
118 static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
120 unsigned long oldval, res;
125 __asm__ __volatile__("@ atomic_cmpxchg\n"
129 "strexeq %0, %5, [%3]\n"
130 : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
131 : "r" (&ptr->counter), "Ir" (old), "r" (new)
140 static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
142 unsigned long tmp, tmp2;
145 __asm__ __volatile__("@ atomic_clear_mask\n"
146 "1: ldrex %0, [%3]\n"
148 " strex %1, %0, [%3]\n"
151 : "=&r" (tmp), "=&r" (tmp2), "+Qo" (*addr)
152 : "r" (addr), "Ir" (mask)
156 #else /* ARM_ARCH_6 */
159 #error SMP not supported on pre-ARMv6 CPUs
162 static inline int atomic_add_return(int i, atomic_t *v)
167 raw_local_irq_save(flags);
169 v->counter = val += i;
170 raw_local_irq_restore(flags);
174 #define atomic_add(i, v) (void) atomic_add_return(i, v)
176 static inline int atomic_sub_return(int i, atomic_t *v)
181 raw_local_irq_save(flags);
183 v->counter = val -= i;
184 raw_local_irq_restore(flags);
188 #define atomic_sub(i, v) (void) atomic_sub_return(i, v)
190 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
195 raw_local_irq_save(flags);
197 if (likely(ret == old))
199 raw_local_irq_restore(flags);
204 static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
208 raw_local_irq_save(flags);
210 raw_local_irq_restore(flags);
213 #endif /* __LINUX_ARM_ARCH__ */
215 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
217 static inline int __atomic_add_unless(atomic_t *v, int a, int u)
222 while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
227 #define atomic_inc(v) atomic_add(1, v)
228 #define atomic_dec(v) atomic_sub(1, v)
230 #define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
231 #define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
232 #define atomic_inc_return(v) (atomic_add_return(1, v))
233 #define atomic_dec_return(v) (atomic_sub_return(1, v))
234 #define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
236 #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
238 #define smp_mb__before_atomic_dec() smp_mb()
239 #define smp_mb__after_atomic_dec() smp_mb()
240 #define smp_mb__before_atomic_inc() smp_mb()
241 #define smp_mb__after_atomic_inc() smp_mb()
243 #ifndef CONFIG_GENERIC_ATOMIC64
245 u64 __aligned(8) counter;
248 #define ATOMIC64_INIT(i) { (i) }
250 #ifdef CONFIG_ARM_LPAE
251 static inline u64 atomic64_read(const atomic64_t *v)
255 __asm__ __volatile__("@ atomic64_read\n"
256 " ldrd %0, %H0, [%1]"
258 : "r" (&v->counter), "Qo" (v->counter)
264 static inline void atomic64_set(atomic64_t *v, u64 i)
266 __asm__ __volatile__("@ atomic64_set\n"
267 " strd %2, %H2, [%1]"
269 : "r" (&v->counter), "r" (i)
273 static inline u64 atomic64_read(const atomic64_t *v)
277 __asm__ __volatile__("@ atomic64_read\n"
278 " ldrexd %0, %H0, [%1]"
280 : "r" (&v->counter), "Qo" (v->counter)
286 static inline void atomic64_set(atomic64_t *v, u64 i)
290 prefetchw(&v->counter);
291 __asm__ __volatile__("@ atomic64_set\n"
292 "1: ldrexd %0, %H0, [%2]\n"
293 " strexd %0, %3, %H3, [%2]\n"
296 : "=&r" (tmp), "=Qo" (v->counter)
297 : "r" (&v->counter), "r" (i)
302 static inline void atomic64_add(u64 i, atomic64_t *v)
307 prefetchw(&v->counter);
308 __asm__ __volatile__("@ atomic64_add\n"
309 "1: ldrexd %0, %H0, [%3]\n"
311 " adc %H0, %H0, %H4\n"
312 " strexd %1, %0, %H0, [%3]\n"
315 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
316 : "r" (&v->counter), "r" (i)
320 static inline u64 atomic64_add_return(u64 i, atomic64_t *v)
327 __asm__ __volatile__("@ atomic64_add_return\n"
328 "1: ldrexd %0, %H0, [%3]\n"
330 " adc %H0, %H0, %H4\n"
331 " strexd %1, %0, %H0, [%3]\n"
334 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
335 : "r" (&v->counter), "r" (i)
343 static inline void atomic64_sub(u64 i, atomic64_t *v)
348 prefetchw(&v->counter);
349 __asm__ __volatile__("@ atomic64_sub\n"
350 "1: ldrexd %0, %H0, [%3]\n"
352 " sbc %H0, %H0, %H4\n"
353 " strexd %1, %0, %H0, [%3]\n"
356 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
357 : "r" (&v->counter), "r" (i)
361 static inline u64 atomic64_sub_return(u64 i, atomic64_t *v)
368 __asm__ __volatile__("@ atomic64_sub_return\n"
369 "1: ldrexd %0, %H0, [%3]\n"
371 " sbc %H0, %H0, %H4\n"
372 " strexd %1, %0, %H0, [%3]\n"
375 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
376 : "r" (&v->counter), "r" (i)
384 static inline u64 atomic64_cmpxchg(atomic64_t *ptr, u64 old, u64 new)
392 __asm__ __volatile__("@ atomic64_cmpxchg\n"
393 "ldrexd %1, %H1, [%3]\n"
397 "strexdeq %0, %5, %H5, [%3]"
398 : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
399 : "r" (&ptr->counter), "r" (old), "r" (new)
408 static inline u64 atomic64_xchg(atomic64_t *ptr, u64 new)
415 __asm__ __volatile__("@ atomic64_xchg\n"
416 "1: ldrexd %0, %H0, [%3]\n"
417 " strexd %1, %4, %H4, [%3]\n"
420 : "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter)
421 : "r" (&ptr->counter), "r" (new)
429 static inline u64 atomic64_dec_if_positive(atomic64_t *v)
436 __asm__ __volatile__("@ atomic64_dec_if_positive\n"
437 "1: ldrexd %0, %H0, [%3]\n"
439 " sbc %H0, %H0, #0\n"
442 " strexd %1, %0, %H0, [%3]\n"
446 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
455 static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u)
463 __asm__ __volatile__("@ atomic64_add_unless\n"
464 "1: ldrexd %0, %H0, [%4]\n"
470 " adc %H0, %H0, %H6\n"
471 " strexd %2, %0, %H0, [%4]\n"
475 : "=&r" (val), "+r" (ret), "=&r" (tmp), "+Qo" (v->counter)
476 : "r" (&v->counter), "r" (u), "r" (a)
485 #define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
486 #define atomic64_inc(v) atomic64_add(1LL, (v))
487 #define atomic64_inc_return(v) atomic64_add_return(1LL, (v))
488 #define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
489 #define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
490 #define atomic64_dec(v) atomic64_sub(1LL, (v))
491 #define atomic64_dec_return(v) atomic64_sub_return(1LL, (v))
492 #define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
493 #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
495 #endif /* !CONFIG_GENERIC_ATOMIC64 */