2 * Chip-specific setup code for the AT91SAM9G45 family
4 * Copyright (C) 2009 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/dma-mapping.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <mach/at91sam9g45.h>
20 #include <mach/at91_pmc.h>
21 #include <mach/at91_rstc.h>
29 /* --------------------------------------------------------------------
31 * -------------------------------------------------------------------- */
34 * The peripheral clocks.
36 static struct clk pioA_clk = {
38 .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
39 .type = CLK_TYPE_PERIPHERAL,
41 static struct clk pioB_clk = {
43 .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
44 .type = CLK_TYPE_PERIPHERAL,
46 static struct clk pioC_clk = {
48 .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
49 .type = CLK_TYPE_PERIPHERAL,
51 static struct clk pioDE_clk = {
53 .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
54 .type = CLK_TYPE_PERIPHERAL,
56 static struct clk trng_clk = {
58 .pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
59 .type = CLK_TYPE_PERIPHERAL,
61 static struct clk usart0_clk = {
63 .pmc_mask = 1 << AT91SAM9G45_ID_US0,
64 .type = CLK_TYPE_PERIPHERAL,
66 static struct clk usart1_clk = {
68 .pmc_mask = 1 << AT91SAM9G45_ID_US1,
69 .type = CLK_TYPE_PERIPHERAL,
71 static struct clk usart2_clk = {
73 .pmc_mask = 1 << AT91SAM9G45_ID_US2,
74 .type = CLK_TYPE_PERIPHERAL,
76 static struct clk usart3_clk = {
78 .pmc_mask = 1 << AT91SAM9G45_ID_US3,
79 .type = CLK_TYPE_PERIPHERAL,
81 static struct clk mmc0_clk = {
83 .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
84 .type = CLK_TYPE_PERIPHERAL,
86 static struct clk twi0_clk = {
88 .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
89 .type = CLK_TYPE_PERIPHERAL,
91 static struct clk twi1_clk = {
93 .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
94 .type = CLK_TYPE_PERIPHERAL,
96 static struct clk spi0_clk = {
98 .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
99 .type = CLK_TYPE_PERIPHERAL,
101 static struct clk spi1_clk = {
103 .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
104 .type = CLK_TYPE_PERIPHERAL,
106 static struct clk ssc0_clk = {
108 .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
109 .type = CLK_TYPE_PERIPHERAL,
111 static struct clk ssc1_clk = {
113 .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
114 .type = CLK_TYPE_PERIPHERAL,
116 static struct clk tcb0_clk = {
118 .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
119 .type = CLK_TYPE_PERIPHERAL,
121 static struct clk pwm_clk = {
123 .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
124 .type = CLK_TYPE_PERIPHERAL,
126 static struct clk tsc_clk = {
128 .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
129 .type = CLK_TYPE_PERIPHERAL,
131 static struct clk dma_clk = {
133 .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
134 .type = CLK_TYPE_PERIPHERAL,
136 static struct clk uhphs_clk = {
138 .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
139 .type = CLK_TYPE_PERIPHERAL,
141 static struct clk lcdc_clk = {
143 .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
144 .type = CLK_TYPE_PERIPHERAL,
146 static struct clk ac97_clk = {
148 .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
149 .type = CLK_TYPE_PERIPHERAL,
151 static struct clk macb_clk = {
153 .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
154 .type = CLK_TYPE_PERIPHERAL,
156 static struct clk isi_clk = {
158 .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
159 .type = CLK_TYPE_PERIPHERAL,
161 static struct clk udphs_clk = {
163 .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
164 .type = CLK_TYPE_PERIPHERAL,
166 static struct clk mmc1_clk = {
168 .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
169 .type = CLK_TYPE_PERIPHERAL,
172 /* Video decoder clock - Only for sam9m10/sam9m11 */
173 static struct clk vdec_clk = {
175 .pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
176 .type = CLK_TYPE_PERIPHERAL,
179 static struct clk *periph_clocks[] __initdata = {
210 static struct clk_lookup periph_clocks_lookups[] = {
211 /* One additional fake clock for macb_hclk */
212 CLKDEV_CON_ID("hclk", &macb_clk),
213 /* One additional fake clock for ohci */
214 CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
215 CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
216 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
217 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
218 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
219 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
220 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
221 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
222 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
223 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
224 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
225 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
226 CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
227 /* more usart lookup table for DT entries */
228 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
229 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
230 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
231 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
232 CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
233 /* fake hclk clock */
234 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
235 CLKDEV_CON_ID("pioA", &pioA_clk),
236 CLKDEV_CON_ID("pioB", &pioB_clk),
237 CLKDEV_CON_ID("pioC", &pioC_clk),
238 CLKDEV_CON_ID("pioD", &pioDE_clk),
239 CLKDEV_CON_ID("pioE", &pioDE_clk),
242 static struct clk_lookup usart_clocks_lookups[] = {
243 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
244 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
245 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
246 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
247 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
251 * The two programmable clocks.
252 * You must configure pin multiplexing to bring these signals out.
254 static struct clk pck0 = {
256 .pmc_mask = AT91_PMC_PCK0,
257 .type = CLK_TYPE_PROGRAMMABLE,
260 static struct clk pck1 = {
262 .pmc_mask = AT91_PMC_PCK1,
263 .type = CLK_TYPE_PROGRAMMABLE,
267 static void __init at91sam9g45_register_clocks(void)
271 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
272 clk_register(periph_clocks[i]);
274 clkdev_add_table(periph_clocks_lookups,
275 ARRAY_SIZE(periph_clocks_lookups));
276 clkdev_add_table(usart_clocks_lookups,
277 ARRAY_SIZE(usart_clocks_lookups));
279 if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
280 clk_register(&vdec_clk);
286 static struct clk_lookup console_clock_lookup;
288 void __init at91sam9g45_set_console_clock(int id)
290 if (id >= ARRAY_SIZE(usart_clocks_lookups))
293 console_clock_lookup.con_id = "usart";
294 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
295 clkdev_add(&console_clock_lookup);
298 /* --------------------------------------------------------------------
300 * -------------------------------------------------------------------- */
302 static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
304 .id = AT91SAM9G45_ID_PIOA,
305 .regbase = AT91SAM9G45_BASE_PIOA,
307 .id = AT91SAM9G45_ID_PIOB,
308 .regbase = AT91SAM9G45_BASE_PIOB,
310 .id = AT91SAM9G45_ID_PIOC,
311 .regbase = AT91SAM9G45_BASE_PIOC,
313 .id = AT91SAM9G45_ID_PIODE,
314 .regbase = AT91SAM9G45_BASE_PIOD,
316 .id = AT91SAM9G45_ID_PIODE,
317 .regbase = AT91SAM9G45_BASE_PIOE,
321 static void at91sam9g45_restart(char mode, const char *cmd)
323 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
326 /* --------------------------------------------------------------------
327 * AT91SAM9G45 processor initialization
328 * -------------------------------------------------------------------- */
330 static void __init at91sam9g45_map_io(void)
332 at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
333 init_consistent_dma_size(SZ_4M);
336 static void __init at91sam9g45_ioremap_registers(void)
338 at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
339 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
340 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
343 static void __init at91sam9g45_initialize(void)
345 arm_pm_restart = at91sam9g45_restart;
346 at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
348 /* Register GPIO subsystem */
349 at91_gpio_init(at91sam9g45_gpio, 5);
352 /* --------------------------------------------------------------------
353 * Interrupt initialization
354 * -------------------------------------------------------------------- */
357 * The default interrupt priority levels (0 = lowest, 7 = highest).
359 static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
360 7, /* Advanced Interrupt Controller (FIQ) */
361 7, /* System Peripherals */
362 1, /* Parallel IO Controller A */
363 1, /* Parallel IO Controller B */
364 1, /* Parallel IO Controller C */
365 1, /* Parallel IO Controller D and E */
371 0, /* Multimedia Card Interface 0 */
372 6, /* Two-Wire Interface 0 */
373 6, /* Two-Wire Interface 1 */
374 5, /* Serial Peripheral Interface 0 */
375 5, /* Serial Peripheral Interface 1 */
376 4, /* Serial Synchronous Controller 0 */
377 4, /* Serial Synchronous Controller 1 */
378 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
379 0, /* Pulse Width Modulation Controller */
380 0, /* Touch Screen Controller */
381 0, /* DMA Controller */
382 2, /* USB Host High Speed port */
383 3, /* LDC Controller */
384 5, /* AC97 Controller */
386 0, /* Image Sensor Interface */
387 2, /* USB Device High speed port */
389 0, /* Multimedia Card Interface 1 */
391 0, /* Advanced Interrupt Controller (IRQ0) */
394 struct at91_init_soc __initdata at91sam9g45_soc = {
395 .map_io = at91sam9g45_map_io,
396 .default_irq_priority = at91sam9g45_default_irq_priority,
397 .ioremap_registers = at91sam9g45_ioremap_registers,
398 .register_clocks = at91sam9g45_register_clocks,
399 .init = at91sam9g45_initialize,