arch/arm/mach-exynos/clock-exynos4.c

   1 /*
   2  * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS4 - Clock support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/syscore_ops.h>
  16
  17 #include <plat/cpu-freq.h>
  18 #include <plat/clock.h>
  19 #include <plat/cpu.h>
  20 #include <plat/pll.h>
  21 #include <plat/s5p-clock.h>
  22 #include <plat/clock-clksrc.h>
  23 #include <plat/pm.h>
  24
  25 #include <mach/map.h>
  26 #include <mach/regs-clock.h>
  27 #include <mach/sysmmu.h>
  28
  29 #include "common.h"
  30 #include "clock-exynos4.h"
  31
  32 #ifdef CONFIG_PM_SLEEP
  33 static struct sleep_save exynos4_clock_save[] = {
  34         SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
  35         SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
  36         SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
  37         SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
  38         SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
  39         SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
  40         SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
  41         SAVE_ITEM(EXYNOS4_CLKSRC_TV),
  42         SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
  43         SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
  44         SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
  45         SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
  46         SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
  47         SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
  48         SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
  49         SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
  50         SAVE_ITEM(EXYNOS4_CLKDIV_TV),
  51         SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
  52         SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
  53         SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
  54         SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
  55         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
  56         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
  57         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
  58         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
  59         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
  60         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
  61         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
  62         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
  63         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
  64         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
  65         SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
  66         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
  67         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
  68         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
  69         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
  70         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
  71         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
  72         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
  73         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
  74         SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
  75         SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
  76         SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
  77         SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
  78         SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
  79         SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
  80         SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
  81         SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
  82         SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
  83         SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
  84         SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
  85         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
  86         SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
  87         SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
  88         SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
  89         SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
  90         SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
  91         SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
  92         SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
  93         SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
  94         SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
  95 };
  96 #endif
  97
  98 static struct clk exynos4_clk_sclk_hdmi27m = {
  99         .name           = "sclk_hdmi27m",
 100         .rate           = 27000000,
 101 };
 102
 103 static struct clk exynos4_clk_sclk_hdmiphy = {
 104         .name           = "sclk_hdmiphy",
 105 };
 106
 107 static struct clk exynos4_clk_sclk_usbphy0 = {
 108         .name           = "sclk_usbphy0",
 109         .rate           = 27000000,
 110 };
 111
 112 static struct clk exynos4_clk_sclk_usbphy1 = {
 113         .name           = "sclk_usbphy1",
 114 };
 115
 116 static struct clk dummy_apb_pclk = {
 117         .name           = "apb_pclk",
 118         .id             = -1,
 119 };
 120
 121 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 122 {
 123         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
 124 }
 125
 126 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
 127 {
 128         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
 129 }
 130
 131 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
 132 {
 133         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
 134 }
 135
 136 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 137 {
 138         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
 139 }
 140
 141 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
 142 {
 143         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
 144 }
 145
 146 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
 147 {
 148         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
 149 }
 150
 151 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 152 {
 153         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
 154 }
 155
 156 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
 157 {
 158         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
 159 }
 160
 161 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
 162 {
 163         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
 164 }
 165
 166 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
 167 {
 168         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
 169 }
 170
 171 int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
 172 {
 173         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
 174 }
 175
 176 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
 177 {
 178         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
 179 }
 180
 181 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 182 {
 183         return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
 184 }
 185
 186 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 187 {
 188         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
 189 }
 190
 191 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
 192 {
 193         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
 194 }
 195
 196 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 197 {
 198         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
 199 }
 200
 201 int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
 202 {
 203         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
 204 }
 205
 206 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
 207 {
 208         return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
 209 }
 210
 211 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
 212 {
 213         return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
 214 }
 215
 216 /* Core list of CMU_CPU side */
 217
 218 static struct clksrc_clk exynos4_clk_mout_apll = {
 219         .clk    = {
 220                 .name           = "mout_apll",
 221         },
 222         .sources = &clk_src_apll,
 223         .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
 224 };
 225
 226 static struct clksrc_clk exynos4_clk_sclk_apll = {
 227         .clk    = {
 228                 .name           = "sclk_apll",
 229                 .parent         = &exynos4_clk_mout_apll.clk,
 230         },
 231         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
 232 };
 233
 234 static struct clksrc_clk exynos4_clk_mout_epll = {
 235         .clk    = {
 236                 .name           = "mout_epll",
 237         },
 238         .sources = &clk_src_epll,
 239         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
 240 };
 241
 242 struct clksrc_clk exynos4_clk_mout_mpll = {
 243         .clk    = {
 244                 .name           = "mout_mpll",
 245         },
 246         .sources = &clk_src_mpll,
 247
 248         /* reg_src will be added in each SoCs' clock */
 249 };
 250
 251 static struct clk *exynos4_clkset_moutcore_list[] = {
 252         [0] = &exynos4_clk_mout_apll.clk,
 253         [1] = &exynos4_clk_mout_mpll.clk,
 254 };
 255
 256 static struct clksrc_sources exynos4_clkset_moutcore = {
 257         .sources        = exynos4_clkset_moutcore_list,
 258         .nr_sources     = ARRAY_SIZE(exynos4_clkset_moutcore_list),
 259 };
 260
 261 static struct clksrc_clk exynos4_clk_moutcore = {
 262         .clk    = {
 263                 .name           = "moutcore",
 264         },
 265         .sources = &exynos4_clkset_moutcore,
 266         .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
 267 };
 268
 269 static struct clksrc_clk exynos4_clk_coreclk = {
 270         .clk    = {
 271                 .name           = "core_clk",
 272                 .parent         = &exynos4_clk_moutcore.clk,
 273         },
 274         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
 275 };
 276
 277 static struct clksrc_clk exynos4_clk_armclk = {
 278         .clk    = {
 279                 .name           = "armclk",
 280                 .parent         = &exynos4_clk_coreclk.clk,
 281         },
 282 };
 283
 284 static struct clksrc_clk exynos4_clk_aclk_corem0 = {
 285         .clk    = {
 286                 .name           = "aclk_corem0",
 287                 .parent         = &exynos4_clk_coreclk.clk,
 288         },
 289         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
 290 };
 291
 292 static struct clksrc_clk exynos4_clk_aclk_cores = {
 293         .clk    = {
 294                 .name           = "aclk_cores",
 295                 .parent         = &exynos4_clk_coreclk.clk,
 296         },
 297         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
 298 };
 299
 300 static struct clksrc_clk exynos4_clk_aclk_corem1 = {
 301         .clk    = {
 302                 .name           = "aclk_corem1",
 303                 .parent         = &exynos4_clk_coreclk.clk,
 304         },
 305         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
 306 };
 307
 308 static struct clksrc_clk exynos4_clk_periphclk = {
 309         .clk    = {
 310                 .name           = "periphclk",
 311                 .parent         = &exynos4_clk_coreclk.clk,
 312         },
 313         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
 314 };
 315
 316 /* Core list of CMU_CORE side */
 317
 318 static struct clk *exynos4_clkset_corebus_list[] = {
 319         [0] = &exynos4_clk_mout_mpll.clk,
 320         [1] = &exynos4_clk_sclk_apll.clk,
 321 };
 322
 323 struct clksrc_sources exynos4_clkset_mout_corebus = {
 324         .sources        = exynos4_clkset_corebus_list,
 325         .nr_sources     = ARRAY_SIZE(exynos4_clkset_corebus_list),
 326 };
 327
 328 static struct clksrc_clk exynos4_clk_mout_corebus = {
 329         .clk    = {
 330                 .name           = "mout_corebus",
 331         },
 332         .sources = &exynos4_clkset_mout_corebus,
 333         .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
 334 };
 335
 336 static struct clksrc_clk exynos4_clk_sclk_dmc = {
 337         .clk    = {
 338                 .name           = "sclk_dmc",
 339                 .parent         = &exynos4_clk_mout_corebus.clk,
 340         },
 341         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
 342 };
 343
 344 static struct clksrc_clk exynos4_clk_aclk_cored = {
 345         .clk    = {
 346                 .name           = "aclk_cored",
 347                 .parent         = &exynos4_clk_sclk_dmc.clk,
 348         },
 349         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
 350 };
 351
 352 static struct clksrc_clk exynos4_clk_aclk_corep = {
 353         .clk    = {
 354                 .name           = "aclk_corep",
 355                 .parent         = &exynos4_clk_aclk_cored.clk,
 356         },
 357         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
 358 };
 359
 360 static struct clksrc_clk exynos4_clk_aclk_acp = {
 361         .clk    = {
 362                 .name           = "aclk_acp",
 363                 .parent         = &exynos4_clk_mout_corebus.clk,
 364         },
 365         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
 366 };
 367
 368 static struct clksrc_clk exynos4_clk_pclk_acp = {
 369         .clk    = {
 370                 .name           = "pclk_acp",
 371                 .parent         = &exynos4_clk_aclk_acp.clk,
 372         },
 373         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
 374 };
 375
 376 /* Core list of CMU_TOP side */
 377
 378 struct clk *exynos4_clkset_aclk_top_list[] = {
 379         [0] = &exynos4_clk_mout_mpll.clk,
 380         [1] = &exynos4_clk_sclk_apll.clk,
 381 };
 382
 383 static struct clksrc_sources exynos4_clkset_aclk = {
 384         .sources        = exynos4_clkset_aclk_top_list,
 385         .nr_sources     = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
 386 };
 387
 388 static struct clksrc_clk exynos4_clk_aclk_200 = {
 389         .clk    = {
 390                 .name           = "aclk_200",
 391         },
 392         .sources = &exynos4_clkset_aclk,
 393         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
 394         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
 395 };
 396
 397 static struct clksrc_clk exynos4_clk_aclk_100 = {
 398         .clk    = {
 399                 .name           = "aclk_100",
 400         },
 401         .sources = &exynos4_clkset_aclk,
 402         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
 403         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
 404 };
 405
 406 static struct clksrc_clk exynos4_clk_aclk_160 = {
 407         .clk    = {
 408                 .name           = "aclk_160",
 409         },
 410         .sources = &exynos4_clkset_aclk,
 411         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
 412         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
 413 };
 414
 415 struct clksrc_clk exynos4_clk_aclk_133 = {
 416         .clk    = {
 417                 .name           = "aclk_133",
 418         },
 419         .sources = &exynos4_clkset_aclk,
 420         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
 421         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
 422 };
 423
 424 static struct clk *exynos4_clkset_vpllsrc_list[] = {
 425         [0] = &clk_fin_vpll,
 426         [1] = &exynos4_clk_sclk_hdmi27m,
 427 };
 428
 429 static struct clksrc_sources exynos4_clkset_vpllsrc = {
 430         .sources        = exynos4_clkset_vpllsrc_list,
 431         .nr_sources     = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
 432 };
 433
 434 static struct clksrc_clk exynos4_clk_vpllsrc = {
 435         .clk    = {
 436                 .name           = "vpll_src",
 437                 .enable         = exynos4_clksrc_mask_top_ctrl,
 438                 .ctrlbit        = (1 << 0),
 439         },
 440         .sources = &exynos4_clkset_vpllsrc,
 441         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
 442 };
 443
 444 static struct clk *exynos4_clkset_sclk_vpll_list[] = {
 445         [0] = &exynos4_clk_vpllsrc.clk,
 446         [1] = &clk_fout_vpll,
 447 };
 448
 449 static struct clksrc_sources exynos4_clkset_sclk_vpll = {
 450         .sources        = exynos4_clkset_sclk_vpll_list,
 451         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
 452 };
 453
 454 static struct clksrc_clk exynos4_clk_sclk_vpll = {
 455         .clk    = {
 456                 .name           = "sclk_vpll",
 457         },
 458         .sources = &exynos4_clkset_sclk_vpll,
 459         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
 460 };
 461
 462 static struct clk exynos4_init_clocks_off[] = {
 463         {
 464                 .name           = "timers",
 465                 .parent         = &exynos4_clk_aclk_100.clk,
 466                 .enable         = exynos4_clk_ip_peril_ctrl,
 467                 .ctrlbit        = (1<<24),
 468         }, {
 469                 .name           = "csis",
 470                 .devname        = "s5p-mipi-csis.0",
 471                 .enable         = exynos4_clk_ip_cam_ctrl,
 472                 .ctrlbit        = (1 << 4),
 473         }, {
 474                 .name           = "csis",
 475                 .devname        = "s5p-mipi-csis.1",
 476                 .enable         = exynos4_clk_ip_cam_ctrl,
 477                 .ctrlbit        = (1 << 5),
 478         }, {
 479                 .name           = "jpeg",
 480                 .id             = 0,
 481                 .enable         = exynos4_clk_ip_cam_ctrl,
 482                 .ctrlbit        = (1 << 6),
 483         }, {
 484                 .name           = "fimc",
 485                 .devname        = "exynos4-fimc.0",
 486                 .enable         = exynos4_clk_ip_cam_ctrl,
 487                 .ctrlbit        = (1 << 0),
 488         }, {
 489                 .name           = "fimc",
 490                 .devname        = "exynos4-fimc.1",
 491                 .enable         = exynos4_clk_ip_cam_ctrl,
 492                 .ctrlbit        = (1 << 1),
 493         }, {
 494                 .name           = "fimc",
 495                 .devname        = "exynos4-fimc.2",
 496                 .enable         = exynos4_clk_ip_cam_ctrl,
 497                 .ctrlbit        = (1 << 2),
 498         }, {
 499                 .name           = "fimc",
 500                 .devname        = "exynos4-fimc.3",
 501                 .enable         = exynos4_clk_ip_cam_ctrl,
 502                 .ctrlbit        = (1 << 3),
 503         }, {
 504                 .name           = "tsi",
 505                 .enable         = exynos4_clk_ip_fsys_ctrl,
 506                 .ctrlbit        = (1 << 4),
 507         }, {
 508                 .name           = "hsmmc",
 509                 .devname        = "exynos4-sdhci.0",
 510                 .parent         = &exynos4_clk_aclk_133.clk,
 511                 .enable         = exynos4_clk_ip_fsys_ctrl,
 512                 .ctrlbit        = (1 << 5),
 513         }, {
 514                 .name           = "hsmmc",
 515                 .devname        = "exynos4-sdhci.1",
 516                 .parent         = &exynos4_clk_aclk_133.clk,
 517                 .enable         = exynos4_clk_ip_fsys_ctrl,
 518                 .ctrlbit        = (1 << 6),
 519         }, {
 520                 .name           = "hsmmc",
 521                 .devname        = "exynos4-sdhci.2",
 522                 .parent         = &exynos4_clk_aclk_133.clk,
 523                 .enable         = exynos4_clk_ip_fsys_ctrl,
 524                 .ctrlbit        = (1 << 7),
 525         }, {
 526                 .name           = "hsmmc",
 527                 .devname        = "exynos4-sdhci.3",
 528                 .parent         = &exynos4_clk_aclk_133.clk,
 529                 .enable         = exynos4_clk_ip_fsys_ctrl,
 530                 .ctrlbit        = (1 << 8),
 531         }, {
 532                 .name           = "dwmmc",
 533                 .parent         = &exynos4_clk_aclk_133.clk,
 534                 .enable         = exynos4_clk_ip_fsys_ctrl,
 535                 .ctrlbit        = (1 << 9),
 536         }, {
 537                 .name           = "onenand",
 538                 .enable         = exynos4_clk_ip_fsys_ctrl,
 539                 .ctrlbit        = (1 << 15),
 540         }, {
 541                 .name           = "nfcon",
 542                 .enable         = exynos4_clk_ip_fsys_ctrl,
 543                 .ctrlbit        = (1 << 16),
 544         }, {
 545                 .name           = "dac",
 546                 .devname        = "s5p-sdo",
 547                 .enable         = exynos4_clk_ip_tv_ctrl,
 548                 .ctrlbit        = (1 << 2),
 549         }, {
 550                 .name           = "mixer",
 551                 .devname        = "s5p-mixer",
 552                 .enable         = exynos4_clk_ip_tv_ctrl,
 553                 .ctrlbit        = (1 << 1),
 554         }, {
 555                 .name           = "vp",
 556                 .devname        = "s5p-mixer",
 557                 .enable         = exynos4_clk_ip_tv_ctrl,
 558                 .ctrlbit        = (1 << 0),
 559         }, {
 560                 .name           = "hdmi",
 561                 .devname        = "exynos4-hdmi",
 562                 .enable         = exynos4_clk_ip_tv_ctrl,
 563                 .ctrlbit        = (1 << 3),
 564         }, {
 565                 .name           = "hdmiphy",
 566                 .devname        = "exynos4-hdmi",
 567                 .enable         = exynos4_clk_hdmiphy_ctrl,
 568                 .ctrlbit        = (1 << 0),
 569         }, {
 570                 .name           = "dacphy",
 571                 .devname        = "s5p-sdo",
 572                 .enable         = exynos4_clk_dac_ctrl,
 573                 .ctrlbit        = (1 << 0),
 574         }, {
 575                 .name           = "adc",
 576                 .enable         = exynos4_clk_ip_peril_ctrl,
 577                 .ctrlbit        = (1 << 15),
 578         }, {
 579                 .name           = "tmu_apbif",
 580                 .enable         = exynos4_clk_ip_perir_ctrl,
 581                 .ctrlbit        = (1 << 17),
 582         }, {
 583                 .name           = "keypad",
 584                 .enable         = exynos4_clk_ip_perir_ctrl,
 585                 .ctrlbit        = (1 << 16),
 586         }, {
 587                 .name           = "rtc",
 588                 .enable         = exynos4_clk_ip_perir_ctrl,
 589                 .ctrlbit        = (1 << 15),
 590         }, {
 591                 .name           = "watchdog",
 592                 .parent         = &exynos4_clk_aclk_100.clk,
 593                 .enable         = exynos4_clk_ip_perir_ctrl,
 594                 .ctrlbit        = (1 << 14),
 595         }, {
 596                 .name           = "usbhost",
 597                 .enable         = exynos4_clk_ip_fsys_ctrl ,
 598                 .ctrlbit        = (1 << 12),
 599         }, {
 600                 .name           = "otg",
 601                 .enable         = exynos4_clk_ip_fsys_ctrl,
 602                 .ctrlbit        = (1 << 13),
 603         }, {
 604                 .name           = "spi",
 605                 .devname        = "exynos4210-spi.0",
 606                 .enable         = exynos4_clk_ip_peril_ctrl,
 607                 .ctrlbit        = (1 << 16),
 608         }, {
 609                 .name           = "spi",
 610                 .devname        = "exynos4210-spi.1",
 611                 .enable         = exynos4_clk_ip_peril_ctrl,
 612                 .ctrlbit        = (1 << 17),
 613         }, {
 614                 .name           = "spi",
 615                 .devname        = "exynos4210-spi.2",
 616                 .enable         = exynos4_clk_ip_peril_ctrl,
 617                 .ctrlbit        = (1 << 18),
 618         }, {
 619                 .name           = "iis",
 620                 .devname        = "samsung-i2s.1",
 621                 .enable         = exynos4_clk_ip_peril_ctrl,
 622                 .ctrlbit        = (1 << 20),
 623         }, {
 624                 .name           = "iis",
 625                 .devname        = "samsung-i2s.2",
 626                 .enable         = exynos4_clk_ip_peril_ctrl,
 627                 .ctrlbit        = (1 << 21),
 628         }, {
 629                 .name           = "pcm",
 630                 .devname        = "samsung-pcm.1",
 631                 .enable         = exynos4_clk_ip_peril_ctrl,
 632                 .ctrlbit        = (1 << 22),
 633         }, {
 634                 .name           = "pcm",
 635                 .devname        = "samsung-pcm.2",
 636                 .enable         = exynos4_clk_ip_peril_ctrl,
 637                 .ctrlbit        = (1 << 23),
 638         }, {
 639                 .name           = "slimbus",
 640                 .enable         = exynos4_clk_ip_peril_ctrl,
 641                 .ctrlbit        = (1 << 25),
 642         }, {
 643                 .name           = "spdif",
 644                 .devname        = "samsung-spdif",
 645                 .enable         = exynos4_clk_ip_peril_ctrl,
 646                 .ctrlbit        = (1 << 26),
 647         }, {
 648                 .name           = "ac97",
 649                 .devname        = "samsung-ac97",
 650                 .enable         = exynos4_clk_ip_peril_ctrl,
 651                 .ctrlbit        = (1 << 27),
 652         }, {
 653                 .name           = "mfc",
 654                 .devname        = "s5p-mfc",
 655                 .enable         = exynos4_clk_ip_mfc_ctrl,
 656                 .ctrlbit        = (1 << 0),
 657         }, {
 658                 .name           = "i2c",
 659                 .devname        = "s3c2440-i2c.0",
 660                 .parent         = &exynos4_clk_aclk_100.clk,
 661                 .enable         = exynos4_clk_ip_peril_ctrl,
 662                 .ctrlbit        = (1 << 6),
 663         }, {
 664                 .name           = "i2c",
 665                 .devname        = "s3c2440-i2c.1",
 666                 .parent         = &exynos4_clk_aclk_100.clk,
 667                 .enable         = exynos4_clk_ip_peril_ctrl,
 668                 .ctrlbit        = (1 << 7),
 669         }, {
 670                 .name           = "i2c",
 671                 .devname        = "s3c2440-i2c.2",
 672                 .parent         = &exynos4_clk_aclk_100.clk,
 673                 .enable         = exynos4_clk_ip_peril_ctrl,
 674                 .ctrlbit        = (1 << 8),
 675         }, {
 676                 .name           = "i2c",
 677                 .devname        = "s3c2440-i2c.3",
 678                 .parent         = &exynos4_clk_aclk_100.clk,
 679                 .enable         = exynos4_clk_ip_peril_ctrl,
 680                 .ctrlbit        = (1 << 9),
 681         }, {
 682                 .name           = "i2c",
 683                 .devname        = "s3c2440-i2c.4",
 684                 .parent         = &exynos4_clk_aclk_100.clk,
 685                 .enable         = exynos4_clk_ip_peril_ctrl,
 686                 .ctrlbit        = (1 << 10),
 687         }, {
 688                 .name           = "i2c",
 689                 .devname        = "s3c2440-i2c.5",
 690                 .parent         = &exynos4_clk_aclk_100.clk,
 691                 .enable         = exynos4_clk_ip_peril_ctrl,
 692                 .ctrlbit        = (1 << 11),
 693         }, {
 694                 .name           = "i2c",
 695                 .devname        = "s3c2440-i2c.6",
 696                 .parent         = &exynos4_clk_aclk_100.clk,
 697                 .enable         = exynos4_clk_ip_peril_ctrl,
 698                 .ctrlbit        = (1 << 12),
 699         }, {
 700                 .name           = "i2c",
 701                 .devname        = "s3c2440-i2c.7",
 702                 .parent         = &exynos4_clk_aclk_100.clk,
 703                 .enable         = exynos4_clk_ip_peril_ctrl,
 704                 .ctrlbit        = (1 << 13),
 705         }, {
 706                 .name           = "i2c",
 707                 .devname        = "s3c2440-hdmiphy-i2c",
 708                 .parent         = &exynos4_clk_aclk_100.clk,
 709                 .enable         = exynos4_clk_ip_peril_ctrl,
 710                 .ctrlbit        = (1 << 14),
 711         }, {
 712                 .name           = SYSMMU_CLOCK_NAME,
 713                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
 714                 .enable         = exynos4_clk_ip_mfc_ctrl,
 715                 .ctrlbit        = (1 << 1),
 716         }, {
 717                 .name           = SYSMMU_CLOCK_NAME,
 718                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
 719                 .enable         = exynos4_clk_ip_mfc_ctrl,
 720                 .ctrlbit        = (1 << 2),
 721         }, {
 722                 .name           = SYSMMU_CLOCK_NAME,
 723                 .devname        = SYSMMU_CLOCK_DEVNAME(tv, 2),
 724                 .enable         = exynos4_clk_ip_tv_ctrl,
 725                 .ctrlbit        = (1 << 4),
 726         }, {
 727                 .name           = SYSMMU_CLOCK_NAME,
 728                 .devname        = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
 729                 .enable         = exynos4_clk_ip_cam_ctrl,
 730                 .ctrlbit        = (1 << 11),
 731         }, {
 732                 .name           = SYSMMU_CLOCK_NAME,
 733                 .devname        = SYSMMU_CLOCK_DEVNAME(rot, 4),
 734                 .enable         = exynos4_clk_ip_image_ctrl,
 735                 .ctrlbit        = (1 << 4),
 736         }, {
 737                 .name           = SYSMMU_CLOCK_NAME,
 738                 .devname        = SYSMMU_CLOCK_DEVNAME(fimc0, 5),
 739                 .enable         = exynos4_clk_ip_cam_ctrl,
 740                 .ctrlbit        = (1 << 7),
 741         }, {
 742                 .name           = SYSMMU_CLOCK_NAME,
 743                 .devname        = SYSMMU_CLOCK_DEVNAME(fimc1, 6),
 744                 .enable         = exynos4_clk_ip_cam_ctrl,
 745                 .ctrlbit        = (1 << 8),
 746         }, {
 747                 .name           = SYSMMU_CLOCK_NAME,
 748                 .devname        = SYSMMU_CLOCK_DEVNAME(fimc2, 7),
 749                 .enable         = exynos4_clk_ip_cam_ctrl,
 750                 .ctrlbit        = (1 << 9),
 751         }, {
 752                 .name           = SYSMMU_CLOCK_NAME,
 753                 .devname        = SYSMMU_CLOCK_DEVNAME(fimc3, 8),
 754                 .enable         = exynos4_clk_ip_cam_ctrl,
 755                 .ctrlbit        = (1 << 10),
 756         }, {
 757                 .name           = SYSMMU_CLOCK_NAME,
 758                 .devname        = SYSMMU_CLOCK_DEVNAME(fimd0, 10),
 759                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 760                 .ctrlbit        = (1 << 4),
 761         }
 762 };
 763
 764 static struct clk exynos4_init_clocks_on[] = {
 765         {
 766                 .name           = "uart",
 767                 .devname        = "s5pv210-uart.0",
 768                 .enable         = exynos4_clk_ip_peril_ctrl,
 769                 .ctrlbit        = (1 << 0),
 770         }, {
 771                 .name           = "uart",
 772                 .devname        = "s5pv210-uart.1",
 773                 .enable         = exynos4_clk_ip_peril_ctrl,
 774                 .ctrlbit        = (1 << 1),
 775         }, {
 776                 .name           = "uart",
 777                 .devname        = "s5pv210-uart.2",
 778                 .enable         = exynos4_clk_ip_peril_ctrl,
 779                 .ctrlbit        = (1 << 2),
 780         }, {
 781                 .name           = "uart",
 782                 .devname        = "s5pv210-uart.3",
 783                 .enable         = exynos4_clk_ip_peril_ctrl,
 784                 .ctrlbit        = (1 << 3),
 785         }, {
 786                 .name           = "uart",
 787                 .devname        = "s5pv210-uart.4",
 788                 .enable         = exynos4_clk_ip_peril_ctrl,
 789                 .ctrlbit        = (1 << 4),
 790         }, {
 791                 .name           = "uart",
 792                 .devname        = "s5pv210-uart.5",
 793                 .enable         = exynos4_clk_ip_peril_ctrl,
 794                 .ctrlbit        = (1 << 5),
 795         }
 796 };
 797
 798 static struct clk exynos4_clk_pdma0 = {
 799         .name           = "dma",
 800         .devname        = "dma-pl330.0",
 801         .enable         = exynos4_clk_ip_fsys_ctrl,
 802         .ctrlbit        = (1 << 0),
 803 };
 804
 805 static struct clk exynos4_clk_pdma1 = {
 806         .name           = "dma",
 807         .devname        = "dma-pl330.1",
 808         .enable         = exynos4_clk_ip_fsys_ctrl,
 809         .ctrlbit        = (1 << 1),
 810 };
 811
 812 static struct clk exynos4_clk_mdma1 = {
 813         .name           = "dma",
 814         .devname        = "dma-pl330.2",
 815         .enable         = exynos4_clk_ip_image_ctrl,
 816         .ctrlbit        = ((1 << 8) | (1 << 5) | (1 << 2)),
 817 };
 818
 819 static struct clk exynos4_clk_fimd0 = {
 820         .name           = "fimd",
 821         .devname        = "exynos4-fb.0",
 822         .enable         = exynos4_clk_ip_lcd0_ctrl,
 823         .ctrlbit        = (1 << 0),
 824 };
 825
 826 struct clk *exynos4_clkset_group_list[] = {
 827         [0] = &clk_ext_xtal_mux,
 828         [1] = &clk_xusbxti,
 829         [2] = &exynos4_clk_sclk_hdmi27m,
 830         [3] = &exynos4_clk_sclk_usbphy0,
 831         [4] = &exynos4_clk_sclk_usbphy1,
 832         [5] = &exynos4_clk_sclk_hdmiphy,
 833         [6] = &exynos4_clk_mout_mpll.clk,
 834         [7] = &exynos4_clk_mout_epll.clk,
 835         [8] = &exynos4_clk_sclk_vpll.clk,
 836 };
 837
 838 struct clksrc_sources exynos4_clkset_group = {
 839         .sources        = exynos4_clkset_group_list,
 840         .nr_sources     = ARRAY_SIZE(exynos4_clkset_group_list),
 841 };
 842
 843 static struct clk *exynos4_clkset_mout_g2d0_list[] = {
 844         [0] = &exynos4_clk_mout_mpll.clk,
 845         [1] = &exynos4_clk_sclk_apll.clk,
 846 };
 847
 848 struct clksrc_sources exynos4_clkset_mout_g2d0 = {
 849         .sources        = exynos4_clkset_mout_g2d0_list,
 850         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
 851 };
 852
 853 static struct clk *exynos4_clkset_mout_g2d1_list[] = {
 854         [0] = &exynos4_clk_mout_epll.clk,
 855         [1] = &exynos4_clk_sclk_vpll.clk,
 856 };
 857
 858 struct clksrc_sources exynos4_clkset_mout_g2d1 = {
 859         .sources        = exynos4_clkset_mout_g2d1_list,
 860         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
 861 };
 862
 863 static struct clk *exynos4_clkset_mout_mfc0_list[] = {
 864         [0] = &exynos4_clk_mout_mpll.clk,
 865         [1] = &exynos4_clk_sclk_apll.clk,
 866 };
 867
 868 static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
 869         .sources        = exynos4_clkset_mout_mfc0_list,
 870         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
 871 };
 872
 873 static struct clksrc_clk exynos4_clk_mout_mfc0 = {
 874         .clk    = {
 875                 .name           = "mout_mfc0",
 876         },
 877         .sources = &exynos4_clkset_mout_mfc0,
 878         .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
 879 };
 880
 881 static struct clk *exynos4_clkset_mout_mfc1_list[] = {
 882         [0] = &exynos4_clk_mout_epll.clk,
 883         [1] = &exynos4_clk_sclk_vpll.clk,
 884 };
 885
 886 static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
 887         .sources        = exynos4_clkset_mout_mfc1_list,
 888         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
 889 };
 890
 891 static struct clksrc_clk exynos4_clk_mout_mfc1 = {
 892         .clk    = {
 893                 .name           = "mout_mfc1",
 894         },
 895         .sources = &exynos4_clkset_mout_mfc1,
 896         .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
 897 };
 898
 899 static struct clk *exynos4_clkset_mout_mfc_list[] = {
 900         [0] = &exynos4_clk_mout_mfc0.clk,
 901         [1] = &exynos4_clk_mout_mfc1.clk,
 902 };
 903
 904 static struct clksrc_sources exynos4_clkset_mout_mfc = {
 905         .sources        = exynos4_clkset_mout_mfc_list,
 906         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
 907 };
 908
 909 static struct clk *exynos4_clkset_sclk_dac_list[] = {
 910         [0] = &exynos4_clk_sclk_vpll.clk,
 911         [1] = &exynos4_clk_sclk_hdmiphy,
 912 };
 913
 914 static struct clksrc_sources exynos4_clkset_sclk_dac = {
 915         .sources        = exynos4_clkset_sclk_dac_list,
 916         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
 917 };
 918
 919 static struct clksrc_clk exynos4_clk_sclk_dac = {
 920         .clk            = {
 921                 .name           = "sclk_dac",
 922                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 923                 .ctrlbit        = (1 << 8),
 924         },
 925         .sources = &exynos4_clkset_sclk_dac,
 926         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
 927 };
 928
 929 static struct clksrc_clk exynos4_clk_sclk_pixel = {
 930         .clk            = {
 931                 .name           = "sclk_pixel",
 932                 .parent         = &exynos4_clk_sclk_vpll.clk,
 933         },
 934         .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
 935 };
 936
 937 static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
 938         [0] = &exynos4_clk_sclk_pixel.clk,
 939         [1] = &exynos4_clk_sclk_hdmiphy,
 940 };
 941
 942 static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
 943         .sources        = exynos4_clkset_sclk_hdmi_list,
 944         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
 945 };
 946
 947 static struct clksrc_clk exynos4_clk_sclk_hdmi = {
 948         .clk            = {
 949                 .name           = "sclk_hdmi",
 950                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 951                 .ctrlbit        = (1 << 0),
 952         },
 953         .sources = &exynos4_clkset_sclk_hdmi,
 954         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
 955 };
 956
 957 static struct clk *exynos4_clkset_sclk_mixer_list[] = {
 958         [0] = &exynos4_clk_sclk_dac.clk,
 959         [1] = &exynos4_clk_sclk_hdmi.clk,
 960 };
 961
 962 static struct clksrc_sources exynos4_clkset_sclk_mixer = {
 963         .sources        = exynos4_clkset_sclk_mixer_list,
 964         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
 965 };
 966
 967 static struct clksrc_clk exynos4_clk_sclk_mixer = {
 968         .clk    = {
 969                 .name           = "sclk_mixer",
 970                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 971                 .ctrlbit        = (1 << 4),
 972         },
 973         .sources = &exynos4_clkset_sclk_mixer,
 974         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
 975 };
 976
 977 static struct clksrc_clk *exynos4_sclk_tv[] = {
 978         &exynos4_clk_sclk_dac,
 979         &exynos4_clk_sclk_pixel,
 980         &exynos4_clk_sclk_hdmi,
 981         &exynos4_clk_sclk_mixer,
 982 };
 983
 984 static struct clksrc_clk exynos4_clk_dout_mmc0 = {
 985         .clk    = {
 986                 .name           = "dout_mmc0",
 987         },
 988         .sources = &exynos4_clkset_group,
 989         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
 990         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 991 };
 992
 993 static struct clksrc_clk exynos4_clk_dout_mmc1 = {
 994         .clk    = {
 995                 .name           = "dout_mmc1",
 996         },
 997         .sources = &exynos4_clkset_group,
 998         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
 999         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
1000 };
1001
1002 static struct clksrc_clk exynos4_clk_dout_mmc2 = {
1003         .clk    = {
1004                 .name           = "dout_mmc2",
1005         },
1006         .sources = &exynos4_clkset_group,
1007         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
1008         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1009 };
1010
1011 static struct clksrc_clk exynos4_clk_dout_mmc3 = {
1012         .clk    = {
1013                 .name           = "dout_mmc3",
1014         },
1015         .sources = &exynos4_clkset_group,
1016         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
1017         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1018 };
1019
1020 static struct clksrc_clk exynos4_clk_dout_mmc4 = {
1021         .clk            = {
1022                 .name           = "dout_mmc4",
1023         },
1024         .sources = &exynos4_clkset_group,
1025         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
1026         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1027 };
1028
1029 static struct clksrc_clk exynos4_clksrcs[] = {
1030         {
1031                 .clk    = {
1032                         .name           = "sclk_pwm",
1033                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
1034                         .ctrlbit        = (1 << 24),
1035                 },
1036                 .sources = &exynos4_clkset_group,
1037                 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1038                 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1039         }, {
1040                 .clk    = {
1041                         .name           = "sclk_csis",
1042                         .devname        = "s5p-mipi-csis.0",
1043                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1044                         .ctrlbit        = (1 << 24),
1045                 },
1046                 .sources = &exynos4_clkset_group,
1047                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
1048                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1049         }, {
1050                 .clk    = {
1051                         .name           = "sclk_csis",
1052                         .devname        = "s5p-mipi-csis.1",
1053                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1054                         .ctrlbit        = (1 << 28),
1055                 },
1056                 .sources = &exynos4_clkset_group,
1057                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
1058                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1059         }, {
1060                 .clk    = {
1061                         .name           = "sclk_cam0",
1062                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1063                         .ctrlbit        = (1 << 16),
1064                 },
1065                 .sources = &exynos4_clkset_group,
1066                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
1067                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1068         }, {
1069                 .clk    = {
1070                         .name           = "sclk_cam1",
1071                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1072                         .ctrlbit        = (1 << 20),
1073                 },
1074                 .sources = &exynos4_clkset_group,
1075                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
1076                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1077         }, {
1078                 .clk    = {
1079                         .name           = "sclk_fimc",
1080                         .devname        = "exynos4-fimc.0",
1081                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1082                         .ctrlbit        = (1 << 0),
1083                 },
1084                 .sources = &exynos4_clkset_group,
1085                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
1086                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1087         }, {
1088                 .clk    = {
1089                         .name           = "sclk_fimc",
1090                         .devname        = "exynos4-fimc.1",
1091                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1092                         .ctrlbit        = (1 << 4),
1093                 },
1094                 .sources = &exynos4_clkset_group,
1095                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
1096                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1097         }, {
1098                 .clk    = {
1099                         .name           = "sclk_fimc",
1100                         .devname        = "exynos4-fimc.2",
1101                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1102                         .ctrlbit        = (1 << 8),
1103                 },
1104                 .sources = &exynos4_clkset_group,
1105                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
1106                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1107         }, {
1108                 .clk    = {
1109                         .name           = "sclk_fimc",
1110                         .devname        = "exynos4-fimc.3",
1111                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1112                         .ctrlbit        = (1 << 12),
1113                 },
1114                 .sources = &exynos4_clkset_group,
1115                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
1116                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1117         }, {
1118                 .clk    = {
1119                         .name           = "sclk_fimd",
1120                         .devname        = "exynos4-fb.0",
1121                         .enable         = exynos4_clksrc_mask_lcd0_ctrl,
1122                         .ctrlbit        = (1 << 0),
1123                 },
1124                 .sources = &exynos4_clkset_group,
1125                 .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
1126                 .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1127         }, {
1128                 .clk    = {
1129                         .name           = "sclk_mfc",
1130                         .devname        = "s5p-mfc",
1131                 },
1132                 .sources = &exynos4_clkset_mout_mfc,
1133                 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
1134                 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1135         }, {
1136                 .clk    = {
1137                         .name           = "sclk_dwmmc",
1138                         .parent         = &exynos4_clk_dout_mmc4.clk,
1139                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1140                         .ctrlbit        = (1 << 16),
1141                 },
1142                 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1143         }
1144 };
1145
1146 static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1147         .clk    = {
1148                 .name           = "uclk1",
1149                 .devname        = "exynos4210-uart.0",
1150                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1151                 .ctrlbit        = (1 << 0),
1152         },
1153         .sources = &exynos4_clkset_group,
1154         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1155         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1156 };
1157
1158 static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1159         .clk    = {
1160                 .name           = "uclk1",
1161                 .devname        = "exynos4210-uart.1",
1162                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1163                 .ctrlbit        = (1 << 4),
1164         },
1165         .sources = &exynos4_clkset_group,
1166         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1167         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1168 };
1169
1170 static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1171         .clk    = {
1172                 .name           = "uclk1",
1173                 .devname        = "exynos4210-uart.2",
1174                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1175                 .ctrlbit        = (1 << 8),
1176         },
1177         .sources = &exynos4_clkset_group,
1178         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1179         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1180 };
1181
1182 static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1183         .clk    = {
1184                 .name           = "uclk1",
1185                 .devname        = "exynos4210-uart.3",
1186                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1187                 .ctrlbit        = (1 << 12),
1188         },
1189         .sources = &exynos4_clkset_group,
1190         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1191         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1192 };
1193
1194 static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1195         .clk    = {
1196                 .name           = "sclk_mmc",
1197                 .devname        = "exynos4-sdhci.0",
1198                 .parent         = &exynos4_clk_dout_mmc0.clk,
1199                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1200                 .ctrlbit        = (1 << 0),
1201         },
1202         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1203 };
1204
1205 static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1206         .clk    = {
1207                 .name           = "sclk_mmc",
1208                 .devname        = "exynos4-sdhci.1",
1209                 .parent         = &exynos4_clk_dout_mmc1.clk,
1210                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1211                 .ctrlbit        = (1 << 4),
1212         },
1213         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1214 };
1215
1216 static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1217         .clk    = {
1218                 .name           = "sclk_mmc",
1219                 .devname        = "exynos4-sdhci.2",
1220                 .parent         = &exynos4_clk_dout_mmc2.clk,
1221                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1222                 .ctrlbit        = (1 << 8),
1223         },
1224         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1225 };
1226
1227 static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1228         .clk    = {
1229                 .name           = "sclk_mmc",
1230                 .devname        = "exynos4-sdhci.3",
1231                 .parent         = &exynos4_clk_dout_mmc3.clk,
1232                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1233                 .ctrlbit        = (1 << 12),
1234         },
1235         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1236 };
1237
1238 static struct clksrc_clk exynos4_clk_mdout_spi0 = {
1239         .clk    = {
1240                 .name           = "mdout_spi",
1241                 .devname        = "exynos4210-spi.0",
1242         },
1243         .sources = &exynos4_clkset_group,
1244         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1245         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1246 };
1247
1248 static struct clksrc_clk exynos4_clk_mdout_spi1 = {
1249         .clk    = {
1250                 .name           = "mdout_spi",
1251                 .devname        = "exynos4210-spi.1",
1252         },
1253         .sources = &exynos4_clkset_group,
1254         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1255         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1256 };
1257
1258 static struct clksrc_clk exynos4_clk_mdout_spi2 = {
1259         .clk    = {
1260                 .name           = "mdout_spi",
1261                 .devname        = "exynos4210-spi.2",
1262         },
1263         .sources = &exynos4_clkset_group,
1264         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1265         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1266 };
1267
1268 static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1269         .clk    = {
1270                 .name           = "sclk_spi",
1271                 .devname        = "exynos4210-spi.0",
1272                 .parent         = &exynos4_clk_mdout_spi0.clk,
1273                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1274                 .ctrlbit        = (1 << 16),
1275         },
1276         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
1277 };
1278
1279 static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1280         .clk    = {
1281                 .name           = "sclk_spi",
1282                 .devname        = "exynos4210-spi.1",
1283                 .parent         = &exynos4_clk_mdout_spi1.clk,
1284                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1285                 .ctrlbit        = (1 << 20),
1286         },
1287         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
1288 };
1289
1290 static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1291         .clk    = {
1292                 .name           = "sclk_spi",
1293                 .devname        = "exynos4210-spi.2",
1294                 .parent         = &exynos4_clk_mdout_spi2.clk,
1295                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1296                 .ctrlbit        = (1 << 24),
1297         },
1298         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
1299 };
1300
1301 /* Clock initialization code */
1302 static struct clksrc_clk *exynos4_sysclks[] = {
1303         &exynos4_clk_mout_apll,
1304         &exynos4_clk_sclk_apll,
1305         &exynos4_clk_mout_epll,
1306         &exynos4_clk_mout_mpll,
1307         &exynos4_clk_moutcore,
1308         &exynos4_clk_coreclk,
1309         &exynos4_clk_armclk,
1310         &exynos4_clk_aclk_corem0,
1311         &exynos4_clk_aclk_cores,
1312         &exynos4_clk_aclk_corem1,
1313         &exynos4_clk_periphclk,
1314         &exynos4_clk_mout_corebus,
1315         &exynos4_clk_sclk_dmc,
1316         &exynos4_clk_aclk_cored,
1317         &exynos4_clk_aclk_corep,
1318         &exynos4_clk_aclk_acp,
1319         &exynos4_clk_pclk_acp,
1320         &exynos4_clk_vpllsrc,
1321         &exynos4_clk_sclk_vpll,
1322         &exynos4_clk_aclk_200,
1323         &exynos4_clk_aclk_100,
1324         &exynos4_clk_aclk_160,
1325         &exynos4_clk_aclk_133,
1326         &exynos4_clk_dout_mmc0,
1327         &exynos4_clk_dout_mmc1,
1328         &exynos4_clk_dout_mmc2,
1329         &exynos4_clk_dout_mmc3,
1330         &exynos4_clk_dout_mmc4,
1331         &exynos4_clk_mout_mfc0,
1332         &exynos4_clk_mout_mfc1,
1333 };
1334
1335 static struct clk *exynos4_clk_cdev[] = {
1336         &exynos4_clk_pdma0,
1337         &exynos4_clk_pdma1,
1338         &exynos4_clk_mdma1,
1339         &exynos4_clk_fimd0,
1340 };
1341
1342 static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1343         &exynos4_clk_sclk_uart0,
1344         &exynos4_clk_sclk_uart1,
1345         &exynos4_clk_sclk_uart2,
1346         &exynos4_clk_sclk_uart3,
1347         &exynos4_clk_sclk_mmc0,
1348         &exynos4_clk_sclk_mmc1,
1349         &exynos4_clk_sclk_mmc2,
1350         &exynos4_clk_sclk_mmc3,
1351         &exynos4_clk_sclk_spi0,
1352         &exynos4_clk_sclk_spi1,
1353         &exynos4_clk_sclk_spi2,
1354         &exynos4_clk_mdout_spi0,
1355         &exynos4_clk_mdout_spi1,
1356         &exynos4_clk_mdout_spi2,
1357 };
1358
1359 static struct clk_lookup exynos4_clk_lookup[] = {
1360         CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
1361         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1362         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1363         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1364         CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1365         CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1366         CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1367         CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1368         CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1369         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1370         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1371         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
1372         CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1373         CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1374         CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1375 };
1376
1377 static int xtal_rate;
1378
1379 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1380 {
1381         if (soc_is_exynos4210())
1382                 return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1383                                         pll_4508);
1384         else if (soc_is_exynos4212() || soc_is_exynos4412())
1385                 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1386         else
1387                 return 0;
1388 }
1389
1390 static struct clk_ops exynos4_fout_apll_ops = {
1391         .get_rate = exynos4_fout_apll_get_rate,
1392 };
1393
1394 static u32 exynos4_vpll_div[][8] = {
1395         {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
1396         { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1397 };
1398
1399 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1400 {
1401         return clk->rate;
1402 }
1403
1404 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1405 {
1406         unsigned int vpll_con0, vpll_con1 = 0;
1407         unsigned int i;
1408
1409         /* Return if nothing changed */
1410         if (clk->rate == rate)
1411                 return 0;
1412
1413         vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1414         vpll_con0 &= ~(0x1 << 27 |                                      \
1415                         PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
1416                         PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
1417                         PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1418
1419         vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1420         vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
1421                         PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1422                         PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1423
1424         for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
1425                 if (exynos4_vpll_div[i][0] == rate) {
1426                         vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1427                         vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1428                         vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1429                         vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1430                         vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1431                         vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1432                         vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1433                         break;
1434                 }
1435         }
1436
1437         if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1438                 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1439                                 __func__);
1440                 return -EINVAL;
1441         }
1442
1443         __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
1444         __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1445
1446         /* Wait for VPLL lock */
1447         while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1448                 continue;
1449
1450         clk->rate = rate;
1451         return 0;
1452 }
1453
1454 static struct clk_ops exynos4_vpll_ops = {
1455         .get_rate = exynos4_vpll_get_rate,
1456         .set_rate = exynos4_vpll_set_rate,
1457 };
1458
1459 void __init_or_cpufreq exynos4_setup_clocks(void)
1460 {
1461         struct clk *xtal_clk;
1462         unsigned long apll = 0;
1463         unsigned long mpll = 0;
1464         unsigned long epll = 0;
1465         unsigned long vpll = 0;
1466         unsigned long vpllsrc;
1467         unsigned long xtal;
1468         unsigned long armclk;
1469         unsigned long sclk_dmc;
1470         unsigned long aclk_200;
1471         unsigned long aclk_100;
1472         unsigned long aclk_160;
1473         unsigned long aclk_133;
1474         unsigned int ptr;
1475
1476         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1477
1478         xtal_clk = clk_get(NULL, "xtal");
1479         BUG_ON(IS_ERR(xtal_clk));
1480
1481         xtal = clk_get_rate(xtal_clk);
1482
1483         xtal_rate = xtal;
1484
1485         clk_put(xtal_clk);
1486
1487         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1488
1489         if (soc_is_exynos4210()) {
1490                 apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1491                                         pll_4508);
1492                 mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1493                                         pll_4508);
1494                 epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1495                                         __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1496
1497                 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1498                 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1499                                         __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1500         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1501                 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
1502                 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
1503                 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1504                                         __raw_readl(EXYNOS4_EPLL_CON1));
1505
1506                 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1507                 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1508                                         __raw_readl(EXYNOS4_VPLL_CON1));
1509         } else {
1510                 /* nothing */
1511         }
1512
1513         clk_fout_apll.ops = &exynos4_fout_apll_ops;
1514         clk_fout_mpll.rate = mpll;
1515         clk_fout_epll.rate = epll;
1516         clk_fout_vpll.ops = &exynos4_vpll_ops;
1517         clk_fout_vpll.rate = vpll;
1518
1519         printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1520                         apll, mpll, epll, vpll);
1521
1522         armclk = clk_get_rate(&exynos4_clk_armclk.clk);
1523         sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
1524
1525         aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
1526         aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
1527         aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
1528         aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1529
1530         printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1531                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1532                         armclk, sclk_dmc, aclk_200,
1533                         aclk_100, aclk_160, aclk_133);
1534
1535         clk_f.rate = armclk;
1536         clk_h.rate = sclk_dmc;
1537         clk_p.rate = aclk_100;
1538
1539         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
1540                 s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1541 }
1542
1543 static struct clk *exynos4_clks[] __initdata = {
1544         &exynos4_clk_sclk_hdmi27m,
1545         &exynos4_clk_sclk_hdmiphy,
1546         &exynos4_clk_sclk_usbphy0,
1547         &exynos4_clk_sclk_usbphy1,
1548 };
1549
1550 #ifdef CONFIG_PM_SLEEP
1551 static int exynos4_clock_suspend(void)
1552 {
1553         s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1554         return 0;
1555 }
1556
1557 static void exynos4_clock_resume(void)
1558 {
1559         s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1560 }
1561
1562 #else
1563 #define exynos4_clock_suspend NULL
1564 #define exynos4_clock_resume NULL
1565 #endif
1566
1567 static struct syscore_ops exynos4_clock_syscore_ops = {
1568         .suspend        = exynos4_clock_suspend,
1569         .resume         = exynos4_clock_resume,
1570 };
1571
1572 void __init exynos4_register_clocks(void)
1573 {
1574         int ptr;
1575
1576         s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1577
1578         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
1579                 s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1580
1581         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
1582                 s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1583
1584         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
1585                 s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1586
1587         s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
1588         s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1589
1590         s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
1591         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
1592                 s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1593
1594         s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1595         s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1596         clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1597
1598         register_syscore_ops(&exynos4_clock_syscore_ops);
1599         s3c24xx_register_clock(&dummy_apb_pclk);
1600
1601         s3c_pwmclk_init();
1602 }