2 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS - Suspend support
7 * Based on arch/arm/mach-s3c2410/pm.c
8 * Copyright (c) 2006 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/suspend.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/cpu_pm.h>
21 #include <linux/irq.h>
22 #include <linux/irqchip.h>
23 #include <linux/irqdomain.h>
24 #include <linux/of_address.h>
25 #include <linux/err.h>
26 #include <linux/regulator/machine.h>
28 #include <asm/cacheflush.h>
29 #include <asm/hardware/cache-l2x0.h>
30 #include <asm/firmware.h>
32 #include <asm/smp_scu.h>
33 #include <asm/suspend.h>
35 #include <plat/pm-common.h>
38 #include "exynos-pmu.h"
40 #include "regs-srom.h"
42 #define REG_TABLE_END (-1U)
44 #define EXYNOS5420_CPU_STATE 0x28
47 * struct exynos_wkup_irq - PMU IRQ to mask mapping
48 * @hwirq: Hardware IRQ signal of the PMU
49 * @mask: Mask in PMU wake-up mask register
51 struct exynos_wkup_irq {
56 static struct sleep_save exynos_core_save[] = {
58 SAVE_ITEM(S5P_SROM_BW),
59 SAVE_ITEM(S5P_SROM_BC0),
60 SAVE_ITEM(S5P_SROM_BC1),
61 SAVE_ITEM(S5P_SROM_BC2),
62 SAVE_ITEM(S5P_SROM_BC3),
65 struct exynos_pm_data {
66 const struct exynos_wkup_irq *wkup_irq;
67 unsigned int wake_disable_mask;
68 unsigned int *release_ret_regs;
70 void (*pm_prepare)(void);
71 void (*pm_resume_prepare)(void);
72 void (*pm_resume)(void);
73 int (*pm_suspend)(void);
74 int (*cpu_suspend)(unsigned long);
77 static const struct exynos_pm_data *pm_data;
79 static int exynos5420_cpu_state;
80 static unsigned int exynos_pmu_spare3;
86 static u32 exynos_irqwake_intmask = 0xffffffff;
88 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
89 { 73, BIT(1) }, /* RTC alarm */
90 { 74, BIT(2) }, /* RTC tick */
94 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
95 { 44, BIT(1) }, /* RTC alarm */
96 { 45, BIT(2) }, /* RTC tick */
100 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
101 { 43, BIT(1) }, /* RTC alarm */
102 { 44, BIT(2) }, /* RTC tick */
106 static unsigned int exynos_release_ret_regs[] = {
107 S5P_PAD_RET_MAUDIO_OPTION,
108 S5P_PAD_RET_GPIO_OPTION,
109 S5P_PAD_RET_UART_OPTION,
110 S5P_PAD_RET_MMCA_OPTION,
111 S5P_PAD_RET_MMCB_OPTION,
112 S5P_PAD_RET_EBIA_OPTION,
113 S5P_PAD_RET_EBIB_OPTION,
117 static unsigned int exynos3250_release_ret_regs[] = {
118 S5P_PAD_RET_MAUDIO_OPTION,
119 S5P_PAD_RET_GPIO_OPTION,
120 S5P_PAD_RET_UART_OPTION,
121 S5P_PAD_RET_MMCA_OPTION,
122 S5P_PAD_RET_MMCB_OPTION,
123 S5P_PAD_RET_EBIA_OPTION,
124 S5P_PAD_RET_EBIB_OPTION,
125 S5P_PAD_RET_MMC2_OPTION,
126 S5P_PAD_RET_SPI_OPTION,
130 static unsigned int exynos5420_release_ret_regs[] = {
131 EXYNOS_PAD_RET_DRAM_OPTION,
132 EXYNOS_PAD_RET_MAUDIO_OPTION,
133 EXYNOS_PAD_RET_JTAG_OPTION,
134 EXYNOS5420_PAD_RET_GPIO_OPTION,
135 EXYNOS5420_PAD_RET_UART_OPTION,
136 EXYNOS5420_PAD_RET_MMCA_OPTION,
137 EXYNOS5420_PAD_RET_MMCB_OPTION,
138 EXYNOS5420_PAD_RET_MMCC_OPTION,
139 EXYNOS5420_PAD_RET_HSI_OPTION,
140 EXYNOS_PAD_RET_EBIA_OPTION,
141 EXYNOS_PAD_RET_EBIB_OPTION,
142 EXYNOS5420_PAD_RET_SPI_OPTION,
143 EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
147 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
149 const struct exynos_wkup_irq *wkup_irq;
151 if (!pm_data->wkup_irq)
153 wkup_irq = pm_data->wkup_irq;
155 while (wkup_irq->mask) {
156 if (wkup_irq->hwirq == data->hwirq) {
158 exynos_irqwake_intmask |= wkup_irq->mask;
160 exynos_irqwake_intmask &= ~wkup_irq->mask;
169 static struct irq_chip exynos_pmu_chip = {
171 .irq_eoi = irq_chip_eoi_parent,
172 .irq_mask = irq_chip_mask_parent,
173 .irq_unmask = irq_chip_unmask_parent,
174 .irq_retrigger = irq_chip_retrigger_hierarchy,
175 .irq_set_wake = exynos_irq_set_wake,
177 .irq_set_affinity = irq_chip_set_affinity_parent,
181 static int exynos_pmu_domain_xlate(struct irq_domain *domain,
182 struct device_node *controller,
184 unsigned int intsize,
185 unsigned long *out_hwirq,
186 unsigned int *out_type)
188 if (domain->of_node != controller)
189 return -EINVAL; /* Shouldn't happen, really... */
191 return -EINVAL; /* Not GIC compliant */
193 return -EINVAL; /* No PPI should point to this domain */
195 *out_hwirq = intspec[1];
196 *out_type = intspec[2];
200 static int exynos_pmu_domain_alloc(struct irq_domain *domain,
202 unsigned int nr_irqs, void *data)
204 struct of_phandle_args *args = data;
205 struct of_phandle_args parent_args;
206 irq_hw_number_t hwirq;
209 if (args->args_count != 3)
210 return -EINVAL; /* Not GIC compliant */
211 if (args->args[0] != 0)
212 return -EINVAL; /* No PPI should point to this domain */
214 hwirq = args->args[1];
216 for (i = 0; i < nr_irqs; i++)
217 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
218 &exynos_pmu_chip, NULL);
221 parent_args.np = domain->parent->of_node;
222 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_args);
225 static const struct irq_domain_ops exynos_pmu_domain_ops = {
226 .xlate = exynos_pmu_domain_xlate,
227 .alloc = exynos_pmu_domain_alloc,
228 .free = irq_domain_free_irqs_common,
231 static int __init exynos_pmu_irq_init(struct device_node *node,
232 struct device_node *parent)
234 struct irq_domain *parent_domain, *domain;
237 pr_err("%s: no parent, giving up\n", node->full_name);
241 parent_domain = irq_find_host(parent);
242 if (!parent_domain) {
243 pr_err("%s: unable to obtain parent domain\n", node->full_name);
247 pmu_base_addr = of_iomap(node, 0);
249 if (!pmu_base_addr) {
250 pr_err("%s: failed to find exynos pmu register\n",
255 domain = irq_domain_add_hierarchy(parent_domain, 0, 0,
256 node, &exynos_pmu_domain_ops,
259 iounmap(pmu_base_addr);
266 #define EXYNOS_PMU_IRQ(symbol, name) IRQCHIP_DECLARE(symbol, name, exynos_pmu_irq_init)
268 EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu");
269 EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu");
270 EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu");
271 EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu");
272 EXYNOS_PMU_IRQ(exynos4415_pmu_irq, "samsung,exynos4415-pmu");
273 EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu");
274 EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu");
276 static int exynos_cpu_do_idle(void)
278 /* issue the standby signal into the pm unit. */
281 pr_info("Failed to suspend the system\n");
282 return 1; /* Aborting suspend */
284 static void exynos_flush_cache_all(void)
290 static int exynos_cpu_suspend(unsigned long arg)
292 exynos_flush_cache_all();
293 return exynos_cpu_do_idle();
296 static int exynos3250_cpu_suspend(unsigned long arg)
299 return exynos_cpu_do_idle();
302 static int exynos5420_cpu_suspend(unsigned long arg)
304 /* MCPM works with HW CPU identifiers */
305 unsigned int mpidr = read_cpuid_mpidr();
306 unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
307 unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
309 __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
311 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
312 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
316 pr_info("Failed to suspend the system\n");
318 /* return value != 0 means failure */
322 static void exynos_pm_set_wakeup_mask(void)
324 /* Set wake-up mask registers */
325 pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
326 pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
329 static void exynos_pm_enter_sleep_mode(void)
331 /* Set value of power down register for sleep mode */
332 exynos_sys_powerdown_conf(SYS_SLEEP);
333 pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1);
336 static void exynos_pm_prepare(void)
338 exynos_set_delayed_reset_assertion(false);
340 /* Set wake-up mask registers */
341 exynos_pm_set_wakeup_mask();
343 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
345 exynos_pm_enter_sleep_mode();
347 /* ensure at least INFORM0 has the resume address */
348 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
351 static void exynos3250_pm_prepare(void)
355 /* Set wake-up mask registers */
356 exynos_pm_set_wakeup_mask();
358 tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
359 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
360 pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
362 exynos_pm_enter_sleep_mode();
364 /* ensure at least INFORM0 has the resume address */
365 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
368 static void exynos5420_pm_prepare(void)
372 /* Set wake-up mask registers */
373 exynos_pm_set_wakeup_mask();
375 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
377 exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
379 * The cpu state needs to be saved and restored so that the
380 * secondary CPUs will enter low power start. Though the U-Boot
381 * is setting the cpu state with low power flag, the kernel
382 * needs to restore it back in case, the primary cpu fails to
383 * suspend for any reason.
385 exynos5420_cpu_state = __raw_readl(sysram_base_addr +
386 EXYNOS5420_CPU_STATE);
388 exynos_pm_enter_sleep_mode();
390 /* ensure at least INFORM0 has the resume address */
391 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
392 pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
394 tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
395 tmp &= ~EXYNOS5_USE_RETENTION;
396 pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
398 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
399 tmp |= EXYNOS5420_UFS;
400 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
402 tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
403 tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
404 pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
406 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
407 tmp |= EXYNOS5420_EMULATION;
408 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
410 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
411 tmp |= EXYNOS5420_EMULATION;
412 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
416 static int exynos_pm_suspend(void)
418 exynos_pm_central_suspend();
420 /* Setting SEQ_OPTION register */
421 pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
422 S5P_CENTRAL_SEQ_OPTION);
424 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
425 exynos_cpu_save_register();
430 static int exynos5420_pm_suspend(void)
434 exynos_pm_central_suspend();
436 /* Setting SEQ_OPTION register */
438 this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
440 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
441 S5P_CENTRAL_SEQ_OPTION);
443 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
444 S5P_CENTRAL_SEQ_OPTION);
448 static void exynos_pm_release_retention(void)
452 for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++)
453 pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR,
454 pm_data->release_ret_regs[i]);
457 static void exynos_pm_resume(void)
459 u32 cpuid = read_cpuid_part();
461 if (exynos_pm_central_resume())
464 /* For release retention */
465 exynos_pm_release_retention();
467 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
469 if (cpuid == ARM_CPU_PART_CORTEX_A9)
470 scu_enable(S5P_VA_SCU);
472 if (call_firmware_op(resume) == -ENOSYS
473 && cpuid == ARM_CPU_PART_CORTEX_A9)
474 exynos_cpu_restore_register();
478 /* Clear SLEEP mode set in INFORM1 */
479 pmu_raw_writel(0x0, S5P_INFORM1);
480 exynos_set_delayed_reset_assertion(true);
483 static void exynos3250_pm_resume(void)
485 u32 cpuid = read_cpuid_part();
487 if (exynos_pm_central_resume())
490 /* For release retention */
491 exynos_pm_release_retention();
493 pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
495 if (call_firmware_op(resume) == -ENOSYS
496 && cpuid == ARM_CPU_PART_CORTEX_A9)
497 exynos_cpu_restore_register();
501 /* Clear SLEEP mode set in INFORM1 */
502 pmu_raw_writel(0x0, S5P_INFORM1);
505 static void exynos5420_prepare_pm_resume(void)
507 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
508 WARN_ON(mcpm_cpu_powered_up());
511 static void exynos5420_pm_resume(void)
515 /* Restore the CPU0 low power state register */
516 tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
517 pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
518 EXYNOS5_ARM_CORE0_SYS_PWR_REG);
520 /* Restore the sysram cpu state register */
521 __raw_writel(exynos5420_cpu_state,
522 sysram_base_addr + EXYNOS5420_CPU_STATE);
524 pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
525 S5P_CENTRAL_SEQ_OPTION);
527 if (exynos_pm_central_resume())
530 /* For release retention */
531 exynos_pm_release_retention();
533 pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
535 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
539 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
540 tmp &= ~EXYNOS5420_UFS;
541 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
543 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
544 tmp &= ~EXYNOS5420_EMULATION;
545 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
547 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
548 tmp &= ~EXYNOS5420_EMULATION;
549 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
551 /* Clear SLEEP mode set in INFORM1 */
552 pmu_raw_writel(0x0, S5P_INFORM1);
559 static int exynos_suspend_enter(suspend_state_t state)
565 S3C_PMDBG("%s: suspending the system...\n", __func__);
567 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
568 exynos_irqwake_intmask, exynos_get_eint_wake_mask());
570 if (exynos_irqwake_intmask == -1U
571 && exynos_get_eint_wake_mask() == -1U) {
572 pr_err("%s: No wake-up sources!\n", __func__);
573 pr_err("%s: Aborting sleep\n", __func__);
578 if (pm_data->pm_prepare)
579 pm_data->pm_prepare();
581 s3c_pm_check_store();
583 ret = call_firmware_op(suspend);
585 ret = cpu_suspend(0, pm_data->cpu_suspend);
589 if (pm_data->pm_resume_prepare)
590 pm_data->pm_resume_prepare();
591 s3c_pm_restore_uarts();
593 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
594 pmu_raw_readl(S5P_WAKEUP_STAT));
596 s3c_pm_check_restore();
598 S3C_PMDBG("%s: resuming the system...\n", __func__);
603 static int exynos_suspend_prepare(void)
608 * REVISIT: It would be better if struct platform_suspend_ops
609 * .prepare handler get the suspend_state_t as a parameter to
610 * avoid hard-coding the suspend to mem state. It's safe to do
611 * it now only because the suspend_valid_only_mem function is
612 * used as the .valid callback used to check if a given state
613 * is supported by the platform anyways.
615 ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
617 pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
621 s3c_pm_check_prepare();
626 static void exynos_suspend_finish(void)
630 s3c_pm_check_cleanup();
632 ret = regulator_suspend_finish();
634 pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
637 static const struct platform_suspend_ops exynos_suspend_ops = {
638 .enter = exynos_suspend_enter,
639 .prepare = exynos_suspend_prepare,
640 .finish = exynos_suspend_finish,
641 .valid = suspend_valid_only_mem,
644 static const struct exynos_pm_data exynos3250_pm_data = {
645 .wkup_irq = exynos3250_wkup_irq,
646 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
647 .release_ret_regs = exynos3250_release_ret_regs,
648 .pm_suspend = exynos_pm_suspend,
649 .pm_resume = exynos3250_pm_resume,
650 .pm_prepare = exynos3250_pm_prepare,
651 .cpu_suspend = exynos3250_cpu_suspend,
654 static const struct exynos_pm_data exynos4_pm_data = {
655 .wkup_irq = exynos4_wkup_irq,
656 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
657 .release_ret_regs = exynos_release_ret_regs,
658 .pm_suspend = exynos_pm_suspend,
659 .pm_resume = exynos_pm_resume,
660 .pm_prepare = exynos_pm_prepare,
661 .cpu_suspend = exynos_cpu_suspend,
664 static const struct exynos_pm_data exynos5250_pm_data = {
665 .wkup_irq = exynos5250_wkup_irq,
666 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
667 .release_ret_regs = exynos_release_ret_regs,
668 .pm_suspend = exynos_pm_suspend,
669 .pm_resume = exynos_pm_resume,
670 .pm_prepare = exynos_pm_prepare,
671 .cpu_suspend = exynos_cpu_suspend,
674 static const struct exynos_pm_data exynos5420_pm_data = {
675 .wkup_irq = exynos5250_wkup_irq,
676 .wake_disable_mask = (0x7F << 7) | (0x1F << 1),
677 .release_ret_regs = exynos5420_release_ret_regs,
678 .pm_resume_prepare = exynos5420_prepare_pm_resume,
679 .pm_resume = exynos5420_pm_resume,
680 .pm_suspend = exynos5420_pm_suspend,
681 .pm_prepare = exynos5420_pm_prepare,
682 .cpu_suspend = exynos5420_cpu_suspend,
685 static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
687 .compatible = "samsung,exynos3250-pmu",
688 .data = &exynos3250_pm_data,
690 .compatible = "samsung,exynos4210-pmu",
691 .data = &exynos4_pm_data,
693 .compatible = "samsung,exynos4212-pmu",
694 .data = &exynos4_pm_data,
696 .compatible = "samsung,exynos4412-pmu",
697 .data = &exynos4_pm_data,
699 .compatible = "samsung,exynos5250-pmu",
700 .data = &exynos5250_pm_data,
702 .compatible = "samsung,exynos5420-pmu",
703 .data = &exynos5420_pm_data,
708 static struct syscore_ops exynos_pm_syscore_ops;
710 void __init exynos_pm_init(void)
712 const struct of_device_id *match;
713 struct device_node *np;
716 np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
718 pr_err("Failed to find PMU node\n");
722 if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
723 pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
727 pm_data = (const struct exynos_pm_data *) match->data;
729 /* All wakeup disable */
730 tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
731 tmp |= pm_data->wake_disable_mask;
732 pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
734 exynos_pm_syscore_ops.suspend = pm_data->pm_suspend;
735 exynos_pm_syscore_ops.resume = pm_data->pm_resume;
737 register_syscore_ops(&exynos_pm_syscore_ops);
738 suspend_set_ops(&exynos_suspend_ops);