3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
19 select AUDIT_ARCH_COMPAT_GENERIC
20 select ARM_GIC_V2M if PCI_MSI
22 select ARM_GIC_V3_ITS if PCI_MSI
23 select BUILDTIME_EXTABLE_SORT
24 select CLONE_BACKWARDS
27 select CPU_PM if (SUSPEND || CPU_IDLE)
28 select DCACHE_WORD_ACCESS
29 select GENERIC_ALLOCATOR
30 select GENERIC_CLOCKEVENTS
31 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
32 select GENERIC_CPU_AUTOPROBE
33 select GENERIC_EARLY_IOREMAP
34 select GENERIC_IRQ_PROBE
35 select GENERIC_IRQ_SHOW
36 select GENERIC_IRQ_SHOW_LEVEL
37 select GENERIC_PCI_IOMAP
38 select GENERIC_SCHED_CLOCK
39 select GENERIC_SMP_IDLE_THREAD
40 select GENERIC_STRNCPY_FROM_USER
41 select GENERIC_STRNLEN_USER
42 select GENERIC_TIME_VSYSCALL
43 select HANDLE_DOMAIN_IRQ
44 select HARDIRQS_SW_RESEND
45 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
46 select HAVE_ARCH_AUDITSYSCALL
47 select HAVE_ARCH_BITREVERSE
48 select HAVE_ARCH_JUMP_LABEL
50 select HAVE_ARCH_SECCOMP_FILTER
51 select HAVE_ARCH_TRACEHOOK
53 select HAVE_C_RECORDMCOUNT
54 select HAVE_CC_STACKPROTECTOR
55 select HAVE_CMPXCHG_DOUBLE
56 select HAVE_DEBUG_BUGVERBOSE
57 select HAVE_DEBUG_KMEMLEAK
58 select HAVE_DMA_API_DEBUG
60 select HAVE_DMA_CONTIGUOUS
61 select HAVE_DYNAMIC_FTRACE
62 select HAVE_EFFICIENT_UNALIGNED_ACCESS
63 select HAVE_FTRACE_MCOUNT_RECORD
64 select HAVE_FUNCTION_TRACER
65 select HAVE_FUNCTION_GRAPH_TRACER
66 select HAVE_GENERIC_DMA_COHERENT
67 select HAVE_HW_BREAKPOINT if PERF_EVENTS
69 select HAVE_PATA_PLATFORM
70 select HAVE_PERF_EVENTS
72 select HAVE_PERF_USER_STACK_DUMP
73 select HAVE_RCU_TABLE_FREE
74 select HAVE_SYSCALL_TRACEPOINTS
76 select IRQ_FORCED_THREADING
77 select MODULES_USE_ELF_RELA
80 select OF_EARLY_FLATTREE
81 select OF_RESERVED_MEM
82 select PERF_USE_VMALLOC
87 select SYSCTL_EXCEPTION_TRACE
88 select HAVE_CONTEXT_TRACKING
90 ARM 64-bit (AArch64) Linux support.
95 config ARCH_PHYS_ADDR_T_64BIT
104 config STACKTRACE_SUPPORT
107 config LOCKDEP_SUPPORT
110 config TRACE_IRQFLAGS_SUPPORT
113 config RWSEM_XCHGADD_ALGORITHM
116 config GENERIC_HWEIGHT
122 config GENERIC_CALIBRATE_DELAY
128 config HAVE_GENERIC_RCU_GUP
131 config ARCH_DMA_ADDR_T_64BIT
134 config NEED_DMA_MAP_STATE
137 config NEED_SG_DMA_LENGTH
146 config KERNEL_MODE_NEON
149 config FIX_EARLYCON_MEM
152 config PGTABLE_LEVELS
154 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
155 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
156 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
157 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
159 source "init/Kconfig"
161 source "kernel/Kconfig.freezer"
163 menu "Platform selection"
168 This enables support for Samsung Exynos SoC family
171 bool "ARMv8 based Samsung Exynos7"
173 select COMMON_CLK_SAMSUNG
174 select HAVE_S3C2410_WATCHDOG if WATCHDOG
175 select HAVE_S3C_RTC if RTC_CLASS
177 select PINCTRL_EXYNOS
180 This enables support for Samsung Exynos7 SoC family
182 config ARCH_FSL_LS2085A
183 bool "Freescale LS2085A SOC"
185 This enables support for Freescale LS2085A SOC.
188 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
192 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
195 bool "Qualcomm Platforms"
198 This enables support for the ARMv8 based Qualcomm chipsets.
201 bool "AMD Seattle SoC Family"
203 This enables support for AMD Seattle SOC Family
206 bool "NVIDIA Tegra SoC Family"
207 select ARCH_HAS_RESET_CONTROLLER
208 select ARCH_REQUIRE_GPIOLIB
212 select GENERIC_CLOCKEVENTS
215 select RESET_CONTROLLER
217 This enables support for the NVIDIA Tegra SoC family.
219 config ARCH_TEGRA_132_SOC
220 bool "NVIDIA Tegra132 SoC"
221 depends on ARCH_TEGRA
222 select PINCTRL_TEGRA124
223 select USB_ULPI if USB_PHY
224 select USB_ULPI_VIEWPORT if USB_PHY
226 Enable support for NVIDIA Tegra132 SoC, based on the Denver
227 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
228 but contains an NVIDIA Denver CPU complex in place of
229 Tegra124's "4+1" Cortex-A15 CPU complex.
232 bool "Spreadtrum SoC platform"
234 Support for Spreadtrum ARM based SoCs
237 bool "Cavium Inc. Thunder SoC Family"
239 This enables support for Cavium's Thunder Family of SoCs.
242 bool "ARMv8 software model (Versatile Express)"
243 select ARCH_REQUIRE_GPIOLIB
244 select COMMON_CLK_VERSATILE
245 select POWER_RESET_VEXPRESS
246 select VEXPRESS_CONFIG
248 This enables support for the ARMv8 software model (Versatile
252 bool "AppliedMicro X-Gene SOC Family"
254 This enables support for AppliedMicro X-Gene SOC Family
257 bool "Xilinx ZynqMP Family"
259 This enables support for Xilinx ZynqMP Family
268 This feature enables support for PCI bus system. If you say Y
269 here, the kernel will include drivers and infrastructure code
270 to support PCI bus devices.
275 config PCI_DOMAINS_GENERIC
281 source "drivers/pci/Kconfig"
282 source "drivers/pci/pcie/Kconfig"
283 source "drivers/pci/hotplug/Kconfig"
287 menu "Kernel Features"
289 menu "ARM errata workarounds via the alternatives framework"
291 config ARM64_ERRATUM_826319
292 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
295 This option adds an alternative code sequence to work around ARM
296 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
297 AXI master interface and an L2 cache.
299 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
300 and is unable to accept a certain write via this interface, it will
301 not progress on read data presented on the read data channel and the
304 The workaround promotes data cache clean instructions to
305 data cache clean-and-invalidate.
306 Please note that this does not necessarily enable the workaround,
307 as it depends on the alternative framework, which will only patch
308 the kernel if an affected CPU is detected.
312 config ARM64_ERRATUM_827319
313 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
316 This option adds an alternative code sequence to work around ARM
317 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
318 master interface and an L2 cache.
320 Under certain conditions this erratum can cause a clean line eviction
321 to occur at the same time as another transaction to the same address
322 on the AMBA 5 CHI interface, which can cause data corruption if the
323 interconnect reorders the two transactions.
325 The workaround promotes data cache clean instructions to
326 data cache clean-and-invalidate.
327 Please note that this does not necessarily enable the workaround,
328 as it depends on the alternative framework, which will only patch
329 the kernel if an affected CPU is detected.
333 config ARM64_ERRATUM_824069
334 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
337 This option adds an alternative code sequence to work around ARM
338 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
339 to a coherent interconnect.
341 If a Cortex-A53 processor is executing a store or prefetch for
342 write instruction at the same time as a processor in another
343 cluster is executing a cache maintenance operation to the same
344 address, then this erratum might cause a clean cache line to be
345 incorrectly marked as dirty.
347 The workaround promotes data cache clean instructions to
348 data cache clean-and-invalidate.
349 Please note that this option does not necessarily enable the
350 workaround, as it depends on the alternative framework, which will
351 only patch the kernel if an affected CPU is detected.
355 config ARM64_ERRATUM_819472
356 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
359 This option adds an alternative code sequence to work around ARM
360 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
361 present when it is connected to a coherent interconnect.
363 If the processor is executing a load and store exclusive sequence at
364 the same time as a processor in another cluster is executing a cache
365 maintenance operation to the same address, then this erratum might
366 cause data corruption.
368 The workaround promotes data cache clean instructions to
369 data cache clean-and-invalidate.
370 Please note that this does not necessarily enable the workaround,
371 as it depends on the alternative framework, which will only patch
372 the kernel if an affected CPU is detected.
376 config ARM64_ERRATUM_832075
377 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
380 This option adds an alternative code sequence to work around ARM
381 erratum 832075 on Cortex-A57 parts up to r1p2.
383 Affected Cortex-A57 parts might deadlock when exclusive load/store
384 instructions to Write-Back memory are mixed with Device loads.
386 The workaround is to promote device loads to use Load-Acquire
388 Please note that this does not necessarily enable the workaround,
389 as it depends on the alternative framework, which will only patch
390 the kernel if an affected CPU is detected.
394 config ARM64_ERRATUM_845719
395 bool "Cortex-A53: 845719: a load might read incorrect data"
399 This option adds an alternative code sequence to work around ARM
400 erratum 845719 on Cortex-A53 parts up to r0p4.
402 When running a compat (AArch32) userspace on an affected Cortex-A53
403 part, a load at EL0 from a virtual address that matches the bottom 32
404 bits of the virtual address used by a recent load at (AArch64) EL1
405 might return incorrect data.
407 The workaround is to write the contextidr_el1 register on exception
408 return to a 32-bit task.
409 Please note that this does not necessarily enable the workaround,
410 as it depends on the alternative framework, which will only patch
411 the kernel if an affected CPU is detected.
420 default ARM64_4K_PAGES
422 Page size (translation granule) configuration.
424 config ARM64_4K_PAGES
427 This feature enables 4KB pages support.
429 config ARM64_64K_PAGES
432 This feature enables 64KB pages support (4KB by default)
433 allowing only two levels of page tables and faster TLB
434 look-up. AArch32 emulation is not available when this feature
440 prompt "Virtual address space size"
441 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
442 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
444 Allows choosing one of multiple possible virtual address
445 space sizes. The level of translation table is determined by
446 a combination of page size and virtual address space size.
448 config ARM64_VA_BITS_39
450 depends on ARM64_4K_PAGES
452 config ARM64_VA_BITS_42
454 depends on ARM64_64K_PAGES
456 config ARM64_VA_BITS_48
463 default 39 if ARM64_VA_BITS_39
464 default 42 if ARM64_VA_BITS_42
465 default 48 if ARM64_VA_BITS_48
467 config CPU_BIG_ENDIAN
468 bool "Build big-endian kernel"
470 Say Y if you plan on running a kernel in big-endian mode.
473 bool "Symmetric Multi-Processing"
475 This enables support for systems with more than one CPU. If
476 you say N here, the kernel will run on single and
477 multiprocessor machines, but will use only one CPU of a
478 multiprocessor machine. If you say Y here, the kernel will run
479 on many, but not all, single processor machines. On a single
480 processor machine, the kernel will run faster if you say N
483 If you don't know what to do here, say N.
486 bool "Multi-core scheduler support"
489 Multi-core scheduler support improves the CPU scheduler's decision
490 making when dealing with multi-core CPU chips at a cost of slightly
491 increased overhead in some places. If unsure say N here.
494 bool "SMT scheduler support"
497 Improves the CPU scheduler's decision making when dealing with
498 MultiThreading at a cost of slightly increased overhead in some
499 places. If unsure say N here.
502 int "Maximum number of CPUs (2-4096)"
505 # These have to remain sorted largest to smallest
509 bool "Support for hot-pluggable CPUs"
512 Say Y here to experiment with turning CPUs off and on. CPUs
513 can be controlled through /sys/devices/system/cpu.
515 source kernel/Kconfig.preempt
525 config ARCH_HAS_HOLES_MEMORYMODEL
526 def_bool y if SPARSEMEM
528 config ARCH_SPARSEMEM_ENABLE
530 select SPARSEMEM_VMEMMAP_ENABLE
532 config ARCH_SPARSEMEM_DEFAULT
533 def_bool ARCH_SPARSEMEM_ENABLE
535 config ARCH_SELECT_MEMORY_MODEL
536 def_bool ARCH_SPARSEMEM_ENABLE
538 config HAVE_ARCH_PFN_VALID
539 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
541 config HW_PERF_EVENTS
542 bool "Enable hardware performance counter support for perf events"
543 depends on PERF_EVENTS
546 Enable hardware performance counter support for perf events. If
547 disabled, perf events will use software events only.
549 config SYS_SUPPORTS_HUGETLBFS
552 config ARCH_WANT_GENERAL_HUGETLB
555 config ARCH_WANT_HUGE_PMD_SHARE
556 def_bool y if !ARM64_64K_PAGES
558 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
561 config ARCH_HAS_CACHE_LINE_SIZE
567 bool "Enable seccomp to safely compute untrusted bytecode"
569 This kernel feature is useful for number crunching applications
570 that may need to compute untrusted bytecode during their
571 execution. By using pipes or other transports made available to
572 the process as file descriptors supporting the read/write
573 syscalls, it's possible to isolate those applications in
574 their own address space using seccomp. Once seccomp is
575 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
576 and the task is only allowed to execute a few safe syscalls
577 defined by each seccomp mode.
584 bool "Xen guest support on ARM64"
585 depends on ARM64 && OF
588 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
590 config FORCE_MAX_ZONEORDER
592 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
595 menuconfig ARMV8_DEPRECATED
596 bool "Emulate deprecated/obsolete ARMv8 instructions"
599 Legacy software support may require certain instructions
600 that have been deprecated or obsoleted in the architecture.
602 Enable this config to enable selective emulation of these
610 bool "Emulate SWP/SWPB instructions"
612 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
613 they are always undefined. Say Y here to enable software
614 emulation of these instructions for userspace using LDXR/STXR.
616 In some older versions of glibc [<=2.8] SWP is used during futex
617 trylock() operations with the assumption that the code will not
618 be preempted. This invalid assumption may be more likely to fail
619 with SWP emulation enabled, leading to deadlock of the user
622 NOTE: when accessing uncached shared regions, LDXR/STXR rely
623 on an external transaction monitoring block called a global
624 monitor to maintain update atomicity. If your system does not
625 implement a global monitor, this option can cause programs that
626 perform SWP operations to uncached memory to deadlock.
630 config CP15_BARRIER_EMULATION
631 bool "Emulate CP15 Barrier instructions"
633 The CP15 barrier instructions - CP15ISB, CP15DSB, and
634 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
635 strongly recommended to use the ISB, DSB, and DMB
636 instructions instead.
638 Say Y here to enable software emulation of these
639 instructions for AArch32 userspace code. When this option is
640 enabled, CP15 barrier usage is traced which can help
641 identify software that needs updating.
645 config SETEND_EMULATION
646 bool "Emulate SETEND instruction"
648 The SETEND instruction alters the data-endianness of the
649 AArch32 EL0, and is deprecated in ARMv8.
651 Say Y here to enable software emulation of the instruction
652 for AArch32 userspace code.
654 Note: All the cpus on the system must have mixed endian support at EL0
655 for this feature to be enabled. If a new CPU - which doesn't support mixed
656 endian - is hotplugged in after this feature has been enabled, there could
657 be unexpected results in the applications.
667 string "Default kernel command string"
670 Provide a set of default command-line options at build time by
671 entering them here. As a minimum, you should specify the the
672 root device (e.g. root=/dev/nfs).
675 bool "Always use the default kernel command string"
677 Always use the default kernel command string, even if the boot
678 loader passes other arguments to the kernel.
679 This is useful if you cannot or don't want to change the
680 command-line options your boot loader passes to the kernel.
686 bool "UEFI runtime support"
687 depends on OF && !CPU_BIG_ENDIAN
690 select EFI_PARAMS_FROM_FDT
691 select EFI_RUNTIME_WRAPPERS
696 This option provides support for runtime services provided
697 by UEFI firmware (such as non-volatile variables, realtime
698 clock, and platform reset). A UEFI stub is also provided to
699 allow the kernel to be booted as an EFI application. This
700 is only useful on systems that have UEFI firmware.
703 bool "Enable support for SMBIOS (DMI) tables"
707 This enables SMBIOS/DMI feature for systems.
709 This option is only useful on systems that have UEFI firmware.
710 However, even with this option, the resultant kernel should
711 continue to boot on existing non-UEFI platforms.
715 menu "Userspace binary formats"
717 source "fs/Kconfig.binfmt"
720 bool "Kernel support for 32-bit EL0"
721 depends on !ARM64_64K_PAGES || EXPERT
722 select COMPAT_BINFMT_ELF
724 select OLD_SIGSUSPEND3
725 select COMPAT_OLD_SIGACTION
727 This option enables support for a 32-bit EL0 running under a 64-bit
728 kernel at EL1. AArch32-specific components such as system calls,
729 the user helper functions, VFP support and the ptrace interface are
730 handled appropriately by the kernel.
732 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
733 will only be able to execute AArch32 binaries that were compiled with
734 64k aligned segments.
736 If you want to execute 32-bit userspace applications, say Y.
738 config SYSVIPC_COMPAT
740 depends on COMPAT && SYSVIPC
744 menu "Power management options"
746 source "kernel/power/Kconfig"
748 config ARCH_SUSPEND_POSSIBLE
753 menu "CPU Power Management"
755 source "drivers/cpuidle/Kconfig"
757 source "drivers/cpufreq/Kconfig"
763 source "drivers/Kconfig"
765 source "drivers/firmware/Kconfig"
767 source "drivers/acpi/Kconfig"
771 source "arch/arm64/kvm/Kconfig"
773 source "arch/arm64/Kconfig.debug"
775 source "security/Kconfig"
777 source "crypto/Kconfig"
779 source "arch/arm64/crypto/Kconfig"