2 * Based on arch/arm/include/asm/atomic.h
4 * Copyright (C) 1996 Russell King.
5 * Copyright (C) 2002 Deep Blue Solutions Ltd.
6 * Copyright (C) 2012 ARM Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #ifndef __ASM_ATOMIC_LL_SC_H
22 #define __ASM_ATOMIC_LL_SC_H
24 #ifndef __ARM64_IN_ATOMIC_IMPL
25 #error "please don't include this file directly"
29 * AArch64 UP and SMP safe atomic ops. We use load exclusive and
30 * store exclusive to ensure that these are atomic. We may loop
31 * to ensure that the update happens.
33 * NOTE: these functions do *not* follow the PCS and must explicitly
34 * save any clobbered registers other than x0 (regardless of return
35 * value). This is achieved through -fcall-saved-* compiler flags for
36 * this file, which unfortunately don't work on a per-function basis
37 * (the optimize attribute silently ignores these options).
40 #define ATOMIC_OP(op, asm_op) \
42 __LL_SC_PREFIX(atomic_##op(int i, atomic_t *v)) \
47 asm volatile("// atomic_" #op "\n" \
48 " prfm pstl1strm, %2\n" \
50 " " #asm_op " %w0, %w0, %w3\n" \
51 " stxr %w1, %w0, %2\n" \
53 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
56 __LL_SC_EXPORT(atomic_##op);
58 #define ATOMIC_OP_RETURN(op, asm_op) \
60 __LL_SC_PREFIX(atomic_##op##_return(int i, atomic_t *v)) \
65 asm volatile("// atomic_" #op "_return\n" \
66 " prfm pstl1strm, %2\n" \
68 " " #asm_op " %w0, %w0, %w3\n" \
69 " stlxr %w1, %w0, %2\n" \
71 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
78 __LL_SC_EXPORT(atomic_##op##_return);
80 #define ATOMIC_OPS(op, asm_op) \
81 ATOMIC_OP(op, asm_op) \
82 ATOMIC_OP_RETURN(op, asm_op)
88 ATOMIC_OP(andnot, bic)
93 #undef ATOMIC_OP_RETURN
96 #define ATOMIC64_OP(op, asm_op) \
98 __LL_SC_PREFIX(atomic64_##op(long i, atomic64_t *v)) \
103 asm volatile("// atomic64_" #op "\n" \
104 " prfm pstl1strm, %2\n" \
106 " " #asm_op " %0, %0, %3\n" \
107 " stxr %w1, %0, %2\n" \
109 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
112 __LL_SC_EXPORT(atomic64_##op);
114 #define ATOMIC64_OP_RETURN(op, asm_op) \
115 __LL_SC_INLINE long \
116 __LL_SC_PREFIX(atomic64_##op##_return(long i, atomic64_t *v)) \
121 asm volatile("// atomic64_" #op "_return\n" \
122 " prfm pstl1strm, %2\n" \
124 " " #asm_op " %0, %0, %3\n" \
125 " stlxr %w1, %0, %2\n" \
127 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
134 __LL_SC_EXPORT(atomic64_##op##_return);
136 #define ATOMIC64_OPS(op, asm_op) \
137 ATOMIC64_OP(op, asm_op) \
138 ATOMIC64_OP_RETURN(op, asm_op)
140 ATOMIC64_OPS(add, add)
141 ATOMIC64_OPS(sub, sub)
143 ATOMIC64_OP(and, and)
144 ATOMIC64_OP(andnot, bic)
146 ATOMIC64_OP(xor, eor)
149 #undef ATOMIC64_OP_RETURN
153 __LL_SC_PREFIX(atomic64_dec_if_positive(atomic64_t *v))
158 asm volatile("// atomic64_dec_if_positive\n"
159 " prfm pstl1strm, %2\n"
163 " stlxr %w1, %0, %2\n"
167 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
173 __LL_SC_EXPORT(atomic64_dec_if_positive);
175 #define __CMPXCHG_CASE(w, sz, name, mb, rel, cl) \
176 __LL_SC_INLINE unsigned long \
177 __LL_SC_PREFIX(__cmpxchg_case_##name(volatile void *ptr, \
179 unsigned long new)) \
181 unsigned long tmp, oldval; \
184 " prfm pstl1strm, %[v]\n" \
185 "1: ldxr" #sz "\t%" #w "[oldval], %[v]\n" \
186 " eor %" #w "[tmp], %" #w "[oldval], %" #w "[old]\n" \
187 " cbnz %" #w "[tmp], 2f\n" \
188 " st" #rel "xr" #sz "\t%w[tmp], %" #w "[new], %[v]\n" \
189 " cbnz %w[tmp], 1b\n" \
191 " mov %" #w "[oldval], %" #w "[old]\n" \
193 : [tmp] "=&r" (tmp), [oldval] "=&r" (oldval), \
194 [v] "+Q" (*(unsigned long *)ptr) \
195 : [old] "Lr" (old), [new] "r" (new) \
200 __LL_SC_EXPORT(__cmpxchg_case_##name);
202 __CMPXCHG_CASE(w, b, 1, , , )
203 __CMPXCHG_CASE(w, h, 2, , , )
204 __CMPXCHG_CASE(w, , 4, , , )
205 __CMPXCHG_CASE( , , 8, , , )
206 __CMPXCHG_CASE(w, b, mb_1, dmb ish, l, "memory")
207 __CMPXCHG_CASE(w, h, mb_2, dmb ish, l, "memory")
208 __CMPXCHG_CASE(w, , mb_4, dmb ish, l, "memory")
209 __CMPXCHG_CASE( , , mb_8, dmb ish, l, "memory")
211 #undef __CMPXCHG_CASE
213 #define __CMPXCHG_DBL(name, mb, rel, cl) \
215 __LL_SC_PREFIX(__cmpxchg_double##name(unsigned long old1, \
216 unsigned long old2, \
217 unsigned long new1, \
218 unsigned long new2, \
219 volatile void *ptr)) \
221 unsigned long tmp, ret; \
223 asm volatile("// __cmpxchg_double" #name "\n" \
224 " prfm pstl1strm, %2\n" \
225 "1: ldxp %0, %1, %2\n" \
226 " eor %0, %0, %3\n" \
227 " eor %1, %1, %4\n" \
228 " orr %1, %0, %1\n" \
230 " st" #rel "xp %w0, %5, %6, %2\n" \
234 : "=&r" (tmp), "=&r" (ret), "+Q" (*(unsigned long *)ptr) \
235 : "r" (old1), "r" (old2), "r" (new1), "r" (new2) \
240 __LL_SC_EXPORT(__cmpxchg_double##name);
242 __CMPXCHG_DBL( , , , )
243 __CMPXCHG_DBL(_mb, dmb ish, l, "memory")
247 #endif /* __ASM_ATOMIC_LL_SC_H */