arch/arm64/include/asm/sysreg.h

   1 /*
   2  * Macros for accessing system registers with older binutils.
   3  *
   4  * Copyright (C) 2014 ARM Ltd.
   5  * Author: Catalin Marinas <catalin.marinas@arm.com>
   6  *
   7  * This program is free software: you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef __ASM_SYSREG_H
  21 #define __ASM_SYSREG_H
  22
  23 #include <asm/opcodes.h>
  24
  25 #define SCTLR_EL1_CP15BEN       (0x1 << 5)
  26 #define SCTLR_EL1_SED           (0x1 << 8)
  27
  28 /*
  29  * ARMv8 ARM reserves the following encoding for system registers:
  30  * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
  31  *  C5.2, version:ARM DDI 0487A.f)
  32  *      [20-19] : Op0
  33  *      [18-16] : Op1
  34  *      [15-12] : CRn
  35  *      [11-8]  : CRm
  36  *      [7-5]   : Op2
  37  */
  38 #define sys_reg(op0, op1, crn, crm, op2) \
  39         ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))
  40
  41 #define REG_PSTATE_PAN_IMM                     sys_reg(0, 0, 4, 0, 4)
  42 #define SCTLR_EL1_SPAN                         (1 << 23)
  43
  44 #define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 | REG_PSTATE_PAN_IMM |\
  45                                      (!!x)<<8 | 0x1f)
  46
  47
  48 #define ID_AA64MMFR0_TGRAN4_SHIFT       28
  49 #define ID_AA64MMFR0_TGRAN64_SHIFT      24
  50 #define ID_AA64MMFR0_TGRAN16_SHIFT      20
  51
  52 #define ID_AA64MMFR0_TGRAN4_NI          0xf
  53 #define ID_AA64MMFR0_TGRAN4_SUPPORTED   0x0
  54 #define ID_AA64MMFR0_TGRAN64_NI         0xf
  55 #define ID_AA64MMFR0_TGRAN64_SUPPORTED  0x0
  56 #define ID_AA64MMFR0_TGRAN16_NI         0x0
  57 #define ID_AA64MMFR0_TGRAN16_SUPPORTED  0x1
  58
  59 #if defined(CONFIG_ARM64_4K_PAGES)
  60 #define ID_AA64MMFR0_TGRAN_SHIFT        ID_AA64MMFR0_TGRAN4_SHIFT
  61 #define ID_AA64MMFR0_TGRAN_SUPPORTED    ID_AA64MMFR0_TGRAN4_SUPPORTED
  62 #elif defined(CONFIG_ARM64_64K_PAGES)
  63 #define ID_AA64MMFR0_TGRAN_SHIFT        ID_AA64MMFR0_TGRAN64_SHIFT
  64 #define ID_AA64MMFR0_TGRAN_SUPPORTED    ID_AA64MMFR0_TGRAN64_SUPPORTED
  65 #endif
  66
  67 #ifdef __ASSEMBLY__
  68
  69         .irp    num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
  70         .equ    __reg_num_x\num, \num
  71         .endr
  72         .equ    __reg_num_xzr, 31
  73
  74         .macro  mrs_s, rt, sreg
  75         .inst   0xd5200000|(\sreg)|(__reg_num_\rt)
  76         .endm
  77
  78         .macro  msr_s, sreg, rt
  79         .inst   0xd5000000|(\sreg)|(__reg_num_\rt)
  80         .endm
  81
  82 #else
  83
  84 asm(
  85 "       .irp    num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
  86 "       .equ    __reg_num_x\\num, \\num\n"
  87 "       .endr\n"
  88 "       .equ    __reg_num_xzr, 31\n"
  89 "\n"
  90 "       .macro  mrs_s, rt, sreg\n"
  91 "       .inst   0xd5200000|(\\sreg)|(__reg_num_\\rt)\n"
  92 "       .endm\n"
  93 "\n"
  94 "       .macro  msr_s, sreg, rt\n"
  95 "       .inst   0xd5000000|(\\sreg)|(__reg_num_\\rt)\n"
  96 "       .endm\n"
  97 );
  98
  99 static inline void config_sctlr_el1(u32 clear, u32 set)
 100 {
 101         u32 val;
 102
 103         asm volatile("mrs %0, sctlr_el1" : "=r" (val));
 104         val &= ~clear;
 105         val |= set;
 106         asm volatile("msr sctlr_el1, %0" : : "r" (val));
 107 }
 108 #endif
 109
 110 #endif  /* __ASM_SYSREG_H */