2 * Contains CPU feature definitions
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "CPU features: " fmt
21 #include <linux/bsearch.h>
22 #include <linux/sort.h>
23 #include <linux/types.h>
25 #include <asm/cpufeature.h>
26 #include <asm/processor.h>
27 #include <asm/sysreg.h>
29 static bool mixed_endian_el0 = true;
30 unsigned long elf_hwcap __read_mostly;
31 EXPORT_SYMBOL_GPL(elf_hwcap);
34 #define COMPAT_ELF_HWCAP_DEFAULT \
35 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
36 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
37 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
38 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
39 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
41 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
42 unsigned int compat_elf_hwcap2 __read_mostly;
45 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
48 bool cpu_supports_mixed_endian_el0(void)
50 return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
53 bool system_supports_mixed_endian_el0(void)
55 return mixed_endian_el0;
58 static void update_mixed_endian_el0_support(struct cpuinfo_arm64 *info)
60 mixed_endian_el0 &= id_aa64mmfr0_mixed_endian_el0(info->reg_id_aa64mmfr0);
63 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
69 .safe_val = SAFE_VAL, \
72 #define ARM64_FTR_END \
77 static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
78 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
79 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
80 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
81 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
82 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
83 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
84 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
85 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
86 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
90 static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
91 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
92 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
93 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
94 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
95 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
96 /* Linux doesn't care about the EL3 */
97 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
98 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
99 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
100 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
104 static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
105 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
106 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
107 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
108 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
109 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
110 /* Linux shouldn't care about secure memory */
111 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
112 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
113 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
115 * Differing PARange is fine as long as all peripherals and memory are mapped
116 * within the minimum PARange of all CPUs
118 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
122 static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
123 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
124 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
125 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
126 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
127 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
128 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
129 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
133 static struct arm64_ftr_bits ftr_ctr[] = {
134 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
135 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
136 ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
137 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
138 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
140 * Linux can handle differing I-cache policies. Userspace JITs will
141 * make use of *minLine
143 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0), /* L1Ip */
144 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0), /* RAZ */
145 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
149 static struct arm64_ftr_bits ftr_id_mmfr0[] = {
150 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0), /* InnerShr */
151 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */
152 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
153 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */
154 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */
155 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* OuterShr */
156 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
157 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
161 static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
162 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
163 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
164 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
165 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
166 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
167 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
168 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
172 static struct arm64_ftr_bits ftr_mvfr2[] = {
173 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
174 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */
175 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */
179 static struct arm64_ftr_bits ftr_dczid[] = {
180 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0), /* RAZ */
181 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
182 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
187 static struct arm64_ftr_bits ftr_id_isar5[] = {
188 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
189 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0), /* RAZ */
190 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
191 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
192 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
193 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
194 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
198 static struct arm64_ftr_bits ftr_id_mmfr4[] = {
199 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
200 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */
201 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
205 static struct arm64_ftr_bits ftr_id_pfr0[] = {
206 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0), /* RAZ */
207 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */
208 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */
209 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */
210 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */
215 * Common ftr bits for a 32bit register with all hidden, strict
216 * attributes, with 4bit feature fields and a default safe value of
217 * 0. Covers the following 32bit registers:
218 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
220 static struct arm64_ftr_bits ftr_generic_32bits[] = {
221 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
222 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
223 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
224 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
225 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
226 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
227 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
228 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
232 static struct arm64_ftr_bits ftr_generic[] = {
233 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
237 static struct arm64_ftr_bits ftr_generic32[] = {
238 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
242 static struct arm64_ftr_bits ftr_aa64raz[] = {
243 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
247 #define ARM64_FTR_REG(id, table) \
251 .ftr_bits = &((table)[0]), \
254 static struct arm64_ftr_reg arm64_ftr_regs[] = {
256 /* Op1 = 0, CRn = 0, CRm = 1 */
257 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
258 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
259 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_generic_32bits),
260 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
261 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
262 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
263 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
265 /* Op1 = 0, CRn = 0, CRm = 2 */
266 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
267 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
268 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
269 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
270 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
271 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
272 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
274 /* Op1 = 0, CRn = 0, CRm = 3 */
275 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
276 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
277 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
279 /* Op1 = 0, CRn = 0, CRm = 4 */
280 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
281 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
283 /* Op1 = 0, CRn = 0, CRm = 5 */
284 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
285 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
287 /* Op1 = 0, CRn = 0, CRm = 6 */
288 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
289 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
291 /* Op1 = 0, CRn = 0, CRm = 7 */
292 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
293 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
295 /* Op1 = 3, CRn = 0, CRm = 0 */
296 ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
297 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
299 /* Op1 = 3, CRn = 14, CRm = 0 */
300 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
303 static int search_cmp_ftr_reg(const void *id, const void *regp)
305 return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
309 * get_arm64_ftr_reg - Lookup a feature register entry using its
310 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
311 * ascending order of sys_id , we use binary search to find a matching
314 * returns - Upon success, matching ftr_reg entry for id.
315 * - NULL on failure. It is upto the caller to decide
316 * the impact of a failure.
318 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
320 return bsearch((const void *)(unsigned long)sys_id,
322 ARRAY_SIZE(arm64_ftr_regs),
323 sizeof(arm64_ftr_regs[0]),
327 static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
329 u64 mask = arm64_ftr_mask(ftrp);
332 reg |= (ftr_val << ftrp->shift) & mask;
336 static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
340 switch (ftrp->type) {
342 ret = ftrp->safe_val;
345 ret = new < cur ? new : cur;
347 case FTR_HIGHER_SAFE:
348 ret = new > cur ? new : cur;
357 static int __init sort_cmp_ftr_regs(const void *a, const void *b)
359 return ((const struct arm64_ftr_reg *)a)->sys_id -
360 ((const struct arm64_ftr_reg *)b)->sys_id;
363 static void __init swap_ftr_regs(void *a, void *b, int size)
365 struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
366 *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
367 *(struct arm64_ftr_reg *)b = tmp;
370 static void __init sort_ftr_regs(void)
372 /* Keep the array sorted so that we can do the binary search */
374 ARRAY_SIZE(arm64_ftr_regs),
375 sizeof(arm64_ftr_regs[0]),
381 * Initialise the CPU feature register from Boot CPU values.
382 * Also initiliases the strict_mask for the register.
384 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
387 u64 strict_mask = ~0x0ULL;
388 struct arm64_ftr_bits *ftrp;
389 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
393 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
394 s64 ftr_new = arm64_ftr_value(ftrp, new);
396 val = arm64_ftr_set_value(ftrp, val, ftr_new);
398 strict_mask &= ~arm64_ftr_mask(ftrp);
401 reg->strict_mask = strict_mask;
404 void __init init_cpu_features(struct cpuinfo_arm64 *info)
406 /* Before we start using the tables, make sure it is sorted */
409 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
410 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
411 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
412 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
413 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
414 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
415 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
416 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
417 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
418 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
419 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
420 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
421 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
422 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
423 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
424 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
425 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
426 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
427 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
428 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
429 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
430 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
431 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
432 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
433 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
434 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
435 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
437 /* This will be removed later, once we start using the infrastructure */
438 update_mixed_endian_el0_support(info);
441 static void update_cpu_ftr_reg(u32 sys_reg, u64 new)
443 struct arm64_ftr_bits *ftrp;
444 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
448 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
449 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
450 s64 ftr_new = arm64_ftr_value(ftrp, new);
452 if (ftr_cur == ftr_new)
454 /* Find a safe value */
455 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
456 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
461 /* Update CPU feature register from non-boot CPU */
462 void update_cpu_features(struct cpuinfo_arm64 *info)
464 update_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
465 update_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
466 update_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
467 update_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
468 update_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
469 update_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
470 update_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
471 update_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
472 update_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
473 update_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
474 update_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
475 update_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
476 update_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
477 update_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
478 update_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
479 update_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
480 update_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
481 update_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
482 update_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
483 update_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
484 update_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
485 update_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
486 update_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
487 update_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
488 update_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
489 update_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
490 update_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
492 update_mixed_endian_el0_support(info);
496 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
498 int val = cpuid_feature_extract_field(reg, entry->field_pos);
500 return val >= entry->min_field_value;
503 #define __ID_FEAT_CHK(reg) \
504 static bool __maybe_unused \
505 has_##reg##_feature(const struct arm64_cpu_capabilities *entry) \
509 val = read_cpuid(reg##_el1); \
510 return feature_matches(val, entry); \
513 __ID_FEAT_CHK(id_aa64pfr0);
514 __ID_FEAT_CHK(id_aa64mmfr1);
515 __ID_FEAT_CHK(id_aa64isar0);
517 static const struct arm64_cpu_capabilities arm64_features[] = {
519 .desc = "GIC system register CPU interface",
520 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
521 .matches = has_id_aa64pfr0_feature,
523 .min_field_value = 1,
525 #ifdef CONFIG_ARM64_PAN
527 .desc = "Privileged Access Never",
528 .capability = ARM64_HAS_PAN,
529 .matches = has_id_aa64mmfr1_feature,
531 .min_field_value = 1,
532 .enable = cpu_enable_pan,
534 #endif /* CONFIG_ARM64_PAN */
535 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
537 .desc = "LSE atomic instructions",
538 .capability = ARM64_HAS_LSE_ATOMICS,
539 .matches = has_id_aa64isar0_feature,
541 .min_field_value = 2,
543 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
547 void check_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
552 for (i = 0; caps[i].desc; i++) {
553 if (!caps[i].matches(&caps[i]))
556 if (!cpus_have_cap(caps[i].capability))
557 pr_info("%s %s\n", info, caps[i].desc);
558 cpus_set_cap(caps[i].capability);
561 /* second pass allows enable() to consider interacting capabilities */
562 for (i = 0; caps[i].desc; i++) {
563 if (cpus_have_cap(caps[i].capability) && caps[i].enable)
568 void check_local_cpu_features(void)
570 check_cpu_capabilities(arm64_features, "detected feature:");
573 void __init setup_cpu_features(void)
581 * Check for sane CTR_EL0.CWG value.
583 cwg = cache_type_cwg();
584 cls = cache_line_size();
586 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
588 if (L1_CACHE_BYTES < cls)
589 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
590 L1_CACHE_BYTES, cls);
593 * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
594 * The blocks we test below represent incremental functionality
595 * for non-negative values. Negative values are reserved.
597 features = read_cpuid(ID_AA64ISAR0_EL1);
598 block = cpuid_feature_extract_field(features, 4);
603 elf_hwcap |= HWCAP_PMULL;
605 elf_hwcap |= HWCAP_AES;
611 if (cpuid_feature_extract_field(features, 8) > 0)
612 elf_hwcap |= HWCAP_SHA1;
614 if (cpuid_feature_extract_field(features, 12) > 0)
615 elf_hwcap |= HWCAP_SHA2;
617 if (cpuid_feature_extract_field(features, 16) > 0)
618 elf_hwcap |= HWCAP_CRC32;
620 block = cpuid_feature_extract_field(features, 20);
625 elf_hwcap |= HWCAP_ATOMICS;
635 * ID_ISAR5_EL1 carries similar information as above, but pertaining to
636 * the AArch32 32-bit execution state.
638 features = read_cpuid(ID_ISAR5_EL1);
639 block = cpuid_feature_extract_field(features, 4);
644 compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL;
646 compat_elf_hwcap2 |= COMPAT_HWCAP2_AES;
652 if (cpuid_feature_extract_field(features, 8) > 0)
653 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1;
655 if (cpuid_feature_extract_field(features, 12) > 0)
656 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2;
658 if (cpuid_feature_extract_field(features, 16) > 0)
659 compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32;